* For ARMC6, core types `Cortex-M4` and `Cortex-M7` did not explicitly
add `--fpu=none`, so it defaulted to assuming FPU present. This would
cause a compilation error if the target's cmsis.h had `__FPU_PRESENT`
defined to 0.
* For GCC, `Cortex-M33FE` did not include `+dsp` in the architecture
selection.
* For ARMC5 and ARMC6, `Cortex-M0+` did not pass `M0plus` to the
non-Clang tools.
In rtos-less code, heap is defined by assuming one-region. Through weak-reference to
ARM_LIB_HEAP, heap definition is fixed if ARM_LIB_HEAP is defined.
* Unify PSA generators
* Replace scanning for mbed_spm templates with json
* Make generate_source_files and parse_manifests common
* Make assert_int an internal function
* Use parse_manifests in pytests
* Update docs
- Remove un-needed files
- Disable printf and uart
- Modify include paths
- Guard macros from mbed_lib with ifndef
(cherry picked from commit 1f30b52488)
(cherry picked from commit 71cd34df32)
Flash driver 3.30:
Moved ipcWaitMessageStc structure to the RAM section called ".cy_sharedmem"
Added support Secure Boot devices
Moved CY_FLASH_EFFECTIVE_PAGE_SIZE to flash_api.c (the macro is Mbed specific).
GeneratedSource folders are BSP specific. No parts of the kit BSP can be reused
as generic chip support package. Remove TARGET_CY8C62XX directory,
and use flat BSP inheritance model:
MCU_PSOC6 -> MCU_PSOC6_M4 -> CY8CKIT_062_WIFI_BT
MCU_PSOC6 -> MCU_PSOC6_M0 -> CY8CKIT_062_WIFI_BT_M0
- Remove un-needed files
- Disable printf and uart
- Modify include paths
- Guard macros from mbed_lib with ifndef
(cherry picked from commit 1f30b52488)
(cherry picked from commit 71cd34df32)
According to their cmsis.h, FPU is present, so change targets.json to
use it.
* ARM_MPS2_M4: already was Cortex-M4F
* ARM_MPS2_M7: Cortex-M7 -> M7FD
* FVP_MPS2_M4: Cortex-M4 -> M4F
* FVP_MPS2_M7: Cortex-M7 -> M7FD
If they do not in fact have FPU, then cmsis.h should be modified to set
`__FPU_PRESENT` to 0. This will currently cause compilation problems
with ARMC6, but I'll be submitting a fix for that.
Since commit 12c6b1bd8, the i.MX RT1050 has effectively had its data
cache disabled, as the SDRAM was marked Shareable; for the Cortex-M7,
shareable memory is not cached.
This was done to make the Ethernet driver work without any cache
maintenance code. This commit adds cache maintenance and memory barriers
to the Ethernet driver, and removes the Shareable attribute from the
SDRAM, so the data cache is used again.
Cache code in the base fsl_enet.c driver has not been activated - the
bulk of it is in higher-level Read and Write calls that we're not using,
and there is one flawed invalidate in its initialisation. Instead
imx_emac.cpp takes full cache responsibility.
This commit also marks the SDRAM as read/write-allocate. As the
Cortex-M7 has its "Dynamic read allocate mode" to automatically switch
back to read-allocate in cases where write allocate is working poorly
(eg large memset), this should result in a performance boost with no
downside.
Activating write-allocate is also an attempt to provoke any flaws in
cache maintenance - the Ethernet transmit buffers for example will be
more likely to have a little data in the cache that needs cleaning.
The ESP chip returns timeout, but keeps trying to connect, so we want to
keep track of time ourselves, instead of relying on the chip's timeout.
This fixes failing WIFI-CONNECT-SECURE-FAIL test.
PDL Flash API requires that the data buffer is 32-bit aligned, otherwise
programming can hung. Buffer declared as uint8_t array is not always
properly aligned, e.g. with gcc 6 when -Os option is used.
Kevin Bracey
ccli8
Deepika
Oren Cohen
Anna Bridge
Michael Schwarcz
Lei Zhang
Hennadiy Kytsun
Mirela Chirica
Amanda Butler
samgrove
j3hill
Brian Daniels
Michal Paszta
Leszek Rusinowicz