When doing so, do not disbale GPIO clocks as they may be used by other
drivers !
As a result, debug will be disabled by default, but can be enabled by
either modifying code or selecting MBED debug profile.
Issue was seen when running BLE_GAP example from
mbed-os-example-ble.
In STM32WB, the M0 core cannot be reset except if the whole target
is reset. So in case of re-initialization of the BLE stack, the
transport layer should not be initialized again. The HCI reset
command will do the job.
These files are not BLE specific, but also needed for some clock setting
for instance.
In order to compile an MBED2 application, we need to move the files.
- move hw_conf.h file to targets/TARGET_STM/TARGET_STM32WB directory as
this is used also out of BLE feature.
- create a dedicated hal_deepsleep function as the behavior in WB is a lot
different from other existing STM32 targets
- update clock tree configuration to directly clock the entire tree @ 32MHz
out of HSE. This is needed as we want to let the M0 core running without
any change on M0-side of clocks when M4 enters /exits deep sleep.
The STM32WB Coridio driver includes:
- the Cordio HCI driver handling the reset sequence. During reset sequence
the TX POWER level is set and the BD address is defined if found in OTP
or option bytes. The rest of the sequence is based on the standard CORDIO
HCI driver example.
- The Transport Layer part handles sending and receiving messages to the
WB controller running on cortex-M0 of the STM32WB target. The messages
are shared through shared memory and mailboxes system based on IPCC HW.
There are two EventQueue.h in mbed-os codebase:
events/EventQueue.h
features/FEATURE_BLE/ble/pal/EventQueue.h
By accident, `mbed compile` generates includes.txt with the correct
order of include search paths. This is not the case for the CMake
exporter: targets with FEATURE_BLE enables fail to compile with errors:
mbed-os/features/cellular/framework/AT/ATHandler.h:99:60: error:
'events' has not been declared
Update all places to always include either "events/EventQueue.h"
or "ble/pal/EventQueue.h": to always find the correct header.
`pscrk` is set to the address of `csrk`, but `csrk` is out of scope when using the resulting value. There's no guarantee that the memory is still valid.
Added WiFi_Bt CM4 PSA target in mbedos json
Added SPE-NSPE mailbox initialization for CM4 SystemInit
Made similar to FUTURE_SEQUANA configurations
Copied FUTURE_SEQUANA CM0 SPM part for WiFi_Bt smoke test
Added CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets
Sorted files for new CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets
Copied files for CY8CKIT_062_WIFI_BT_M0_PSA from FUTURE_SEQUANA
Copied and updated cm0p start files
Corrected according to FUTURE_SEQUANA
Changes to M0 startup files to have SPM started
Fixed implicit declaration warning
Commented interrupts enabling according to FUTURE_SEQUANA flow
Updated prebuild spm_smore CM0 hex for CM4 target
Turned on greentea environment
Used special memory region for common CM0/CM4 data
Updated prebuild CM0 SPM hex
Placed shared memory region for flash operations into SPM shared memory region
Updated cyprotection code and configuration
Start address of protected regions is set by a defined number from target.json
Added masters pcMask configuration
Added support for PSA target to WIFI_BT board
Enabled resources protection for SPM
Aligned RAM usage according to Cypress FlashBoot and CyBootloader
alligned protection config
Added CYW943012P6EVB_01_M0 target
Enlarged heap size, remobed nv_seed
Added heap reservation in linker script from mbed-os
Removed heap size definition
turned on nv_seed config
Removed nv_seed macros
Enabled protection for PSoC6 CM0
Added PSoC6 CM0 PSA readme
Enabled mbed_hal-spm test
Enabled nv_seed and removed unneeded ipc config define
Added SPDX string to feature_ble cypress target files
Removed unneeded supported_toolchains lines for Cypress targets
Disabled protection settings
Corrected flash initialization for PSoC6 CM0 PSA
Changed PSoC6 IPC6 protection for flash
Enabled special flash initialization and enabled protection settings
Updated and added new prebuild PSoC6 CM0 PSA hex files
Disabled HW TRNG and CRC for PSoC6 CM4 PSA target
Added missing const to allow types to match
Updated PSoC6 WIFI_BT_PSA prebuilt directory
Moved PSoC6 shared section usage area definition to begin of ld
Added initial ARM_STD linker and startup files for PSoC6 CM0
Added initial IAR linker and startup files for PSoC6 CM0
Added defines to disable some SPM protection settings for PSoC64
Moved Flash function variables into separate memory region
Added defines for new Public area definition
Updated PSoC6 CM0_PSA hex-files
paul-szczepanek-arm
Marc Emmers
Laurent Meunier
bcostm
Desmond Chen
Nick
Vincent Coubard
Volodymyr Medvid
Jan Jongboom
Donatien Garnier
Vivek Pallantla
Oleg Kapshii