The current timeout is set to 1200s that seems to be a little bit short
to finish all test cases, the timeout happens towards the end of the
last test case.
Change-Id: I914608c34828b493a80e133cd132537a297bfc84
Signed-off-by: Bence Kaposzta <bence.kaposzta@arm.com>
1. In drivers/Timer.cpp make sure that hardware timer is initialized outside of critical section.
This is because on PSoC 6 hardware resources are shared between both cores
and we have to make sure that the other core is not already using a particular resource.
This mechanism is based on interprocessor communication taht cannot be handled iside of
critical section.
2. Added support for post-binary hook function for PSoC 6 targets, so the hex image for M0+ CPU core
can be merged with M4 core image for the final image.
3. Added possibility to use hook function from exportes, so the M0+ hex image could be included
in the generated project.
4. Included hex images in the build dependency list, so the update of image is catched by the
build process.
1. Complete set of HAL drivers for all peripherals of CY8C63xx PSoC chips.
2. Cypress PDL library updated to official 3.0.1 version.
3. Tree structure reorganized and cleaned up:
+ TARGET_Cypress
+--+ TARGET_PSOC6+ -> code & libs applicable to all PSoC 6 based devices
+--+ TARGET_CY86XX -> code & libs applicable to PSoC 63 based devices
| +--- TARGET_MCU_PSOC6_M0 -> code & libs applicable to PSoC6 Corted M0+ core
| +--- TARGET_MCU_PSOC6_M4 -> code & libs applicable to PSoC6 Corted M0F core
|
+--+ TARGET_FUTURE_SEQUANA -> code applicable to Sequana board, both cores
+--- TARGET_FUTURE_SEQUANA_M0 -> code applicable only to M0+ core on Sequana board
Due to buggy flow control logic in the UARTE, the stop signal
is not being set as it is supposed to when the the module is
not ready to receive data.
This commit signals the sender to halt transmitting when a DMA
buffer is full and only continue again when the atomic FIFO
buffer has been emptied. This allows platforms with hardware
flow control to minimize all buffers and rely on flow control
instead.
LPC devices require a checksummed vector table to boot. To ensure
this most programmers automatically compute the checksum when
programming flash. This causes problems with verification if the
original image does not have a checksummed vector table. This is because
when reading the data back the checksum location differs from the
original image.
To fix this verification failure this patch adds a post build hook to
checksum the vector table of the LPC54XXX. This fixes flash
verification failures due to the checksum not matching.
The preprocessor based macro check #if evaluates all
enums as 0 and hence the code does not get compiled.
Since move this to a runtime check where the pin variable
can be correctly evaluated.
Delete mbed_overrides.c as it has a target specific mbed_sdk_init() to
resolve linking problem.
This is a follow on patch to:
https://github.com/ARMmbed/mbed-os/pull/8046
Add 16-bit access mode when writing the transfer size to prevent
the QSPI transaction from starting
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
While investigating the RX issue on NRF52_DK after SDK 14 updates,
it is observed that the RX FIFO doesn't get filled up, when the
flow control is disabled. Hence the readable never returns true.
If using Serial interface, the stdio file handles (0, 1, 2) get opened.
This results in configuring the flow control for STDIO, and it is observed
that the RX FIFO gets filled.
However, if RawSerial is used, the STDIO file handles
don't get opened. During the debug process it was observed that if the
flow control is configured once and then set to disabled, RX worked
as expected.
Alternative to this approach is that user application specifically
enables flow control as done in mbed's Greentea test suite. See https://goo.gl/r8nBYH
See https://goo.gl/8VB2qg step 14 for _initio's description.
See test code to reproduce the issue and test fix here: https://goo.gl/AQU1xG
Description
The change in behavior with NRF52's UART RX is documented here. #6891
This change is a fix for the above issue.
While investigating the RX issue on NRF52_DK after SDK 14 updates,
it is observed that the RX FIFO doesn't get filled up, when the
flow control is disabled. Hence the readable never returns true.
If using Serial interface, the stdio file handles (0, 1, 2) get opened.
This results in configuring the flow control for STDIO, and it is observed
that the RX FIFO gets filled.
However, if RawSerial is used, the STDIO file handles
don't get opened. During the debug process it was observed that if the
flow control is configured once and then set to disabled, RX worked
as expected.
Alternative to this approach is that user application specifically
enables flow control as done in mbed's Greentea test suite. See https://goo.gl/r8nBYH
See https://goo.gl/8VB2qg step 14 for _initio's description.
See test code to reproduce the issue and test fix here: https://goo.gl/AQU1xG
Description
The change in behavior with NRF52's UART RX is documented here. #6891
This change is a fix for the above issue.
shileiyu
Deepika
Qinghao Shi
jeromecoutant
Adam Heinrich
Leon Lindenfelser
Mahesh Mahadevan
Ganesh Ramachandran
Bence Kaposzta
bcostm
micgur01
Leszek Rusinowicz
Adrien Chardon
Ammad Rehmat
aqin
Marcus Chang
Russ Butler
Naveen Kaje
Mac Lobdell