LXT/HXT are external crystl oscillator and can be absent on custom board.
This enables configuring LXT/HXT presence:
1. By default, LXT/HXT are configured to be present, except M252 which has no HXT.
2. When LXT is configured to not present, lp_ticker/watchdog will clock by LIRC instead.
3. Limitations:
(1) On all targets, LIRC-clocked lp_ticker gets inaccurate and fails to pass tests.
(2) On NUC472/M453, HIRC-clocked PLL doesn't output 1MHz-aligned frequency. us_ticker gets slight inaccurate.
(3) On all targets, LIRC-clocked RTC is not supported due to no H/W path/RTC clock source reset to LXT on reset/RTC not trimmed for other clock rates.
4. On M263, TRNG's clock source defaults to LXT and needs special handling without LXT.
5. On M252, replace target.hxt-enable with target.hxt-present for consistency.
Refactor all Nuvoton targets to be CMake buildsystem targets. This removes
the need for checking MBED_TARGET_LABELS repeatedly and allows us to be
more flexible in the way we include MBED_TARGET source in the build.
A side effect of this is it will allow us to support custom targets
without breaking the build for 'standard' targets, as we use CMake's
standard mechanism for adding build rules to the build system, rather
than implementing our own layer of logic to exclude files not needed for
the target being built. Using this approach, if an MBED_TARGET is not
linked to using `target_link_libraries` its source files will not be
added to the build. This means custom target source can be added to the
user's application CMakeLists.txt without polluting the build system
when trying to compile for a standard MBED_TARGET.
Workaround a bug where the boot stack size configuration option is not
passed on to armlink, the Arm Compiler's linker. Prefer
MBED_CONF_TARGET_BOOT_STACK_SIZE if present, as this is what the
configuration system should provide. Fall back to MBED_BOOT_STACK_SIZE
if MBED_CONF_TARGET_BOOT_STACK_SIZE is not defined, as in the case of
buggy tools. If both MBED_CONF_TARGET_BOOT_STACK_SIZE and
MBED_BOOT_STACK_SIZE are not defined, then we fall back to a hard-coded
value provided by the linkerscript. See
https://github.com/ARMmbed/mbed-os/issues/13474 for more information.
To allow overriding of the boot stack size from the Mbed configuration
system, consistently use MBED_CONF_TARGET_BOOT_STACK_SIZE rather than
MBED_BOOT_STACK_SIZE.
Fixes#10319
This caused a conflict. As CMSIS update introduced low level init, lets use the types
from CMSIS. We could potentionally use __cmsis_start but as I saw for some targets,
the init routine is slightly different. So rather keep what we have in targets, and just
use types already defined in CMSIS.
In no MISO case, skip SPI read so that no more write/read delay contribute to SPI inter-frame delay when data is written successively.
Update targets:
- NUMAKER_PFM_NANO130
- NUMAKER_PFM_NUC472
- NUMAKER_PFM_M453
- NUMAKER_PFM_M487/NUMAKER_IOT_M487
- NU_PFM_M2351_*
- NUMAKER_IOT_M263A
- NUMAKER_M252KG
Add a "used" attribute to __vector_handlers to fix ARMC6 build with
the "-flto" flag.
(Error: L6236E: No section matches selector - no section to be FIRST/LAST. )
This attribute, attached to a function/variable, means that code must be emitted
for the function even if it appears that the function is not referenced.
On IAR, configure heap to 1KiB at a minimum and expandable, dependent on available SRAM. This requires IAR 8.x.
Support targets:
- NUMAKER_PFM_NUC472 w/ and w/o XRAM
- NUMAKER_PFM_M453
- NUMAKER_PFM_M487/NUMAKER_IOT_M487
- NUMAKER_IOT_M263A
- NUMAKER_M252KG
Reasons to remove TRNG support:
1. M252 just has 32KiB SRAM and cannot afford mbedtls application.
2. Implementing TRNG HAL with PRNG H/W has security concern.
Without free-up of peripheral pins, peripheral pins of the same peripheral may
share by multiple ports after port iteration, and this peripheral may fail with
pin interference.
In Nuvoton, only new-design chips support GPIO input pull-high/pull-low modes.
Targets not supporting this feature are listed below:
- NUMAKER_PFM_NANO130
- NUMAKER_PFM_NUC472
- NUMAKER_PFM_M453
Fix logic error on replying NACK at the end of transfer.
This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-i2c/
i2c - test single byte read i2c API.
Better IP initialization sequence:
1. Configure IP pins
2. Select IP clock source and then enable it
3. Reset the IP (SYS_ResetModule)
NOTE1: IP reset takes effect regardless of IP clock. So it doesn't matter if
IP clock enable is before IP reset.
NOTE2: Non-configured pins may disturb IP's state, so IP pinout first and then
IP reset.
NOTE3: IP reset at the end of IP initialization sequence can cover unexpected
situation.
Chun-Chieh Li
George Psimenos
cyliangtw
Martin Kojtal
Hugues Kamba
pea-pod
Jaeden Amero
talorion
Przemyslaw Stekiel
Maciej Bocianski