3 Commits (feature-nrf52-low-power-ble)

Author	SHA1	Message	Date
pea-pod	e1c754b179	Add SPI bitwidths to ST targets where supported	2021-01-11 07:53:07 -06:00
jeromecoutant	81f919b6c2	STM32L4 : license header alignment	2020-10-20 08:51:36 +02:00
Laurent MEUNIER	20bd774a6c	STM32 SPI specific mode for higher performance ... This commit implements a SPI mode which will offer better performance thanks to usage of Lower Layer API which use fewer registers access, at the cost of lower robustness (no error management).	2017-06-16 10:23:48 +02:00