Commit Graph

14 Commits (feature-cpuid)

Author SHA1 Message Date
Vladimir Umek 0ff62f6b9e RTX5: fixed __get_PSP function for Cortex-A on IAR (#288) 2017-12-21 14:09:25 +09:00
Robert Rostohar 56602562ad Core(A): Updated __FPU_Enable function (VFP register count detection) 2017-12-21 14:09:25 +09:00
Robert Rostohar 461c215636 RTX5: Cortex-A exception handlers updated (VFP register count detection) 2017-12-21 14:09:24 +09:00
Christopher Haster 7e45aee8a5 Fixed mutex assert in armcc fopen and related memory leak
armcc fopen allocated a mutex using the retargeted system-level
_mutex_initialize function. Interestingly, malloc also uses this
same _mutex_initialization function, which prevents a full solution
relying on malloc. The solution previously implemented involved using
the rtx mutex pool for the first 8 mutexes, then falling back on
malloc.

The previous implementation relied on osMutexNew returning an error
on out-of-memory. An unrelated change causes osMutexNew to instead
assert (except for release mode). This meant if you exceed 8 system-
level mutexes in armcc you will hit an assert. Since the filesystem
code can call fopen an unlimited number of times, this is a problem.

Solution is to keep track of which static mutexes we've allocated, so
we know before calling osMutexNew if we need to call malloc.

Also _mutex_free never deallocated the malloced mutexes, which would
cause fopen to leak memory.
2017-11-22 16:53:19 -06:00
Jaeden Amero 75ad20b65f RTX5: uVisor: Switch threads very carefully
uVisor doesn't set the PSP of the target thread. The RTOS sets the PSP
of the target thread from the target thread's TCB. However, when
interrupts of higher priority than PendSV happen between the call to
uVisor to switch boxes, and the RTOS setting PSP, the uVisor vIRQ
interrupt handler will attempt to use an invalid PSP (the PSP from
before the box and thread switch). This leads to a crash. Make box and
thread switching atomic by disabling interrupts immediately before the
box switching until immediately after the new PSP is set.
2017-11-01 09:25:43 +00:00
Jaeden Amero 474f6c63ba RTX5: uVisor: Use OsEventObserver 2017-11-01 09:25:43 +00:00
Jaeden Amero 12a47f0031 RTX5: uVisor: Extend thread control block with context
OsEventObserver objects expect a context to be maintained per thread on
their behalf. Add this context to the thread control block and extend
the thread creation functions with the ability to supply a context.
2017-11-01 09:25:43 +00:00
Jaeden Amero f363ccbb59 RTX5: uVisor: Add OsEventObserver
Add the OsEventObserver mechanism. A client interested in receiving
notifications on certain OS events can register to receive notifications
with osRegisterForOsEvents. This is useful for clients like the secure
memory allocator, which observes thread switching events in order to
swap in and out different memory allocator objects.
2017-11-01 09:25:42 +00:00
Jaeden Amero 372b7b8b47 RTX5: uVisor: Defer to uVisor for SVCall priority
Only set the SVCall priority if uVisor is not present. If uVisor is
present, keep using whatever priorities it has already set up.
2017-11-01 09:25:42 +00:00
Bartek Szatkowski b8aa068def CMSIS/RTX: Rename asm files to upper case .S 2017-11-01 09:25:42 +00:00
Bartek Szatkowski 4523b5d266 CMSIS/RTX: Allow overwriting _mutex_initialize symbol for ARMC 2017-11-01 09:25:42 +00:00
Bartek Szatkowski 1b131edd69 CMSIS/RTX: Patch RTX so irq_cm4f.s files work with no FPU targets 2017-11-01 09:25:42 +00:00
Bartek Szatkowski 5d6abd6572 CMSIS/RTX: Patch RTX includes to match mbed OS scheme 2017-11-01 09:25:42 +00:00
Bartek Szatkowski a03591d6e3 CMSIS/RTX: Update CMSIS and RTX to 22b68c
This includes Cortex A support and directory reshuffle.
2017-11-01 09:25:42 +00:00