In most cases, we can control degraded QSPI H/W to standard through BSP SPI driver directly as if it is just SPI H/W.
However, BSP SPI driver distinguishes among SPI H/W instances in below functions:
- SPI_Open
- SPI_Close
- SPI_SetBusClock
- SPI_GetBusClock
In these cases, we must change to QSPI version instead for QSPI H/W.
Change target:
- NUMAKER_PFM_M487
- NUMAKER_IOT_M487
- NU_PFM_M2351*
In no MISO case, skip SPI read so that no more write/read delay contribute to SPI inter-frame delay when data is written successively.
Update targets:
- NUMAKER_PFM_NANO130
- NUMAKER_PFM_NUC472
- NUMAKER_PFM_M453
- NUMAKER_PFM_M487/NUMAKER_IOT_M487
- NU_PFM_M2351_*
- NUMAKER_IOT_M263A
- NUMAKER_M252KG
Align with mainline BSP and fix relevant bugs:
1. Align with SPI module naming
(1) Remove SPI5
(2) Degrade QSPI0 to SPI4 so that it can use for standard SPI
2. Fix some code lacking GPIO H
3. Implement __PC(...) by following BSP instead of with MBED_CALLER_ADDR()
4. Add SCU_IRQHandler(). Change printf(...) with interrupt-safe error(...)
5. Other minor alignment change
Without free-up of peripheral pins, peripheral pins of the same peripheral may
share by multiple ports after port iteration, and this peripheral may fail with
pin interference.
Better IP initialization sequence:
1. Configure IP pins
2. Select IP clock source and then enable it
3. Reset the IP (SYS_ResetModule)
NOTE1: IP reset takes effect regardless of IP clock. So it doesn't matter if
IP clock enable is before IP reset.
NOTE2: Non-configured pins may disturb IP's state, so IP pinout first and then
IP reset.
NOTE3: IP reset at the end of IP initialization sequence can cover unexpected
situation.
Chun-Chieh Li
Russ Butler