Previously mbed CLI1 parses index.json to get the sector information for
a target which has "bootloader_supported" with "true" in targets
configuration in targets.json as going further with CLI2 like to get
sectors info from target.json as part of targets configuration, so
this PR changes copy sectors info into targets JSON and retain the
existing sectors info in index.json until CLI1 deprecate
Previously mbed CLI1 parses index.json to get the memory information as
going further with CLI2 like to get mem info from target.json as part of
targets configuration, so this PR changes copy all memory regions into
targets JSON and retain the existing mem info in index.json until CLI1 deprecate
QSPIF was disabled on CYW9P62S1_43012EVB_01 because its S25FS512S
flash chip has multiple configurations but our SFDP parser did not
support this scenario. Now having added support for this, we can
enable QSPIF (the component label for QSPIFBlockDevice) and QSPI
(the label for Quad-SPI communication).
Change MCUboot image versioning to meet requirements below:
1. Major.Minor.Revision must be non-decremental when used to derive security counter (-s 'auto').
2. Make Major.Minor.Revision+Build incremental to identify the firmware itself through psa_fwu_query().
3. Get around MCUboot failure with TF-M underestimated MAX_BOOT_RECORD_SZ
Import mcu partition header (renamed to partition_M2354_im.h) for resolving peripheral base with security.
Though Mbed is non-secure only and needn't secure peripheral base, some BSP driver code still rely on it.
`HAL_SPI_Receive_IT` HAL function causes dummy reads in 3-wire mode,
that causes data corruption in RX FIFO/register. It isn't possible
to fix it without signification refactoring, but we may prevent data
corruption with the following fixes:
- RX buffer/register cleanup after asynchronous transfer in 3-wire mode
- Explicit RX buffer/register cleanup after SPI initialization
(for cases if we re-create SPI object).
All STM32 families except STM32H7 has the following 3-wire SPI peculiarity in master receive mode:
SPI continuously generates clock signal till it's disabled by a software. It causes that a software
must disable SPI in time. Otherwise, "dummy" reads will be generated.
Current STM32 synchronous SPI 3-wire implementation relies on HAL library functions HAL_SPI_Receive/HAL_SPI_Transmit.
It performs some SPI state checks to detect errors, but unfortunately it isn't fast enough to disable SPI in time.
Additionally, a multithreading environment or interrupt events may cause extra delays.
This commit contains the custom transmit/receive function for SPI 3-wire mode. It uses critical sections to
prevents accidental interrupt event delays, disables SPI after each frame receiving and disables SPI during
frame generation. It adds some delay between SPI frames (~700 ns), but gives reliable 3-wire SPI communications.
- move a code that waits readable SPI state from `spi_master_write`
function to inline functions `msp_writable` and `msp_wait_writable`
- move a code that waits writeable SPI state from `spi_master_write`
function to inline functions `msp_readable` and `msp_wait_readable`
- move a code that writes data to SPI from `spi_master_write`
function to inline function `msp_write_data`
- move a code that reads data from SPI from `spi_master_write`
function to inline function `msp_read_data`
This commit enables the Overriding of HAL callbacks and IRQHandler
in stm32xx_emac.cpp. Hence the user can have their own
implementations of callbacks and IRQHandler functions.
Signed-off-by: Kather Rafi Ibrahim <katherrafi.i@hcl.com>
As per STM32H7-series reference manuals:
"Up to 64 filter elements can be configured for 29-bit extended IDs."
This commit fixes a bug which prevented receiving CAN-messages
with extended IDs.
Rajkumar Kanagaraj
Jaeden Amero
Lingkai Dong
Jerome Coutant
Martin Kojtal
Charles
Chun-Chieh Li
Konstantin Kochin
Lukas Karel
Kather Rafi Ibrahim
cyliangtw
Leon
Samu Ampio
Dustin Crossman