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STM32H7 ST CUBE V1.5.0 update

pull/11583/head
jeromecoutant 2019-09-27 10:41:43 +02:00
parent ba7b4799f9
commit fff88617b7
76 changed files with 6479 additions and 4179 deletions
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200
targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/stm32h743xx.h
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@ -298,6 +298,7 @@ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode A
} ADC_Common_TypeDef;
/**
* @brief VREFBUF
*/
@ -734,7 +735,7 @@ typedef struct
uint32_t RESERVED15[14];
__IO uint32_t MMCTSCGPR;
__IO uint32_t MMCTMCGPR;
int32_t RESERVED16[5];
uint32_t RESERVED16[5];
__IO uint32_t MMCTPCGR;
uint32_t RESERVED17[10];
__IO uint32_t MMCRCRCEPR;
@ -2033,7 +2034,6 @@ typedef struct
#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL)
#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL)
#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL)
#define ART_BASE (D2_AHB1PERIPH_BASE + 0x4400UL)
#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL)
#define ETH_MAC_BASE (ETH_BASE)
@ -2382,7 +2382,6 @@ typedef struct
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
#define SDMMC ((SDMMC_TypeDef *) SDMMC_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
@ -2392,11 +2391,11 @@ typedef struct
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
#define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE)
#define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE)
#define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE)
#define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE)
#define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE)
#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
@ -3890,6 +3889,7 @@ typedef struct
#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */
/******************************************************************************/
/* */
/* VREFBUF */
@ -10513,7 +10513,7 @@ typedef struct
/******************* Bits definition for FLASH_ACR register **********************/
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
#define FLASH_ACR_LATENCY_2WS (0x00000002UL)
@ -10532,318 +10532,318 @@ typedef struct
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
/******************* Bits definition for FLASH_CR register ***********************/
#define FLASH_CR_LOCK_Pos (0U)
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */
#define FLASH_CR_PG_Pos (1U)
#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */
#define FLASH_CR_PG FLASH_CR_PG_Msk
#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Internal buffer control bit */
#define FLASH_CR_SER_Pos (2U)
#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */
#define FLASH_CR_SER FLASH_CR_SER_Msk
#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */
#define FLASH_CR_BER_Pos (3U)
#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */
#define FLASH_CR_BER FLASH_CR_BER_Msk
#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */
#define FLASH_CR_PSIZE_Pos (4U)
#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000030 */
#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk /*!< Program size */
#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000010 */
#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000020 */
#define FLASH_CR_FW_Pos (6U)
#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000040 */
#define FLASH_CR_FW FLASH_CR_FW_Msk
#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */
#define FLASH_CR_START_Pos (7U)
#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000080 */
#define FLASH_CR_START FLASH_CR_START_Msk
#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */
#define FLASH_CR_SNB_Pos (8U)
#define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos) /*!< 0x00000700 */
#define FLASH_CR_SNB FLASH_CR_SNB_Msk
#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */
#define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */
#define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */
#define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */
#define FLASH_CR_CRC_EN_Pos (15U)
#define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos) /*!< 0x00008000 */
#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk
#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk /*!< CRC control bit */
#define FLASH_CR_EOPIE_Pos (16U)
#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */
#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-program interrupt control bit */
#define FLASH_CR_WRPERRIE_Pos (17U)
#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */
#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk
#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */
#define FLASH_CR_PGSERRIE_Pos (18U)
#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */
#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk
#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */
#define FLASH_CR_STRBERRIE_Pos (19U)
#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */
#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk
#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */
#define FLASH_CR_INCERRIE_Pos (21U)
#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00200000 */
#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk
#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */
#define FLASH_CR_OPERRIE_Pos (22U)
#define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos) /*!< 0x00400000 */
#define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk
#define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk /*!< Write/erase error interrupt enable bit */
#define FLASH_CR_RDPERRIE_Pos (23U)
#define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos) /*!< 0x00800000 */
#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk
#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk /*!< Read protection error interrupt enable bit */
#define FLASH_CR_RDSERRIE_Pos (24U)
#define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos) /*!< 0x01000000 */
#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk
#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk /*!< Secure error interrupt enable bit */
#define FLASH_CR_SNECCERRIE_Pos (25U)
#define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */
#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk
#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk /*!< ECC single correction error interrupt enable bit */
#define FLASH_CR_DBECCERRIE_Pos (26U)
#define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */
#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk
#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk /*!< ECC double detection error interrupt enable bit */
#define FLASH_CR_CRCENDIE_Pos (27U)
#define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos) /*!< 0x08000000 */
#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk
#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk /*!< CRC end of calculation interrupt enable bit */
#define FLASH_CR_CRCRDERRIE_Pos (28U)
#define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */
#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk
#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk /*!< CRC read error interrupt enable bit */
/******************* Bits definition for FLASH_SR register ***********************/
#define FLASH_SR_BSY_Pos (0U)
#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
#define FLASH_SR_BSY FLASH_SR_BSY_Msk
#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */
#define FLASH_SR_WBNE_Pos (1U)
#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */
#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk
#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */
#define FLASH_SR_QW_Pos (2U)
#define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos) /*!< 0x00000004 */
#define FLASH_SR_QW FLASH_SR_QW_Msk
#define FLASH_SR_QW FLASH_SR_QW_Msk /*!< Wait queue flag */
#define FLASH_SR_CRC_BUSY_Pos (3U)
#define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos) /*!< 0x00000008 */
#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk
#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk /*!< CRC busy flag */
#define FLASH_SR_EOP_Pos (16U)
#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */
#define FLASH_SR_EOP FLASH_SR_EOP_Msk
#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */
#define FLASH_SR_WRPERR_Pos (17U)
#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */
#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */
#define FLASH_SR_PGSERR_Pos (18U)
#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */
#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */
#define FLASH_SR_STRBERR_Pos (19U)
#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */
#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk
#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */
#define FLASH_SR_INCERR_Pos (21U)
#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00200000 */
#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk
#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */
#define FLASH_SR_OPERR_Pos (22U)
#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00400000 */
#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Write/erase error flag */
#define FLASH_SR_RDPERR_Pos (23U)
#define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos) /*!< 0x00800000 */
#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk
#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk /*!< Read protection error flag */
#define FLASH_SR_RDSERR_Pos (24U)
#define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos) /*!< 0x01000000 */
#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk
#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk /*!< Secure error flag */
#define FLASH_SR_SNECCERR_Pos (25U)
#define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos) /*!< 0x02000000 */
#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk
#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk /*!< Single correction error flag */
#define FLASH_SR_DBECCERR_Pos (26U)
#define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos) /*!< 0x04000000 */
#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk
#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk /*!< ECC double detection error flag */
#define FLASH_SR_CRCEND_Pos (27U)
#define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos) /*!< 0x08000000 */
#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk
#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk /*!< CRC end of calculation flag */
#define FLASH_SR_CRCRDERR_Pos (28U)
#define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos) /*!< 0x10000000 */
#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk
#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk /*!< CRC read error flag */
/******************* Bits definition for FLASH_CCR register *******************/
#define FLASH_CCR_CLR_EOP_Pos (16U)
#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */
#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk
#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */
#define FLASH_CCR_CLR_WRPERR_Pos (17U)
#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */
#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk
#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */
#define FLASH_CCR_CLR_PGSERR_Pos (18U)
#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */
#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk
#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */
#define FLASH_CCR_CLR_STRBERR_Pos (19U)
#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */
#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk
#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */
#define FLASH_CCR_CLR_INCERR_Pos (21U)
#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */
#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk
#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */
#define FLASH_CCR_CLR_OPERR_Pos (22U)
#define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */
#define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk
#define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk /*!< OPERR flag clear bit */
#define FLASH_CCR_CLR_RDPERR_Pos (23U)
#define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */
#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk
#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk /*!< RDPERR flag clear bit */
#define FLASH_CCR_CLR_RDSERR_Pos (24U)
#define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */
#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk
#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk /*!< RDSERR flag clear bit */
#define FLASH_CCR_CLR_SNECCERR_Pos (25U)
#define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */
#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk
#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk /*!< SNECCERR flag clear bit */
#define FLASH_CCR_CLR_DBECCERR_Pos (26U)
#define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */
#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk
#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk /*!< DBECCERR flag clear bit */
#define FLASH_CCR_CLR_CRCEND_Pos (27U)
#define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */
#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk
#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk /*!< CRCEND flag clear bit */
#define FLASH_CCR_CLR_CRCRDERR_Pos (28U)
#define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */
#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk
#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk /*!< CRCRDERR flag clear bit */
/******************* Bits definition for FLASH_OPTCR register *******************/
#define FLASH_OPTCR_OPTLOCK_Pos (0U)
#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */
#define FLASH_OPTCR_OPTSTART_Pos (1U)
#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */
#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk
#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */
#define FLASH_OPTCR_MER_Pos (4U)
#define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos) /*!< 0x00000010 */
#define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk
#define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk /*!< Mass erase request */
#define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)
#define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk
#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */
#define FLASH_OPTCR_SWAP_BANK_Pos (31U)
#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk
#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */
/******************* Bits definition for FLASH_OPTSR register ***************/
#define FLASH_OPTSR_OPT_BUSY_Pos (0U)
#define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */
#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk
#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk /*!< Option byte change ongoing flag */
#define FLASH_OPTSR_BOR_LEV_Pos (2U)
#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */
#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk
#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option status bit */
#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */
#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */
#define FLASH_OPTSR_IWDG1_SW_Pos (4U)
#define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */
#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk
#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk /*!< IWDG1 control mode option status bit */
#define FLASH_OPTSR_NRST_STOP_D1_Pos (6U)
#define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */
#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk
#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk /*!< D1 domain DStop entry reset option status bit */
#define FLASH_OPTSR_NRST_STBY_D1_Pos (7U)
#define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */
#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk
#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk /*!< D1 domain DStandby entry reset option status bit */
#define FLASH_OPTSR_RDP_Pos (8U)
#define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos) /*!< 0x0000FF00 */
#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk
#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk /*!< Readout protection level option status byte */
#define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U)
#define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */
#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk
#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk /*!< IWDG Stop mode freeze option status bit */
#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U)
#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */
#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk
#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk /*!< IWDG Standby mode freeze option status bit */
#define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U)
#define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */
#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk
#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk /*!< ST RAM size option status */
#define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */
#define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */
#define FLASH_OPTSR_SECURITY_Pos (21U)
#define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */
#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk
#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk /*!< Security enable option status bit */
#define FLASH_OPTSR_IO_HSLV_Pos (29U)
#define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */
#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk
#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk /*!< I/O high-speed at low-voltage status bit */
#define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)
#define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk
#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk /*!< Option byte change error flag */
#define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U)
#define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk
#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk /*!< Bank swapping option status bit */
/******************* Bits definition for FLASH_OPTCCR register *******************/
#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)
#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk
#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk /*!< OPTCHANGEERR reset bit */
/******************* Bits definition for FLASH_PRAR register *********************/
#define FLASH_PRAR_PROT_AREA_START_Pos (0U)
#define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */
#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk
#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk /*!< PCROP area start status bits */
#define FLASH_PRAR_PROT_AREA_END_Pos (16U)
#define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */
#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk
#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk /*!< PCROP area end status bits */
#define FLASH_PRAR_DMEP_Pos (31U)
#define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos) /*!< 0x80000000 */
#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk
#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk /*!< PCROP protected erase enable option status bit */
/******************* Bits definition for FLASH_SCAR register *********************/
#define FLASH_SCAR_SEC_AREA_START_Pos (0U)
#define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */
#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk
#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk /*!< Secure-only area start status bits */
#define FLASH_SCAR_SEC_AREA_END_Pos (16U)
#define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */
#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk
#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk /*!< Secure-only area end status bits */
#define FLASH_SCAR_DMES_Pos (31U)
#define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos) /*!< 0x80000000 */
#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk
#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk /*!< Secure access protected erase enable option status bit */
/******************* Bits definition for FLASH_WPSN register *********************/
#define FLASH_WPSN_WRPSN_Pos (0U)
#define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos) /*!< 0x000000FF */
#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk
#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk /*!< Sector write protection option status byte */
/******************* Bits definition for FLASH_BOOT_CUR register ****************/
#define FLASH_BOOT_ADD0_Pos (0U)
#define FLASH_BOOT_ADD0_Msk (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */
#define FLASH_BOOT_ADD0 FLASH_BOOT_ADD0_Msk
#define FLASH_BOOT_ADD0 FLASH_BOOT_ADD0_Msk /*!< Arm Cortex-M7 boot address 0 */
#define FLASH_BOOT_ADD1_Pos (16U)
#define FLASH_BOOT_ADD1_Msk (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */
#define FLASH_BOOT_ADD1 FLASH_BOOT_ADD1_Msk
#define FLASH_BOOT_ADD1 FLASH_BOOT_ADD1_Msk /*!< Arm Cortex-M7 boot address 1 */
/******************* Bits definition for FLASH_CRCCR register ********************/
#define FLASH_CRCCR_CRC_SECT_Pos (0U)
#define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */
#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk
#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk /*!< CRC sector number */
#define FLASH_CRCCR_CRC_BY_SECT_Pos (8U)
#define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */
#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk
#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk /*!< CRC sector mode select bit */
#define FLASH_CRCCR_ADD_SECT_Pos (9U)
#define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */
#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk
#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk /*!< CRC sector select bit */
#define FLASH_CRCCR_CLEAN_SECT_Pos (10U)
#define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */
#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk
#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk /*!< CRC sector list clear bit */
#define FLASH_CRCCR_START_CRC_Pos (16U)
#define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */
#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk
#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk /*!< CRC start bit */
#define FLASH_CRCCR_CLEAN_CRC_Pos (17U)
#define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */
#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk
#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk /*!< CRC clear bit */
#define FLASH_CRCCR_CRC_BURST_Pos (20U)
#define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */
#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk
#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk /*!< CRC burst size */
#define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */
#define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */
#define FLASH_CRCCR_ALL_BANK_Pos (22U)
#define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */
#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk
#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk /*!< CRC select bit */
/******************* Bits definition for FLASH_CRCSADD register ****************/
#define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U)
#define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */
#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk
#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk /*!< CRC start address */
/******************* Bits definition for FLASH_CRCEADD register ****************/
#define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U)
#define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */
#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk
#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk /*!< CRC end address */
/******************* Bits definition for FLASH_CRCDATA register ***************/
#define FLASH_CRCDATA_CRC_DATA_Pos (0U)
#define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */
#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk
#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk /*!< CRC result */
/******************* Bits definition for FLASH_ECC_FA register *******************/
#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U)
#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */
#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk
#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk /*!< ECC error address */
/******************************************************************************/
/* */
@ -19091,6 +19091,8 @@ typedef struct
/* */
/******************************************************************************/
#define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature */
#define TIM17_TI1_SPDIF_FS_SUPPORT /*!< TIM17 Trigger input 1 to SPDIF FS connection feature */
/******************* Bit definition for TIM_CR1 register ********************/
#define TIM_CR1_CEN_Pos (0U)
#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */

236
targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/device/stm32h747xx.h
View File

@ -321,6 +321,15 @@ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode A
} ADC_Common_TypeDef;
/**
* @brief ART
*/
typedef struct
{
__IO uint32_t CTR; /*!< ART accelerator - control register */
}ART_TypeDef;
/**
* @brief VREFBUF
*/
@ -839,7 +848,7 @@ typedef struct
uint32_t RESERVED15[14];
__IO uint32_t MMCTSCGPR;
__IO uint32_t MMCTMCGPR;
int32_t RESERVED16[5];
uint32_t RESERVED16[5];
__IO uint32_t MMCTPCGR;
uint32_t RESERVED17[10];
__IO uint32_t MMCRCRCEPR;
@ -2537,7 +2546,6 @@ typedef struct
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
#define SDMMC ((SDMMC_TypeDef *) SDMMC_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
@ -2547,11 +2555,11 @@ typedef struct
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
#define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE)
#define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE)
#define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE)
#define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE)
#define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE)
#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
@ -2584,6 +2592,8 @@ typedef struct
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)
#define RCC_C2 ((RCC_Core_TypeDef *) RCC_C2_BASE)
#define ART ((ART_TypeDef *) ART_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
@ -4052,6 +4062,20 @@ typedef struct
#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */
/******************************************************************************/
/* */
/* ART accelerator */
/* */
/******************************************************************************/
/******************* Bit definition for ART_CTR register ********************/
#define ART_CTR_EN_Pos (0U)
#define ART_CTR_EN_Msk (0x1UL << ART_CTR_EN_Pos) /*!< 0x00000001 */
#define ART_CTR_EN ART_CTR_EN_Msk /*!< Cache enable*/
#define ART_CTR_PCACHEADDR_Pos (8U)
#define ART_CTR_PCACHEADDR_Msk (0xFFFUL << ART_CTR_PCACHEADDR_Pos) /*!< 0x000FFF00 */
#define ART_CTR_PCACHEADDR ART_CTR_PCACHEADDR_Msk /*!< Cacheable page index */
/******************************************************************************/
/* */
/* VREFBUF */
@ -13749,7 +13773,7 @@ typedef struct
/******************* Bits definition for FLASH_ACR register **********************/
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
#define FLASH_ACR_LATENCY_2WS (0x00000002UL)
@ -13768,340 +13792,340 @@ typedef struct
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
/******************* Bits definition for FLASH_CR register ***********************/
#define FLASH_CR_LOCK_Pos (0U)
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */
#define FLASH_CR_PG_Pos (1U)
#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */
#define FLASH_CR_PG FLASH_CR_PG_Msk
#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Internal buffer control bit */
#define FLASH_CR_SER_Pos (2U)
#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */
#define FLASH_CR_SER FLASH_CR_SER_Msk
#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */
#define FLASH_CR_BER_Pos (3U)
#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */
#define FLASH_CR_BER FLASH_CR_BER_Msk
#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */
#define FLASH_CR_PSIZE_Pos (4U)
#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000030 */
#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk /*!< Program size */
#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000010 */
#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000020 */
#define FLASH_CR_FW_Pos (6U)
#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000040 */
#define FLASH_CR_FW FLASH_CR_FW_Msk
#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */
#define FLASH_CR_START_Pos (7U)
#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000080 */
#define FLASH_CR_START FLASH_CR_START_Msk
#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */
#define FLASH_CR_SNB_Pos (8U)
#define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos) /*!< 0x00000700 */
#define FLASH_CR_SNB FLASH_CR_SNB_Msk
#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */
#define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */
#define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */
#define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */
#define FLASH_CR_CRC_EN_Pos (15U)
#define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos) /*!< 0x00008000 */
#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk
#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk /*!< CRC control bit */
#define FLASH_CR_EOPIE_Pos (16U)
#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */
#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-program interrupt control bit */
#define FLASH_CR_WRPERRIE_Pos (17U)
#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */
#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk
#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */
#define FLASH_CR_PGSERRIE_Pos (18U)
#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */
#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk
#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */
#define FLASH_CR_STRBERRIE_Pos (19U)
#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */
#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk
#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */
#define FLASH_CR_INCERRIE_Pos (21U)
#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00200000 */
#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk
#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */
#define FLASH_CR_OPERRIE_Pos (22U)
#define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos) /*!< 0x00400000 */
#define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk
#define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk /*!< Write/erase error interrupt enable bit */
#define FLASH_CR_RDPERRIE_Pos (23U)
#define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos) /*!< 0x00800000 */
#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk
#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk /*!< Read protection error interrupt enable bit */
#define FLASH_CR_RDSERRIE_Pos (24U)
#define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos) /*!< 0x01000000 */
#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk
#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk /*!< Secure error interrupt enable bit */
#define FLASH_CR_SNECCERRIE_Pos (25U)
#define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */
#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk
#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk /*!< ECC single correction error interrupt enable bit */
#define FLASH_CR_DBECCERRIE_Pos (26U)
#define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */
#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk
#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk /*!< ECC double detection error interrupt enable bit */
#define FLASH_CR_CRCENDIE_Pos (27U)
#define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos) /*!< 0x08000000 */
#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk
#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk /*!< CRC end of calculation interrupt enable bit */
#define FLASH_CR_CRCRDERRIE_Pos (28U)
#define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */
#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk
#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk /*!< CRC read error interrupt enable bit */
/******************* Bits definition for FLASH_SR register ***********************/
#define FLASH_SR_BSY_Pos (0U)
#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
#define FLASH_SR_BSY FLASH_SR_BSY_Msk
#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */
#define FLASH_SR_WBNE_Pos (1U)
#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */
#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk
#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */
#define FLASH_SR_QW_Pos (2U)
#define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos) /*!< 0x00000004 */
#define FLASH_SR_QW FLASH_SR_QW_Msk
#define FLASH_SR_QW FLASH_SR_QW_Msk /*!< Wait queue flag */
#define FLASH_SR_CRC_BUSY_Pos (3U)
#define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos) /*!< 0x00000008 */
#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk
#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk /*!< CRC busy flag */
#define FLASH_SR_EOP_Pos (16U)
#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */
#define FLASH_SR_EOP FLASH_SR_EOP_Msk
#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */
#define FLASH_SR_WRPERR_Pos (17U)
#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */
#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */
#define FLASH_SR_PGSERR_Pos (18U)
#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */
#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */
#define FLASH_SR_STRBERR_Pos (19U)
#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */
#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk
#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */
#define FLASH_SR_INCERR_Pos (21U)
#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00200000 */
#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk
#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */
#define FLASH_SR_OPERR_Pos (22U)
#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00400000 */
#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Write/erase error flag */
#define FLASH_SR_RDPERR_Pos (23U)
#define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos) /*!< 0x00800000 */
#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk
#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk /*!< Read protection error flag */
#define FLASH_SR_RDSERR_Pos (24U)
#define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos) /*!< 0x01000000 */
#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk
#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk /*!< Secure error flag */
#define FLASH_SR_SNECCERR_Pos (25U)
#define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos) /*!< 0x02000000 */
#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk
#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk /*!< Single correction error flag */
#define FLASH_SR_DBECCERR_Pos (26U)
#define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos) /*!< 0x04000000 */
#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk
#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk /*!< ECC double detection error flag */
#define FLASH_SR_CRCEND_Pos (27U)
#define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos) /*!< 0x08000000 */
#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk
#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk /*!< CRC end of calculation flag */
#define FLASH_SR_CRCRDERR_Pos (28U)
#define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos) /*!< 0x10000000 */
#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk
#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk /*!< CRC read error flag */
/******************* Bits definition for FLASH_CCR register *******************/
#define FLASH_CCR_CLR_EOP_Pos (16U)
#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */
#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk
#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */
#define FLASH_CCR_CLR_WRPERR_Pos (17U)
#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */
#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk
#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */
#define FLASH_CCR_CLR_PGSERR_Pos (18U)
#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */
#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk
#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */
#define FLASH_CCR_CLR_STRBERR_Pos (19U)
#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */
#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk
#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */
#define FLASH_CCR_CLR_INCERR_Pos (21U)
#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */
#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk
#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */
#define FLASH_CCR_CLR_OPERR_Pos (22U)
#define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */
#define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk
#define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk /*!< OPERR flag clear bit */
#define FLASH_CCR_CLR_RDPERR_Pos (23U)
#define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */
#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk
#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk /*!< RDPERR flag clear bit */
#define FLASH_CCR_CLR_RDSERR_Pos (24U)
#define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */
#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk
#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk /*!< RDSERR flag clear bit */
#define FLASH_CCR_CLR_SNECCERR_Pos (25U)
#define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */
#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk
#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk /*!< SNECCERR flag clear bit */
#define FLASH_CCR_CLR_DBECCERR_Pos (26U)
#define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */
#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk
#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk /*!< DBECCERR flag clear bit */
#define FLASH_CCR_CLR_CRCEND_Pos (27U)
#define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */
#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk
#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk /*!< CRCEND flag clear bit */
#define FLASH_CCR_CLR_CRCRDERR_Pos (28U)
#define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */
#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk
#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk /*!< CRCRDERR flag clear bit */
/******************* Bits definition for FLASH_OPTCR register *******************/
#define FLASH_OPTCR_OPTLOCK_Pos (0U)
#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */
#define FLASH_OPTCR_OPTSTART_Pos (1U)
#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */
#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk
#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */
#define FLASH_OPTCR_MER_Pos (4U)
#define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos) /*!< 0x00000010 */
#define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk
#define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk /*!< Mass erase request */
#define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)
#define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk
#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */
#define FLASH_OPTCR_SWAP_BANK_Pos (31U)
#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk
#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */
/******************* Bits definition for FLASH_OPTSR register ***************/
#define FLASH_OPTSR_OPT_BUSY_Pos (0U)
#define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */
#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk
#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk /*!< Option byte change ongoing flag */
#define FLASH_OPTSR_BOR_LEV_Pos (2U)
#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */
#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk
#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option status bit */
#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */
#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */
#define FLASH_OPTSR_IWDG1_SW_Pos (4U)
#define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */
#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk
#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk /*!< IWDG1 control mode option status bit */
#define FLASH_OPTSR_IWDG2_SW_Pos (5U)
#define FLASH_OPTSR_IWDG2_SW_Msk (0x1UL << FLASH_OPTSR_IWDG2_SW_Pos) /*!< 0x00000020 */
#define FLASH_OPTSR_IWDG2_SW FLASH_OPTSR_IWDG2_SW_Msk
#define FLASH_OPTSR_IWDG2_SW FLASH_OPTSR_IWDG2_SW_Msk /*!< IWDG2 control mode option status bit */
#define FLASH_OPTSR_NRST_STOP_D1_Pos (6U)
#define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */
#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk
#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk /*!< D1 domain DStop entry reset option status bit */
#define FLASH_OPTSR_NRST_STBY_D1_Pos (7U)
#define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */
#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk
#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk /*!< D1 domain DStandby entry reset option status bit */
#define FLASH_OPTSR_RDP_Pos (8U)
#define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos) /*!< 0x0000FF00 */
#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk
#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk /*!< Readout protection level option status byte */
#define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U)
#define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */
#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk
#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk /*!< IWDG Stop mode freeze option status bit */
#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U)
#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */
#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk
#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk /*!< IWDG Standby mode freeze option status bit */
#define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U)
#define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */
#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk
#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk /*!< ST RAM size option status */
#define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */
#define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */
#define FLASH_OPTSR_SECURITY_Pos (21U)
#define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */
#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk
#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk /*!< Security enable option status bit */
#define FLASH_OPTSR_BCM4_Pos (22U)
#define FLASH_OPTSR_BCM4_Msk (0x1UL << FLASH_OPTSR_BCM4_Pos) /*!< 0x00400000 */
#define FLASH_OPTSR_BCM4 FLASH_OPTSR_BCM4_Msk
#define FLASH_OPTSR_BCM4 FLASH_OPTSR_BCM4_Msk /*!< Arm Cortex-M4 boot option status bit */
#define FLASH_OPTSR_BCM7_Pos (23U)
#define FLASH_OPTSR_BCM7_Msk (0x1UL << FLASH_OPTSR_BCM7_Pos) /*!< 0x00800000 */
#define FLASH_OPTSR_BCM7 FLASH_OPTSR_BCM7_Msk
#define FLASH_OPTSR_BCM7 FLASH_OPTSR_BCM7_Msk /*!< Arm Cortex-M7 boot option status bit */
#define FLASH_OPTSR_NRST_STOP_D2_Pos (24U)
#define FLASH_OPTSR_NRST_STOP_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos) /*!< 0x01000000 */
#define FLASH_OPTSR_NRST_STOP_D2 FLASH_OPTSR_NRST_STOP_D2_Msk
#define FLASH_OPTSR_NRST_STOP_D2 FLASH_OPTSR_NRST_STOP_D2_Msk /*!< D2 domain DStop entry reset option status bit */
#define FLASH_OPTSR_NRST_STBY_D2_Pos (25U)
#define FLASH_OPTSR_NRST_STBY_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos) /*!< 0x02000000 */
#define FLASH_OPTSR_NRST_STBY_D2 FLASH_OPTSR_NRST_STBY_D2_Msk
#define FLASH_OPTSR_NRST_STBY_D2 FLASH_OPTSR_NRST_STBY_D2_Msk /*!< D2 domain DStandby entry reset option status bit */
#define FLASH_OPTSR_IO_HSLV_Pos (29U)
#define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */
#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk
#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk /*!< I/O high-speed at low-voltage status bit */
#define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)
#define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk
#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk /*!< Option byte change error flag */
#define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U)
#define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk
#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk /*!< Bank swapping option status bit */
/******************* Bits definition for FLASH_OPTCCR register *******************/
#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)
#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk
#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk /*!< OPTCHANGEERR reset bit */
/******************* Bits definition for FLASH_PRAR register *********************/
#define FLASH_PRAR_PROT_AREA_START_Pos (0U)
#define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */
#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk
#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk /*!< PCROP area start status bits */
#define FLASH_PRAR_PROT_AREA_END_Pos (16U)
#define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */
#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk
#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk /*!< PCROP area end status bits */
#define FLASH_PRAR_DMEP_Pos (31U)
#define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos) /*!< 0x80000000 */
#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk
#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk /*!< PCROP protected erase enable option status bit */
/******************* Bits definition for FLASH_SCAR register *********************/
#define FLASH_SCAR_SEC_AREA_START_Pos (0U)
#define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */
#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk
#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk /*!< Secure-only area start status bits */
#define FLASH_SCAR_SEC_AREA_END_Pos (16U)
#define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */
#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk
#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk /*!< Secure-only area end status bits */
#define FLASH_SCAR_DMES_Pos (31U)
#define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos) /*!< 0x80000000 */
#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk
#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk /*!< Secure access protected erase enable option status bit */
/******************* Bits definition for FLASH_WPSN register *********************/
#define FLASH_WPSN_WRPSN_Pos (0U)
#define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos) /*!< 0x000000FF */
#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk
#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk /*!< Sector write protection option status byte */
/******************* Bits definition for FLASH_BOOT7_CUR register ****************/
#define FLASH_BOOT7_BCM7_ADD0_Pos (0U)
#define FLASH_BOOT7_BCM7_ADD0_Msk (0xFFFFUL << FLASH_BOOT7_BCM7_ADD0_Pos) /*!< 0x0000FFFF */
#define FLASH_BOOT7_BCM7_ADD0 FLASH_BOOT7_BCM7_ADD0_Msk
#define FLASH_BOOT7_BCM7_ADD0 FLASH_BOOT7_BCM7_ADD0_Msk /*!< Arm Cortex-M7 boot address 0 */
#define FLASH_BOOT7_BCM7_ADD1_Pos (16U)
#define FLASH_BOOT7_BCM7_ADD1_Msk (0xFFFFUL << FLASH_BOOT7_BCM7_ADD1_Pos) /*!< 0xFFFF0000 */
#define FLASH_BOOT7_BCM7_ADD1 FLASH_BOOT7_BCM7_ADD1_Msk
#define FLASH_BOOT7_BCM7_ADD1 FLASH_BOOT7_BCM7_ADD1_Msk /*!< Arm Cortex-M7 boot address 1 */
/******************* Bits definition for FLASH_BOOT4 register ********************/
#define FLASH_BOOT4_BCM4_ADD0_Pos (0U)
#define FLASH_BOOT4_BCM4_ADD0_Msk (0xFFFFUL << FLASH_BOOT4_BCM4_ADD0_Pos) /*!< 0x0000FFFF */
#define FLASH_BOOT4_BCM4_ADD0 FLASH_BOOT4_BCM4_ADD0_Msk
#define FLASH_BOOT4_BCM4_ADD0 FLASH_BOOT4_BCM4_ADD0_Msk /*!< Arm Cortex-M4 boot address 0 */
#define FLASH_BOOT4_BCM4_ADD1_Pos (16U)
#define FLASH_BOOT4_BCM4_ADD1_Msk (0xFFFFUL << FLASH_BOOT4_BCM4_ADD1_Pos) /*!< 0xFFFF0000 */
#define FLASH_BOOT4_BCM4_ADD1 FLASH_BOOT4_BCM4_ADD1_Msk
#define FLASH_BOOT4_BCM4_ADD1 FLASH_BOOT4_BCM4_ADD1_Msk /*!< Arm Cortex-M4 boot address 1 */
/******************* Bits definition for FLASH_CRCCR register ********************/
#define FLASH_CRCCR_CRC_SECT_Pos (0U)
#define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */
#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk
#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk /*!< CRC sector number */
#define FLASH_CRCCR_CRC_BY_SECT_Pos (8U)
#define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */
#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk
#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk /*!< CRC sector mode select bit */
#define FLASH_CRCCR_ADD_SECT_Pos (9U)
#define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */
#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk
#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk /*!< CRC sector select bit */
#define FLASH_CRCCR_CLEAN_SECT_Pos (10U)
#define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */
#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk
#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk /*!< CRC sector list clear bit */
#define FLASH_CRCCR_START_CRC_Pos (16U)
#define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */
#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk
#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk /*!< CRC start bit */
#define FLASH_CRCCR_CLEAN_CRC_Pos (17U)
#define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */
#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk
#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk /*!< CRC clear bit */
#define FLASH_CRCCR_CRC_BURST_Pos (20U)
#define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */
#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk
#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk /*!< CRC burst size */
#define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */
#define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */
#define FLASH_CRCCR_ALL_BANK_Pos (22U)
#define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */
#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk
#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk /*!< CRC select bit */
/******************* Bits definition for FLASH_CRCSADD register ****************/
#define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U)
#define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */
#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk
#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk /*!< CRC start address */
/******************* Bits definition for FLASH_CRCEADD register ****************/
#define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U)
#define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */
#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk
#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk /*!< CRC end address */
/******************* Bits definition for FLASH_CRCDATA register ***************/
#define FLASH_CRCDATA_CRC_DATA_Pos (0U)
#define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */
#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk
#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk /*!< CRC result */
/******************* Bits definition for FLASH_ECC_FA register *******************/
#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U)
#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */
#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk
#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk /*!< ECC error address */
/******************************************************************************/
/* */
@ -22894,6 +22918,8 @@ typedef struct
/* */
/******************************************************************************/
#define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature */
#define TIM17_TI1_SPDIF_FS_SUPPORT /*!< TIM17 Trigger input 1 to SPDIF FS connection feature */
/******************* Bit definition for TIM_CR1 register ********************/
#define TIM_CR1_CEN_Pos (0U)
#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */

147
targets/TARGET_STM/TARGET_STM32H7/device/stm32_hal_legacy.h
View File

@ -7,7 +7,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@ -236,6 +236,11 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
#if defined(STM32G4)
#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH)
#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH)
#endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
@ -491,7 +496,13 @@
#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
#if defined(STM32G4)
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */
/**
* @}
*/
@ -500,7 +511,7 @@
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{
*/
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
@ -559,12 +570,12 @@
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7)
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
#if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
@ -606,6 +617,124 @@
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
#if defined(STM32G4)
#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
#endif /* STM32G4 */
#if defined(STM32H7)
#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
#endif /* STM32H7 */
/**
* @}
*/
@ -1280,7 +1409,7 @@
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
@ -2985,7 +3114,7 @@
#if defined(STM32L4)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#elif defined(STM32WB) || defined(STM32G0)
#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
@ -3113,7 +3242,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx)
#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@ -3229,7 +3358,7 @@
#define SDIO_IRQHandler SDMMC1_IRQHandler
#endif
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4)
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
@ -3476,7 +3605,7 @@
/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
* @{
*/
#if defined (STM32H7) || defined (STM32F3)
#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart

4
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx.h
View File

@ -88,10 +88,10 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.5.0
* @brief CMSIS Device version number V1.6.0
*/
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x06) /*!< [23:16] sub1 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\

53
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal.c
View File

@ -47,10 +47,10 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
* @brief STM32H7xx HAL Driver version number V1.5.0
* @brief STM32H7xx HAL Driver version number V1.6.0
*/
#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
#define __STM32H7xx_HAL_VERSION_SUB1 (0x05UL) /*!< [23:16] sub1 version */
#define __STM32H7xx_HAL_VERSION_SUB1 (0x06UL) /*!< [23:16] sub1 version */
#define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */
#define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
@ -63,9 +63,17 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
static __IO uint32_t uwTick;
static uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
static HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
/* Exported variables --------------------------------------------------------*/
/** @defgroup HAL_Exported_Variables HAL Exported Variables
* @{
*/
__IO uint32_t uwTick;
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
@ -125,6 +133,14 @@ static HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
*/
HAL_StatusTypeDef HAL_Init(void)
{
#if defined(DUAL_CORE) && defined(CORE_CM4)
/* Configure Cortex-M4 Instruction cache through ART accelerator */
__HAL_RCC_ART_CLK_ENABLE(); /* Enable the Cortex-M4 ART Clock */
__HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */
__HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */
#endif /* DUAL_CORE && CORE_CM4 */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
@ -453,6 +469,33 @@ uint32_t HAL_GetDEVID(void)
return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
}
/**
* @brief Return the first word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw0(void)
{
return(READ_REG(*((uint32_t *)UID_BASE)));
}
/**
* @brief Return the second word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw1(void)
{
return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
}
/**
* @brief Return the third word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw2(void)
{
return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
}
/**
* @brief Configure the internal voltage reference buffer voltage scale.
* @param VoltageScaling specifies the output voltage to achieve

40
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal.h
View File

@ -624,6 +624,31 @@ typedef enum
/* Exported macro ------------------------------------------------------------*/
/** @defgroup ART_Exported_Macros ART Exported Macros
* @{
*/
#if defined(DUAL_CORE)
/** @brief ART Enable Macro.
* Enable the Cortex-M4 ART cache.
*/
#define __HAL_ART_ENABLE() SET_BIT(ART->CTR, ART_CTR_EN)
/** @brief ART Disable Macro.
* Disable the Cortex-M4 ART cache.
*/
#define __HAL_ART_DISABLE() CLEAR_BIT(ART->CTR, ART_CTR_EN)
/** @brief ART Cache BaseAddress Config.
* Configure the Cortex-M4 ART cache Base Address.
*/
#define __HAL_ART_CONFIG_BASE_ADDRESS(__BASE_ADDRESS__) MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((__BASE_ADDRESS__) >> 12U) & 0x000FFF00UL))
#endif /* DUAL_CORE */
/**
* @}
*/
/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
* @{
*/
@ -874,6 +899,18 @@ typedef enum
* @}
*/
/* Exported variables --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Variables
* @{
*/
extern __IO uint32_t uwTick;
extern uint32_t uwTickPrio;
extern HAL_TickFreqTypeDef uwTickFreq;
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/* Initialization and de-initialization functions ******************************/
@ -895,6 +932,9 @@ void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
uint32_t HAL_GetUIDw0(void);
uint32_t HAL_GetUIDw1(void);
uint32_t HAL_GetUIDw2(void);
void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface);
void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState );
void HAL_SYSCFG_EnableBOOST(void);

24
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc.c
View File

@ -590,6 +590,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode) );
}
if (hadc->Init.DiscontinuousConvMode == ENABLE)
{
tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
@ -650,7 +651,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
/* - Oversampling mode (continued/resumed) */
MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
ADC_CFGR2_ROVSE |
(hadc->Init.Oversampling.Ratio << 16) |
((hadc->Init.Oversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
hadc->Init.Oversampling.RightBitShift |
hadc->Init.Oversampling.TriggeredMode |
hadc->Init.Oversampling.OversamplingStopReset);
@ -2726,6 +2727,10 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
/* Set ADC selected offset signed saturation */
LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift));
/* Set ADC selected offset right shift */
LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE);
}
else
{
@ -2765,7 +2770,9 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
{
/* Set sampling time of the selected ADC channel */
/* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), sConfig->SamplingTime);
LL_ADC_SetChannelSamplingTime(hadc->Instance,
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
sConfig->SamplingTime);
}
/* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
@ -2930,15 +2937,18 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
switch (AnalogWDGConfig->WatchdogMode)
{
case ADC_ANALOGWATCHDOG_SINGLE_REG:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR));
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
LL_ADC_GROUP_REGULAR));
break;
case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_INJECTED));
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
LL_ADC_GROUP_INJECTED));
break;
case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR_INJECTED));
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
LL_ADC_GROUP_REGULAR_INJECTED));
break;
case ADC_ANALOGWATCHDOG_ALL_REG:
@ -3631,8 +3641,10 @@ void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc)
CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
}
}
else /* STM32H7 silicon Rev.B and above */
else /* STM32H7 silicon Rev.V */
{
freq /= 2U; /* divider by 2 for Rev.V */
if (freq <= 6250000UL)
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL);

22
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc.h
View File

@ -50,7 +50,7 @@
typedef struct
{
uint32_t Ratio; /*!< Configures the oversampling ratio.
This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
This parameter can be a value between 1 and 1024 */
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
@ -656,23 +656,6 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @}
*/
/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
* @{
*/
#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_512 (LL_ADC_OVS_RATIO_512) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_1024 (LL_ADC_OVS_RATIO_1024) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift
* @{
*/
@ -1724,7 +1707,8 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
pADC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/**

71
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc_ex.c
View File

@ -65,15 +65,17 @@
ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime
once the ADC is enabled */
/* Fixed timeout value for ADC calibration. */
/* Fixed timeout value for ADC calibration. */
/* Values defined to be higher than worst cases: low clock frequency, */
/* maximum prescalers. */
/* Ex of profile low frequency : f_ADC at 4,577 Khz (minimum value */
/* according to Data sheet), calibration_time MAX = 16384 / f_ADC */
/* 16384 / 4577.63671875 = 3.58s */
/* At maximum CPU speed (400 MHz), this means */
/* 3.58 * 400 MHz = 1432000000 CPU cycles */
#define ADC_CALIBRATION_TIMEOUT (1432000000U) /*!< ADC calibration time-out value */
/* Ex of profile low frequency : f_ADC at 0.125 Mhz (minimum value */
/* according to Data sheet), calibration_time MAX = 165010 / f_ADC */
/* 165010 / 125000 = 1.32s */
/* At maximum CPU speed (480 MHz), this means */
/* 1.32 * 480 MHz = 633600000 CPU cycles */
#define ADC_CALIBRATION_TIMEOUT (633600000U) /*!< ADC calibration time-out value */
/**
* @}
@ -234,9 +236,9 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef* hadc,
if (tmp_hal_status == HAL_OK)
{
for(cnt = 0UL; cnt < 6UL; cnt++)
for(cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL; cnt--)
{
LinearCalib_Buffer[cnt]=LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> cnt);
LinearCalib_Buffer[cnt-1U]=LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT-cnt));
}
}
@ -354,14 +356,53 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc,
return HAL_ERROR;
}
for(cnt = 0UL; cnt < 6UL; cnt++)
/* Enable the ADC peripheral */
if (ADC_Enable(hadc) != HAL_OK)
{
LL_ADC_SetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> cnt, LinearCalib_Buffer[cnt]);
return HAL_ERROR;
}
else
{
for(cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL ; cnt--)
{
LL_ADC_SetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT-cnt), LinearCalib_Buffer[cnt-1U]);
}
(void)ADC_Disable(hadc);
}
return HAL_OK;
}
/**
* @brief Load the calibration factor from engi bytes
* @param hadc ADC handle
* @retval HAL state
*/
HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_FactorLoad(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t cnt;
uint32_t LinearCalib_Buffer[ADC_LINEAR_CALIB_REG_COUNT];
/* Linearity calibration is retrieved from engi bytes
read values from registers and put them to the CALFACT2 register */
/* If needed linearity calibration can be done in runtime using
LL_ADC_GetCalibrationLinearFactor() */
for (cnt = 0UL; cnt < ADC_LINEAR_CALIB_REG_COUNT; cnt++)
{
LinearCalib_Buffer[cnt] = *(uint32_t*)(ADC_LINEAR_CALIB_REG_1_ADDR + cnt);
}
if (HAL_ADCEx_LinearCalibration_SetValue(hadc,(uint32_t*)LinearCalib_Buffer) != HAL_OK)
{
tmp_hal_status = HAL_ERROR;
}
return tmp_hal_status;
}
/**
* @brief Enable ADC, start conversion of injected group.
* @note Interruptions enabled in this function: None.
@ -1980,7 +2021,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
ADC_CFGR2_OVSR |
ADC_CFGR2_OVSS,
ADC_CFGR2_JOVSE |
sConfigInjected->InjecOversampling.Ratio |
((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
sConfigInjected->InjecOversampling.RightBitShift
);
}
@ -2002,11 +2043,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
{
/* Set ADC selected offset number */
LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel, tmpOffsetShifted);
LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel,
tmpOffsetShifted);
/* Set ADC selected offset signed saturation */
LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
/* Set ADC selected offset right shift */
LL_ADC_SetDataRightShift(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetRightShift == (uint32_t)ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE);
}
else
{

8
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc_ex.h
View File

@ -47,7 +47,7 @@
typedef struct
{
uint32_t Ratio; /*!< Configures the oversampling ratio.
This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
This parameter can be a value between 1 and 1024 */
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
@ -455,6 +455,7 @@ typedef struct
* @note When multimode feature is not available, the macro always returns SET.
* @retval SET (ADC is independent) or RESET (ADC is not).
*/
#define ADC_IS_INDEPENDENT(__HANDLE__) \
( ( ( ((__HANDLE__)->Instance) == ADC3) \
)? \
@ -641,6 +642,7 @@ typedef struct
* @retval Common control register
*/
#define ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON)
/**
* @brief Report common register to ADC3
* @param __HANDLE__: ADC handle
@ -707,7 +709,6 @@ typedef struct
* @param __HANDLE__: ADC handle
* @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)
*/
#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \
( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
)? \
@ -1015,7 +1016,7 @@ typedef struct
* @param RATIO: programmed ADC oversampling ratio.
* @retval SET (RATIO is a valid value) or RESET (RATIO is invalid)
*/
#define IS_ADC_OVERSAMPLING_RATIO(RATIO) ((RATIO) < 1024UL)
#define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) >= 1UL) && ((RATIO) <= 1024UL))
/**
* @brief Verify the ADC oversampling shift.
@ -1098,6 +1099,7 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc,
HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer);
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer);
HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_FactorLoad(ADC_HandleTypeDef *hadc);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);

12
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_conf.h
View File

@ -121,15 +121,6 @@
#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
@ -144,7 +135,7 @@
#endif /* LSE_STARTUP_TIMEOUT */
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000) /*!< LSI Typical Value in Hz*/
#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
@ -169,6 +160,7 @@
#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
#define USE_RTOS 0
#define USE_SD_TRANSCEIVER 1U /*!< use uSD Transceiver */
#define USE_SPI_CRC 1U /*!< use CRC in SPI */
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */

143
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cryp.c
View File

@ -139,13 +139,15 @@
(##) Final phase: IP generates the authenticated tag (T) using the last block of data.
*** Callback registration ***
=============================================
=============================
[..]
The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
to register an interrupt callback.
[..]
Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
(+) InCpltCallback : Input FIFO transfer completed callback.
(+) OutCpltCallback : Output FIFO transfer completed callback.
@ -155,6 +157,7 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
weak function.
@ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
@ -166,6 +169,7 @@
(+) MspInitCallback : CRYP MspInit.
(+) MspDeInitCallback : CRYP MspDeInit.
[..]
By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
all callbacks are set to the corresponding weak functions :
examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
@ -175,6 +179,7 @@
if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
keep and use the user MspInit/MspDeInit functions (registered beforehand)
[..]
Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
@ -183,6 +188,7 @@
using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
or @ref HAL_CRYP_Init() function.
[..]
When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@ -331,7 +337,9 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
#if !defined (CRYP_VER_2_2)
static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
#endif /*End of not defined CRYP_VER_2_2*/
static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
@ -440,9 +448,10 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
/* Set the key size(This bit field is ‘don’t care’ in the DES or TDES modes) data type and Algorithm */
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
#if !defined (CRYP_VER_2_2)
/* Read Device ID to indicate CRYP1 IP Version */
hcryp->Version = HAL_GetREVID();
#endif /*End of not defined CRYP_VER_2_2*/
/* Reset Error Code field */
hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
@ -1149,7 +1158,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
{
uint32_t algo;
HAL_StatusTypeDef status = HAL_OK;
HAL_StatusTypeDef status;
if (hcryp->State == HAL_CRYP_STATE_READY)
{
@ -1217,6 +1226,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input
/* Enable CRYP to start DES/TDES process*/
__HAL_CRYP_ENABLE(hcryp);
status = HAL_OK;
break;
case CRYP_AES_ECB:
@ -2318,7 +2328,9 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
/* Compute the number of padding bytes in last block of payload */
npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
#if !defined (CRYP_VER_2_2)
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
/* Case of AES GCM payload encryption or AES CCM payload decryption to get right tag */
temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR;
@ -2795,7 +2807,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
/* Disable the CRYP peripheral */
__HAL_CRYP_DISABLE(hcryp);
#if !defined (CRYP_VER_2_2)
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
@ -2849,7 +2863,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
if ((hcryp->Size % 16U) != 0U)
{
#if !defined (CRYP_VER_2_2)
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
/* Compute the number of padding bytes in last block of payload */
npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
@ -2924,12 +2940,14 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
}
}
}
#if !defined (CRYP_VER_2_2)
else /* Workaround to be used */
{
/* Workaround 2 for STM32H7 below rev.B To generate correct TAG only when size of the last block of
payload is inferior to 128 bits, in case of GCM encryption or CCM decryption*/
CRYP_Workaround(hcryp, Timeout);
} /* end of NPBLB or Workaround*/
#endif /*End of not defined CRYP_VER_2_2*/
}
@ -3070,7 +3088,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
/* Disable the CRYP peripheral */
__HAL_CRYP_DISABLE(hcryp);
#if !defined (CRYP_VER_2_2)
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
@ -3103,7 +3123,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
/* Compute the number of padding bytes in last block of payload */
npblb = 16U - (uint32_t)hcryp->Size;
#if !defined (CRYP_VER_2_2)
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
/* Set Npblb in case of AES GCM payload encryption to get right tag*/
if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
@ -3222,6 +3244,15 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
#if defined (CRYP_VER_2_2)
{
/* for STM32H7 rev.B and above Write B0 packet into CRYP_DR*/
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
}
#else
if (hcryp->Version >= REV_ID_B)
{
/* for STM32H7 rev.B and above Write B0 packet into CRYP_DR*/
@ -3261,6 +3292,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
}
}
#endif
/* Get tick */
tickstart = HAL_GetTick();
@ -3301,8 +3333,9 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
/* Disable the CRYP peripheral */
__HAL_CRYP_DISABLE(hcryp);
#if !defined (CRYP_VER_2_2)
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
@ -3355,7 +3388,9 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
if ((hcryp->Size % 16U) != 0U)
{
#if !defined (CRYP_VER_2_2)
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
/* Compute the number of padding bytes in last block of payload */
npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
@ -3430,6 +3465,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
}
}
}
#if !defined (CRYP_VER_2_2)
else /* No NPBLB, Workaround to be used */
{
/* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext blocks size is multiple of
@ -3437,6 +3473,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
is selected, then the TAG message will be wrong.*/
CRYP_Workaround(hcryp, Timeout);
}
#endif /*End of not defined CRYP_VER_2_2*/
}
/* Return function status */
@ -3473,7 +3510,9 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
__HAL_CRYP_ENABLE(hcryp);
/*Write the B0 packet into CRYP_DR*/
#if !defined (CRYP_VER_2_2)
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
/* for STM32H7 rev.B and above data has not to be swapped */
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
@ -3481,6 +3520,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
}
#if !defined (CRYP_VER_2_2)
else /* data has to be swapped according to the DATATYPE */
{
if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
@ -3512,7 +3552,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
}
}
#endif /*End of not defined CRYP_VER_2_2*/
/*Wait for the CRYPEN bit to be cleared*/
count = CRYP_TIMEOUT_GCMCCMINITPHASE;
do
@ -3580,8 +3620,9 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
__HAL_CRYP_ENABLE(hcryp);
/*Write the B0 packet into CRYP_DR*/
#if !defined (CRYP_VER_2_2)
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
/* for STM32H7 rev.B and above data has not to be swapped */
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
@ -3589,6 +3630,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
}
#if !defined (CRYP_VER_2_2)
else /* data has to be swapped according to the DATATYPE */
{
if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
@ -3620,6 +3662,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
}
}
#endif /*End of not defined CRYP_VER_2_2*/
/*Wait for the CRYPEN bit to be cleared*/
count = CRYP_TIMEOUT_GCMCCMINITPHASE;
do
@ -3654,8 +3697,9 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
/* Disable the CRYP peripheral */
__HAL_CRYP_DISABLE(hcryp);
#if !defined (CRYP_VER_2_2)
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
@ -3686,7 +3730,9 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
/* Compute the number of padding bytes in last block of payload */
npblb = 16U - (uint32_t)(hcryp->Size);
#if !defined (CRYP_VER_2_2)
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
/* Set Npblb in case of AES CCM payload decryption to get right tag*/
if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
@ -3781,9 +3827,15 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
uint32_t lastwordsize;
uint32_t npblb;
uint32_t temp_cr_algodir;
uint8_t negative = 0U;
/***************************** Payload phase *******************************/
if ((hcryp->Size / 4U) < hcryp->CrypInCount)
{
negative = 1U;
}
if (hcryp->Size == 0U)
{
/* Disable interrupts */
@ -3796,7 +3848,8 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
hcryp->State = HAL_CRYP_STATE_READY;
}
else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
else if ((((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) &&
(negative == 0U))
{
if ((hcryp->Instance->IMSCR & CRYP_IMSCR_INIM)!= 0x0U)
{
@ -3876,7 +3929,9 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
/* Compute the number of padding bytes in last block of payload */
npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
#if !defined (CRYP_VER_2_2)
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
/* Set Npblb in case of AES GCM payload encryption and CCM decryption to get right tag */
temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR;
@ -4252,7 +4307,9 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
/* Disable the CRYP peripheral */
__HAL_CRYP_DISABLE(hcryp);
#if !defined (CRYP_VER_2_2)
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
@ -4300,7 +4357,7 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
}
}
#if !defined (CRYP_VER_2_2)
/**
* @brief Workaround used for GCM/CCM mode.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
@ -4341,9 +4398,8 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
/* Disable CRYP to start the final phase */
__HAL_CRYP_DISABLE(hcryp);
/*Load CRYP_IV1R register content in a temporary variable. Decrement the value
by 1 and reinsert the result in CRYP_IV1R register*/
hcryp->Instance->IV1RR = 0x5U;
/*Update CRYP_IV1R register and ALGOMODE*/
hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R)-1U);
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
/* Enable CRYP to start the final phase */
@ -4406,6 +4462,67 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
/* configured final phase */
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
if ( (hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_32B)
{
if ((npblb %4U)==1U)
{
intermediate_data[lastwordsize-1U] &= 0xFFFFFF00U;
}
if ((npblb %4U)==2U)
{
intermediate_data[lastwordsize-1U] &= 0xFFFF0000U;
}
if ((npblb %4U)==3U)
{
intermediate_data[lastwordsize-1U] &= 0xFF000000U;
}
}
else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_8B)
{
if ((npblb %4U)==1U)
{
intermediate_data[lastwordsize-1U] &= __REV(0xFFFFFF00U);
}
if ((npblb %4U)==2U)
{
intermediate_data[lastwordsize-1U] &= __REV(0xFFFF0000U);
}
if ((npblb %4U)==3U)
{
intermediate_data[lastwordsize-1U] &= __REV(0xFF000000U);
}
}
else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_16B)
{
if ((npblb %4U)==1U)
{
intermediate_data[lastwordsize-1U] &= __ROR((0xFFFFFF00U), 16);
}
if ((npblb %4U)==2U)
{
intermediate_data[lastwordsize-1U] &= __ROR((0xFFFF0000U), 16);
}
if ((npblb %4U)==3U)
{
intermediate_data[lastwordsize-1U] &= __ROR((0xFF000000U), 16);
}
}
else /*CRYP_DATATYPE_1B*/
{
if ((npblb %4U)==1U)
{
intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFFFF00U);
}
if ((npblb %4U)==2U)
{
intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFF0000U);
}
if ((npblb %4U)==3U)
{
intermediate_data[lastwordsize-1U] &= __RBIT(0xFF000000U);
}
}
for (index = 0U; index < lastwordsize ; index ++)
{
/*Write the intermediate_data in the IN FIFO */
@ -4589,7 +4706,7 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
}
#endif /*End of not defined CRYP_VER_2_2*/
/**
* @brief Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.

8
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cryp_ex.c
View File

@ -157,14 +157,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
/* Write the number of bits in header (64 bits) followed by the number of bits
in the payload */
#if !defined (CRYP_VER_2_2)
/* STM32H7 rev.B and above : data has to be inserted normally (no swapping)*/
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = (uint32_t)(headerlength);
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = (uint32_t)(inputlength);
}
#if !defined (CRYP_VER_2_2)
else/* data has to be swapped according to the DATATYPE */
{
if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
@ -200,6 +203,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
/* Nothing to do */
}
}
#endif /*End of not defined CRYP_VER_2_2*/
/* Wait for OFNE flag to be raised */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
@ -312,8 +316,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
ctr0[2] = hcryp->Init.B0[2];
ctr0[3] = hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
#if !defined (CRYP_VER_2_2)
/*STM32H7 rev.B and above : data has to be inserted normally (no swapping)*/
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
@ -323,6 +329,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
}
#if !defined (CRYP_VER_2_2)
else /* data has to be swapped according to the DATATYPE */
{
if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
@ -366,6 +373,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
}
}
#endif /*End of not defined CRYP_VER_2_2*/
/* Wait for OFNE flag to be raised */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))

3
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash.c
View File

@ -462,6 +462,7 @@ void HAL_FLASH_IRQHandler(void)
/* Check FLASH Bank1 operation error flags */
errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \
FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1);
if(errorflag != 0U)
{
/* Save the error code */
@ -556,7 +557,7 @@ void HAL_FLASH_IRQHandler(void)
* Mass Erase: Bank number which has been requested to erase
* Sectors Erase: Sector which has been erased
* (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
* Program Address which was selected for data program
* Program: Address which was selected for data program
* @retval None
*/
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)

2
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash.h
View File

@ -134,7 +134,7 @@ typedef struct
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
#define FLASH_TYPEPROGRAM_FLASHWORD 0x03U /*!< Program a flash word (256-bit) at a specified address */
#define FLASH_TYPEPROGRAM_FLASHWORD 0x01U /*!< Program a flash word (256-bit) at a specified address */
/**
* @}
*/

1
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash_ex.c
View File

@ -462,6 +462,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
}
#endif /*DUAL_CORE*/
/*Bank1 secure area configuration*/
if((pOBInit->OptionType & OPTIONBYTE_SECURE_AREA) == OPTIONBYTE_SECURE_AREA)
{

11
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash_ex.h
View File

@ -715,16 +715,7 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
((LATENCY) == FLASH_LATENCY_14) || \
((LATENCY) == FLASH_LATENCY_15))
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \
(((ADDRESS) >= FLASH_OTP_BANK1_BASE) && ((ADDRESS) <= FLASH_OTP_BANK1_END)) || \
(((ADDRESS) >= FLASH_OTP_BANK2_BASE) && ((ADDRESS) <= FLASH_OTP_BANK2_END)))
#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))
#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL)
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))

9
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_gpio.c
View File

@ -330,10 +330,10 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/*------------------------- EXTI Mode Configuration --------------------*/
/* Clear the External Interrupt or Event for the current IO */
tmp = SYSCFG->EXTICR[position >> 2U];
tmp &= (0x0FUL << (8U * (position & 0x03U)));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U))))
tmp &= (0x0FUL << (4U * (position & 0x03U)));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
{
tmp = 0x0FUL << (8U * (position & 0x03U));
tmp = 0x0FUL << (4U * (position & 0x03U));
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
/* Clear EXTI line configuration for Current CPU */
@ -487,9 +487,10 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
GPIOx->LCKR = GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Read LCKK bit*/
/* Read LCKK register. This read is mandatory to complete key lock sequence*/
tmp = GPIOx->LCKR;
/* read again in order to confirm lock is active */
if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U)
{
return HAL_OK;

24
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hcd.c
View File

@ -373,14 +373,13 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
uint16_t length,
uint8_t do_ping)
{
UNUSED(do_ping);
hhcd->hc[ch_num].ep_is_in = direction;
hhcd->hc[ch_num].ep_type = ep_type;
if (token == 0U)
{
hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
hhcd->hc[ch_num].do_ping = do_ping;
}
else
{
@ -534,11 +533,10 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
/* Handle Host Disconnect Interrupts */
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
{
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
/* Cleanup HPRT */
USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U)
{
/* Handle Host Port Disconnect Interrupt */
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->DisconnectCallback(hhcd);
@ -547,7 +545,7 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
}
}
/* Handle Host Port Interrupts */
@ -1009,6 +1007,7 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
__HAL_HCD_ENABLE(hhcd);
(void)USB_DriveVbus(hhcd->Instance, 1U);
__HAL_UNLOCK(hhcd);
return HAL_OK;
}
@ -1023,6 +1022,7 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
__HAL_LOCK(hhcd);
(void)USB_StopHost(hhcd->Instance);
__HAL_UNLOCK(hhcd);
return HAL_OK;
}
@ -1555,8 +1555,6 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
{
if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
{
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->ConnectCallback(hhcd);
#else
@ -1593,10 +1591,8 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
}
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->PortEnabledCallback(hhcd);
hhcd->ConnectCallback(hhcd);
#else
HAL_HCD_PortEnabled_Callback(hhcd);
HAL_HCD_Connect_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
@ -1607,12 +1603,6 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
#else
HAL_HCD_PortDisabled_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
/* Cleanup HPRT */
USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
}
}

25
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hrtim.c
View File

@ -274,6 +274,7 @@
Use Functions HAL_HRTIM_RegisterCallback() or HAL_HRTIM_TIMxRegisterCallback()
to register an interrupt callback.
[..]
Function HAL_HRTIM_RegisterCallback() allows to register following callbacks:
(+) Fault1Callback : Fault 1 interrupt callback function
(+) Fault2Callback : Fault 2 interrupt callback function
@ -287,6 +288,7 @@
(+) MspInitCallback : HRTIM MspInit callback function
(+) MspDeInitCallback : HRTIM MspInit callback function
[..]
Function HAL_HRTIM_TIMxRegisterCallback() allows to register following callbacks:
(+) RegistersUpdateCallback : Timer x Update interrupt callback function
(+) RepetitionEventCallback : Timer x Repetition interrupt callback function
@ -304,13 +306,16 @@
(+) Output2ResetCallback : Timer x output 2 reset interrupt callback function
(+) BurstDMATransferCallback : Timer x Burst DMA completed interrupt callback function
[..]
Both functions take as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
Use function HAL_HRTIM_UnRegisterCallback or HAL_HRTIM_TIMxUnRegisterCallback
to reset a callback to the default weak function. Both functions take as parameters
the HAL peripheral handle and the Callback ID.
[..]
By default, after the HAL_HRTIM_Init() and when the state is HAL_HRTIM_STATE_RESET
all callbacks are set to the corresponding weak functions (e.g HAL_HRTIM_Fault1Callback)
Exception done for MspInit and MspDeInit functions that are reset to the legacy
@ -319,14 +324,16 @@
not null, the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() keep and use the user
MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in HAL_HRTIM_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in HAL_HRTIM_STATE_READY or HAL_HRTIM_STATE_RESET states, thus registered
(user) MspInit/DeInit callbacks can be used during the Init/DeInit.
Then, the user first registers the MspInit/MspDeInit user callbacks
using HAL_HRTIM_RegisterCallback() before calling HAL_HRTIM_DeInit()
or @ref HAL_HRTIM_Init() function.
or HAL_HRTIM_Init() function.
[..]
When the compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all
callbacks are set to the corresponding weak functions.
@ -1198,7 +1205,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
{
uint32_t CompareUnit = (uint32_t)RESET;
HRTIM_OutputCfgTypeDef OutputCfg = {0};
HRTIM_OutputCfgTypeDef OutputCfg;
/* Check parameters */
assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
@ -4657,6 +4664,11 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
{
/* nothing to do */
}
}
else
{
/* Clear HRTIM_TIMxCR.DELCMP2 bitfield */
MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U);
}
break;
}
@ -4697,6 +4709,11 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
{
/* nothing to do */
}
}
else
{
/* Clear HRTIM_TIMxCR.DELCMP4 bitfield */
MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U);
}
break;
}
@ -6415,7 +6432,7 @@ uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef * hhrtim,
* @brief This function handles HRTIM interrupt request.
* @param hhrtim pointer to HAL HRTIM handle
* @param TimerIdx Timer index
* This parameter can be any value of @ref HRTIM_Timer_Index
* This parameter can be any value of HRTIM_Timer_Index
* @retval None
*/
void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,
@ -7452,7 +7469,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
* @}
*/
/** @addtogroup HRTIM_Private_Functions HRTIM Private Functions
/** @addtogroup HRTIM_Private_Functions
* @{
*/

142
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hrtim.h
View File

@ -973,67 +973,15 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */
#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */
#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */
/* Timer Events mapping for Timer A */
#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer B */
#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer C */
#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer D */
#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer E */
#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer F */
#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
#define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */
#define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */
#define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */
@ -1066,67 +1014,15 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
/* Timer Events mapping for Timer A */
#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer B */
#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer C */
#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer D */
#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer E */
#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer F */
#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
#define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
@ -2115,7 +2011,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
*/
/* Private macros --------------------------------------------------------*/
/** @addtogroup HRTIM_Private_Macros HRTIM Private Macros
/** @addtogroup HRTIM_Private_Macros
* @{
*/
#define IS_HRTIM_TIMERINDEX(TIMERINDEX)\

4
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hsem.c
View File

@ -233,7 +233,11 @@ void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID)
assert_param(IS_HSEM_PROCESSID(ProcessID));
/* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0 */
#if USE_MULTI_CORE_SHARED_CODE != 0U
HSEM->R[SemID] = (ProcessID | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID));
#else
HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT);
#endif
}

89
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_irda.c
View File

@ -225,7 +225,8 @@
* @param __PRESCALER__ IRDA clock prescaler value.
* @retval Division result
*/
#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))
#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)])\
+ ((__BAUD__)/2U)) / (__BAUD__))
/**
* @}
*/
@ -240,7 +241,8 @@ void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout);
static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
@ -476,7 +478,8 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
pIRDA_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@ -715,6 +718,7 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
While receiving data, transmission should be avoided as the data to be transmitted
could be corrupted.
[..]
(#) There are two modes of transfer:
(++) Blocking mode: the communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
@ -752,26 +756,26 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
(++) HAL_IRDA_ErrorCallback()
(#) Non-Blocking mode transfers could be aborted using Abort API's :
(+) HAL_IRDA_Abort()
(+) HAL_IRDA_AbortTransmit()
(+) HAL_IRDA_AbortReceive()
(+) HAL_IRDA_Abort_IT()
(+) HAL_IRDA_AbortTransmit_IT()
(+) HAL_IRDA_AbortReceive_IT()
(++) HAL_IRDA_Abort()
(++) HAL_IRDA_AbortTransmit()
(++) HAL_IRDA_AbortReceive()
(++) HAL_IRDA_Abort_IT()
(++) HAL_IRDA_AbortTransmit_IT()
(++) HAL_IRDA_AbortReceive_IT()
(#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
(+) HAL_IRDA_AbortCpltCallback()
(+) HAL_IRDA_AbortTransmitCpltCallback()
(+) HAL_IRDA_AbortReceiveCpltCallback()
(++) HAL_IRDA_AbortCpltCallback()
(++) HAL_IRDA_AbortTransmitCpltCallback()
(++) HAL_IRDA_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
If user wants to abort it, Abort services should be called by user.
(+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
@ -781,10 +785,13 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
/**
* @brief Send an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be sent.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Specify timeout value.
* @retval HAL status
*/
@ -867,10 +874,13 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
/**
* @brief Receive an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be received.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Specify timeout value.
* @retval HAL status
*/
@ -955,10 +965,13 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
/**
* @brief Send an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be sent.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@ -997,10 +1010,13 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData
/**
* @brief Receive an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be received.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@ -1046,10 +1062,13 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
/**
* @brief Send an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData pointer to data buffer.
* @param Size amount of data to be sent.
* @param pData pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@ -1121,12 +1140,15 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
/**
* @brief Receive an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @note When the IRDA parity is enabled (PCE = 1), the received data contains
* the parity bit (MSB position).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be received.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@ -2151,7 +2173,8 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
{
/* Return IRDA handle state */
uint32_t temp1, temp2;
uint32_t temp1;
uint32_t temp2;
temp1 = (uint32_t)hirda->gState;
temp2 = (uint32_t)hirda->RxState;
@ -2216,6 +2239,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
PLL2_ClocksTypeDef pll2_clocks;
PLL3_ClocksTypeDef pll3_clocks;
uint32_t pclk;
/* Check the communication parameters */
assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
@ -2244,7 +2268,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler);
/*-------------------------- USART GTPR Configuration ----------------------*/
MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, hirda->Init.Prescaler);
MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler);
/*-------------------------- USART BRR Configuration -----------------------*/
IRDA_GETCLOCKSOURCE(hirda, clocksource);
@ -2252,10 +2276,12 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
switch (clocksource)
{
case IRDA_CLOCKSOURCE_D2PCLK1:
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
pclk = HAL_RCC_GetPCLK1Freq();
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_D2PCLK2:
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
pclk = HAL_RCC_GetPCLK2Freq();
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_PLL2Q:
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
@ -2349,7 +2375,8 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
* @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)

14
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_irda.h
View File

@ -305,7 +305,7 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @}
*/
/** @defgroup IRDA_ClockPrescaler Clock Prescaler
/** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler
* @{
*/
#define IRDA_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
@ -608,7 +608,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (SET or RESET).
*/
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
* @param __HANDLE__ specifies the IRDA Handle.
@ -662,7 +663,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
&= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
/** @brief Enable UART/USART associated to IRDA Handle.
* @param __HANDLE__ specifies the IRDA Handle.
@ -709,7 +711,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @param __MODE__ IRDA communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
& (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
/** @brief Ensure that IRDA power mode is valid.
* @param __MODE__ IRDA power mode.
@ -801,7 +804,8 @@ void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
pIRDA_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */

281
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_irda_ex.h
View File

@ -33,6 +33,7 @@ extern "C" {
*/
/** @defgroup IRDAEx IRDAEx
* @brief IRDA Extended HAL module driver
* @{
*/
@ -69,6 +70,285 @@ extern "C" {
* @param __CLOCKSOURCE__ output variable.
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
*/
#if defined(UART9) && defined(USART10)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_USART1CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART1CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_USART2CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART2CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_USART3CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART3CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
case RCC_UART4CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_UART4CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_UART4CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_UART4CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_UART4CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
break; \
case RCC_UART4CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if ((__HANDLE__)->Instance == UART5) \
{ \
switch(__HAL_RCC_GET_UART5_SOURCE()) \
{ \
case RCC_UART5CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_UART5CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_UART5CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_UART5CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_UART5CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
break; \
case RCC_UART5CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
switch(__HAL_RCC_GET_USART6_SOURCE()) \
{ \
case RCC_USART6CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_USART6CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART6CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART6CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART6CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
break; \
case RCC_USART6CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART7) \
{ \
switch(__HAL_RCC_GET_UART7_SOURCE()) \
{ \
case RCC_UART7CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_UART7CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_UART7CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_UART7CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_UART7CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
break; \
case RCC_UART7CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART8) \
{ \
switch(__HAL_RCC_GET_UART8_SOURCE()) \
{ \
case RCC_UART8CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_UART8CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_UART8CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_UART8CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_UART8CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
break; \
case RCC_UART8CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART9) \
{ \
switch(__HAL_RCC_GET_UART9_SOURCE()) \
{ \
case RCC_UART9CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_UART9CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_UART9CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_UART9CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_UART9CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
break; \
case RCC_UART9CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART10) \
{ \
switch(__HAL_RCC_GET_USART10_SOURCE()) \
{ \
case RCC_USART10CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_USART10CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART10CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART10CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART10CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
break; \
case RCC_USART10CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#else
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
@ -292,6 +572,7 @@ extern "C" {
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif /* UART9 && USART10 */
/** @brief Compute the mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.

14
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_iwdg.c
View File

@ -49,19 +49,19 @@
==============================================================================
[..]
(#) Use IWDG using HAL_IWDG_Init() function to :
(+) Enable instance by writing Start keyword in IWDG_KEY register. LSI
(++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
clock is forced ON and IWDG counter starts counting down.
(+) Enable write access to configuration registers:
(++) Enable write access to configuration registers:
IWDG_PR, IWDG_RLR and IWDG_WINR.
(+) Configure the IWDG prescaler and counter reload value. This reload
(++) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
(+) Wait for status flags to be reset.
(+) Depending on window parameter:
(++) If Window Init parameter is same as Window register value,
(++) Wait for status flags to be reset.
(++) Depending on window parameter:
(+++) If Window Init parameter is same as Window register value,
nothing more is done but reload counter value in order to exit
function with exact time base.
(++) Else modify Window register. This will automatically reload
(+++) Else modify Window register. This will automatically reload
watchdog counter.
(#) Then the application program must refresh the IWDG counter at regular

504
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_lptim.c
View File

@ -92,19 +92,19 @@
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
[..]
Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback.
@ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
the Callback ID and a pointer to the user callback function.
[..]
Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the
default weak function.
@ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
[..]
These functions allow to register/unregister following callbacks:
(+) MspInitCallback : LPTIM Base Msp Init Callback.
@ -117,15 +117,18 @@
(+) DirectionUpCallback : Up-counting direction change Callback.
(+) DirectionDownCallback : Down-counting direction change Callback.
[..]
By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions:
examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback().
[..]
Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
functionalities in the Init/DeInit only when these callbacks are null
(not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
[..]
Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
@ -133,6 +136,7 @@
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
[..]
When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@ -148,7 +152,8 @@
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* ******************************************************************************
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@ -176,6 +181,7 @@
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag);
/* Exported functions --------------------------------------------------------*/
@ -350,6 +356,11 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
/* Disable the LPTIM Peripheral Clock */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
if (hlptim->MspDeInitCallback == NULL)
{
@ -458,12 +469,30 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
/* Wait for the completion of the write operation to the LPTIM_CMP register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@ -490,6 +519,11 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
@ -519,6 +553,41 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P
/* Reset WAVE bit to set PWM mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
/* Wait for the completion of the write operation to the LPTIM_CMP register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Enable Autoreload write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
@ -541,12 +610,6 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@ -573,6 +636,11 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
@ -624,12 +692,30 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
/* Wait for the completion of the write operation to the LPTIM_CMP register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
@ -656,6 +742,11 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
@ -685,6 +776,41 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3
/* Reset WAVE bit to set one pulse mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
/* Wait for the completion of the write operation to the LPTIM_CMP register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Enable Autoreload write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
@ -707,12 +833,6 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
@ -739,6 +859,11 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
@ -790,12 +915,30 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
/* Wait for the completion of the write operation to the LPTIM_CMP register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
@ -822,6 +965,11 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
@ -851,6 +999,41 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Set WAVE bit to enable the set once mode */
hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
/* Wait for the completion of the write operation to the LPTIM_CMP register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Enable Autoreload write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
@ -873,12 +1056,6 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
@ -905,6 +1082,11 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
@ -970,9 +1152,18 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@ -999,6 +1190,11 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Reset ENC bit to disable the encoder interface */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
@ -1046,6 +1242,29 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Set ENC bit to enable the encoder interface */
hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Enable "switch to down direction" interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
@ -1055,9 +1274,6 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@ -1084,6 +1300,11 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Reset ENC bit to disable the encoder interface */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
@ -1127,12 +1348,30 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
/* Load the Timeout value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
/* Wait for the completion of the write operation to the LPTIM_CMP register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@ -1159,6 +1398,11 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Reset TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
@ -1193,18 +1437,47 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Set TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
/* Load the Timeout value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
/* Wait for the completion of the write operation to the LPTIM_CMP register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Enable Compare match interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Load the Timeout value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@ -1231,6 +1504,11 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Reset TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
@ -1272,9 +1550,18 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@ -1301,6 +1588,11 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
@ -1333,6 +1625,29 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
}
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Enable Autoreload write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
@ -1342,9 +1657,6 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@ -1371,12 +1683,16 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
/* Disable Autoreload match interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
/* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
@ -1973,16 +2289,40 @@ static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
}
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
* @brief LPTimer Wait for flag set
* @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
* the configuration information for LPTIM module.
* @param flag The lptim flag
* @retval HAL status
*/
static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag)
{
HAL_StatusTypeDef result = HAL_OK;
uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
do
{
count--;
if (count == 0UL)
{
result = HAL_TIMEOUT;
}
}
while((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
return result;
}
/**
* @brief Disable LPTIM HW instance.
* @param lptim pointer to a LPTIM_HandleTypeDef structure that contains
* @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
* the configuration information for LPTIM module.
* @note The following sequence is required to solve LPTIM disable HW limitation.
* Please check Errata Sheet ES0335 for more details under "MCU may remain
* stuck in LPTIM interrupt when entering Stop mode" section.
* @retval None
*/
void LPTIM_Disable(LPTIM_HandleTypeDef *lptim)
void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
{
uint32_t tmpclksource = 0;
uint32_t tmpIER;
@ -1995,7 +2335,7 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *lptim)
/*********** Save LPTIM Config ***********/
/* Save LPTIM source clock */
switch ((uint32_t)lptim->Instance)
switch ((uint32_t)hlptim->Instance)
{
case LPTIM1_BASE:
tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
@ -2003,28 +2343,34 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *lptim)
case LPTIM2_BASE:
tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE();
break;
#if defined(LPTIM3)
case LPTIM3_BASE:
tmpclksource = __HAL_RCC_GET_LPTIM3_SOURCE();
break;
#endif /* LPTIM3 */
#if defined(LPTIM4)
case LPTIM4_BASE:
tmpclksource = __HAL_RCC_GET_LPTIM4_SOURCE();
break;
#endif /* LPTIM4 */
#if defined(LPTIM5)
case LPTIM5_BASE:
tmpclksource = __HAL_RCC_GET_LPTIM5_SOURCE();
break;
#endif /* LPTIM5 */
default:
break;
}
/* Save LPTIM configuration registers */
tmpIER = lptim->Instance->IER;
tmpCFGR = lptim->Instance->CFGR;
tmpCMP = lptim->Instance->CMP;
tmpARR = lptim->Instance->ARR;
tmpCFGR2 = lptim->Instance->CFGR2;
tmpIER = hlptim->Instance->IER;
tmpCFGR = hlptim->Instance->CFGR;
tmpCMP = hlptim->Instance->CMP;
tmpARR = hlptim->Instance->ARR;
tmpCFGR2 = hlptim->Instance->CFGR2;
/*********** Reset LPTIM ***********/
switch ((uint32_t)lptim->Instance)
switch ((uint32_t)hlptim->Instance)
{
case LPTIM1_BASE:
__HAL_RCC_LPTIM1_FORCE_RESET();
@ -2034,30 +2380,33 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *lptim)
__HAL_RCC_LPTIM2_FORCE_RESET();
__HAL_RCC_LPTIM2_RELEASE_RESET();
break;
#if defined(LPTIM3)
case LPTIM3_BASE:
__HAL_RCC_LPTIM3_FORCE_RESET();
__HAL_RCC_LPTIM3_RELEASE_RESET();
break;
#endif /* LPTIM3 */
#if defined(LPTIM4)
case LPTIM4_BASE:
__HAL_RCC_LPTIM4_FORCE_RESET();
__HAL_RCC_LPTIM4_RELEASE_RESET();
break;
#endif /* LPTIM4 */
#if defined(LPTIM5)
case LPTIM5_BASE:
__HAL_RCC_LPTIM5_FORCE_RESET();
__HAL_RCC_LPTIM5_RELEASE_RESET();
break;
#endif /* LPTIM5 */
default:
break;
}
/*********** Restore LPTIM Config ***********/
uint32_t Ref_Time;
uint32_t Time_Elapsed;
if ((tmpCMP != 0UL) || (tmpARR != 0UL))
{
/* Force LPTIM source kernel clock from APB */
switch ((uint32_t)lptim->Instance)
switch ((uint32_t)hlptim->Instance)
{
case LPTIM1_BASE:
__HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_D2PCLK1);
@ -2065,15 +2414,21 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *lptim)
case LPTIM2_BASE:
__HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_D3PCLK1);
break;
#if defined(LPTIM3)
case LPTIM3_BASE:
__HAL_RCC_LPTIM3_CONFIG(RCC_LPTIM3CLKSOURCE_D3PCLK1);
break;
#endif /* LPTIM3 */
#if defined(LPTIM4)
case LPTIM4_BASE:
__HAL_RCC_LPTIM4_CONFIG(RCC_LPTIM4CLKSOURCE_D3PCLK1);
break;
#endif /* LPTIM4 */
#if defined(LPTIM5)
case LPTIM5_BASE:
__HAL_RCC_LPTIM5_CONFIG(RCC_LPTIM5CLKSOURCE_D3PCLK1);
break;
#endif /* LPTIM5 */
default:
break;
}
@ -2081,35 +2436,34 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *lptim)
if (tmpCMP != 0UL)
{
/* Restore CMP register (LPTIM should be enabled first) */
lptim->Instance->CR |= LPTIM_CR_ENABLE;
lptim->Instance->CMP = tmpCMP;
/* Polling on CMP write ok status after above restore operation */
Ref_Time = HAL_GetTick();
do
{
Time_Elapsed = HAL_GetTick() - Ref_Time;
} while ((!(__HAL_LPTIM_GET_FLAG(lptim, LPTIM_FLAG_CMPOK))) && (Time_Elapsed <= TIMEOUT));
hlptim->Instance->CR |= LPTIM_CR_ENABLE;
hlptim->Instance->CMP = tmpCMP;
__HAL_LPTIM_CLEAR_FLAG(lptim, LPTIM_FLAG_CMPOK);
/* Wait for the completion of the write operation to the LPTIM_CMP register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
{
hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
}
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
}
if (tmpARR != 0UL)
{
/* Restore ARR register (LPTIM should be enabled first) */
lptim->Instance->CR |= LPTIM_CR_ENABLE;
lptim->Instance->ARR = tmpARR;
/* Polling on ARR write ok status after above restore operation */
Ref_Time = HAL_GetTick();
do
{
Time_Elapsed = HAL_GetTick() - Ref_Time;
} while ((!(__HAL_LPTIM_GET_FLAG(lptim, LPTIM_FLAG_ARROK))) && (Time_Elapsed <= TIMEOUT));
hlptim->Instance->CR |= LPTIM_CR_ENABLE;
hlptim->Instance->ARR = tmpARR;
__HAL_LPTIM_CLEAR_FLAG(lptim, LPTIM_FLAG_ARROK);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
}
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
}
/* Restore LPTIM source kernel clock */
switch ((uint32_t)lptim->Instance)
switch ((uint32_t)hlptim->Instance)
{
case LPTIM1_BASE:
__HAL_RCC_LPTIM1_CONFIG(tmpclksource);
@ -2117,25 +2471,31 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *lptim)
case LPTIM2_BASE:
__HAL_RCC_LPTIM2_CONFIG(tmpclksource);
break;
#if defined(LPTIM3)
case LPTIM3_BASE:
__HAL_RCC_LPTIM3_CONFIG(tmpclksource);
break;
#endif /* LPTIM3 */
#if defined(LPTIM4)
case LPTIM4_BASE:
__HAL_RCC_LPTIM4_CONFIG(tmpclksource);
break;
#endif /* LPTIM4 */
#if defined(LPTIM5)
case LPTIM5_BASE:
__HAL_RCC_LPTIM5_CONFIG(tmpclksource);
break;
#endif /* LPTIM5 */
default:
break;
}
}
/* Restore configuration registers (LPTIM should be disabled first) */
lptim->Instance->CR &= ~(LPTIM_CR_ENABLE);
lptim->Instance->IER = tmpIER;
lptim->Instance->CFGR = tmpCFGR;
lptim->Instance->CFGR2 = tmpCFGR2;
hlptim->Instance->CR &= ~(LPTIM_CR_ENABLE);
hlptim->Instance->IER = tmpIER;
hlptim->Instance->CFGR = tmpCFGR;
hlptim->Instance->CFGR2 = tmpCFGR2;
__enable_irq();
}

11
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_lptim.h
View File

@ -13,7 +13,8 @@
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* ******************************************************************************
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -399,6 +400,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @note The following sequence is required to solve LPTIM disable HW limitation.
* Please check Errata Sheet ES0335 for more details under "MCU may remain
* stuck in LPTIM interrupt when entering Stop mode" section.
* @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
* check for TIMEOUT.
* @retval None
*/
#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
@ -435,6 +438,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @param __HANDLE__ LPTIM handle
* @param __VALUE__ Autoreload value
* @retval None
* @note The ARR register can only be modified when the LPTIM instance is enabled.
*/
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
@ -443,6 +447,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @param __HANDLE__ LPTIM handle
* @param __VALUE__ Compare value
* @retval None
* @note The CMP register can only be modified when the LPTIM instance is enabled.
*/
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
@ -491,6 +496,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
* @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
*/
#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
@ -507,6 +513,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
* @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
*/
#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
@ -745,7 +752,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
* @{
*/
void LPTIM_Disable(LPTIM_HandleTypeDef *lptim);
void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/

484
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_mmc.c
View File

@ -33,8 +33,9 @@
(+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
and according to your pin assignment;
(##) NVIC configuration if you need to use interrupt process when using DMA transfer.
(+++) Configure the SDMMC interrupt priorities using functions HAL_NVIC_SetPriority();
(##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT()
and HAL_MMC_WriteBlocks_IT() APIs).
(+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
(+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
(+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
and __HAL_MMC_DISABLE_IT() inside the communication process.
@ -98,6 +99,17 @@
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
You could also check the DMA transfer process through the MMC Rx interrupt event.
(+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT().
This function allows the read of 512 bytes blocks.
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
You could also check the IT transfer process through the MMC Rx interrupt event.
*** MMC Card Write operation ***
===============================
@ -107,12 +119,38 @@
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
(+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA().
This function support only 512-bytes block length (the block size should be
chosen as 512 byte).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
You could also check the DMA transfer process through the MMC Tx interrupt event.
(+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT().
This function allows the read of 512 bytes blocks.
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
You could also check the IT transfer process through the MMC Tx interrupt event.
*** MMC card information ***
===========================
[..]
(+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo().
It returns useful information about the MMC card such as block size, card type,
block number ...
*** MMC card CSD register ***
============================
[..]
(+) The HAL_MMC_GetCardCSD() API allows to get the parameters of the CSD register.
Some of the CSD parameters are useful for card initialization and identification.
*** MMC card CID register ***
============================
@ -240,7 +278,9 @@ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus);
static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc);
static void MMC_Write_IT(MMC_HandleTypeDef *hmmc);
static void MMC_Read_IT(MMC_HandleTypeDef *hmmc);
static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pBlockNbr, uint32_t Timeout);
static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state);
static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state);
HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout);
/**
@ -498,7 +538,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
uint32_t count, data;
uint32_t count, data, dataremaining;
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
@ -521,7 +561,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
hmmc->Instance->DCTRL = 0;
hmmc->Instance->DCTRL = 0U;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
@ -574,9 +614,10 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
}
/* Poll on SDMMC flags */
dataremaining = config.DataLength;
while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
{
/* Read data from SDMMC Rx FIFO */
for(count = 0U; count < 8U; count++)
@ -591,6 +632,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
*tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
tempbuff++;
}
dataremaining -= 32U;
}
if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
@ -680,7 +722,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
uint32_t count, data;
uint32_t count, data, dataremaining;
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
@ -703,7 +745,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
hmmc->Instance->DCTRL = 0;
hmmc->Instance->DCTRL = 0U;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
@ -756,9 +798,10 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
}
/* Write block(s) in polling mode */
dataremaining = config.DataLength;
while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE))
if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
{
/* Write data to SDMMC Tx FIFO */
for(count = 0U; count < 8U; count++)
@ -773,6 +816,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
tempbuff++;
(void)SDMMC_WriteFIFO(hmmc->Instance, &data);
}
dataremaining -= 32U;
}
if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
@ -1170,7 +1214,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData
* @note You could also check the DMA transfer process through the MMC Tx
* interrupt event.
* @param hmmc: Pointer to MMC handle
* @param pData: pointer to the buffer that will contain the data to transmit
* @param pData: Pointer to the buffer that will contain the data to transmit
* @param BlockAdd: Block Address where data will be written
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
@ -1220,6 +1264,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
@ -1328,7 +1373,6 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd,
end_add *= 512U;
}
/* Send CMD35 MMC_ERASE_GRP_START with argument as addr */
errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add);
if(errorstate != HAL_MMC_ERROR_NONE)
@ -1383,7 +1427,12 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
uint32_t context = hmmc->Context;
/* Check for SDMMC interrupt flags */
if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DATAEND) != RESET)
if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
{
MMC_Read_IT(hmmc);
}
else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET)
{
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND);
@ -1480,17 +1529,12 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
}
}
else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXFIFOHE) != RESET)
else if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
{
MMC_Write_IT(hmmc);
}
else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXFIFOHF) != RESET)
{
MMC_Read_IT(hmmc);
}
else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL| SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR) != RESET)
else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL| SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET)
{
/* Set Error code */
if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET)
@ -1513,8 +1557,6 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
/* Clear All flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DCRCFAIL);
/* Disable all interrupts */
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
@ -1559,8 +1601,9 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
}
}
else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_IDMABTC) != RESET)
else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_IDMABTC) != RESET)
{
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_IT_IDMABTC);
if(READ_BIT(hmmc->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U)
{
/* Current buffer is buffer0, Transfer complete for buffer1 */
@ -1601,7 +1644,6 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
#endif
}
}
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_IT_IDMABTC);
}
else
@ -1622,7 +1664,7 @@ HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc)
/**
* @brief Return the MMC error code
* @param hmmc : pointer to a MMC_HandleTypeDef structure that contains
* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
* @retval MMC Error Code
*/
@ -1657,7 +1699,7 @@ __weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)
UNUSED(hmmc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MMC_ErrorCallback can be implemented in the user file
the HAL_MMC_RxCpltCallback can be implemented in the user file
*/
}
@ -1687,7 +1729,7 @@ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
UNUSED(hmmc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MMC_ErrorCallback can be implemented in the user file
the HAL_MMC_AbortCallback can be implemented in the user file
*/
}
@ -1953,7 +1995,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTyp
* @brief Returns information the information of the card which are stored on
* the CSD register.
* @param hmmc: Pointer to MMC handle
* @param pCSD: Pointer to a HAL_MMC_CardInfoTypedef structure that
* @param pCSD: Pointer to a HAL_MMC_CardCSDTypeDef structure that
* contains all CSD register parameters
* @retval HAL status
*/
@ -1987,7 +2029,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp
pCSD->Reserved2 = 0U; /*!< Reserved */
if(MMC_ReadExtCSD(hmmc, &block_nbr, 0x0FFFFFFFU) != HAL_OK)
if(MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */
{
return HAL_ERROR;
}
@ -2101,10 +2143,10 @@ HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoT
*/
HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode)
{
__IO uint32_t count = 0;
__IO uint32_t count = 0U;
SDMMC_InitTypeDef Init;
uint32_t errorstate;
uint32_t response = 0, busy = 0;
uint32_t response = 0U, busy = 0U;
/* Check the parameters */
assert_param(IS_SDMMC_BUS_WIDE(WideMode));
@ -2114,7 +2156,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32
if(WideMode == SDMMC_BUS_WIDE_8B)
{
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200);
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
@ -2122,7 +2164,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32
}
else if(WideMode == SDMMC_BUS_WIDE_4B)
{
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100);
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
@ -2130,7 +2172,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32
}
else if(WideMode == SDMMC_BUS_WIDE_1B)
{
errorstate = SDMMC_CmdSwitch(hmmc->Instance, SDMMC_BUS_WIDE_1B /*0x03B70000*/);
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
@ -2141,6 +2183,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32
/* WideMode is not a valid argument*/
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
}
/* Check for switch error and violation of the trial number of sending CMD 13 */
while(busy == 0U)
{
@ -2153,7 +2196,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32
count++;
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
@ -2179,7 +2222,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32
count--;
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
@ -2213,6 +2256,162 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32
return HAL_OK;
}
/**
* @brief Configure the speed bus mode
* @param hmmc: Pointer to the MMC handle
* @param SpeedMode: Specifies the MMC card speed bus mode
* This parameter can be one of the following values:
* @arg SDMMC_SPEED_MODE_AUTO: Max speed mode supported by the card
* @arg SDMMC_SPEED_MODE_DEFAULT: Default Speed (MMC @ 26MHz)
* @arg SDMMC_SPEED_MODE_HIGH: High Speed (MMC @ 52 MHz)
* @arg SDMMC_SPEED_MODE_DDR: High Speed DDR (MMC DDR @ 52 MHz)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode)
{
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
uint32_t device_type;
uint32_t errorstate;
/* Check the parameters */
assert_param(IS_SDMMC_SPEED_MODE(SpeedMode));
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
if(MMC_ReadExtCSD(hmmc, &device_type, 196, 0x0FFFFFFFU) != HAL_OK) /* Field DEVICE_TYPE [196] */
{
return HAL_ERROR;
}
switch (SpeedMode)
{
case SDMMC_SPEED_MODE_AUTO:
{
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U))
{
/* High Speed DDR mode allowed */
errorstate = MMC_HighSpeed(hmmc, ENABLE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
else
{
errorstate = MMC_DDR_Mode(hmmc, ENABLE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
}
}
else if ((device_type & 0x02U) != 0U)
{
/* High Speed mode allowed */
errorstate = MMC_HighSpeed(hmmc, ENABLE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
}
else
{
/* Nothing to do : keep current speed */
}
break;
}
case SDMMC_SPEED_MODE_DDR:
{
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U))
{
/* High Speed DDR mode allowed */
errorstate = MMC_HighSpeed(hmmc, ENABLE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
else
{
errorstate = MMC_DDR_Mode(hmmc, ENABLE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
}
}
else
{
/* High Speed DDR mode not allowed */
hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
status = HAL_ERROR;
}
break;
}
case SDMMC_SPEED_MODE_HIGH:
{
if ((device_type & 0x02U) != 0U)
{
/* High Speed mode allowed */
errorstate = MMC_HighSpeed(hmmc, ENABLE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
}
else
{
/* High Speed mode not allowed */
hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
status = HAL_ERROR;
}
break;
}
case SDMMC_SPEED_MODE_DEFAULT:
{
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U)
{
/* High Speed DDR mode activated */
errorstate = MMC_DDR_Mode(hmmc, DISABLE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
}
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U)
{
/* High Speed mode activated */
errorstate = MMC_HighSpeed(hmmc, DISABLE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
}
break;
}
default:
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
status = HAL_ERROR;
break;
}
/* Verify that MMC card is ready to use after Speed mode switch*/
tickstart = HAL_GetTick();
while ((HAL_MMC_GetCardState(hmmc) != HAL_MMC_CARD_TRANSFER))
{
if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
/* Change State */
hmmc->State = HAL_MMC_STATE_READY;
return status;
}
/**
* @brief Gets the current mmc card data state.
* @param hmmc: pointer to MMC handle
@ -2222,7 +2421,7 @@ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
{
uint32_t cardstate;
uint32_t errorstate;
uint32_t resp1 = 0;
uint32_t resp1 = 0U;
errorstate = MMC_SendStatus(hmmc, &resp1);
if(errorstate != HAL_MMC_ERROR_NONE)
@ -2250,7 +2449,7 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc)
SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
/* Clear All flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
/* If IDMA Context, disable Internal DMA */
hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
@ -2290,7 +2489,7 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc)
hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
/* Clear All flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
CardState = HAL_MMC_GetCardState(hmmc);
hmmc->State = HAL_MMC_STATE_READY;
@ -2338,7 +2537,7 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
{
HAL_MMC_CardCSDTypeDef CSD;
uint32_t errorstate;
uint16_t mmc_rca = 1;
uint16_t mmc_rca = 1U;
MMC_InitTypeDef Init;
/* Check the power State */
@ -2357,10 +2556,10 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
else
{
/* Get Card identification number data */
hmmc->CID[0] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
hmmc->CID[1] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2);
hmmc->CID[2] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3);
hmmc->CID[3] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4);
hmmc->CID[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
hmmc->CID[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2);
hmmc->CID[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3);
hmmc->CID[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4);
}
/* Send CMD3 SET_REL_ADDR with argument 0 */
@ -2390,10 +2589,10 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
}
/* Get the Card Class */
hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20);
hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20U);
/* Select the Card */
errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
@ -2406,7 +2605,7 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
}
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
@ -2433,8 +2632,8 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
*/
static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc)
{
__IO uint32_t count = 0;
uint32_t response = 0, validvoltage = 0;
__IO uint32_t count = 0U;
uint32_t response = 0U, validvoltage = 0U;
uint32_t errorstate;
/* CMD0: GO_IDLE_STATE */
@ -2489,10 +2688,9 @@ static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc)
(void)SDMMC_PowerState_OFF(hmmc->Instance);
}
/**
* @brief Returns the current card's status.
* @param hmmc: pointer to MMC handle
* @param hmmc: Pointer to MMC handle
* @param pCardStatus: pointer to the buffer that will contain the MMC card
* status (Card Status register)
* @retval error state
@ -2507,7 +2705,7 @@ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
}
/* Send Status command */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16));
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
@ -2522,11 +2720,12 @@ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
/**
* @brief Reads extended CSD register to get the sectors number of the device
* @param hmmc: Pointer to MMC handle
* @param pBlockNbr: Pointer to the read buffer
* @param pFieldData: Pointer to the read buffer
* @param pFieldIndex: Index of the field to be read
* @param Timeout: Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pBlockNbr, uint32_t Timeout)
HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
@ -2535,7 +2734,7 @@ HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pBlockNbr, u
uint32_t i = 0;
uint32_t tmp_data;
hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
/* Initialize data control register */
hmmc->Instance->DCTRL = 0;
@ -2589,9 +2788,11 @@ HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pBlockNbr, u
for(count = 0U; count < 8U; count++)
{
tmp_data = SDMMC_ReadFIFO(hmmc->Instance);
if ((i == 48U) && (count == 5U))
/* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */
/* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */
if ((i + count) == ((uint32_t)FieldIndex/4U))
{
*pBlockNbr = tmp_data;
*pFieldData = tmp_data;
}
}
i += 8U;
@ -2615,7 +2816,7 @@ HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pBlockNbr, u
}
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
@ -2635,6 +2836,8 @@ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc)
tmp = hmmc->pRxBuffPtr;
if (hmmc->RxXferSize >= 32U)
{
/* Read data from SDMMC Rx FIFO */
for(count = 0U; count < 8U; count++)
{
@ -2650,6 +2853,8 @@ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc)
}
hmmc->pRxBuffPtr = tmp;
hmmc->RxXferSize -= 32U;
}
}
/**
@ -2665,6 +2870,8 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc)
tmp = hmmc->pTxBuffPtr;
if (hmmc->TxXferSize >= 32U)
{
/* Write data to SDMMC Tx FIFO */
for(count = 0U; count < 8U; count++)
{
@ -2680,6 +2887,168 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc)
}
hmmc->pTxBuffPtr = tmp;
hmmc->TxXferSize -= 32U;
}
}
/**
* @brief Switches the MMC card to high speed mode.
* @param hmmc: MMC handle
* @param state: State of high speed mode
* @retval MMC Card error state
*/
static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state)
{
uint32_t errorstate = HAL_MMC_ERROR_NONE;
uint32_t response, count;
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) && (state == DISABLE))
{
/* Index : 185 - Value : 0 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90000U);
}
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U) && (state != DISABLE))
{
/* Index : 185 - Value : 1 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90100U);
}
if(errorstate == HAL_MMC_ERROR_NONE)
{
/* Check for switch error */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if(errorstate == HAL_MMC_ERROR_NONE)
{
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
if ((response & 0x80U) != 0U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
else
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
while(((response & 0x100U) == 0U) && (count != 0U))
{
count--;
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
}
/* Configure high speed */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
{
if (state == DISABLE)
{
CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
}
else
{
SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
}
}
}
}
}
return errorstate;
}
/**
* @brief Switches the MMC card to Double Data Rate (DDR) mode.
* @param hmmc: MMC handle
* @param state: State of DDR mode
* @retval MMC Card error state
*/
static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state)
{
uint32_t errorstate = HAL_MMC_ERROR_NONE;
uint32_t response, count;
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U) && (state == DISABLE))
{
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U)
{
/* Index : 183 - Value : 5 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70500U);
}
else
{
/* Index : 183 - Value : 6 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70600U);
}
}
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) && (state != DISABLE))
{
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U)
{
/* Index : 183 - Value : 1 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
}
else
{
/* Index : 183 - Value : 2 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
}
}
if(errorstate == HAL_MMC_ERROR_NONE)
{
/* Check for switch error */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if(errorstate == HAL_MMC_ERROR_NONE)
{
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
if ((response & 0x80U) != 0U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
else
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
while(((response & 0x100U) == 0U) && (count != 0U))
{
count--;
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
}
/* Configure DDR mode */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
{
if (state == DISABLE)
{
CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR);
}
else
{
SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR);
}
}
}
}
}
return errorstate;
}
/**
@ -2742,7 +3111,6 @@ __weak void HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc
*/
}
/**
* @}
*/

18
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_mmc.h
View File

@ -135,9 +135,9 @@ typedef struct
HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
uint32_t CSD[4]; /*!< MMC card specific data table */
uint32_t CSD[4U]; /*!< MMC card specific data table */
uint32_t CID[4]; /*!< MMC card identification number table */
uint32_t CID[4U]; /*!< MMC card identification number table */
uint32_t Ext_CSD[128];
@ -462,8 +462,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDMMC_FLAG_DHOLD: Data transfer Hold
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
* @arg SDMMC_FLAG_CPSMACT: Command path state machine active
* @arg SDMMC_FLAG_DPSMACT: Data path state machine active
* @arg SDMMC_FLAG_CPSMACT: Command path state machine active
* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
@ -529,22 +529,16 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
* @arg SDMMC_IT_DPSMACT: Data path state machine active interrupt
* @arg SDMMC_IT_CPSMACT: Command path state machine active interrupt
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDMMC_IT_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
* @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
* @retval The new state of MMC IT (SET or RESET).
*/
@ -567,13 +561,16 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
* @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
* @retval None
*/
@ -639,6 +636,7 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca
* @{
*/
HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode);
/**
* @}
*/

10
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_pcd.c
View File

@ -1039,7 +1039,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t i, ep_intr, epint, epnum = 0U;
uint32_t i, ep_intr, epint, epnum;
uint32_t fifoemptymsk, temp;
USB_OTG_EPTypeDef *ep;
@ -1360,6 +1360,10 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/* Handle Incomplete ISO IN Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
{
/* Keep application checking the corresponding Iso IN endpoint
causing the incomplete Interrupt */
epnum = 0U;
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
#else
@ -1372,6 +1376,10 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/* Handle Incomplete ISO OUT Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
{
/* Keep application checking the corresponding Iso OUT endpoint
causing the incomplete Interrupt */
epnum = 0U;
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
#else

4
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_ramecc.c
View File

@ -134,7 +134,7 @@ HAL_StatusTypeDef HAL_RAMECC_Init(RAMECC_HandleTypeDef *hramecc)
hramecc->Instance->CR &= ~RAMECC_CR_ECCELEN;
/* Disable all global interrupts */
((RAMECC_TypeDef *)((uint32_t)&hramecc->Instance & 0xFFFFFF00U))->IER &= \
((RAMECC_TypeDef *)((uint32_t)hramecc->Instance & 0xFFFFFF00U))->IER &= \
~(RAMECC_IER_GIE | RAMECC_IER_GECCSEIE | RAMECC_IER_GECCDEIE | RAMECC_IER_GECCDEBWIE);
/* Disable all interrupts monitor */
@ -175,7 +175,7 @@ HAL_StatusTypeDef HAL_RAMECC_DeInit(RAMECC_HandleTypeDef *hramecc)
hramecc->Instance->CR &= ~RAMECC_CR_ECCELEN;
/* Disable all global interrupts */
((RAMECC_TypeDef *)((uint32_t)&hramecc->Instance & 0xFFFFFF00U))->IER &= \
((RAMECC_TypeDef *)((uint32_t)hramecc->Instance & 0xFFFFFF00U))->IER &= \
~(RAMECC_IER_GIE | RAMECC_IER_GECCSEIE | RAMECC_IER_GECCDEIE | RAMECC_IER_GECCDEBWIE);
/* Disable all interrupts monitor */

2
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_ramecc.h
View File

@ -136,7 +136,7 @@ typedef struct __RAMECC_HandleTypeDef
#define __HAL_RAMECC_DISABLE_GLOBAL_IT(__HANDLE__, __INTERRUPT__) ((((RAMECC_TypeDef *)((uint32_t)&(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) &= ~((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID))
#define __HAL_RAMECC_DISABLE_GLOBAL_IT(__HANDLE__, __INTERRUPT__) ((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) &= ~((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID))
#define __HAL_RAMECC_DISABLE_MONITOR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~((__INTERRUPT__) & ~RAMECC_IT_MONITOR_ID))
/**

4
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.c
View File

@ -214,7 +214,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
SystemCoreClock = HSI_VALUE;
/* Adapt Systick interrupt period */
if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
if(HAL_InitTick(uwTickPrio) != HAL_OK)
{
return HAL_ERROR;
}
@ -1048,7 +1048,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
/* Configure the source of time base considering new system clocks settings*/
halstatus = HAL_InitTick (TICK_INT_PRIORITY);
halstatus = HAL_InitTick (uwTickPrio);
return halstatus;
}

27
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc_ex.c
View File

@ -1908,6 +1908,33 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
break;
}
default :
{
frequency = 0;
break;
}
}
}
else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
{
/* Get SDMMC clock source */
srcclk= __HAL_RCC_GET_SDMMC_SOURCE();
switch (srcclk)
{
case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */
{
HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
frequency = pll1_clocks.PLL1_Q_Frequency;
break;
}
case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */
{
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
frequency = pll2_clocks.PLL2_R_Frequency;
break;
}
default :
{
frequency = 0;

323
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd.c
View File

@ -27,14 +27,15 @@
SDMMC driver functions to interface with SD and uSD cards devices.
It is used as follows:
(#)Initialize the SDMMC low level resources by implement the HAL_SD_MspInit() API:
(#)Initialize the SDMMC low level resources by implementing the HAL_SD_MspInit() API:
(##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
(##) SDMMC pins configuration for SD card
(+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
and according to your pin assignment;
(##) NVIC configuration if you need to use interrupt process when using DMA transfer.
(+++) Configure the SDMMC interrupt priorities using functions HAL_NVIC_SetPriority();
(##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
and HAL_SD_WriteBlocks_IT() APIs).
(+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
(+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
(+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT()
and __HAL_SD_DISABLE_IT() inside the communication process.
@ -49,7 +50,7 @@
================================================
[..]
To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
the SD Card and put it into StandBy State (Ready for data transfer).
SDMMC Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
This function provide the following operations:
(#) Apply the SD Card initialization process at 400KHz and check the SD Card
@ -62,11 +63,16 @@
In initialization mode and according to the SD Card standard,
make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
(#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo
structure. This structure provide also ready computed SD Card capacity
and Block size.
This phase of initialization is done through SDMMC_Init() and
SDMMC_PowerState_ON() SDMMC low level APIs.
-@- These information are stored in SD handle structure in case of future use.
(#) Initialize the SD card. The API used is HAL_SD_InitCard().
This phase allows the card initialization and identification
and check the SD Card type (Standard Capacity or High Capacity)
The initialization flow is compatible with SD standard.
This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
of plug-off plug-in.
(#) Configure the SD Card Data transfer frequency. You can change or adapt this
frequency by adjusting the "ClockDiv" field.
@ -85,12 +91,26 @@
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
(+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
You could also check the DMA transfer process through the SD Rx interrupt event.
(+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
You could also check the IT transfer process through the SD Rx interrupt event.
*** SD Card Write operation ***
===============================
@ -100,19 +120,49 @@
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
(+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
This function support only 512-bytes block length (the block size should be
chosen as 512 byte).
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
You could also check the DMA transfer process through the SD Tx interrupt event.
(+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
You could also check the IT transfer process through the SD Tx interrupt event.
*** SD card status ***
======================
[..]
(+) At any time, you can check the SD Card status and get the SD card state
by using the HAL_SD_GetStatusInfo() function. This function checks first if the
SD card is still connected and then get the internal SD Card transfer state.
(+) The SD Status contains status bits that are related to the SD Memory
Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().
*** SD card information ***
===========================
[..]
(+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
It returns useful information about the SD card such as block size, card type,
block number ...
*** SD card CSD register ***
============================
(+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
Some of the CSD parameters are useful for card initialization and identification.
*** SD card CID register ***
============================
(+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
Some of the CSD parameters are useful for card initialization and identification.
*** SD HAL driver macros list ***
==================================
@ -283,7 +333,7 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd);
*/
HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
{
HAL_SD_CardStatusTypedef CardStatus;
HAL_SD_CardStatusTypeDef CardStatus;
uint32_t speedgrade, unitsize;
uint32_t tickstart;
@ -305,6 +355,14 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
{
/* Allocate lock resource and initialize it */
hsd->Lock = HAL_UNLOCKED;
#if (USE_SD_TRANSCEIVER != 0U)
/* Force SDMMC_TRANSCEIVER_PRESENT for Legacy usage */
if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_UNKNOWN)
{
hsd->Init.TranceiverPresent = SDMMC_TRANSCEIVER_PRESENT;
}
#endif
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/* Reset Callback pointers in HAL_SD_STATE_RESET only */
hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
@ -316,7 +374,10 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
hsd->Write_DMADblBuf0CpltCallback = HAL_SDEx_Write_DMADoubleBuffer0CpltCallback;
hsd->Write_DMADblBuf1CpltCallback = HAL_SDEx_Write_DMADoubleBuffer1CpltCallback;
#if (USE_SD_TRANSCEIVER != 0U)
if hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
{
hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback;
}
#endif /* USE_SD_TRANSCEIVER */
if(hsd->MspInitCallback == NULL)
@ -405,6 +466,7 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
uint32_t errorstate;
HAL_StatusTypeDef status;
SD_InitTypeDef Init;
uint32_t sdmmc_clk;
/* Default SDMMC peripheral configuration for SD card initialization */
Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
@ -414,8 +476,11 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
Init.ClockDiv = SDMMC_INIT_CLK_DIV;
#if (USE_SD_TRANSCEIVER != 0U) || defined (USE_SD_DIRPOL)
if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
{
/* Set Transceiver polarity */
hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
}
#endif /* USE_SD_TRANSCEIVER */
/* Initialize SDMMC peripheral interface with default configuration */
@ -432,6 +497,19 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
return HAL_ERROR;
}
/* wait 74 Cycles: required power up waiting time before starting
the SD initialization sequence */
sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC)/(2U*SDMMC_INIT_CLK_DIV);
if(sdmmc_clk != 0U)
{
HAL_Delay(1U+ (74U*1000U/(sdmmc_clk)));
}
else
{
HAL_Delay(2U);
}
/* Identify card operating voltage */
errorstate = SD_PowerON(hsd);
if(errorstate != HAL_SD_ERROR_NONE)
@ -473,6 +551,8 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
#if (USE_SD_TRANSCEIVER != 0U)
/* Desactivate the 1.8V Mode */
if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
if(hsd->DriveTransceiver_1_8V_Callback == NULL)
{
@ -482,6 +562,7 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
#else
HAL_SD_DriveTransceiver_1_8V_Callback(RESET);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
#endif /* USE_SD_TRANSCEIVER */
/* Set SD power state to off */
@ -573,7 +654,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
uint32_t count, data;
uint32_t count, data, dataremaining;
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
@ -645,13 +726,15 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
/* Poll on SDMMC flags */
dataremaining = config.DataLength;
while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
{
/* Read data from SDMMC Rx FIFO */
for(count = 0U; count < 8U; count++)
@ -666,6 +749,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
*tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
tempbuff++;
}
dataremaining -= 32U;
}
if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
@ -674,6 +758,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
hsd->State= HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_TIMEOUT;
}
}
@ -692,6 +777,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
}
@ -704,6 +790,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
@ -712,6 +799,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
@ -720,6 +808,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else
@ -758,7 +847,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
uint32_t count, data;
uint32_t count, data, dataremaining;
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
@ -830,13 +919,15 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
/* Write block(s) in polling mode */
dataremaining = config.DataLength;
while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))
if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
{
/* Write data to SDMMC Tx FIFO */
for(count = 0U; count < 8U; count++)
@ -851,6 +942,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
tempbuff++;
(void)SDMMC_WriteFIFO(hsd->Instance, &data);
}
dataremaining -= 32U;
}
if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
@ -859,6 +951,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_TIMEOUT;
}
}
@ -877,6 +970,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
}
@ -889,6 +983,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
@ -897,6 +992,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))
@ -905,6 +1001,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else
@ -1018,6 +1115,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
@ -1123,6 +1221,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
@ -1231,6 +1330,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
__HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
@ -1339,6 +1439,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
__HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
@ -1467,7 +1568,12 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
uint32_t context = hsd->Context;
/* Check for SDMMC interrupt flags */
if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DATAEND) != RESET)
if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
{
SD_Read_IT(hsd);
}
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET)
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND);
@ -1498,6 +1604,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
@ -1537,6 +1644,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
}
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
@ -1560,17 +1668,12 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
}
}
else if((__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
else if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
{
SD_Write_IT(hsd);
}
else if((__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
{
SD_Read_IT(hsd);
}
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR) != RESET)
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET)
{
/* Set Error code */
if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET)
@ -1608,6 +1711,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
{
/* Set the SD state to ready to be able to start again the process */
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->ErrorCallback(hsd);
#else
@ -1637,12 +1741,13 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
}
}
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_IDMABTC) != RESET)
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_IDMABTC) != RESET)
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC);
if(READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U)
{
/* Current buffer is buffer0, Transfer complete for buffer1 */
if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->Write_DMADblBuf1CpltCallback(hsd);
@ -1679,7 +1784,6 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC);
}
else
{
@ -2083,11 +2187,11 @@ HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd)
* @brief Returns information the information of the card which are stored on
* the CID register.
* @param hsd: Pointer to SD handle
* @param pCID: Pointer to a HAL_SD_CIDTypedef structure that
* @param pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that
* contains all CID register parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID)
HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
{
pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U);
@ -2116,11 +2220,11 @@ HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef
* @brief Returns information the information of the card which are stored on
* the CSD register.
* @param hsd: Pointer to SD handle
* @param pCSD: Pointer to a HAL_SD_CardInfoTypedef structure that
* @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that
* contains all CSD register parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD)
HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
{
pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U);
@ -2230,11 +2334,11 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef
/**
* @brief Gets the SD status info.
* @param hsd: Pointer to SD handle
* @param pStatus: Pointer to the HAL_SD_CardStatusTypedef structure that
* @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that
* will contain the SD card status information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus)
HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
{
uint32_t sd_status[16];
uint32_t errorstate;
@ -2420,6 +2524,8 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
hsd->State = HAL_SD_STATE_BUSY;
#if (USE_SD_TRANSCEIVER != 0U)
if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
{
switch (SpeedMode)
{
case SDMMC_SPEED_MODE_AUTO:
@ -2427,7 +2533,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
hsd->Instance->CLKCR |= 0x00100000U;
hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED;
/* Enable Ultra High Speed */
if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE)
{
@ -2458,13 +2564,13 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
hsd->Instance->CLKCR |= 0x00100000U;
/* Enable UltraHigh Speed */
if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
status = HAL_ERROR;
}
hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED;
}
else
{
@ -2478,13 +2584,13 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
hsd->Instance->CLKCR |= 0x00100000U;
/* Enable DDR Mode*/
if (SD_DDR_Mode(hsd) != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
status = HAL_ERROR;
}
hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED | SDMMC_CLKCR_DDR;
}
else
{
@ -2520,6 +2626,59 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
status = HAL_ERROR;
break;
}
}
else
{
switch (SpeedMode)
{
case SDMMC_SPEED_MODE_AUTO:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) ||
(hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
/* Enable High Speed */
if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
status = HAL_ERROR;
}
}
else
{
/*Nothing to do, Use defaultSpeed */
}
break;
}
case SDMMC_SPEED_MODE_HIGH:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) ||
(hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
/* Enable High Speed */
if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
status = HAL_ERROR;
}
}
else
{
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
status = HAL_ERROR;
}
break;
}
case SDMMC_SPEED_MODE_DEFAULT:
break;
case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
default:
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
status = HAL_ERROR;
break;
}
}
#else
switch (SpeedMode)
{
@ -2572,7 +2731,6 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
}
#endif /* USE_SD_TRANSCEIVER */
/* Verify that SD card is ready to use after Speed mode switch*/
tickstart = HAL_GetTick();
while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER))
@ -2595,7 +2753,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
* @param hsd: pointer to SD handle
* @retval Card state
*/
HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
{
uint32_t cardstate;
uint32_t errorstate;
@ -2609,7 +2767,7 @@ HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
cardstate = ((resp1 >> 9U) & 0x0FU);
return (HAL_SD_CardStateTypedef)cardstate;
return (HAL_SD_CardStateTypeDef)cardstate;
}
/**
@ -2620,14 +2778,14 @@ HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
*/
HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
{
HAL_SD_CardStateTypedef CardState;
HAL_SD_CardStateTypeDef CardState;
/* DIsable All interrupts */
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
/* Clear All flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
/* If IDMA Context, disable Internal DMA */
hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
@ -2657,7 +2815,7 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
*/
HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
{
HAL_SD_CardStateTypedef CardState;
HAL_SD_CardStateTypeDef CardState;
/* Disable All interrupts */
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
@ -2714,9 +2872,9 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
*/
static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
{
HAL_SD_CardCSDTypedef CSD;
HAL_SD_CardCSDTypeDef CSD;
uint32_t errorstate;
uint16_t sd_rca = 1;
uint16_t sd_rca = 1U;
/* Check the power State */
if(SDMMC_GetPowerState(hsd->Instance) == 0U)
@ -2736,10 +2894,10 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
else
{
/* Get Card identification number data */
hsd->CID[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
hsd->CID[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
hsd->CID[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
hsd->CID[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
hsd->CID[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
}
}
@ -2767,15 +2925,15 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
else
{
/* Get Card Specific Data */
hsd->CSD[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
hsd->CSD[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
hsd->CSD[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
hsd->CSD[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
}
}
/* Get the Card Class */
hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20);
hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20U);
/* Get CSD parameters */
if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK)
@ -2784,7 +2942,7 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
}
/* Select the Card */
errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16));
errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
@ -2803,8 +2961,8 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
*/
static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
{
__IO uint32_t count = 0;
uint32_t response = 0, validvoltage = 0;
__IO uint32_t count = 0U;
uint32_t response = 0U, validvoltage = 0U;
uint32_t errorstate;
#if (USE_SD_TRANSCEIVER != 0U)
uint32_t tickstart = HAL_GetTick();
@ -2880,6 +3038,8 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
{
hsd->SdCard.CardType = CARD_SDHC_SDXC;
#if (USE_SD_TRANSCEIVER != 0U)
if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
{
if((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY)
{
hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
@ -2953,6 +3113,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
}
}
#endif /* USE_SD_TRANSCEIVER */
}
@ -2992,7 +3153,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
}
/* Set block size for card if it is not equal to current block size for card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
@ -3000,7 +3161,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
}
/* Send CMD55 */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
@ -3009,7 +3170,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = 64;
config.DataLength = 64U;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
@ -3093,7 +3254,7 @@ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
}
/* Send Status command */
errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
@ -3112,7 +3273,7 @@ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
*/
static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
{
uint32_t scr[2] = {0, 0};
uint32_t scr[2U] = {0UL, 0UL};
uint32_t errorstate;
if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
@ -3128,17 +3289,17 @@ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
}
/* If requested card supports wide bus operation */
if((scr[1] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
{
/* Send CMD55 APP_CMD with argument as card's RCA.*/
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2);
errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
@ -3159,7 +3320,7 @@ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
*/
static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
{
uint32_t scr[2] = {0, 0};
uint32_t scr[2U] = {0UL, 0UL};
uint32_t errorstate;
if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
@ -3175,17 +3336,17 @@ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
}
/* If requested card supports 1 bit mode operation */
if((scr[1] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
{
/* Send CMD55 APP_CMD with argument as card's RCA */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0);
errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
@ -3211,26 +3372,26 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
uint32_t index = 0;
uint32_t tempscr[2] = {0, 0};
uint32_t index = 0U;
uint32_t tempscr[2U] = {0UL, 0UL};
uint32_t *scr = pSCR;
/* Set Block Size To 8 Bytes */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8);
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send CMD55 APP_CMD with argument as card's RCA */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16));
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = 8;
config.DataLength = 8U;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
@ -3308,6 +3469,8 @@ static void SD_Read_IT(SD_HandleTypeDef *hsd)
tmp = hsd->pRxBuffPtr;
if (hsd->RxXferSize >= 32U)
{
/* Read data from SDMMC Rx FIFO */
for(count = 0U; count < 8U; count++)
{
@ -3323,6 +3486,8 @@ static void SD_Read_IT(SD_HandleTypeDef *hsd)
}
hsd->pRxBuffPtr = tmp;
hsd->RxXferSize -= 32U;
}
}
/**
@ -3338,6 +3503,8 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd)
tmp = hsd->pTxBuffPtr;
if (hsd->TxXferSize >= 32U)
{
/* Write data to SDMMC Tx FIFO */
for(count = 0U; count < 8U; count++)
{
@ -3353,6 +3520,8 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd)
}
hsd->pTxBuffPtr = tmp;
hsd->TxXferSize -= 32U;
}
}
/**
@ -3457,7 +3626,7 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
}
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
/* Test if the switch mode HS is ok */
if ((((uint8_t*)SD_hs)[13] & 2U) != 2U)
@ -3718,8 +3887,8 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd)
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2)
/* Enable DelayBlock Peripheral */
/* SDMMC_FB_CLK tuned feedback clock selected as receive clock, for SDR104 */
MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX,SDMMC_CLKCR_SELCLKRX_1);
/* SDMMC_CKin feedback clock selected as receive clock, for DDR50 */
MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX,SDMMC_CLKCR_SELCLKRX_0);
if (DelayBlock_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)) != HAL_OK)
{
return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);

25
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd.h
View File

@ -66,7 +66,7 @@ typedef enum
/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
* @{
*/
typedef uint32_t HAL_SD_CardStateTypedef;
typedef uint32_t HAL_SD_CardStateTypeDef;
#define HAL_SD_CARD_READY 0x00000001U /*!< Card state is ready */
#define HAL_SD_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
@ -212,7 +212,7 @@ typedef struct
__IO uint8_t ECC; /*!< ECC code */
__IO uint8_t CSD_CRC; /*!< CSD CRC */
__IO uint8_t Reserved4; /*!< Always 1 */
}HAL_SD_CardCSDTypedef;
}HAL_SD_CardCSDTypeDef;
/**
* @}
*/
@ -233,7 +233,7 @@ typedef struct
__IO uint8_t CID_CRC; /*!< CID CRC */
__IO uint8_t Reserved2; /*!< Always 1 */
}HAL_SD_CardCIDTypedef;
}HAL_SD_CardCIDTypeDef;
/**
* @}
*/
@ -256,7 +256,7 @@ typedef struct
__IO uint8_t UhsSpeedGrade; /*!< Carries information about the speed grade of UHS card */
__IO uint8_t UhsAllocationUnitSize; /*!< Carries information about the UHS card's allocation unit size */
__IO uint8_t VideoSpeedClass; /*!< Carries information about the Video Speed Class of UHS card */
}HAL_SD_CardStatusTypedef;
}HAL_SD_CardStatusTypeDef;
/**
* @}
*/
@ -496,8 +496,8 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
* @arg SDMMC_FLAG_DHOLD: Data transfer Hold
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
* @arg SDMMC_FLAG_CPSMACT: Command path state machine active
* @arg SDMMC_FLAG_DPSMACT: Data path state machine active
* @arg SDMMC_FLAG_CPSMACT: Command path state machine active
* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
@ -563,22 +563,16 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
* @arg SDMMC_IT_DPSMACT: Data path state machine active interrupt
* @arg SDMMC_IT_CPSMACT: Command path state machine active interrupt
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDMMC_IT_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
* @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
* @retval The new state of SD IT (SET or RESET).
*/
@ -607,7 +601,6 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
* @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
* @retval None
*/
@ -691,10 +684,10 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
/** @defgroup SD_Exported_Functions_Group4 SD card related functions
* @{
*/
HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID);
HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD);
HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus);
HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
HAL_StatusTypeDef HAL_SD_GetCardCID (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
HAL_StatusTypeDef HAL_SD_GetCardCSD (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
HAL_StatusTypeDef HAL_SD_GetCardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
/**
* @}

3
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd_ex.c
View File

@ -14,7 +14,6 @@
[..]
The SD Extension HAL driver can be used as follows:
(+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function.
(+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions.
@endverbatim
@ -130,7 +129,7 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3
/* Initialize data control register */
hsd->Instance->DCTRL = 0;
/* Clear old Flags*/
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
hsd->ErrorCode = HAL_SD_ERROR_NONE;
hsd->State = HAL_SD_STATE_BUSY;

6
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd_ex.h
View File

@ -18,8 +18,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7xx_HAL_SD_EX_H
#define STM32H7xx_HAL_SD_EX_H
#ifndef STM32H7xx_HAL_SDEX_H
#define STM32H7xx_HAL_SDEX_H
#ifdef __cplusplus
extern "C" {
@ -108,6 +108,6 @@ void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd);
#endif
#endif /* stm32h7xx_HAL_SDEx_H */
#endif /* stm32h7xx_HAL_SDEX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

106
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard.c
View File

@ -231,7 +231,8 @@ void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard);
static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
@ -481,7 +482,8 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@ -603,7 +605,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmart
* @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
@ -754,27 +757,28 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma
(++) HAL_SMARTCARD_RxCpltCallback()
(++) HAL_SMARTCARD_ErrorCallback()
[..]
(#) Non-Blocking mode transfers could be aborted using Abort API's :
(+) HAL_SMARTCARD_Abort()
(+) HAL_SMARTCARD_AbortTransmit()
(+) HAL_SMARTCARD_AbortReceive()
(+) HAL_SMARTCARD_Abort_IT()
(+) HAL_SMARTCARD_AbortTransmit_IT()
(+) HAL_SMARTCARD_AbortReceive_IT()
(++) HAL_SMARTCARD_Abort()
(++) HAL_SMARTCARD_AbortTransmit()
(++) HAL_SMARTCARD_AbortReceive()
(++) HAL_SMARTCARD_Abort_IT()
(++) HAL_SMARTCARD_AbortTransmit_IT()
(++) HAL_SMARTCARD_AbortReceive_IT()
(#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
(+) HAL_SMARTCARD_AbortCpltCallback()
(+) HAL_SMARTCARD_AbortTransmitCpltCallback()
(+) HAL_SMARTCARD_AbortReceiveCpltCallback()
(++) HAL_SMARTCARD_AbortCpltCallback()
(++) HAL_SMARTCARD_AbortTransmitCpltCallback()
(++) HAL_SMARTCARD_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
If user wants to abort it, Abort services should be called by user.
(+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
@ -795,7 +799,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
uint32_t Timeout)
{
uint32_t tickstart;
uint8_t *ptmpdata = pData;
@ -841,7 +846,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui
hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
ptmpdata++;
}
if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK)
if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart,
Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@ -882,7 +888,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
uint32_t Timeout)
{
uint32_t tickstart;
uint8_t *ptmpdata = pData;
@ -1139,7 +1146,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard
hsmartcard->hdmatx->XferAbortCallback = NULL;
/* Enable the SMARTCARD transmit DMA channel */
if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size) == HAL_OK)
if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR,
Size) == HAL_OK)
{
/* Clear the TC flag in the ICR register */
CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
@ -1215,7 +1223,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard,
hsmartcard->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size) == HAL_OK)
if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr,
Size) == HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
@ -1268,7 +1277,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR1,
(USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
/* Disable the SMARTCARD DMA Tx request if enabled */
@ -1326,7 +1337,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
hsmartcard->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@ -1456,7 +1469,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard
hsmartcard->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@ -1484,7 +1499,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
uint32_t abortcplt = 1U;
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR1,
(USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
/* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
@ -1581,7 +1598,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@ -1751,7 +1770,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc
hsmartcard->RxISR = NULL;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@ -1775,7 +1796,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc
hsmartcard->RxISR = NULL;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@ -2206,7 +2229,8 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsma
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Return SMARTCARD handle state */
uint32_t temp1, temp2;
uint32_t temp1;
uint32_t temp2;
temp1 = (uint32_t)hsmartcard->gState;
temp2 = (uint32_t)hsmartcard->RxState;
@ -2271,6 +2295,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
PLL2_ClocksTypeDef pll2_clocks;
PLL3_ClocksTypeDef pll3_clocks;
uint32_t pclk;
/* Check the parameters */
assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
@ -2342,10 +2367,12 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
switch (clocksource)
{
case SMARTCARD_CLOCKSOURCE_D2PCLK1:
tmpreg = (uint16_t)(((HAL_RCC_GetPCLK1Freq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
pclk = HAL_RCC_GetPCLK1Freq();
tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_D2PCLK2:
tmpreg = (uint16_t)(((HAL_RCC_GetPCLK2Freq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
pclk = HAL_RCC_GetPCLK2Freq();
tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_PLL2Q:
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
@ -2480,7 +2507,8 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar
if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
{
/* Wait until TEACK flag is set */
if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart,
SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
{
/* Timeout occurred */
return HAL_TIMEOUT;
@ -2490,7 +2518,8 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar
if ((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
{
/* Wait until REACK flag is set */
if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart,
SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
{
/* Timeout occurred */
return HAL_TIMEOUT;
@ -2517,7 +2546,8 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar
* @param Timeout Timeout duration.
* @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
@ -2720,7 +2750,9 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@ -2767,7 +2799,9 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@ -2827,7 +2861,9 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
hsmartcard->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;

168
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard.h
View File

@ -442,7 +442,7 @@ typedef enum
* @}
*/
/** @defgroup SMARTCARD_ClockPrescaler Clock Prescaler
/** @defgroup SMARTCARD_ClockPrescaler SMARTCARD Clock Prescaler
* @{
*/
#define SMARTCARD_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
@ -729,7 +729,8 @@ typedef enum
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@ -795,7 +796,8 @@ typedef enum
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
&= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
/** @brief Enable the USART associated to the SMARTCARD Handle.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@ -823,6 +825,150 @@ typedef enum
* @param __CLOCKSOURCE__ output variable.
* @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
*/
#if defined(UART9) && defined(USART10)
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if ((__HANDLE__)->Instance == USART1) \
{ \
switch (__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_USART1CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART1CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if ((__HANDLE__)->Instance == USART2) \
{ \
switch (__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_USART2CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART2CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if ((__HANDLE__)->Instance == USART3) \
{ \
switch (__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_USART3CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART3CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if ((__HANDLE__)->Instance == USART6) \
{ \
switch (__HAL_RCC_GET_USART6_SOURCE()) \
{ \
case RCC_USART6CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_USART6CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART6CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART6CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART6CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
break; \
case RCC_USART6CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if ((__HANDLE__)->Instance == USART10) \
{ \
switch (__HAL_RCC_GET_USART10_SOURCE()) \
{ \
case RCC_USART10CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_USART10CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART10CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART10CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART10CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
break; \
case RCC_USART10CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#else
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if ((__HANDLE__)->Instance == USART1) \
@ -938,6 +1084,7 @@ typedef enum
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif /* UART9 && USART10 */
/** @brief Check the Baud rate range.
* @note The maximum Baud Rate is derived from the maximum clock on H7 (100 MHz)
@ -998,7 +1145,8 @@ typedef enum
* @param __CPOL__ SMARTCARD frame polarity.
* @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
*/
#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\
|| ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
/** @brief Ensure that SMARTCARD frame phase is valid.
* @param __CPHA__ SMARTCARD frame phase.
@ -1144,8 +1292,10 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
@ -1157,8 +1307,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma
* @{
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);

19
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard_ex.c
View File

@ -55,11 +55,17 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup SMARTCARDEx_Private_Constants SMARTCARD Extended Private Constants
* @{
*/
/* UART RX FIFO depth */
#define RX_FIFO_DEPTH 8U
/* UART TX FIFO depth */
#define TX_FIFO_DEPTH 8U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
@ -188,8 +194,8 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef
This subsection provides a set of FIFO mode related callback functions.
(#) TX/RX Fifos Callbacks:
(+) HAL_SMARTCARDEx_RxFifoFullCallback()
(+) HAL_SMARTCARDEx_TxFifoEmptyCallback()
(++) HAL_SMARTCARDEx_RxFifoFullCallback()
(++) HAL_SMARTCARDEx_TxFifoEmptyCallback()
@endverbatim
* @{
@ -231,15 +237,16 @@ __weak void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartc
* @}
*/
/** @defgroup SMARTCARD_Exported_Functions_Group3 Extended Peripheral Peripheral Control functions
/** @defgroup SMARTCARDEx_Exported_Functions_Group3 Extended Peripheral FIFO Control functions
* @brief SMARTCARD control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
##### Peripheral FIFO Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the SMARTCARD.
This subsection provides a set of functions allowing to control the SMARTCARD
FIFO feature.
(+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode
(+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode
(+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold
@ -433,7 +440,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hs
* @}
*/
/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended private Functions
/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended Private Functions
* @{
*/

6
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard_ex.h
View File

@ -68,7 +68,7 @@ extern "C" {
* @}
*/
/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARDEx FIFO mode
/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARD FIFO mode
* @brief SMARTCARD FIFO mode
* @{
*/
@ -78,7 +78,7 @@ extern "C" {
* @}
*/
/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARDEx TXFIFO threshold level
/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level
* @brief SMARTCARD TXFIFO level
* @{
*/
@ -92,7 +92,7 @@ extern "C" {
* @}
*/
/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARDEx RXFIFO threshold level
/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level
* @brief SMARTCARD RXFIFO level
* @{
*/

4
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim.c
View File

@ -3747,6 +3747,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @note To output a waveform with a minimum delay user can enable the fast
* mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
* output is forced in response to the edge detection on TIx input,
* without taking in account the comparison.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,

85
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim.h
View File

@ -235,7 +235,12 @@ typedef struct
uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
uint32_t MasterSlaveMode; /*!< Master/slave mode selection
This parameter can be a value of @ref TIM_Master_Slave_Mode */
This parameter can be a value of @ref TIM_Master_Slave_Mode
@note When the Master/slave mode is enabled, the effect of
an event on the trigger input (TRGI) is delayed to allow a
perfect synchronization between the current timer and its
slaves (through TRGO). It is not mandatory in case of timer
synchronization mode. */
} TIM_MasterConfigTypeDef;
/**
@ -1508,12 +1513,62 @@ mode.
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
/**
* @brief Enable fast mode for a given channel.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @note When fast mode is enabled an active edge on the trigger input acts
* like a compare match on CCx output. Delay to sample the trigger
* input and to activate CCx output is reduced to 3 clock cycles.
* @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
* @retval None
*/
#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
/**
* @brief Disable fast mode for a given channel.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @note When fast mode is disabled CCx output behaves normally depending
* on counter and CCRx values even when the trigger is ON. The minimum
* delay to activate CCx output when an active edge occurs on the
* trigger input is 5 clock cycles.
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
/**
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
@ -1876,10 +1931,10 @@ mode.
((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
@ -1888,10 +1943,10 @@ mode.
((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
/**
* @}

32
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim_ex.c
View File

@ -1694,6 +1694,9 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
* @param htim TIM handle
* @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
* contains the BDTR Register configuration information for the TIM peripheral.
* @note Interrupts can be generated when an active level is detected on the
* break input, the break 2 input or the system break input. Break
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
@ -1767,10 +1770,10 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
{
uint32_t tmporx;
uint32_t bkin_enable_mask = 0U;
uint32_t bkin_polarity_mask = 0U;
uint32_t bkin_enable_bitpos = 0U;
uint32_t bkin_polarity_bitpos = 0U;
uint32_t bkin_enable_mask;
uint32_t bkin_polarity_mask;
uint32_t bkin_enable_bitpos;
uint32_t bkin_polarity_bitpos;
/* Check the parameters */
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
@ -1815,12 +1818,20 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
{
bkin_enable_mask = TIM1_AF1_BKDF1BK0E;
bkin_enable_bitpos = 8U;
bkin_polarity_mask = 0U;
bkin_polarity_bitpos = 0U;
break;
}
default:
{
bkin_enable_mask = 0U;
bkin_polarity_mask = 0U;
bkin_enable_bitpos = 0U;
bkin_polarity_bitpos = 0U;
break;
}
}
switch (BreakInput)
{
@ -1882,9 +1893,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
* @arg TIM_TIM1_ETR_GPIO: TIM1_ETR is connected to GPIO
* @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output
* @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output
* @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
* @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
* @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
* @arg TIM_TIM1_ETR_ADC2_AWD1: TIM1_ETR is connected to ADC2 AWD1
* @arg TIM_TIM1_ETR_ADC2_AWD2: TIM1_ETR is connected to ADC2 AWD2
* @arg TIM_TIM1_ETR_ADC2_AWD3: TIM1_ETR is connected to ADC2 AWD3
* @arg TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1
* @arg TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2
* @arg TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3
@ -1969,6 +1980,10 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
* @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
* @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
*
* For TIM12, the parameter can have the following values: (*)
* @arg TIM_TIM12_TI1_GPIO: TIM12 TI1 is connected to GPIO
* @arg TIM_TIM12_TI1_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS
*
* For TIM15, the parameter is one of the following values:
* @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
* @arg TIM_TIM15_TI1_TIM2: TIM15 TI1 is connected to TIM2 CH1
@ -1990,10 +2005,11 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
*
* For TIM17, the parameter can have the following values:
* @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
* @arg TIM_TIM17_TI1_SPDIFFS: TIM17 TI1 is connected to SPDIF FS
* @arg TIM_TIM17_TI1_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS (*)
* @arg TIM_TIM17_TI1_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz
* @arg TIM_TIM17_TI1_MCO1: TIM17 TI1 is connected to MCO1
*
* (*) Value not defined in all devices. \n
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)

37
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim_ex.h
View File

@ -93,9 +93,9 @@ TIMEx_BreakInputConfigTypeDef;
#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */
#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */
#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#define TIM_TIM1_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC2 AWD1 */
#define TIM_TIM1_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC2 AWD2 */
#define TIM_TIM1_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC2 AWD3 */
#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */
#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
#define TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */
@ -103,9 +103,9 @@ TIMEx_BreakInputConfigTypeDef;
#define TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */
#define TIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */
#define TIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */
#define TIM_TIM8_ETR_ADC1_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC1 AWD1 */
#define TIM_TIM8_ETR_ADC1_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC1 AWD2 */
#define TIM_TIM8_ETR_ADC1_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC1 AWD3 */
#define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */
#define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */
#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
#define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */
#define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
#define TIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */
@ -190,6 +190,13 @@ TIMEx_BreakInputConfigTypeDef;
#define TIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5_TI1 is connected to CAN TMP */
#define TIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5_TI1 is connected to CAN RTP */
#if defined(TIM12_TI1_GPIO_SUPPORT)
#define TIM_TIM12_TI1_GPIO 0x00000000U /* !< TIM12 TI1 is connected to GPIO */
#endif /* TIM12_TI1_GPIO_SUPPORT */
#if defined(TIM12_TI1_SPDIF_FS_SUPPORT)
#define TIM_TIM12_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM12 TI1 is connected to SPDIF FS */
#endif /* TIM12_TI1_SPDIF_FS_SUPPORT */
#define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15_TI1 is connected to GPIO */
#define TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15_TI1 is connected to TIM2 CH1 */
#define TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15_TI1 is connected to TIM3 CH1 */
@ -209,8 +216,10 @@ TIMEx_BreakInputConfigTypeDef;
#define TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */
#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */
#define TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 TI1 is connected to RCC LSI */
#define TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 TI1 is connected to RCC LSE */
#if defined(TIM17_TI1_SPDIF_FS_SUPPORT)
#define TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 TI1 is connected to SPDIF FS */
#endif /* TIM17_TI1_SPDIF_FS_SUPPORT */
#define TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 TI1 is connected to RCC HSE 1Mhz */
#define TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */
/**
* @}
@ -285,18 +294,18 @@ TIMEx_BreakInputConfigTypeDef;
((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1))
#define IS_TIM_REMAP(__RREMAP__) (((__RREMAP__) == TIM_TIM1_ETR_GPIO) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC2_AWD1) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC2_AWD2) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC2_AWD3) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\
((__RREMAP__) == TIM_TIM1_ETR_COMP1) ||\
((__RREMAP__) == TIM_TIM1_ETR_COMP2) ||\
((__RREMAP__) == TIM_TIM8_ETR_GPIO) ||\
((__RREMAP__) == TIM_TIM8_ETR_ADC1_AWD1) ||\
((__RREMAP__) == TIM_TIM8_ETR_ADC1_AWD2) ||\
((__RREMAP__) == TIM_TIM8_ETR_ADC1_AWD3) ||\
((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD1) ||\
((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD2) ||\
((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD3) ||\
((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) ||\
((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) ||\
((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) ||\

271
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart.c
View File

@ -334,7 +334,6 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the UART Communication parameters */
@ -354,7 +353,6 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
@ -401,7 +399,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the UART Communication parameters */
@ -424,7 +421,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
/* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
@ -489,7 +485,6 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
huart->gState = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the UART Communication parameters */
@ -515,7 +510,6 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
/* Set the USART LIN Break detection length. */
MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
@ -575,7 +569,6 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
huart->gState = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the UART Communication parameters */
@ -604,7 +597,6 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
/* Set the wake up method by setting the WAKE bit in the CR1 register */
MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
@ -630,7 +622,6 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
huart->Instance->CR1 = 0x0U;
@ -653,7 +644,6 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_RESET;
huart->RxState = HAL_UART_STATE_RESET;
/* Process Unlock */
__HAL_UNLOCK(huart);
return HAL_OK;
@ -712,18 +702,18 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
pUART_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(huart);
if (huart->gState == HAL_UART_STATE_READY)
@ -783,10 +773,8 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_
break;
default :
/* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
@ -804,24 +792,19 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_
break;
default :
/* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(huart);
return status;
@ -852,7 +835,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(huart);
if (HAL_UART_STATE_READY == huart->gState)
@ -912,10 +894,8 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR
break;
default :
/* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
@ -933,24 +913,19 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR
break;
default :
/* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(huart);
return status;
@ -1040,13 +1015,16 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR
/**
* @brief Send an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pData.
* @note When FIFO mode is enabled, writing a data in the TDR register adds one
* data to the TXFIFO. Write operations to the TDR register are performed
* when TXFNF flag is set. From hardware perspective, TXFNF flag and
* TXE are mapped on the same bit-field.
* @param huart UART handle.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be sent.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@ -1064,7 +1042,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE;
@ -1115,7 +1092,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@ -1128,13 +1104,16 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
/**
* @brief Receive an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pData.
* @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
* is not empty. Read operations from the RDR register are performed when
* RXFNE flag is set. From hardware perspective, RXFNE flag and
* RXNE are mapped on the same bit-field.
* @param huart UART handle.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be received.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@ -1153,7 +1132,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE;
@ -1204,7 +1182,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@ -1217,9 +1194,12 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
/**
* @brief Send an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pData.
* @param huart UART handle.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be sent.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@ -1232,7 +1212,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(huart);
huart->pTxBuffPtr = pData;
@ -1256,7 +1235,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
huart->TxISR = UART_TxISR_8BIT_FIFOEN;
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
/* Enable the TX FIFO threshold interrupt */
@ -1274,7 +1252,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
huart->TxISR = UART_TxISR_8BIT;
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
/* Enable the Transmit Data Register Empty interrupt */
@ -1291,9 +1268,12 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
/**
* @brief Receive an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pData.
* @param huart UART handle.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be received.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@ -1306,7 +1286,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(huart);
huart->pRxBuffPtr = pData;
@ -1336,7 +1315,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
huart->RxISR = UART_RxISR_8BIT_FIFOEN;
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
@ -1355,7 +1333,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
huart->RxISR = UART_RxISR_8BIT;
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
@ -1372,9 +1349,12 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
/**
* @brief Send an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pData.
* @param huart UART handle.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be sent.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@ -1387,7 +1367,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(huart);
huart->pTxBuffPtr = pData;
@ -1417,7 +1396,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
/* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(huart);
/* Restore huart->gState to ready */
@ -1429,7 +1407,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
/* Clear the TC flag in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
/* Process Unlocked */
__HAL_UNLOCK(huart);
/* Enable the DMA transfer for transmit request by setting the DMAT bit
@ -1448,9 +1425,12 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
* @brief Receive an amount of data in DMA mode.
* @note When the UART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pData.
* @param huart UART handle.
* @param pData Pointer to data buffer.
* @param Size Amount of data to be received.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@ -1463,7 +1443,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(huart);
huart->pRxBuffPtr = pData;
@ -1492,7 +1471,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
/* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(huart);
/* Restore huart->gState to ready */
@ -1501,7 +1479,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
return HAL_ERROR;
}
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error Interrupt */
@ -1532,7 +1509,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
const HAL_UART_StateTypeDef gstate = huart->gState;
const HAL_UART_StateTypeDef rxstate = huart->RxState;
/* Process Locked */
__HAL_LOCK(huart);
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
@ -1552,7 +1528,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@ -1565,7 +1540,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
*/
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
if (huart->gState == HAL_UART_STATE_BUSY_TX)
@ -1586,7 +1560,6 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@ -1748,7 +1721,6 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
/* Reset Handle ErrorCode to No Error */
huart->ErrorCode = HAL_UART_ERROR_NONE;
return HAL_OK;
@ -2212,7 +2184,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
if (errorflags == 0U)
{
/* UART in mode Receiver ---------------------------------------------------*/
@ -2231,7 +2203,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
/* If some errors occur */
if ((errorflags != 0U)
&& ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))))
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
{
/* UART parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
@ -2267,10 +2239,18 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
huart->ErrorCode |= HAL_UART_ERROR_ORE;
}
/* Call UART Error Call back function if need be --------------------------*/
/* UART Receiver Timeout interrupt occurred ---------------------------------*/
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
huart->ErrorCode |= HAL_UART_ERROR_RTO;
}
/* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
{
/* UART in mode Receiver ---------------------------------------------------*/
/* UART in mode Receiver --------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
@ -2281,11 +2261,14 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
}
}
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
/* If Error is to be considered as blocking :
- Receiver Timeout error in Reception
- Overrun error in Reception
- any error occurs in DMA mode reception
*/
errorcode = huart->ErrorCode;
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
((errorcode & HAL_UART_ERROR_ORE) != 0U))
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
{
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
@ -2551,6 +2534,9 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
===============================================================================
[..]
This subsection provides a set of functions allowing to control the UART.
(+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
(+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
(+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
(+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
(+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
(+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
@ -2564,6 +2550,99 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
* @{
*/
/**
* @brief Update on the fly the receiver timeout value in RTOR register.
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param TimeoutValue receiver timeout value in number of baud blocks. The timeout
* value must be less or equal to 0x0FFFFFFFF.
* @retval None
*/
void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue)
{
if (!(IS_LPUART_INSTANCE(huart->Instance)))
{
assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
}
}
/**
* @brief Enable the UART receiver timeout feature.
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart)
{
if (!(IS_LPUART_INSTANCE(huart->Instance)))
{
if (huart->gState == HAL_UART_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
/* Set the USART RTOEN bit */
SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Disable the UART receiver timeout feature.
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart)
{
if (!(IS_LPUART_INSTANCE(huart->Instance)))
{
if (huart->gState == HAL_UART_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
/* Clear the USART RTOEN bit */
CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Enable UART in mute mode (does not mean UART enters mute mode;
* to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
@ -2572,7 +2651,6 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
*/
HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
@ -2593,7 +2671,6 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
*/
HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
@ -2624,7 +2701,6 @@ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
*/
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
@ -2636,7 +2712,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@ -2649,7 +2724,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
*/
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
@ -2661,7 +2735,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@ -2678,7 +2751,6 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
/* Check the parameters */
assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
@ -2688,7 +2760,6 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@ -2722,7 +2793,8 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
*/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
{
uint32_t temp1, temp2;
uint32_t temp1;
uint32_t temp2;
temp1 = huart->gState;
temp2 = huart->RxState;
@ -2790,6 +2862,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
uint32_t lpuart_ker_ck_pres = 0x00000000U;
PLL2_ClocksTypeDef pll2_clocks;
PLL3_ClocksTypeDef pll3_clocks;
uint32_t pclk;
/* Check the parameters */
assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
@ -2881,7 +2954,6 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
case UART_CLOCKSOURCE_LSE:
lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
@ -2901,7 +2973,8 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
switch (clocksource)
{
case UART_CLOCKSOURCE_D3PCLK1:
usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCCEx_GetD3PCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));
pclk = HAL_RCCEx_GetD3PCLK1Freq();
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_PLL2:
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
@ -2927,7 +3000,6 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
@ -2951,10 +3023,12 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
switch (clocksource)
{
case UART_CLOCKSOURCE_D2PCLK1:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));
pclk = HAL_RCC_GetPCLK1Freq();
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_D2PCLK2:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));
pclk = HAL_RCC_GetPCLK2Freq();
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_PLL2:
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
@ -2980,7 +3054,6 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
@ -3003,10 +3076,12 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
switch (clocksource)
{
case UART_CLOCKSOURCE_D2PCLK1:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));
pclk = HAL_RCC_GetPCLK1Freq();
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_D2PCLK2:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));
pclk = HAL_RCC_GetPCLK2Freq();
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_PLL2:
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
@ -3032,7 +3107,6 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
@ -3175,7 +3249,6 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@ -3190,7 +3263,8 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
@ -3207,6 +3281,26 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
__HAL_UNLOCK(huart);
return HAL_TIMEOUT;
}
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
huart->ErrorCode = HAL_UART_ERROR_RTO;
/* Process Unlocked */
__HAL_UNLOCK(huart);
@ -3214,6 +3308,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_
}
}
}
}
return HAL_OK;
}

52
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart.h
View File

@ -133,8 +133,6 @@ typedef struct
This parameter can be a value of @ref UART_MSB_First. */
} UART_AdvFeatureInitTypeDef;
/**
* @brief HAL UART State definition
* @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition).
@ -190,7 +188,6 @@ typedef enum
UART_CLOCKSOURCE_CSI = 0x20U, /*!< CSI clock source */
UART_CLOCKSOURCE_LSE = 0x40U, /*!< LSE clock source */
UART_CLOCKSOURCE_UNDEFINED = 0x80U /*!< Undefined clock source */
} UART_ClockSourceTypeDef;
/**
@ -335,8 +332,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */
#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
@ -441,11 +440,11 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @}
*/
/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
/** @defgroup UART_Receiver_Timeout UART Receiver Timeout
* @{
*/
#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART receiver timeout disable */
#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART receiver timeout enable */
#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */
#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */
/**
* @}
*/
@ -699,6 +698,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */
#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */
#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */
#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */
#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */
#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */
#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */
@ -749,6 +749,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */
#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */
#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */
#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */
#define UART_IT_ERR 0x0060U /*!< UART error interruption */
@ -773,6 +774,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */
#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */
/**
* @}
*/
@ -826,6 +828,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag
* @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
* @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag
* @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
* @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
* @arg @ref UART_CLEAR_CMF Character Match Clear Flag
@ -894,6 +897,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @arg @ref UART_FLAG_TC Transmission Complete flag
* @arg @ref UART_FLAG_RXNE Receive data register not empty flag
* @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag
* @arg @ref UART_FLAG_RTOF Receiver Timeout flag
* @arg @ref UART_FLAG_IDLE Idle Line detection flag
* @arg @ref UART_FLAG_ORE Overrun Error flag
* @arg @ref UART_FLAG_NE Noise Error flag
@ -920,6 +924,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @arg @ref UART_IT_TC Transmission complete interrupt
* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
* @arg @ref UART_IT_RTO Receive Timeout interrupt
* @arg @ref UART_IT_IDLE Idle line detection interrupt
* @arg @ref UART_IT_PE Parity Error interrupt
* @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error)
@ -947,6 +952,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @arg @ref UART_IT_TC Transmission complete interrupt
* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
* @arg @ref UART_IT_RTO Receive Timeout interrupt
* @arg @ref UART_IT_IDLE Idle line detection interrupt
* @arg @ref UART_IT_PE Parity Error interrupt
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
@ -973,12 +979,14 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @arg @ref UART_IT_TC Transmission complete interrupt
* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
* @arg @ref UART_IT_RTO Receive Timeout interrupt
* @arg @ref UART_IT_IDLE Idle line detection interrupt
* @arg @ref UART_IT_PE Parity Error interrupt
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
/** @brief Check whether the specified UART interrupt source is enabled or not.
* @param __HANDLE__ specifies the UART Handle.
@ -997,6 +1005,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @arg @ref UART_IT_TC Transmission complete interrupt
* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
* @arg @ref UART_IT_RTO Receive Timeout interrupt
* @arg @ref UART_IT_IDLE Idle line detection interrupt
* @arg @ref UART_IT_PE Parity Error interrupt
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
@ -1016,6 +1025,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
* @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag
* @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
* @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
@ -1166,7 +1176,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U) + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))
#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\
+ (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ UART clock.
@ -1174,7 +1185,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U) + ((__BAUD__)/2U)) / (__BAUD__))
#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\
+ ((__BAUD__)/2U)) / (__BAUD__))
/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
* @param __PCLK__ UART clock.
@ -1182,7 +1194,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__))) + ((__BAUD__)/2U)) / (__BAUD__))
#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\
+ ((__BAUD__)/2U)) / (__BAUD__))
/** @brief Check whether or not UART instance is Low Power UART.
* @param __HANDLE__ specifies the UART Handle.
@ -1297,6 +1310,13 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
/** @brief Check the receiver timeout value.
* @note The maximum UART receiver timeout value is 0xFFFFFF.
* @param __TIMEOUTVALUE__ receiver timeout value.
* @retval Test result (TRUE or FALSE)
*/
#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
/**
* @brief Ensure that UART LIN state is valid.
* @param __LIN__ UART LIN state.
@ -1514,7 +1534,8 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
pUART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
@ -1563,6 +1584,10 @@ void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
*/
/* Peripheral Control functions ************************************************/
void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);
HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
@ -1599,7 +1624,8 @@ void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout);
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
/**

6
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart_ex.c
View File

@ -163,7 +163,8 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
* oversampling rate).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
uint32_t DeassertionTime)
{
uint32_t temp;
@ -335,9 +336,6 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
* @{
*/
/**
* @brief By default in multiprocessor mode, when the wake up method is set
* to address mark, the UART handles only 4-bit long addresses detection;

312
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart_ex.h
View File

@ -138,7 +138,8 @@ typedef struct
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
uint32_t DeassertionTime);
/**
* @}
@ -165,7 +166,9 @@ void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
@ -189,6 +192,312 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
* @param __CLOCKSOURCE__ output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
#if defined(UART9) && defined(USART10)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_USART1CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_USART1CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_USART2CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_USART2CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_USART3CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_USART3CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
case RCC_UART4CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_UART4CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_UART4CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_UART4CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART4CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_UART4CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if ((__HANDLE__)->Instance == UART5) \
{ \
switch(__HAL_RCC_GET_UART5_SOURCE()) \
{ \
case RCC_UART5CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_UART5CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_UART5CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_UART5CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART5CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_UART5CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
switch(__HAL_RCC_GET_USART6_SOURCE()) \
{ \
case RCC_USART6CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_USART6CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_USART6CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_USART6CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART6CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_USART6CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART7) \
{ \
switch(__HAL_RCC_GET_UART7_SOURCE()) \
{ \
case RCC_UART7CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_UART7CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_UART7CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_UART7CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART7CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_UART7CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART8) \
{ \
switch(__HAL_RCC_GET_UART8_SOURCE()) \
{ \
case RCC_UART8CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_UART8CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_UART8CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_UART8CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART8CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_UART8CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART9) \
{ \
switch(__HAL_RCC_GET_UART9_SOURCE()) \
{ \
case RCC_UART9CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_UART9CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_UART9CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_UART9CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART9CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_UART9CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART10) \
{ \
switch(__HAL_RCC_GET_USART10_SOURCE()) \
{ \
case RCC_USART10CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_USART10CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_USART10CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_USART10CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART10CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_USART10CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
{ \
case RCC_LPUART1CLKSOURCE_D3PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1; \
break; \
case RCC_LPUART1CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_LPUART1CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_LPUART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_LPUART1CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_LPUART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#else
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
@ -439,6 +748,7 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif /* UART9 && USART10 */
/** @brief Report the UART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.

103
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_usart.c
View File

@ -190,7 +190,8 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma);
static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
static void USART_TxISR_8BIT(USART_HandleTypeDef *husart);
@ -421,7 +422,8 @@ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
* @param pCallback pointer to the Callback function
* @retval HAL status
+ */
HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
pUSART_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@ -732,9 +734,12 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
/**
* @brief Simplex send an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
* @param pTxData Pointer to data buffer.
* @param Size Amount of data to be sent.
* @param pTxData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@ -826,9 +831,12 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
/**
* @brief Receive an amount of data in blocking mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
* @param pRxData Pointer to data buffer.
* @param Size Amount of data to be received.
* @param pRxData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@ -934,14 +942,18 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
/**
* @brief Full-Duplex Send and Receive an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
* @param pTxData pointer to TX data buffer.
* @param pRxData pointer to RX data buffer.
* @param Size amount of data to be sent (same amount to be received).
* @param pTxData pointer to TX data buffer (u8 or u16 data elements).
* @param pRxData pointer to RX data buffer (u8 or u16 data elements).
* @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout)
{
uint8_t *prxdata8bits;
uint16_t *prxdata16bits;
@ -1079,9 +1091,12 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
/**
* @brief Send an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
* @param pTxData pointer to data buffer.
* @param Size amount of data to be sent.
* @param pTxData pointer to data buffer (u8 or u16 data elements).
* @param Size amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
@ -1159,9 +1174,12 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
/**
* @brief Receive an amount of data in interrupt mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
* @param pRxData pointer to data buffer.
* @param Size amount of data to be received.
* @param pRxData pointer to data buffer (u8 or u16 data elements).
* @param Size amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
@ -1259,13 +1277,17 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
/**
* @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
* @param pTxData pointer to TX data buffer.
* @param pRxData pointer to RX data buffer.
* @param Size amount of data to be sent (same amount to be received).
* @param pTxData pointer to TX data buffer (u8 or u16 data elements).
* @param pRxData pointer to RX data buffer (u8 or u16 data elements).
* @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size)
{
if (husart->State == HAL_USART_STATE_READY)
@ -1354,9 +1376,12 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
/**
* @brief Send an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
* @param pTxData pointer to data buffer.
* @param Size amount of data to be sent.
* @param pTxData pointer to data buffer (u8 or u16 data elements).
* @param Size amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
@ -1436,9 +1461,12 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
* @note When the USART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
* @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
* @param pRxData pointer to data buffer.
* @param Size amount of data to be received.
* @param pRxData pointer to data buffer (u8 or u16 data elements).
* @param Size amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
@ -1549,13 +1577,17 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
/**
* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
* @param pTxData pointer to TX data buffer.
* @param pRxData pointer to RX data buffer.
* @param Size amount of data to be received/sent.
* @param pTxData pointer to TX data buffer (u8 or u16 data elements).
* @param pRxData pointer to RX data buffer (u8 or u16 data elements).
* @param Size amount of data elements (u8 or u16) to be received/sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size)
{
HAL_StatusTypeDef status;
uint32_t *tmp;
@ -1825,7 +1857,8 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
{
/* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
/* Disable the USART DMA Tx request if enabled */
@ -1922,7 +1955,8 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
uint32_t abortcplt = 1U;
/* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
/* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
@ -2461,7 +2495,8 @@ void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart)
static void USART_EndTransfer(USART_HandleTypeDef *husart)
{
/* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
/* At end of process, restore husart->State to Ready */
@ -2769,7 +2804,8 @@ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
* @param Timeout timeout duration.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
@ -2805,6 +2841,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
uint32_t usartdiv = 0x00000000;
PLL2_ClocksTypeDef pll2_clocks;
PLL3_ClocksTypeDef pll3_clocks;
uint32_t pclk;
/* Check the parameters */
assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
@ -2851,10 +2888,12 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
switch (clocksource)
{
case USART_CLOCKSOURCE_D2PCLK1:
usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler));
pclk = HAL_RCC_GetPCLK1Freq();
usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
break;
case USART_CLOCKSOURCE_D2PCLK2:
usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler));
pclk = HAL_RCC_GetPCLK2Freq();
usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
break;
case USART_CLOCKSOURCE_PLL2:
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);

163
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_usart.h
View File

@ -594,7 +594,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @arg @ref USART_IT_PE Parity Error interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified USART interrupt source is enabled or not.
* @param __HANDLE__ specifies the USART Handle.
@ -705,13 +706,158 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U) + ((__BAUD__)/2U)) / (__BAUD__))
#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
+ ((__BAUD__)/2U)) / (__BAUD__))
/** @brief Report the USART clock source.
* @param __HANDLE__ specifies the USART Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval the USART clocking source, written in __CLOCKSOURCE__.
*/
#if defined(UART9) && defined(USART10)
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_USART1CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \
break; \
case RCC_USART1CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_USART2CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \
break; \
case RCC_USART2CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_USART3CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \
break; \
case RCC_USART3CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
switch(__HAL_RCC_GET_USART6_SOURCE()) \
{ \
case RCC_USART6CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_USART6CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \
break; \
case RCC_USART6CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3; \
break; \
case RCC_USART6CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART6CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \
break; \
case RCC_USART6CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART10) \
{ \
switch(__HAL_RCC_GET_USART10_SOURCE()) \
{ \
case RCC_USART10CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_USART10CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \
break; \
case RCC_USART10CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3; \
break; \
case RCC_USART10CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART10CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \
break; \
case RCC_USART10CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#else
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
@ -827,6 +973,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif /* UART9 && USART10 */
/** @brief Check USART Baud rate.
* @param __BAUDRATE__ Baudrate specified by the user.
@ -949,7 +1096,8 @@ void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
pUSART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
@ -964,13 +1112,16 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);

6
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_usart_ex.c
View File

@ -54,11 +54,17 @@
#ifdef HAL_USART_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/** @defgroup USARTEx_Private_Constants USARTEx Private Constants
* @{
*/
/* UART RX FIFO depth */
#define RX_FIFO_DEPTH 8U
/* UART TX FIFO depth */
#define TX_FIFO_DEPTH 8U
/**
* @}
*/
/* Private define ------------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/

25
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_adc.h
View File

@ -371,6 +371,14 @@ extern "C" {
#define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
/* Registers addresses with ADC linearity calibration content (programmed during device production, specific to each device) */
#define ADC_LINEAR_CALIB_REG_1_ADDR ((uint32_t*) (0x1FF1EC00UL))
#define ADC_LINEAR_CALIB_REG_2_ADDR ((uint32_t*) (0x1FF1EC04UL))
#define ADC_LINEAR_CALIB_REG_3_ADDR ((uint32_t*) (0x1FF1EC08UL))
#define ADC_LINEAR_CALIB_REG_4_ADDR ((uint32_t*) (0x1FF1EC0CUL))
#define ADC_LINEAR_CALIB_REG_5_ADDR ((uint32_t*) (0x1FF1EC10UL))
#define ADC_LINEAR_CALIB_REG_6_ADDR ((uint32_t*) (0x1FF1EC14UL))
#define ADC_LINEAR_CALIB_REG_COUNT (6UL)
/**
* @}
*/
@ -846,7 +854,6 @@ typedef struct
#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
#define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */
/*!< ADC3 is defined only in the case of STM32H7XX */
#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC3. */
#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC3. */
#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC3. */
@ -1682,6 +1689,8 @@ typedef struct
) \
) \
)
/**
* @brief Helper macro to define ADC analog watchdog parameter:
* define a single channel to monitor with analog watchdog
@ -2077,8 +2086,7 @@ typedef struct
(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
/ __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
(__ADC_RESOLUTION__), \
LL_ADC_RESOLUTION_16B) \
)
LL_ADC_RESOLUTION_16B))
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@ -2565,7 +2573,7 @@ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution
{
MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
}
else /* rev.V */
else /* Rev.V */
{
if(LL_ADC_RESOLUTION_8B == Resolution)
{
@ -2597,7 +2605,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
}
else
else /* Rev.V */
{
if ((uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)) == 0x0000001CUL)
{
@ -4335,7 +4343,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
ADC_JSQR_JSQ2 |
ADC_JSQR_JSQ1 |
ADC_JSQR_JL,
TriggerSource |
(TriggerSource & ADC_JSQR_JEXTSEL) |
(ExternalTriggerEdge * (is_trigger_not_sw)) |
(((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
(((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
@ -5032,7 +5040,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint
* @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
uint32_t AWDThresholdValue)
{
/* Set bits with content of parameter "AWDThresholdValue" with bits */
/* position in register and register position depending on parameters */
@ -6048,7 +6057,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
}
/**
* @brief Get ADC group regular conversion data, range fit for
* @brief Get ADC group injected conversion data, range fit for
* all ADC configurations: all ADC resolutions and
* all oversampling increased data width (for devices
* with feature oversampling).

1
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_gpio.h
View File

@ -713,6 +713,7 @@ __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
WRITE_REG(GPIOx->LCKR, PinMask);
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
/* Read LCKK register. This read is mandatory to complete key lock sequence */
temp = READ_REG(GPIOx->LCKR);
(void) temp;
}

626
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_hrtim.h
View File

@ -281,16 +281,6 @@ static const uint8_t REG_SHIFT_TAB_FLTxE[] =
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup HRTIM_LL_ES_INIT HRTIM Exported Init structure
* @{
*/
/* TO BE COMPLETED */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants
* @{
@ -1007,166 +997,42 @@ static const uint8_t REG_SHIFT_TAB_FLTxE[] =
* @}
*/
/** @defgroup HRTIM_LL_EC_OUTPUTSET_INPUT OUTPUTSET INPUT
/** @defgroup HRTIM_LL_EC_CROSSBAR_INPUT CROSSBAR INPUT
* @{
* @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output.
*/
#define LL_HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */
#define LL_HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transision */
#define LL_HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transision */
/* Timer Events mapping for Timer A */
#define LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its ictive state */
#define LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP2 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV5_TIMCCMP3 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV7_TIMDCMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV9_TIMECMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer B */
#define LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV3_TIMACMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP3 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV7_TIMDCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP1 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV9_TIMECMP2 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer C */
#define LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV9_TIMECMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer D */
#define LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP1 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV6_TIMCCMP3 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV7_TIMCCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV8_TIMECMP1 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV9_TIMECMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer E */
#define LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP3 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV2_TIMACMP4 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV4_TIMBCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP1 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV6_TIMCCMP2 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP1 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV8_TIMDCMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV9_TIMDCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transision */
/**
* @}
*/
/** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
* @{
* @brief Constants defining the events that can be selected to configure the
* set crossbar of a timer output
*/
#define LL_HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */
#define LL_HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
/* Timer Events mapping for Timer A */
#define LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP2 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMCCMP3 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMDCMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMECMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer B */
#define LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMACMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP3 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMDCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP1 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMECMP2 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer C */
#define LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMECMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer D */
#define LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP1 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMCCMP3 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMCCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMECMP1 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMECMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer E */
#define LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP3 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMACMP4 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMBCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP1 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMCCMP2 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP1 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMDCMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMDCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
#define LL_HRTIM_CROSSBAR_NONE 0x00000000U /*!< Reset the output set crossbar */
#define LL_HRTIM_CROSSBAR_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transision */
#define LL_HRTIM_CROSSBAR_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transision */
#define LL_HRTIM_CROSSBAR_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transision */
#define LL_HRTIM_CROSSBAR_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transision */
#define LL_HRTIM_CROSSBAR_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transision */
#define LL_HRTIM_CROSSBAR_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transision */
#define LL_HRTIM_CROSSBAR_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transision */
#define LL_HRTIM_CROSSBAR_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transision */
#define LL_HRTIM_CROSSBAR_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transision */
#define LL_HRTIM_CROSSBAR_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transision */
#define LL_HRTIM_CROSSBAR_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transision */
#define LL_HRTIM_CROSSBAR_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces an output level transision */
#define LL_HRTIM_CROSSBAR_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces an output level transision */
#define LL_HRTIM_CROSSBAR_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces an output level transision */
#define LL_HRTIM_CROSSBAR_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces an output level transision */
#define LL_HRTIM_CROSSBAR_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces an output level transision */
#define LL_HRTIM_CROSSBAR_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces an output level transision */
#define LL_HRTIM_CROSSBAR_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces an output level transision */
#define LL_HRTIM_CROSSBAR_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces an output level transision */
#define LL_HRTIM_CROSSBAR_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces an output level transision */
#define LL_HRTIM_CROSSBAR_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transision */
#define LL_HRTIM_CROSSBAR_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transision */
#define LL_HRTIM_CROSSBAR_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transision */
#define LL_HRTIM_CROSSBAR_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transision */
#define LL_HRTIM_CROSSBAR_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transision */
#define LL_HRTIM_CROSSBAR_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transision */
#define LL_HRTIM_CROSSBAR_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transision */
#define LL_HRTIM_CROSSBAR_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transision */
#define LL_HRTIM_CROSSBAR_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transision */
#define LL_HRTIM_CROSSBAR_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transision */
#define LL_HRTIM_CROSSBAR_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transision */
/**
* @}
*/
@ -2169,7 +2035,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t A
*/
__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
{
register uint32_t shift = ((3U * ADCTrig) & 0x1FU);
register const uint32_t shift = ((3U * ADCTrig) & 0x1FU);
return (READ_BIT(HRTIMx->sCommonRegs.CR1, (uint32_t)(HRTIM_CR1_ADC1USRC) << shift) >> shift);
}
@ -5501,75 +5367,38 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint3
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @param SetSrc This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_OUTPUTSET_NONE
* @arg @ref LL_HRTIM_OUTPUTSET_RESYNC
* @arg @ref LL_HRTIM_OUTPUTSET_TIMPER
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERPER
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMECMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMECMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMCCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_1
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_2
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_3
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_4
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_5
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_6
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_7
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_8
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_9
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_10
* @arg @ref LL_HRTIM_OUTPUTSET_UPDATE
* (source = TIMy and destination = TIMx, Compare Unit = CMPz).
* @arg @ref LL_HRTIM_CROSSBAR_NONE
* @arg @ref LL_HRTIM_CROSSBAR_RESYNC
* @arg @ref LL_HRTIM_CROSSBAR_TIMPER
* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
* @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
* @arg @ref LL_HRTIM_CROSSBAR_EEV_1
* @arg @ref LL_HRTIM_CROSSBAR_EEV_2
* @arg @ref LL_HRTIM_CROSSBAR_EEV_3
* @arg @ref LL_HRTIM_CROSSBAR_EEV_4
* @arg @ref LL_HRTIM_CROSSBAR_EEV_5
* @arg @ref LL_HRTIM_CROSSBAR_EEV_6
* @arg @ref LL_HRTIM_CROSSBAR_EEV_7
* @arg @ref LL_HRTIM_CROSSBAR_EEV_8
* @arg @ref LL_HRTIM_CROSSBAR_EEV_9
* @arg @ref LL_HRTIM_CROSSBAR_EEV_10
* @arg @ref LL_HRTIM_CROSSBAR_UPDATE
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)
@ -5659,75 +5488,38 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @retval SetSrc This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_OUTPUTSET_NONE
* @arg @ref LL_HRTIM_OUTPUTSET_RESYNC
* @arg @ref LL_HRTIM_OUTPUTSET_TIMPER
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERPER
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMECMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMECMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMCCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_1
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_2
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_3
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_4
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_5
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_6
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_7
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_8
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_9
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_10
* @arg @ref LL_HRTIM_OUTPUTSET_UPDATE
* (source = TIMy and destination = TIMx, Compare Unit = CMPz).
* @arg @ref LL_HRTIM_CROSSBAR_NONE
* @arg @ref LL_HRTIM_CROSSBAR_RESYNC
* @arg @ref LL_HRTIM_CROSSBAR_TIMPER
* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
* @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
* @arg @ref LL_HRTIM_CROSSBAR_EEV_1
* @arg @ref LL_HRTIM_CROSSBAR_EEV_2
* @arg @ref LL_HRTIM_CROSSBAR_EEV_3
* @arg @ref LL_HRTIM_CROSSBAR_EEV_4
* @arg @ref LL_HRTIM_CROSSBAR_EEV_5
* @arg @ref LL_HRTIM_CROSSBAR_EEV_6
* @arg @ref LL_HRTIM_CROSSBAR_EEV_7
* @arg @ref LL_HRTIM_CROSSBAR_EEV_8
* @arg @ref LL_HRTIM_CROSSBAR_EEV_9
* @arg @ref LL_HRTIM_CROSSBAR_EEV_10
* @arg @ref LL_HRTIM_CROSSBAR_UPDATE
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
@ -5816,75 +5608,38 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uin
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @param ResetSrc This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_OUTPUTRESET_NONE
* @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMECMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMECMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMCCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
* @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
* (source = TIMy and destination = TIMx, Compare Unit = CMPz).
* @arg @ref LL_HRTIM_CROSSBAR_NONE
* @arg @ref LL_HRTIM_CROSSBAR_RESYNC
* @arg @ref LL_HRTIM_CROSSBAR_TIMPER
* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
* @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
* @arg @ref LL_HRTIM_CROSSBAR_EEV_1
* @arg @ref LL_HRTIM_CROSSBAR_EEV_2
* @arg @ref LL_HRTIM_CROSSBAR_EEV_3
* @arg @ref LL_HRTIM_CROSSBAR_EEV_4
* @arg @ref LL_HRTIM_CROSSBAR_EEV_5
* @arg @ref LL_HRTIM_CROSSBAR_EEV_6
* @arg @ref LL_HRTIM_CROSSBAR_EEV_7
* @arg @ref LL_HRTIM_CROSSBAR_EEV_8
* @arg @ref LL_HRTIM_CROSSBAR_EEV_9
* @arg @ref LL_HRTIM_CROSSBAR_EEV_10
* @arg @ref LL_HRTIM_CROSSBAR_UPDATE
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc)
@ -5974,75 +5729,38 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint3
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @retval ResetSrc This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_OUTPUTRESET_NONE
* @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMECMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMECMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMCCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
* @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
* (source = TIMy and destination = TIMx, Compare Unit = CMPz).
* @arg @ref LL_HRTIM_CROSSBAR_NONE
* @arg @ref LL_HRTIM_CROSSBAR_RESYNC
* @arg @ref LL_HRTIM_CROSSBAR_TIMPER
* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
* @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
* @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
* @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
* @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
* @arg @ref LL_HRTIM_CROSSBAR_EEV_1
* @arg @ref LL_HRTIM_CROSSBAR_EEV_2
* @arg @ref LL_HRTIM_CROSSBAR_EEV_3
* @arg @ref LL_HRTIM_CROSSBAR_EEV_4
* @arg @ref LL_HRTIM_CROSSBAR_EEV_5
* @arg @ref LL_HRTIM_CROSSBAR_EEV_6
* @arg @ref LL_HRTIM_CROSSBAR_EEV_7
* @arg @ref LL_HRTIM_CROSSBAR_EEV_8
* @arg @ref LL_HRTIM_CROSSBAR_EEV_9
* @arg @ref LL_HRTIM_CROSSBAR_EEV_10
* @arg @ref LL_HRTIM_CROSSBAR_UPDATE
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
@ -6611,7 +6329,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t O
* @arg @ref LL_HRTIM_EVENT_9
* @arg @ref LL_HRTIM_EVENT_10
* @param Configuration This parameter must be a combination of all the following values:
* @arg @ref LL_HRTIM_EE_SRC_1 or @ref LL_HRTIM_EE_SRC_2 or @ref LL_HRTIM_EE_SRC_3 or @ref LL_HRTIM_EE_SRC_4
* @arg External event source 1 or External event source 2 or External event source 3 or External event source 4
* @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW
* @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
* @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE
@ -6651,10 +6369,10 @@ __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, u
* @arg @ref LL_HRTIM_EVENT_9
* @arg @ref LL_HRTIM_EVENT_10
* @param Src This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_SRC_1
* @arg @ref LL_HRTIM_EE_SRC_2
* @arg @ref LL_HRTIM_EE_SRC_3
* @arg @ref LL_HRTIM_EE_SRC_4
* @arg External event source 1
* @arg External event source 2
* @arg External event source 3
* @arg External event source 4
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src)
@ -6690,10 +6408,10 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, u
* @arg @ref LL_HRTIM_EVENT_9
* @arg @ref LL_HRTIM_EVENT_10
* @retval EventSrc This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_SRC_1
* @arg @ref LL_HRTIM_EE_SRC_2
* @arg @ref LL_HRTIM_EE_SRC_3
* @arg @ref LL_HRTIM_EE_SRC_4
* @arg External event source 1
* @arg External event source 2
* @arg External event source 3
* @arg External event source 4
*/
__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event)
{
@ -7386,7 +7104,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
__STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
REG_OFFSET_TAB_FLTINR[iFault]));
return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) ==
(HRTIM_IER_FLT1)) ? 1UL : 0UL);

16
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_hsem.h
View File

@ -84,6 +84,9 @@ extern "C" {
#define LL_HSEM_SEMAPHORE_13 HSEM_C1IER_ISE13
#define LL_HSEM_SEMAPHORE_14 HSEM_C1IER_ISE14
#define LL_HSEM_SEMAPHORE_15 HSEM_C1IER_ISE15
#if (HSEM_SEMID_MAX == 15)
#define LL_HSEM_SEMAPHORE_ALL 0x0000FFFFU
#else /* HSEM_SEMID_MAX == 31 */
#define LL_HSEM_SEMAPHORE_16 HSEM_C1IER_ISE16
#define LL_HSEM_SEMAPHORE_17 HSEM_C1IER_ISE17
#define LL_HSEM_SEMAPHORE_18 HSEM_C1IER_ISE18
@ -101,6 +104,7 @@ extern "C" {
#define LL_HSEM_SEMAPHORE_30 HSEM_C1IER_ISE30
#define LL_HSEM_SEMAPHORE_31 HSEM_C1IER_ISE31
#define LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU
#endif /* HSEM_SEMID_MAX == 15 */
/**
* @}
*/
@ -346,6 +350,8 @@ __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uin
* @arg @ref LL_HSEM_SEMAPHORE_30
* @arg @ref LL_HSEM_SEMAPHORE_31
* @arg @ref LL_HSEM_SEMAPHORE_ALL
* @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
* depends on devices.
* @retval None
*/
__STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
@ -391,6 +397,8 @@ __STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t Semaph
* @arg @ref LL_HSEM_SEMAPHORE_30
* @arg @ref LL_HSEM_SEMAPHORE_31
* @arg @ref LL_HSEM_SEMAPHORE_ALL
* @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
* depends on devices.
* @retval None
*/
__STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
@ -436,6 +444,8 @@ __STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t Semap
* @arg @ref LL_HSEM_SEMAPHORE_30
* @arg @ref LL_HSEM_SEMAPHORE_31
* @arg @ref LL_HSEM_SEMAPHORE_ALL
* @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
* depends on devices.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
@ -625,6 +635,8 @@ __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t
* @arg @ref LL_HSEM_SEMAPHORE_30
* @arg @ref LL_HSEM_SEMAPHORE_31
* @arg @ref LL_HSEM_SEMAPHORE_ALL
* @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
* depends on devices.
* @retval None
*/
__STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
@ -670,6 +682,8 @@ __STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t Semap
* @arg @ref LL_HSEM_SEMAPHORE_30
* @arg @ref LL_HSEM_SEMAPHORE_31
* @arg @ref LL_HSEM_SEMAPHORE_ALL
* @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
* depends on devices.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
@ -715,6 +729,8 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_
* @arg @ref LL_HSEM_SEMAPHORE_30
* @arg @ref LL_HSEM_SEMAPHORE_31
* @arg @ref LL_HSEM_SEMAPHORE_ALL
* @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
* depends on devices.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)

21
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lptim.c
View File

@ -13,7 +13,8 @@
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* ******************************************************************************
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
@ -109,21 +110,27 @@ ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx)
LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM2);
LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM2);
}
#if defined(LPTIM3)
else if (LPTIMx == LPTIM3)
{
LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM3);
LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM3);
}
#endif /* LPTIM3 */
#if defined(LPTIM4)
else if (LPTIMx == LPTIM4)
{
LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM4);
LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM4);
}
#endif /* LPTIM4 */
#if defined(LPTIM5)
else if (LPTIMx == LPTIM5)
{
LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM5);
LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM5);
}
#endif /* LPTIM5 */
else
{
result = ERROR;
@ -233,11 +240,17 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
case LPTIM2_BASE:
tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
break;
#if defined(LPTIM3)&&defined(LPTIM4)&&defined(LPTIM5)
case LPTIM3_BASE:
case LPTIM4_BASE:
case LPTIM5_BASE:
tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE);
break;
#elif defined(LPTIM3)
case LPTIM3_BASE:
tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE);
break;
#endif /* LPTIM3 && LPTIM4 && LPTIM5 */
default:
break;
}
@ -266,11 +279,17 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
case LPTIM2_BASE:
LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK4);
break;
#if defined(LPTIM3)&&defined(LPTIM4)&&defined(LPTIM5)
case LPTIM3_BASE:
case LPTIM4_BASE:
case LPTIM5_BASE:
LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE_PCLK4);
break;
#elif defined(LPTIM3)
case LPTIM3_BASE:
LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE_PCLK4);
break;
#endif /* LPTIM3 && LPTIM4 && LPTIM5*/
default:
break;
}

5
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lptim.h
View File

@ -283,7 +283,6 @@ typedef struct
* @}
*/
/**
* @}
*/
@ -304,7 +303,7 @@ typedef struct
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->(__REG__), (__VALUE__))
#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in LPTIM register
@ -312,7 +311,7 @@ typedef struct
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->(__REG__))
#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/

2
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lpuart.c
View File

@ -26,7 +26,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32H7xx_LL_Driver
* @{

12
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lpuart.h
View File

@ -442,7 +442,8 @@ typedef struct
* @param __BAUDRATE__ Baud Rate value to achieve
* @retval LPUARTDIV value to be used for BRR register filling
*/
#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL)\
+ (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
/**
* @}
@ -1341,7 +1342,8 @@ __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
* @param BaudRate Baud Rate
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate)
__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
uint32_t BaudRate)
{
LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
}
@ -1380,6 +1382,10 @@ __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t
{
brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
}
else
{
brrresult = 0x0UL;
}
return (brrresult);
}
@ -2508,7 +2514,7 @@ __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32
*/
__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
{
return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
}
/**

26
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_rcc.h
View File

@ -69,23 +69,23 @@ extern const uint8_t LL_RCC_PrescTable[16];
#define D2CCIP2 0x8UL
#define D3CCIP 0xCUL
#define REG_SHIFT 0U
#define POS_SHIFT 8U
#define CONFIG_SHIFT 16U
#define MASK_SHIFT 24U
#define LL_RCC_REG_SHIFT 0U
#define LL_RCC_POS_SHIFT 8U
#define LL_RCC_CONFIG_SHIFT 16U
#define LL_RCC_MASK_SHIFT 24U
#define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> POS_SHIFT ) & 0x1FUL)
#define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL)
#define LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> MASK_SHIFT ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
#define LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
#define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
#define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
#define LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> REG_SHIFT ) & 0xFFUL)
#define LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL)
#define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << MASK_SHIFT) | \
(( __POS__ ) << POS_SHIFT) | \
(( __REG__ ) << REG_SHIFT) | \
(((__CLK__) >> (__POS__)) << CONFIG_SHIFT)))
#define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \
(( __POS__ ) << LL_RCC_POS_SHIFT) | \
(( __REG__ ) << LL_RCC_REG_SHIFT) | \
(((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT)))
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RCC_LL_Private_Macros RCC Private Macros
@ -2642,7 +2642,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
{
register const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph)));
return (uint32_t) (Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << CONFIG_SHIFT) );
return (uint32_t) (Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT) );
}
/**

22
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_sdmmc.c
View File

@ -302,10 +302,6 @@ HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
/* Set power state to ON */
SDMMCx->POWER |= SDMMC_POWER_PWRCTRL;
/* 1ms: required power up waiting time before starting the SD initialization
sequence */
HAL_Delay(2);
return HAL_OK;
}
@ -741,7 +737,7 @@ uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx)
uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = 0;
sdmmc_cmdinit.Argument = 0U;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
@ -765,7 +761,7 @@ uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx)
uint32_t errorstate;
/* Send CMD12 STOP_TRANSMISSION */
sdmmc_cmdinit.Argument = 0;
sdmmc_cmdinit.Argument = 0U;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
@ -819,7 +815,7 @@ uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx)
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
sdmmc_cmdinit.Argument = 0;
sdmmc_cmdinit.Argument = 0U;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_NO;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
@ -949,7 +945,7 @@ uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx)
uint32_t errorstate;
/* Send CMD51 SD_APP_SEND_SCR */
sdmmc_cmdinit.Argument = 0;
sdmmc_cmdinit.Argument = 0U;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
@ -973,7 +969,7 @@ uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx)
uint32_t errorstate;
/* Send CMD2 ALL_SEND_CID */
sdmmc_cmdinit.Argument = 0;
sdmmc_cmdinit.Argument = 0U;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
@ -1023,7 +1019,7 @@ uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA)
uint32_t errorstate;
/* Send CMD3 SD_CMD_SET_REL_ADDR */
sdmmc_cmdinit.Argument = 0;
sdmmc_cmdinit.Argument = 0U;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
@ -1070,7 +1066,7 @@ uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx)
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
sdmmc_cmdinit.Argument = 0;
sdmmc_cmdinit.Argument = 0U;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
@ -1086,7 +1082,7 @@ uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx)
/**
* @brief Sends host capacity support information and activates the card's
* initialization process. Send SDMMC_CMD_SEND_OP_COND command
* @param SDIOx: Pointer to SDIO register base
* @param SDMMCx: Pointer to SDMMC register base
* @parame Argument: Argument used for the command
* @retval HAL status
*/
@ -1110,7 +1106,7 @@ uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
/**
* @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand
* @param SDIOx: Pointer to SDIO register base
* @param SDMMCx: Pointer to SDMMC register base
* @parame Argument: Argument used for the command
* @retval HAL status
*/

25
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_sdmmc.h
View File

@ -46,7 +46,7 @@
*/
typedef struct
{
uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
uint32_t ClockEdge; /*!< Specifies the SDMMC_CCK clock transition on which Data and Command change.
This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
@ -62,6 +62,10 @@ typedef struct
uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */
#if (USE_SD_TRANSCEIVER != 0U)
uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Tranceiver/Switcher.
This parameter can be a value of @ref SDMMC_LL_TRANCEIVER_PRESENT */
#endif /* USE_SD_TRANSCEIVER */
}SDMMC_InitTypeDef;
@ -397,6 +401,16 @@ typedef struct
* @}
*/
/** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Tranceiver Present
* @{
*/
#define SDMMC_TRANSCEIVER_UNKNOWN ((uint32_t)0x00000000U)
#define SDMMC_TRANSCEIVER_NOT_PRESENT ((uint32_t)0x00000001U)
#define SDMMC_TRANSCEIVER_PRESENT ((uint32_t)0x00000002U)
/**
* @}
*/
/** @defgroup SDMMC_LL_Command_Index Command Index
* @{
@ -778,8 +792,8 @@ typedef struct
* @arg SDMMC_FLAG_DHOLD: Data transfer Hold
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
* @arg SDMMC_FLAG_CPSMACT: Command path state machine active
* @arg SDMMC_FLAG_DPSMACT: Data path state machine active
* @arg SDMMC_FLAG_CPSMACT: Command path state machine active
* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
@ -846,22 +860,16 @@ typedef struct
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
* @arg SDMMC_IT_DPSMACT: Data path state machine active interrupt
* @arg SDMMC_IT_CPSMACT: Command path state machine active interrupt
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDMMC_IT_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
* @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
* @retval The new state of SDMMC_IT (SET or RESET).
*/
@ -890,7 +898,6 @@ typedef struct
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
* @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
* @retval None
*/

2
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_spi.c
View File

@ -28,7 +28,7 @@
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0)
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32H7xx_LL_Driver

63
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_system.h
View File

@ -1975,6 +1975,69 @@ __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
}
/**
* @}
*/
#if defined(DUAL_CORE)
/** @defgroup SYSTEM_LL_EF_ART ART
* @{
*/
/**
* @brief Enable the Cortex-M4 ART cache.
* @rmtoll ART_CTR EN LL_ART_Enable
* @retval None
*/
__STATIC_INLINE void LL_ART_Enable(void)
{
SET_BIT(ART->CTR, ART_CTR_EN);
}
/**
* @brief Disable the Cortex-M4 ART cache.
* @rmtoll ART_CTR EN LL_ART_Disable
* @retval None
*/
__STATIC_INLINE void LL_ART_Disable(void)
{
CLEAR_BIT(ART->CTR, ART_CTR_EN);
}
/**
* @brief Check if the Cortex-M4 ART cache is enabled
* @rmtoll ART_CTR EN LL_ART_IsEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ART_IsEnabled(void)
{
return ((READ_BIT(ART->CTR, ART_CTR_EN) == ART_CTR_EN) ? 1UL : 0UL);
}
/**
* @brief Set the Cortex-M4 ART cache Base Address.
* @rmtoll ART_CTR PCACHEADDR LL_ART_SetBaseAddress
* @param BaseAddress Specifies the Base address of 1 Mbyte address page (cacheable page)
from which the ART accelerator loads code to the cache.
* @retval None
*/
__STATIC_INLINE void LL_ART_SetBaseAddress(uint32_t BaseAddress)
{
MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((BaseAddress) >> 12U) & 0x000FFF00UL));
}
/**
* @brief Get the Cortex-M4 ART cache Base Address.
* @rmtoll ART_CTR PCACHEADDR LL_ART_GetBaseAddress
* @retval the Base address of 1 Mbyte address page (cacheable page)
from which the ART accelerator loads code to the cache
*/
__STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void)
{
return (uint32_t)(READ_BIT(ART->CTR, ART_CTR_PCACHEADDR) << 12U);
}
#endif /* DUAL_CORE */
/**
* @}
*/

4
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_tim.c
View File

@ -730,9 +730,9 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
* and DTG[7:0] can be write-locked depending on the LOCK configuration, it
* can be necessary to configure all of them during the first write access to
* the TIMx_BDTR register.
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @param TIMx Timer Instance
* @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)

166
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_tim.h
View File

@ -1362,7 +1362,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
/**
* @brief Set the timer counter counting mode.
* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
@ -1386,7 +1386,7 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo
/**
* @brief Get actual counter mode.
* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
@ -1439,7 +1439,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
/**
* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
* @rmtoll CR1 CKD LL_TIM_SetClockDivision
@ -1457,7 +1457,7 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi
/**
* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
* @rmtoll CR1 CKD LL_TIM_GetClockDivision
@ -1474,7 +1474,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
/**
* @brief Set the counter value.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @rmtoll CNT CNT LL_TIM_SetCounter
* @param TIMx Timer instance
@ -1488,7 +1488,7 @@ __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
/**
* @brief Get the counter value.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @rmtoll CNT CNT LL_TIM_GetCounter
* @param TIMx Timer instance
@ -1542,7 +1542,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
/**
* @brief Set the auto-reload value.
* @note The counter is blocked while the auto-reload value is null.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
* @rmtoll ARR ARR LL_TIM_SetAutoReload
@ -1558,7 +1558,7 @@ __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload
/**
* @brief Get the auto-reload value.
* @rmtoll ARR ARR LL_TIM_GetAutoReload
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @param TIMx Timer instance
* @retval Auto-reload value
@ -1571,7 +1571,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
/**
* @brief Set the repetition counter value.
* @note For advanced timer instances RepetitionCounter can be up to 65535.
* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
* @param TIMx Timer instance
@ -1585,7 +1585,7 @@ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t Rep
/**
* @brief Get the repetition counter value.
* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
* @param TIMx Timer instance
@ -1631,7 +1631,7 @@ __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
* they are updated only when a commutation event (COM) occurs.
* @note Only on channels that have a complementary output.
* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
* @param TIMx Timer instance
@ -1644,7 +1644,7 @@ __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
/**
* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
* @param TIMx Timer instance
@ -1657,7 +1657,7 @@ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
/**
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
* @param TIMx Timer instance
@ -1701,7 +1701,7 @@ __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
/**
* @brief Set the lock level to freeze the
* configuration of several capture/compare parameters.
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* the lock mechanism is supported by a timer instance.
* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
* @param TIMx Timer instance
@ -2003,7 +2003,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann
/**
* @brief Set the IDLE state of an output channel
* @note This function is significant only for the timer instances
* supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
* supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
* can be used to check whether or not a timer instance provides
* a break input.
* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
@ -2227,7 +2227,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t
/**
* @brief Enable clearing the output channel on an external event.
* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
@ -2254,7 +2254,7 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
/**
* @brief Disable clearing the output channel on an external event.
* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
@ -2283,7 +2283,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
* @note This function enables clearing the output channel on an external event.
* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
@ -2311,7 +2311,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Ch
/**
* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* dead-time insertion feature is supported by a timer instance.
* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
@ -2327,9 +2327,9 @@ __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
/**
* @brief Set compare value for output channel 1 (TIMx_CCR1).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* output channel 1 is supported by a timer instance.
* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
* @param TIMx Timer instance
@ -2344,9 +2344,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t Compare
/**
* @brief Set compare value for output channel 2 (TIMx_CCR2).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* output channel 2 is supported by a timer instance.
* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
* @param TIMx Timer instance
@ -2361,9 +2361,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t Compare
/**
* @brief Set compare value for output channel 3 (TIMx_CCR3).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* output channel is supported by a timer instance.
* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
* @param TIMx Timer instance
@ -2378,9 +2378,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t Compare
/**
* @brief Set compare value for output channel 4 (TIMx_CCR4).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* output channel 4 is supported by a timer instance.
* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
* @param TIMx Timer instance
@ -2394,7 +2394,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t Compare
/**
* @brief Set compare value for output channel 5 (TIMx_CCR5).
* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
* output channel 5 is supported by a timer instance.
* @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
* @param TIMx Timer instance
@ -2408,7 +2408,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t Compare
/**
* @brief Set compare value for output channel 6 (TIMx_CCR6).
* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
* output channel 6 is supported by a timer instance.
* @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
* @param TIMx Timer instance
@ -2423,9 +2423,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t Compare
/**
* @brief Get compare value (TIMx_CCR1) set for output channel 1.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* output channel 1 is supported by a timer instance.
* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
* @param TIMx Timer instance
@ -2439,9 +2439,9 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
/**
* @brief Get compare value (TIMx_CCR2) set for output channel 2.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* output channel 2 is supported by a timer instance.
* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
* @param TIMx Timer instance
@ -2455,9 +2455,9 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
/**
* @brief Get compare value (TIMx_CCR3) set for output channel 3.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* output channel 3 is supported by a timer instance.
* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
* @param TIMx Timer instance
@ -2471,9 +2471,9 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
/**
* @brief Get compare value (TIMx_CCR4) set for output channel 4.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* output channel 4 is supported by a timer instance.
* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
* @param TIMx Timer instance
@ -2486,7 +2486,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
/**
* @brief Get compare value (TIMx_CCR5) set for output channel 5.
* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
* output channel 5 is supported by a timer instance.
* @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
* @param TIMx Timer instance
@ -2499,7 +2499,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
/**
* @brief Get compare value (TIMx_CCR6) set for output channel 6.
* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
* output channel 6 is supported by a timer instance.
* @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
* @param TIMx Timer instance
@ -2512,7 +2512,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
/**
* @brief Select on which reference signal the OC5REF is combined to.
* @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the combined 3-phase PWM mode.
* @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
@ -2816,7 +2816,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann
/**
* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
* @param TIMx Timer instance
@ -2829,7 +2829,7 @@ __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
/**
* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
* @param TIMx Timer instance
@ -2842,7 +2842,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
/**
* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
* @param TIMx Timer instance
@ -2856,9 +2856,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
/**
* @brief Get captured value for input channel 1.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* input channel 1 is supported by a timer instance.
* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
* @param TIMx Timer instance
@ -2872,9 +2872,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
/**
* @brief Get captured value for input channel 2.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* input channel 2 is supported by a timer instance.
* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
* @param TIMx Timer instance
@ -2888,9 +2888,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
/**
* @brief Get captured value for input channel 3.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* input channel 3 is supported by a timer instance.
* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
* @param TIMx Timer instance
@ -2904,9 +2904,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
/**
* @brief Get captured value for input channel 4.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* input channel 4 is supported by a timer instance.
* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
* @param TIMx Timer instance
@ -2927,7 +2927,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
/**
* @brief Enable external clock mode 2.
* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
* @param TIMx Timer instance
@ -2940,7 +2940,7 @@ __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
/**
* @brief Disable external clock mode 2.
* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
* @param TIMx Timer instance
@ -2953,7 +2953,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
/**
* @brief Indicate whether external clock mode 2 is enabled.
* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
* @param TIMx Timer instance
@ -2970,9 +2970,9 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
* function. This timer input must be configured by calling
* the @ref LL_TIM_IC_Config() function.
* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode1.
* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
* SMCR ECE LL_TIM_SetClockSource
@ -2990,7 +2990,7 @@ __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSour
/**
* @brief Set the encoder interface mode.
* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the encoder mode.
* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
* @param TIMx Timer instance
@ -3014,7 +3014,7 @@ __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMo
*/
/**
* @brief Set the trigger output (TRGO) used for timer synchronization .
* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance can operate as a master timer.
* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
* @param TIMx Timer instance
@ -3036,7 +3036,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSy
/**
* @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
* @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
* @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance can be used for ADC synchronization.
* @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
* @param TIMx Timer Instance
@ -3066,7 +3066,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSyn
/**
* @brief Set the synchronization mode of a slave timer.
* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
* @param TIMx Timer instance
@ -3085,7 +3085,7 @@ __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
/**
* @brief Set the selects the trigger input to be used to synchronize the counter.
* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR TS LL_TIM_SetTriggerInput
* @param TIMx Timer instance
@ -3112,7 +3112,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerI
/**
* @brief Enable the Master/Slave mode.
* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
* @param TIMx Timer instance
@ -3125,7 +3125,7 @@ __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
/**
* @brief Disable the Master/Slave mode.
* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
* @param TIMx Timer instance
@ -3138,7 +3138,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
/**
* @brief Indicates whether the Master/Slave mode is enabled.
* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
* @param TIMx Timer instance
@ -3151,7 +3151,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
/**
* @brief Configure the external trigger (ETR) input.
* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an external trigger input.
* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
* SMCR ETPS LL_TIM_ConfigETR\n
@ -3199,7 +3199,7 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u
*/
/**
* @brief Enable the break function.
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR BKE LL_TIM_EnableBRK
* @param TIMx Timer instance
@ -3214,7 +3214,7 @@ __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
* @brief Disable the break function.
* @rmtoll BDTR BKE LL_TIM_DisableBRK
* @param TIMx Timer instance
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @retval None
*/
@ -3225,7 +3225,7 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
/**
* @brief Configure the break input.
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
* BDTR BKF LL_TIM_ConfigBRK
@ -3260,7 +3260,7 @@ __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
/**
* @brief Enable the break 2 function.
* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @rmtoll BDTR BK2E LL_TIM_EnableBRK2
* @param TIMx Timer instance
@ -3273,7 +3273,7 @@ __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
/**
* @brief Disable the break 2 function.
* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @rmtoll BDTR BK2E LL_TIM_DisableBRK2
* @param TIMx Timer instance
@ -3286,7 +3286,7 @@ __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
/**
* @brief Configure the break 2 input.
* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
* BDTR BK2F LL_TIM_ConfigBRK2
@ -3320,7 +3320,7 @@ __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarit
/**
* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
* BDTR OSSR LL_TIM_SetOffStates
@ -3340,7 +3340,7 @@ __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdl
/**
* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
* @param TIMx Timer instance
@ -3353,7 +3353,7 @@ __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
/**
* @brief Disable automatic output (MOE can be set only by software).
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
* @param TIMx Timer instance
@ -3366,7 +3366,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
/**
* @brief Indicate whether automatic output is enabled.
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
* @param TIMx Timer instance
@ -3381,7 +3381,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
* software and is reset in case of break or break2 event
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
* @param TIMx Timer instance
@ -3396,7 +3396,7 @@ __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
* software and is reset in case of break or break2 event.
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
* @param TIMx Timer instance
@ -3409,7 +3409,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
/**
* @brief Indicates whether outputs are enabled.
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
* @param TIMx Timer instance
@ -3423,7 +3423,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
#if defined(TIM_BREAK_INPUT_SUPPORT)
/**
* @brief Enable the signals connected to the designated timer break input.
* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* or not a timer instance allows for break input selection.
* @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
* AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
@ -3452,7 +3452,7 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B
/**
* @brief Disable the signals connected to the designated timer break input.
* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* or not a timer instance allows for break input selection.
* @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
* AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
@ -3481,7 +3481,7 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t
/**
* @brief Set the polarity of the break signal for the timer break input.
* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* or not a timer instance allows for break input selection.
* @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
* AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
@ -3518,7 +3518,7 @@ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint3
*/
/**
* @brief Configures the timer DMA burst feature.
* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
* @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
* not a timer instance supports the DMA burst mode.
* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
* DCR DBA LL_TIM_ConfigDMABurst
@ -3584,7 +3584,7 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB
*/
/**
* @brief Remap TIM inputs (input channel, internal/external triggers).
* @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
* @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
* a some timer inputs can be remapped.
* @retval None
*/

46
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_usart.c
View File

@ -26,13 +26,13 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32H7xx_LL_Driver
* @{
*/
#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8)
#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (USART10)
/** @addtogroup USART_LL
* @{
@ -41,14 +41,6 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup USART_LL_Private_Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup USART_LL_Private_Macros
* @{
@ -208,6 +200,26 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
/* Release reset of UART clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8);
}
#if defined(UART9)
else if (USARTx == UART9)
{
/* Force reset of UART clock */
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART9);
/* Release reset of UART clock */
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART9);
}
#endif /* UART9 */
#if defined(USART10)
else if (USARTx == USART10)
{
/* Force reset of USART clock */
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART10);
/* Release reset of USART clock */
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART10);
}
#endif /* USART10 */
else
{
status = ERROR;
@ -310,6 +322,18 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
{
periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
}
#if defined(UART9)
else if (USARTx == UART9)
{
periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
}
#endif /* UART9 */
#if defined(USART10)
else if (USARTx == USART10)
{
periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
}
#endif /* USART10 */
else
{
/* Nothing to do, as error code is already assigned to ERROR value */
@ -460,7 +484,7 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
* @}
*/
#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 */
#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || USART10 */
/**
* @}

65
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_usart.h
View File

@ -32,7 +32,7 @@ extern "C" {
* @{
*/
#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8)
#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (USART10)
/** @defgroup USART_LL USART
* @{
@ -44,33 +44,26 @@ extern "C" {
* @{
*/
/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
static const uint16_t USART_PRESCALER_TAB[] =
static const uint32_t USART_PRESCALER_TAB[] =
{
(uint16_t)1,
(uint16_t)2,
(uint16_t)4,
(uint16_t)6,
(uint16_t)8,
(uint16_t)10,
(uint16_t)12,
(uint16_t)16,
(uint16_t)32,
(uint16_t)64,
(uint16_t)128,
(uint16_t)256
1UL,
2UL,
4UL,
6UL,
8UL,
10UL,
12UL,
16UL,
32UL,
64UL,
128UL,
256UL
};
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup USART_LL_Private_Constants USART Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup USART_LL_Private_Macros USART Private Macros
@ -570,7 +563,8 @@ typedef struct
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
*/
#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
+ ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @brief Compute USARTDIV value according to Peripheral Clock and
@ -592,7 +586,8 @@ typedef struct
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
*/
#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)])) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
+ ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @}
@ -1864,22 +1859,27 @@ __STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
* @param BaudRate Baud Rate
* @retval None
*/
__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling,
__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
uint32_t OverSampling,
uint32_t BaudRate)
{
register uint32_t usartdiv;
uint32_t usartdiv;
register uint32_t brrtemp;
if (OverSampling == LL_USART_OVERSAMPLING_8)
if (PrescalerValue > LL_USART_PRESCALER_DIV256)
{
usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint16_t)PrescalerValue, BaudRate));
/* Do not overstep the size of USART_PRESCALER_TAB */
}
else if (OverSampling == LL_USART_OVERSAMPLING_8)
{
usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
brrtemp = usartdiv & 0xFFF0U;
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
USARTx->BRR = brrtemp;
}
else
{
USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint16_t)PrescalerValue, BaudRate));
USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
}
}
@ -1909,11 +1909,12 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph
* @arg @ref LL_USART_OVERSAMPLING_8
* @retval Baud Rate
*/
__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling)
__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
uint32_t OverSampling)
{
register uint32_t usartdiv;
register uint32_t brrresult = 0x0U;
register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (uint32_t)(USART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
usartdiv = USARTx->BRR;
@ -4227,7 +4228,7 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t
*/
__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
{
return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
}
/**
@ -4362,7 +4363,7 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitS
* @}
*/
#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 */
#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || USART10 */
/**
* @}

13
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_usb.c
View File

@ -931,7 +931,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin
count32b = ((uint32_t)len + 3U) / 4U;
for (i = 0U; i < count32b; i++)
{
USBx_DFIFO((uint32_t)ch_ep_num) = *((__packed uint32_t *)pSrc);
USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
pSrc++;
}
}
@ -940,15 +940,10 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin
}
/**
* @brief USB_ReadPacket : read a packet from the Tx FIFO associated
* with the EP/channel
* @brief USB_ReadPacket : read a packet from the RX FIFO
* @param USBx Selected device
* @param dest source pointer
* @param len Number of bytes to read
* @param dma USB dma enabled or disabled
* This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @retval pointer to destination buffer
*/
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
@ -960,7 +955,7 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
for (i = 0U; i < count32b; i++)
{
*(__packed uint32_t *)pDest = USBx_DFIFO(0U);
__UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
pDest++;
}
@ -1911,7 +1906,6 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
uint32_t value;
uint32_t i;
(void)USB_DisableGlobalInt(USBx);
/* Flush FIFO */
@ -1950,6 +1944,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
/* Clear any pending Host interrupts */
USBx_HOST->HAINT = 0xFFFFFFFFU;
USBx->GINTSTS = 0xFFFFFFFFU;
(void)USB_EnableGlobalInt(USBx);
return HAL_OK;