From 9e74068fbdd97bd572c8c50072c0524496fabf61 Mon Sep 17 00:00:00 2001
From: Andrew Fritz <afritz@multitech.com>
Date: Wed, 10 Sep 2014 13:14:47 -0500
Subject: [PATCH] Added pin names for SPI buses and SPI chip select lines as
 well as pin names for GPIO pins.

---
 .../TARGET_K64F/TARGET_MTS_GAMBIT/PinNames.h  | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PinNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PinNames.h
index cabb2f9faf..5208e3a51b 100644
--- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PinNames.h
+++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PinNames.h
@@ -206,6 +206,37 @@ typedef enum {
     USBTX = PTB17,
     USBRX = PTB16,
 
+    // SPI Pins
+    SPI0_SOUT = PTC6,
+    SPI0_SIN = PTC7,
+    SPI0_SCK = PTC5,
+
+    SPI1_SOUT = PTE3,
+    SPI1_SIN = PTE1,
+    SPI1_SCK = PTE2,
+
+    // SPI Chip Select Pins
+    SPI0_NCS0 = PTC4,
+    SPI0_NCS1 = PTC3,
+    SPI0_NCS2 = PTC2,
+    SPI0_NCS3 = PTC1,
+
+    SPI1_NCS0 = PTE4,
+    SPI1_NCS1 = PTE0,
+    SPI1_NCS2 = PTE5,
+    SPI1_NCS3 = PTE6,
+
+    // GPIO's
+    AP1_GPIO1 = PTB7,
+    AP1_GPIO2 = PTB6,
+    AP1_GPIO3 = PTB5,
+    AP1_GPIO4 = PTB4,
+
+    AP2_GPIO1 = PTA27,
+    AP2_GPIO2 = PTA26,
+    AP2_GPIO3 = PTA25,
+    AP2_GPIO4 = PTA24,
+
     DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */
 
     // Not connected