mirror of https://github.com/ARMmbed/mbed-os.git
DISCO_F051R8: update device header file with the last STM32CubeF0 hal version
adustm
parent
95bf707325
commit
fbdf211df1
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f051x8.h
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* @author MCD Application Team
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* @version V2.1.0
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* @date 03-Oct-2014
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* @version V2.2.2
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* @date 26-June-2015
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* @brief CMSIS STM32F051x4/STM32F051x6/STM32F051x8 devices Peripheral Access
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* Layer Header File.
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*
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@ -15,7 +15,7 @@
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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@ -60,7 +60,6 @@
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/** @addtogroup Configuration_section_for_CMSIS
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* @{
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*/
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/**
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* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
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*/
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@ -284,14 +283,12 @@ typedef struct
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*/
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typedef struct
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{
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__IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
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__IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
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__IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
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__IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
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__IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
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__IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
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__IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
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__IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
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__IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
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__IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
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__IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
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__IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
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__IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
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__IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
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}OB_TypeDef;
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/**
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@ -369,6 +366,7 @@ typedef struct
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/**
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* @brief Reset and Clock Control
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*/
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typedef struct
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{
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__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
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@ -390,7 +388,6 @@ typedef struct
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/**
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* @brief Real-Time Clock
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*/
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typedef struct
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{
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__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
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@ -426,24 +423,15 @@ typedef struct
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typedef struct
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{
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__IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
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uint16_t RESERVED0; /*!< Reserved, 0x02 */
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__IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
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uint16_t RESERVED1; /*!< Reserved, 0x06 */
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__IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
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uint16_t RESERVED2; /*!< Reserved, 0x0A */
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__IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
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uint16_t RESERVED3; /*!< Reserved, 0x0E */
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__IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
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uint16_t RESERVED4; /*!< Reserved, 0x12 */
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__IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
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uint16_t RESERVED5; /*!< Reserved, 0x16 */
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__IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
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uint16_t RESERVED6; /*!< Reserved, 0x1A */
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__IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
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uint16_t RESERVED7; /*!< Reserved, 0x1E */
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__IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
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uint16_t RESERVED8; /*!< Reserved, 0x22 */
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__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
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__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
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__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
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__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
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__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
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__IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
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__IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
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__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
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__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
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}SPI_TypeDef;
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/**
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@ -535,6 +523,7 @@ typedef struct
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*/
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#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
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#define FLASH_BANK1_END ((uint32_t)0x0800FFFF) /*!< FLASH END address of bank1 */
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#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
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#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
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@ -556,6 +545,7 @@ typedef struct
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#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
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#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
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#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
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#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
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#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
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@ -642,7 +632,6 @@ typedef struct
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#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
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#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
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#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
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/**
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* @}
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*/
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@ -782,7 +771,6 @@ typedef struct
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#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
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#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
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/******************************************************************************/
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/* */
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/* HDMI-CEC (CEC) */
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@ -841,7 +829,6 @@ typedef struct
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#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
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#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
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/******************************************************************************/
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/* */
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/* Analog Comparators (COMP) */
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@ -889,24 +876,24 @@ typedef struct
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#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
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#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
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/* COMPx bits definition */
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#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
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#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
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#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
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#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
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#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
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#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
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#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
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#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
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#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
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#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
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#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
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#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
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#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
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#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
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#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
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#define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /*!< COMPx hysteresis bit 1 */
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#define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /*!< COMPx output level */
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#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
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#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
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#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */
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#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
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#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
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#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */
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#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
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#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
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#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
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#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700) /*!< COMPx output select */
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#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100) /*!< COMPx output select bit 0 */
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#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200) /*!< COMPx output select bit 1 */
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#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400) /*!< COMPx output select bit 2 */
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#define COMP_CSR_COMPxPOL ((uint32_t)0x00000800) /*!< COMPx output polarity */
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#define COMP_CSR_COMPxHYST ((uint32_t)0x00003000) /*!< COMPx hysteresis */
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#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000) /*!< COMPx hysteresis bit 0 */
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#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000) /*!< COMPx hysteresis bit 1 */
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#define COMP_CSR_COMPxOUT ((uint32_t)0x00004000) /*!< COMPx output level */
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#define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000) /*!< COMPx lock */
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/******************************************************************************/
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/* */
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@ -929,7 +916,6 @@ typedef struct
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/******************* Bit definition for CRC_INIT register *******************/
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#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
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/******************************************************************************/
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/* */
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/* Digital to Analog Converter (DAC) */
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@ -1266,8 +1252,8 @@ typedef struct
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#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
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/****************** FLASH Keys **********************************************/
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#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
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#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
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#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
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#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
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to unlock the write access to the FPEC. */
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#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
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#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
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#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
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#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
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#define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
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#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
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#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
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#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
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#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
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#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
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#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
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/* Old BOOT1 bit definition, maintained for legacy purpose */
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#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
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#define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
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#define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /*!< LSE clock selected as HDMI CEC entry clock source */
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/*!< USART2 Clock source selection */
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#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
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#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
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#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
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#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */
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#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
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#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
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#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
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/******************* Bit definition for RCC_CR2 register *******************/
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#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
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#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
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#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
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#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
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#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
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#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
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#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
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#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
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#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
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/***************** Bit definition for SYSCFG_EXTICR1 register **************/
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#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
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#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
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#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
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#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
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#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
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#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
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#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
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#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
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/**
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* @brief EXTI0 configuration
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*/
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#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
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#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
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#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
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#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
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#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
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#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
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#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
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#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
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#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
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#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
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/**
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* @brief EXTI1 configuration
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*/
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#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
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#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
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#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
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#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
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#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
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#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
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#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
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#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
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#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
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#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
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/**
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* @brief EXTI2 configuration
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*/
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#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
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#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
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#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register **************/
|
||||
#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
|
||||
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register **************/
|
||||
#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
|
||||
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register **************/
|
||||
#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
|
||||
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
|
||||
|
|
@ -3497,13 +3476,15 @@ typedef struct
|
|||
((INSTANCE) == DMA1_Channel5))
|
||||
|
||||
/****************************** GPIO Instances ********************************/
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB))
|
||||
|
||||
/****************************** GPIO Lock Instances ****************************/
|
||||
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB))
|
||||
|
||||
|
|
@ -3767,7 +3748,6 @@ typedef struct
|
|||
/****************** UART Instances : Driver enable detection ********************/
|
||||
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2))
|
||||
|
||||
/****************************** WWDG Instances ********************************/
|
||||
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue