diff --git a/libraries/USBDevice/USBDevice/USBDevice.cpp b/libraries/USBDevice/USBDevice/USBDevice.cpp index e64eab5e74..dc3efc96f4 100644 --- a/libraries/USBDevice/USBDevice/USBDevice.cpp +++ b/libraries/USBDevice/USBDevice/USBDevice.cpp @@ -187,7 +187,7 @@ bool USBDevice::controlOut(void) /* Check we should be transferring data OUT */ if (transfer.direction != HOST_TO_DEVICE) { -#if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M) | defined(TARGET_K64F) | defined(TARGET_K22F) +#if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1) /* * We seem to have a pending device-to-host transfer. The host must have * sent a new control request without waiting for us to finish processing diff --git a/libraries/USBDevice/USBDevice/USBEndpoints.h b/libraries/USBDevice/USBDevice/USBEndpoints.h index 130f49a790..e7e78bf018 100644 --- a/libraries/USBDevice/USBDevice/USBEndpoints.h +++ b/libraries/USBDevice/USBDevice/USBEndpoints.h @@ -41,7 +41,7 @@ typedef enum { #include "USBEndpoints_LPC17_LPC23.h" #elif defined(TARGET_LPC11UXX) || defined(TARGET_LPC1347) || defined (TARGET_LPC11U6X) || defined (TARGET_LPC1549) #include "USBEndpoints_LPC11U.h" -#elif defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) | defined(TARGET_K22F) +#elif defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1) #include "USBEndpoints_KL25Z.h" #elif defined (TARGET_STM32F4) #include "USBEndpoints_STM32F4.h" diff --git a/libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp b/libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp index 86452653d4..f92a99979b 100644 --- a/libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp +++ b/libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp @@ -16,7 +16,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) | defined(TARGET_K22F) +#if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1) #include "USBHAL.h" diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c index aa2158efce..4b45c719f0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c @@ -47,6 +47,7 @@ 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode Reference clock source for MCG module is the slow internal clock source 32.768kHz Core clock = 41.94MHz, BusClock = 41.94MHz + This works on Teensy3.1 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode Reference clock source for MCG module is an external crystal 8MHz Core clock = 48MHz, BusClock = 48MHz @@ -56,7 +57,7 @@ 3 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode Reference clock source for MCG module is an external crystal 16MHz Core clock = 72MHz, BusClock = 48MHz - This is the Teensy3.1 72Mhz set up + This is the default Teensy3.1 72Mhz set up */ /*---------------------------------------------------------------------------- @@ -98,7 +99,6 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; /* ---------------------------------------------------------------------------- -- SystemInit() ---------------------------------------------------------------------------- */ - void SystemInit (void) { #if (DISABLE_WDOG) /* Disable the WDOG module */ @@ -106,143 +106,120 @@ void SystemInit (void) { WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */ /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */ WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */ - /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ + /* WDOG_STCTRLH: DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ WDOG->STCTRLH = (uint16_t)0x01D2u; #endif /* (DISABLE_WDOG) */ + #if (CLOCK_SETUP == 0) - /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ - SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 41.94MHz cpu, 41.94MHz system, 20.97MHz flash*/ + SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1); /* Switch to FEI Mode */ /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = (uint8_t)0x06u; - /* MCG->C2: ??=0,??=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */ + MCG->C1 = MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK; + /* MCG->C2: LOCKRE0=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */ MCG->C2 = (uint8_t)0x00u; /* MCG_C4: DMX32=0,DRST_DRS=1 */ MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u); - /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ + /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ MCG->C5 = (uint8_t)0x00u; /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ MCG->C6 = (uint8_t)0x00u; - while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */ - } - while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */ - } + while((MCG->S & MCG_S_IREFST_MASK) == 0u) { } /* Check that the source of the FLL reference clock is the internal reference clock. */ + while((MCG->S & 0x0Cu) != 0x00u) { } /* Wait until output of the FLL is selected */ + #elif (CLOCK_SETUP == 1) - /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ - SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 48MHz cpu, 48MHz system, 24MHz flash*/ + SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1); /* Switch to FBE Mode */ - /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC0->CR = (uint8_t)0x00u; /* MCG->C7: OSCSEL=0 */ MCG->C7 = (uint8_t)0x00u; - /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - MCG->C2 = (uint8_t)0x24u; + /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = MCG_C2_RANGE0(2); /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = (uint8_t)0x9Au; + MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK; /* MCG->C4: DMX32=0,DRST_DRS=0 */ MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; - /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ - MCG->C5 = (uint8_t)0x03u; + /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ + MCG->C5 = MCG_C5_PRDIV0(3); /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ MCG->C6 = (uint8_t)0x00u; - while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ - } -#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ - while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ - } -#endif - while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ - } + while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */ + while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */ /* Switch to PBE Mode */ - /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ - MCG->C5 = (uint8_t)0x03u; + /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ + MCG->C5 = MCG_C5_PRDIV0(3); /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */ - MCG->C6 = (uint8_t)0x40u; - while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */ - } - while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ - } + MCG->C6 = MCG_C6_PLLS_MASK; + while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */ + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ /* Switch to PEE Mode */ /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = (uint8_t)0x1Au; - while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */ - } - while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ - } + MCG->C1 = MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK; + while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */ + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ + #elif (CLOCK_SETUP == 2) - /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ - SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 8MHz cpu, 8MHz system, 8MHz flash*/ + SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1); /* Switch to FBE Mode */ - /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC0->CR = (uint8_t)0x00u; /* MCG->C7: OSCSEL=0 */ MCG->C7 = (uint8_t)0x00u; - /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - MCG->C2 = (uint8_t)0x24u; + /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK; /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = (uint8_t)0x9Au; + MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK; /* MCG->C4: DMX32=0,DRST_DRS=0 */ MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; - /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ + /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ MCG->C5 = (uint8_t)0x00u; /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ MCG->C6 = (uint8_t)0x00u; - while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ - } -#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ - while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ - } -#endif - while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ - } + while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */ + while((MCG->S & 0x0CU) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */ /* Switch to BLPE Mode */ - /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - MCG->C2 = (uint8_t)0x24u; + /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK; #elif (CLOCK_SETUP == 3) - /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ - SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 72MHz cpu, 72MHz system, 36MHz flash*/ + SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1); + /* SIM->CLKDIV2: USBDIV=2,USBFRAC=1 Divide 72MHz system clock for USB 48MHz */ + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC_MASK; + /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 10pF loading capacitors for 16MHz system oscillator*/ + OSC0->CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK; /* Switch to FBE Mode */ - /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - OSC0->CR = (uint8_t)0x0Au; // this is required if there are no external capacitors fitted to the Xtal /* MCG->C7: OSCSEL=0 */ MCG->C7 = (uint8_t)0x00u; - /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - MCG->C2 = (uint8_t)0x24u; + /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK; + //MCG->C2 = (uint8_t)0x24u; /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = (uint8_t)0x9Au; - /* MCG->C4: DMX32=0,DRST_DRS=0 */ - MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; - /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ - MCG->C5 = (uint8_t)0x07u; + MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK; + /* MCG->C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ + MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; + /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=7 */ + MCG->C5 = MCG_C5_PRDIV0(7); /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ MCG->C6 = (uint8_t)0x00u; - while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ - } -#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ - while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ - } -#endif - while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ - } + while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */ + while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */ /* Switch to PBE Mode */ - /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ - MCG->C5 = (uint8_t)0x05u; - /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */ - MCG->C6 = (uint8_t)0x43u; - while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */ - } - while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ - } + /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=5 */ + MCG->C5 = MCG_C5_PRDIV0(5); + /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 */ + MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3); + while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */ + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ /* Switch to PEE Mode */ - /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = (uint8_t)0x22u; - while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */ - } - while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ - } - -#endif /* (CLOCK_SETUP == 3) */ + /* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK; + while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */ + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ +#endif /* (CLOCK_SETUP) */ } /* ---------------------------------------------------------------------------- diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h index 024a276909..a4da0f851a 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h @@ -210,40 +210,40 @@ typedef enum { DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */ // Teensy3.1 Headers - p0 = PTB16, - p1 = PTB17, - p2 = PTD0, - p3 = PTA12, - p4 = PTA13, - p5 = PTD7, - p6 = PTD4, - p7 = PTD2, - p8 = PTD3, - p9 = PTC3, - p10 = PTC4, - p11 = PTC6, - p12 = PTC7, - p13 = PTC5, - p14 = PTD1, - p15 = PTC0, - p16 = PTB0, - p17 = PTB1, - p18 = PTB3, - p19 = PTB2, - p20 = PTD5, - p21 = PTD6, - p22 = PTC1, - p23 = PTC2, - p24 = PTA5, - p25 = PTD19, - p26 = PTE1, - p27 = PTC9, - p28 = PTC8, - p29 = PTC10, - p30 = PTC11, - p31 = PTE0, - p32 = PTB18, - p33 = PTA4, + D0 = PTB16, + D1 = PTB17, + D2 = PTD0, + D3 = PTA12, + D4 = PTA13, + D5 = PTD7, + D6 = PTD4, + D7 = PTD2, + D8 = PTD3, + D9 = PTC3, + D10 = PTC4, + D11 = PTC6, + D12 = PTC7, + D13 = PTC5, + D14 = PTD1, + D15 = PTC0, + D16 = PTB0, + D17 = PTB1, + D18 = PTB3, + D19 = PTB2, + D20 = PTD5, + D21 = PTD6, + D22 = PTC1, + D23 = PTC2, + D24 = PTA5, + D25 = PTB19, + D26 = PTE1, + D27 = PTC9, + D28 = PTC8, + D29 = PTC10, + D30 = PTC11, + D31 = PTE0, + D32 = PTB18, + D33 = PTA4, A0 = PTD1, A1 = PTC0, @@ -255,7 +255,13 @@ typedef enum { A7 = PTD6, A8 = PTC1, A9 = PTC2, - + A15 = PTE1, + A16 = PTC9, + A17 = PTC8, + A18 = PTC10, + A19 = PTC11, + A20 = PTE0, + I2C_SCL = PTB3, I2C_SDA = PTB2, @@ -267,7 +273,18 @@ typedef enum { SERIAL_TX = PTB17, SERIAL_RX = PTB16, - PWM = PTD7, + PWM = PTA12, + PWM1 = PTA13, + PWM2 = PTD7, + PWM3 = PTD4, + PWM4 = PTC3, + PWM5 = PTC4, + PWM6 = PTD5, + PWM7 = PTD6, + PWM8 = PTC1, + PWM9 = PTC2, + PWM10 = PTB19, + PWM11 = PTB18, DAC = DAC0_OUT, diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/rtc.api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/rtc.api.c index 459c7b691a..d7dd1c8050 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/rtc.api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/rtc.api.c @@ -29,9 +29,15 @@ static void init(void) { void rtc_init(void) { init(); - + // Enable the oscillator +#if defined (TARGET_K20D50M) RTC->CR |= RTC_CR_OSCE_MASK; +#else + // Teensy3.1 requires 20pF MCU loading capacitors for 32KHz RTC oscillator + /* RTC->CR: SC2P=0,SC4P=1,SC8P=0,SC16P=1,CLKO=0,OSCE=1,UM=0,SUP=0,SPE=0,SWR=0 */ + RTC->CR |= RTC_CR_OSCE_MASK |RTC_CR_SC16P_MASK | RTC_CR_SC4P_MASK; +#endif //Configure the TSR. default value: 1 RTC->TSR = 1; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c index b5e8df31de..6ccb7e5d88 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c @@ -39,13 +39,32 @@ void deepsleep(void) SCB->SCR = 1<C6 & (1<S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */ MCG->C1 &= ~MCG_C1_CLKS_MASK; +#else + // MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 + MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK; + // MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 + MCG->C6 = MCG_C6_VDIV0(0); + while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } // Check that the oscillator is running + while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output + // MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 + MCG->C5 = MCG_C5_PRDIV0(5); + // MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 + MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3); + while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output + while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } // Wait until the source of the PLLS clock has switched to the PLL + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked + // MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 + MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;; + while((MCG->S & 0x0Cu) != 0x0Cu) { } // Wait until output of the PLL is selected + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked +#endif } - }