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Replace MAX32660, MAX32670 I2C driver with final one in MSDK 

- apply clang-format
- Fix i2c repeated start issue

Signed-off-by: Sadik.Ozer <sadik.ozer@analog.com>
pull/15341/head
Sadik.Ozer 2022-10-27 13:45:14 +03:00
parent 881a901808
commit fb1d9c2878
8 changed files with 2089 additions and 1853 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c
View File

@ -1,5 +1,5 @@
/* **************************************************************************** /* ****************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. * Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files(the "Software"), * copy of this software and associated documentation files(the "Software"),
@ -31,7 +31,6 @@
* *
*************************************************************************** */ *************************************************************************** */
#include <stdio.h> #include <stdio.h>
#include <stddef.h> #include <stddef.h>
#include <stdint.h> #include <stdint.h>
@ -46,7 +45,6 @@
#include "mxc_i2c.h" #include "mxc_i2c.h"
#include "i2c_reva.h" #include "i2c_reva.h"
/* **** Definitions **** */ /* **** Definitions **** */
#define MXC_I2C_FASTPLUS_SPEED 1000000 #define MXC_I2C_FASTPLUS_SPEED 1000000
@ -69,12 +67,10 @@ int MXC_I2C_Init(mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr)
if (i2c == MXC_I2C0) { if (i2c == MXC_I2C0) {
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C0); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C0);
MXC_GPIO_Config(&gpio_cfg_i2c0); MXC_GPIO_Config(&gpio_cfg_i2c0);
} } else if (i2c == MXC_I2C1) {
else if(i2c == MXC_I2C1) {
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C1); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C1);
MXC_GPIO_Config(&gpio_cfg_i2c1); MXC_GPIO_Config(&gpio_cfg_i2c1);
} } else {
else {
return E_NO_DEVICE; return E_NO_DEVICE;
} }
@ -114,15 +110,12 @@ int MXC_I2C_Shutdown(mxc_i2c_regs_t* i2c)
// Configure GPIO for I2C // Configure GPIO for I2C
if (i2c == MXC_I2C0) { if (i2c == MXC_I2C0) {
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C0); MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C0);
} } else if (i2c == MXC_I2C1) {
else if(i2c == MXC_I2C1) {
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1); MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1);
} } else {
else {
return E_NO_DEVICE; return E_NO_DEVICE;
} }
int i2cNum = MXC_I2C_GET_IDX(i2c); int i2cNum = MXC_I2C_GET_IDX(i2c);
// Reconcile this with MXC_SYS_I2C_Init when we figure out what to do abotu system level things // Reconcile this with MXC_SYS_I2C_Init when we figure out what to do abotu system level things
@ -144,7 +137,6 @@ int MXC_I2C_Shutdown(mxc_i2c_regs_t* i2c)
int MXC_I2C_SetFrequency(mxc_i2c_regs_t *i2c, unsigned int hz) int MXC_I2C_SetFrequency(mxc_i2c_regs_t *i2c, unsigned int hz)
{ {
// ME13 doesn't support high speed more // ME13 doesn't support high speed more
if (hz > MXC_I2C_FASTPLUS_SPEED) { if (hz > MXC_I2C_FASTPLUS_SPEED) {
return E_NOT_SUPPORTED; return E_NOT_SUPPORTED;
@ -198,7 +190,8 @@ int MXC_I2C_ReadByte(mxc_i2c_regs_t* i2c, unsigned char* byte, int ack)
int MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t *i2c, unsigned char *byte, mxc_i2c_getAck_t getAck) int MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t *i2c, unsigned char *byte, mxc_i2c_getAck_t getAck)
{ {
return MXC_I2C_RevA_ReadByteInteractive((mxc_i2c_reva_regs_t*) i2c, byte, (mxc_i2c_reva_getAck_t) getAck); return MXC_I2C_RevA_ReadByteInteractive((mxc_i2c_reva_regs_t *)i2c, byte,
(mxc_i2c_reva_getAck_t)getAck);
} }
int MXC_I2C_Write(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len) int MXC_I2C_Write(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len)
@ -216,7 +209,8 @@ int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, unsig
return MXC_I2C_RevA_ReadRXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len); return MXC_I2C_RevA_ReadRXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len);
} }
int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_dma_complete_cb_t callback) int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len,
mxc_i2c_dma_complete_cb_t callback)
{ {
uint8_t i2cNum; uint8_t i2cNum;
mxc_dma_config_t config; mxc_dma_config_t config;
@ -232,7 +226,8 @@ int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned in
config.reqsel = MXC_DMA_REQUEST_I2C1RX; config.reqsel = MXC_DMA_REQUEST_I2C1RX;
break; break;
} }
return MXC_I2C_RevA_ReadRXFIFODMA((mxc_i2c_reva_regs_t*) i2c, bytes, len, (mxc_i2c_reva_dma_complete_cb_t) callback, config, MXC_DMA); return MXC_I2C_RevA_ReadRXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len,
(mxc_i2c_reva_dma_complete_cb_t)callback, config, MXC_DMA);
} }
int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t *i2c) int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t *i2c)
@ -245,7 +240,8 @@ int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, unsi
return MXC_I2C_RevA_WriteTXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len); return MXC_I2C_RevA_WriteTXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len);
} }
int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_dma_complete_cb_t callback) int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len,
mxc_i2c_dma_complete_cb_t callback)
{ {
uint8_t i2cNum; uint8_t i2cNum;
mxc_dma_config_t config; mxc_dma_config_t config;
@ -261,7 +257,8 @@ int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned i
config.reqsel = MXC_DMA_REQUEST_I2C1TX; config.reqsel = MXC_DMA_REQUEST_I2C1TX;
break; break;
} }
return MXC_I2C_RevA_WriteTXFIFODMA((mxc_i2c_reva_regs_t*) i2c, bytes, len, (mxc_i2c_reva_dma_complete_cb_t) callback, config, MXC_DMA); return MXC_I2C_RevA_WriteTXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len,
(mxc_i2c_reva_dma_complete_cb_t)callback, config, MXC_DMA);
} }
int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t *i2c) int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t *i2c)
@ -355,12 +352,14 @@ int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t* req)
int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback) int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback)
{ {
return MXC_I2C_RevA_SlaveTransaction((mxc_i2c_reva_regs_t*) i2c, (mxc_i2c_reva_slave_handler_t) callback, interruptCheck); return MXC_I2C_RevA_SlaveTransaction((mxc_i2c_reva_regs_t *)i2c,
(mxc_i2c_reva_slave_handler_t)callback, interruptCheck);
} }
int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback) int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback)
{ {
return MXC_I2C_RevA_SlaveTransactionAsync((mxc_i2c_reva_regs_t*) i2c, (mxc_i2c_reva_slave_handler_t) callback, interruptCheck); return MXC_I2C_RevA_SlaveTransactionAsync(
(mxc_i2c_reva_regs_t *)i2c, (mxc_i2c_reva_slave_handler_t)callback, interruptCheck);
} }
int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes) int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes)

382
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c
View File

@ -1,5 +1,5 @@
/* **************************************************************************** /* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -50,8 +50,8 @@ typedef struct {
int master; // 1 for Master, 0 for slave int master; // 1 for Master, 0 for slave
int channelTx; // DMA channel for TX transaction int channelTx; // DMA channel for TX transaction
int channelRx; // DMA channel for RX transaction int channelRx; // DMA channel for RX transaction
int writeDone; // Write done flag volatile int writeDone; // Write done flag
int readDone; // Flag done flag volatile int readDone; // Flag done flag
} mxc_i2c_reva_req_state_t; } mxc_i2c_reva_req_state_t;
static mxc_i2c_reva_req_state_t states[MXC_I2C_INSTANCES]; static mxc_i2c_reva_req_state_t states[MXC_I2C_INSTANCES];
@ -66,7 +66,9 @@ void MXC_I2C_RevA_AsyncStop (mxc_i2c_reva_regs_t* i2c);
void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c); void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c);
void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum); void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum);
int MXC_I2C_RevA_DMAHandler(mxc_i2c_reva_req_t *req); int MXC_I2C_RevA_DMAHandler(mxc_i2c_reva_req_t *req);
unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal); unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
mxc_i2c_reva_slave_handler_t callback,
unsigned int interruptEnables, int *retVal);
/* ************************************************************************* */ /* ************************************************************************* */
/* Control/Configuration functions */ /* Control/Configuration functions */
@ -94,8 +96,7 @@ int MXC_I2C_RevA_Init (mxc_i2c_reva_regs_t* i2c, int masterMode, unsigned int sl
if (!masterMode) { if (!masterMode) {
MXC_I2C_SetSlaveAddr((mxc_i2c_regs_t *)i2c, slaveAddr, 0); MXC_I2C_SetSlaveAddr((mxc_i2c_regs_t *)i2c, slaveAddr, 0);
states[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)].master = 0; states[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)].master = 0;
} } else {
else {
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_MST_MODE; i2c->ctrl |= MXC_F_I2C_REVA_CTRL_MST_MODE;
states[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)].master = 1; states[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)].master = 1;
} }
@ -219,8 +220,7 @@ int MXC_I2C_RevA_SetClockStretching (mxc_i2c_reva_regs_t* i2c, int enable)
if (enable) { if (enable) {
i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_CLKSTR_DIS; i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_CLKSTR_DIS;
} } else {
else {
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_CLKSTR_DIS; i2c->ctrl |= MXC_F_I2C_REVA_CTRL_CLKSTR_DIS;
} }
@ -248,8 +248,7 @@ int MXC_I2C_RevA_Start (mxc_i2c_reva_regs_t* i2c)
// If we have an incomplete transfer, we need to do a restart // If we have an incomplete transfer, we need to do a restart
if (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_START) { if (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_START) {
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART;
} } else {
else {
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; // No check for start generation i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; // No check for start generation
} }
@ -264,7 +263,7 @@ int MXC_I2C_RevA_Stop (mxc_i2c_reva_regs_t* i2c)
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP;
while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_STOP); while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_STOP) {}
return E_NO_ERROR; return E_NO_ERROR;
} }
@ -284,7 +283,7 @@ int MXC_I2C_RevA_WriteByte (mxc_i2c_reva_regs_t* i2c, unsigned char byte)
MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK);
i2c->fifo = byte; i2c->fifo = byte;
while (! (i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)); while (!(i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)) {}
return i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DATA_ERR; return i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DATA_ERR;
} }
@ -295,7 +294,7 @@ int MXC_I2C_RevA_ReadByte (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, int ac
return E_NULL_PTR; return E_NULL_PTR;
} }
if (! (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM)) { if (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM) {
return E_UNDERFLOW; return E_UNDERFLOW;
} }
@ -310,7 +309,8 @@ int MXC_I2C_RevA_ReadByte (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, int ac
return E_NO_ERROR; return E_NO_ERROR;
} }
int MXC_I2C_RevA_ReadByteInteractive (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, mxc_i2c_reva_getAck_t getAck) int MXC_I2C_RevA_ReadByteInteractive(mxc_i2c_reva_regs_t *i2c, unsigned char *byte,
mxc_i2c_reva_getAck_t getAck)
{ {
if ((i2c == NULL) || (byte == NULL)) { if ((i2c == NULL) || (byte == NULL)) {
return E_NULL_PTR; return E_NULL_PTR;
@ -324,9 +324,9 @@ int MXC_I2C_RevA_ReadByteInteractive (mxc_i2c_reva_regs_t* i2c, unsigned char* b
if (getAck == NULL) { if (getAck == NULL) {
i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS; i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS;
} } else {
else { i2c->ctrl |= (!!getAck((mxc_i2c_reva_regs_t *)i2c, *byte))
i2c->ctrl |= (!!getAck ((mxc_i2c_reva_regs_t*) i2c, *byte)) << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS; << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS;
} }
return E_NO_ERROR; return E_NO_ERROR;
@ -350,8 +350,7 @@ int MXC_I2C_RevA_Write (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned
if (retVal >= 0) { if (retVal >= 0) {
notAcked += retVal; notAcked += retVal;
} } else {
else {
*len = written; *len = written;
return retVal; return retVal;
} }
@ -388,7 +387,8 @@ int MXC_I2C_RevA_Read (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned
return MXC_I2C_ReadByte((mxc_i2c_regs_t *)i2c, &(bytes[read]), ack); return MXC_I2C_ReadByte((mxc_i2c_regs_t *)i2c, &(bytes[read]), ack);
} }
int MXC_I2C_RevA_ReadRXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) int MXC_I2C_RevA_ReadRXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes,
unsigned int len)
{ {
unsigned read = 0; unsigned read = 0;
@ -403,8 +403,9 @@ int MXC_I2C_RevA_ReadRXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* b
return read; return read;
} }
int MXC_I2C_RevA_ReadRXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, \ int MXC_I2C_RevA_ReadRXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len,
mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma) mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config,
mxc_dma_regs_t *dma)
{ {
uint8_t i2cNum; uint8_t i2cNum;
uint8_t channel; uint8_t channel;
@ -439,9 +440,7 @@ int MXC_I2C_RevA_ReadRXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes,
if (states[i2cNum].master) { if (states[i2cNum].master) {
MXC_DMA_SetCallback(channel, MXC_I2C_RevA_DMACallback); MXC_DMA_SetCallback(channel, MXC_I2C_RevA_DMACallback);
} } else {
else {
MXC_DMA_SetCallback(channel, NULL); MXC_DMA_SetCallback(channel, NULL);
} }
@ -463,7 +462,8 @@ int MXC_I2C_RevA_GetRXFIFOAvailable (mxc_i2c_reva_regs_t* i2c)
return (i2c->rxctrl1 & MXC_F_I2C_REVA_RXCTRL1_LVL) >> MXC_F_I2C_REVA_RXCTRL1_LVL_POS; return (i2c->rxctrl1 & MXC_F_I2C_REVA_RXCTRL1_LVL) >> MXC_F_I2C_REVA_RXCTRL1_LVL_POS;
} }
int MXC_I2C_RevA_WriteTXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) int MXC_I2C_RevA_WriteTXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes,
unsigned int len)
{ {
unsigned written = 0; unsigned written = 0;
@ -478,8 +478,9 @@ int MXC_I2C_RevA_WriteTXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char*
return written; return written;
} }
int MXC_I2C_RevA_WriteTXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, \ int MXC_I2C_RevA_WriteTXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len,
mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma) mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config,
mxc_dma_regs_t *dma)
{ {
uint8_t i2cNum; uint8_t i2cNum;
uint8_t channel; uint8_t channel;
@ -516,8 +517,7 @@ int MXC_I2C_RevA_WriteTXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes,
if (states[i2cNum].master) { if (states[i2cNum].master) {
MXC_DMA_SetCallback(channel, MXC_I2C_RevA_DMACallback); MXC_DMA_SetCallback(channel, MXC_I2C_RevA_DMACallback);
} } else {
else {
MXC_DMA_SetCallback(channel, NULL); MXC_DMA_SetCallback(channel, NULL);
} }
@ -536,22 +536,24 @@ int MXC_I2C_RevA_GetTXFIFOAvailable (mxc_i2c_reva_regs_t* i2c)
return E_NULL_PTR; return E_NULL_PTR;
} }
int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >>
return txFIFOlen - ( (i2c->txctrl1 & MXC_F_I2C_REVA_TXCTRL1_LVL) >> MXC_F_I2C_REVA_TXCTRL1_LVL_POS); MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS;
return txFIFOlen -
((i2c->txctrl1 & MXC_F_I2C_REVA_TXCTRL1_LVL) >> MXC_F_I2C_REVA_TXCTRL1_LVL_POS);
} }
void MXC_I2C_RevA_ClearRXFIFO(mxc_i2c_reva_regs_t *i2c) void MXC_I2C_RevA_ClearRXFIFO(mxc_i2c_reva_regs_t *i2c)
{ {
i2c->rxctrl0 |= MXC_F_I2C_REVA_RXCTRL0_FLUSH; i2c->rxctrl0 |= MXC_F_I2C_REVA_RXCTRL0_FLUSH;
while (i2c->rxctrl0 & MXC_F_I2C_REVA_RXCTRL0_FLUSH); while (i2c->rxctrl0 & MXC_F_I2C_REVA_RXCTRL0_FLUSH) {}
} }
void MXC_I2C_RevA_ClearTXFIFO(mxc_i2c_reva_regs_t *i2c) void MXC_I2C_RevA_ClearTXFIFO(mxc_i2c_reva_regs_t *i2c)
{ {
i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_FLUSH; i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_FLUSH;
while (i2c->txctrl0 & MXC_F_I2C_REVA_TXCTRL0_FLUSH); while (i2c->txctrl0 & MXC_F_I2C_REVA_TXCTRL0_FLUSH) {}
} }
int MXC_I2C_RevA_GetFlags(mxc_i2c_reva_regs_t *i2c, unsigned int *flags0, unsigned int *flags1) int MXC_I2C_RevA_GetFlags(mxc_i2c_reva_regs_t *i2c, unsigned int *flags0, unsigned int *flags1)
@ -673,12 +675,12 @@ void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t* i2c)
void MXC_I2C_RevA_EnableGeneralCall(mxc_i2c_reva_regs_t *i2c) void MXC_I2C_RevA_EnableGeneralCall(mxc_i2c_reva_regs_t *i2c)
{ {
i2c->txctrl0 &= ~MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS; i2c->ctrl |= MXC_F_I2C_REVA_CTRL_GC_ADDR_EN;
} }
void MXC_I2C_RevA_DisableGeneralCall(mxc_i2c_reva_regs_t *i2c) void MXC_I2C_RevA_DisableGeneralCall(mxc_i2c_reva_regs_t *i2c)
{ {
i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS; i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_GC_ADDR_EN;
} }
void MXC_I2C_RevA_SetTimeout(mxc_i2c_reva_regs_t *i2c, unsigned int timeout) void MXC_I2C_RevA_SetTimeout(mxc_i2c_reva_regs_t *i2c, unsigned int timeout)
@ -729,7 +731,8 @@ int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req)
// stop or restart // stop or restart
// return good or error // return good or error
MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK,
MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts
MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c);
MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c);
i2c->inten0 = 0; i2c->inten0 = 0;
@ -743,7 +746,8 @@ int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req)
while (req->tx_len > written) { while (req->tx_len > written) {
if (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_TX_THD) { if (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_TX_THD) {
written += MXC_I2C_WriteTXFIFO ((mxc_i2c_regs_t*) i2c, &req->tx_buf[written], req->tx_len - written); written += MXC_I2C_WriteTXFIFO((mxc_i2c_regs_t *)i2c, &req->tx_buf[written],
req->tx_len - written);
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD;
} }
@ -754,26 +758,27 @@ int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req)
} }
} }
MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_RX_THD, 0); MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c,
MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_RX_THD, 0);
if (req->rx_len != 0) { if (req->rx_len != 0) {
if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) {
i2c->rxctrl1 = 0; i2c->rxctrl1 = 0;
} } else {
else {
i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read
} }
MXC_I2C_Start((mxc_i2c_regs_t *)i2c); // Start or Restart as needed MXC_I2C_Start((mxc_i2c_regs_t *)i2c); // Start or Restart as needed
while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART); while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART) {}
i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit.
} }
while (req->rx_len > read) { while (req->rx_len > read) {
if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) { if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) {
read += MXC_I2C_ReadRXFIFO ((mxc_i2c_regs_t*) i2c, &req->rx_buf[read], req->rx_len - read); read +=
MXC_I2C_ReadRXFIFO((mxc_i2c_regs_t *)i2c, &req->rx_buf[read], req->rx_len - read);
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD;
} }
@ -786,8 +791,7 @@ int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req)
if ((i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) { if ((i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) {
if ((req->rx_len - read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { if ((req->rx_len - read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) {
i2c->rxctrl1 = 0; i2c->rxctrl1 = 0;
} } else {
else {
i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read
} }
@ -799,13 +803,15 @@ int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req)
if (req->restart) { if (req->restart) {
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART;
} } else {
else {
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP;
while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_STOP)) {}
// Wait for Transaction to finish
} }
while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_STOP)); // Wait for Transaction to finish while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)) {}
while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)); // Wait for Transaction to finish // Wait for Transaction to finish
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_STOP; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_STOP;
@ -837,19 +843,39 @@ int MXC_I2C_RevA_MasterTransactionAsync (mxc_i2c_reva_req_t* req)
AsyncRequests[i2cNum] = (void *)req; AsyncRequests[i2cNum] = (void *)req;
AsyncWritten[i2cNum] = 0; AsyncWritten[i2cNum] = 0;
AsyncRead[i2cNum] = 0; AsyncRead[i2cNum] = 0;
MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK,
MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts
MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c);
MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c);
if ((req->rx_len == 0) || (req->tx_len != 0)) { i2c->inten0 = MXC_I2C_REVA_ERROR;
if (req->tx_len) {
i2c->fifo = (req->addr << 1) & ~0x1; // Load the slave address with write bit set i2c->fifo = (req->addr << 1) & ~0x1; // Load the slave address with write bit set
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; } else if (req->rx_len) {
i2c->fifo = (req->addr << 1) | 0x1; // Load the slave address with read bit set
/* Set the number of bytes to read */
if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) {
i2c->rxctrl1 = 0;
} else {
i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read
} }
i2c->inten0 = MXC_I2C_REVA_ERROR | MXC_F_I2C_REVA_INTEN0_TX_THD; /* Enable RX Threshold interrupt for when the FIFO is full */
return E_NO_ERROR; i2c->inten0 |= (MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE);
} else {
/* Must have tx_len and/or rx_len */
return E_BAD_PARAM;
} }
else {
MXC_I2C_Start((mxc_i2c_regs_t *)i2c);
/* Fill the FIFO as nessary */
MXC_I2C_RevA_MasterAsyncHandler(i2cNum);
return E_NO_ERROR;
} else {
return E_BUSY; return E_BUSY;
} }
} }
@ -877,7 +903,8 @@ int MXC_I2C_RevA_MasterTransactionDMA (mxc_i2c_reva_req_t* req, mxc_dma_regs_t*
return E_BAD_PARAM; return E_BAD_PARAM;
} }
MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK,
MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts
MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c);
MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c);
@ -904,25 +931,24 @@ int MXC_I2C_RevA_MasterTransactionDMA (mxc_i2c_reva_req_t* req, mxc_dma_regs_t*
#else #else
MXC_I2C_WriteTXFIFODMA((mxc_i2c_regs_t *)i2c, req->tx_buf, req->tx_len, NULL); MXC_I2C_WriteTXFIFODMA((mxc_i2c_regs_t *)i2c, req->tx_buf, req->tx_len, NULL);
#endif #endif
} } else {
else {
states[i2cNum].writeDone = 1; states[i2cNum].writeDone = 1;
} }
if (req->rx_buf != NULL) { if (req->rx_buf != NULL) {
while(states[i2cNum].writeDone != 1); //Ensure DMA transmit has finished before attempting to receive while (states[i2cNum].writeDone != 1) {}
//Ensure DMA transmit has finished before attempting to receive
if ((states[i2cNum].writeDone) && (!states[i2cNum].readDone)) { if ((states[i2cNum].writeDone) && (!states[i2cNum].readDone)) {
if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) {
i2c->rxctrl1 = 0; i2c->rxctrl1 = 0;
} } else {
else {
i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read
} }
MXC_I2C_Start((mxc_i2c_regs_t *)i2c); // Start or Restart as needed MXC_I2C_Start((mxc_i2c_regs_t *)i2c); // Start or Restart as needed
while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART); while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART) {}
i2c->fifo = ((req->addr) << 1) | 0x1; // Load the slave address with write bit set i2c->fifo = ((req->addr) << 1) | 0x1; // Load the slave address with write bit set
@ -932,8 +958,7 @@ int MXC_I2C_RevA_MasterTransactionDMA (mxc_i2c_reva_req_t* req, mxc_dma_regs_t*
MXC_I2C_ReadRXFIFODMA((mxc_i2c_regs_t *)i2c, req->rx_buf, req->rx_len, NULL); MXC_I2C_ReadRXFIFODMA((mxc_i2c_regs_t *)i2c, req->rx_buf, req->rx_len, NULL);
#endif #endif
} }
} } else {
else {
states[i2cNum].readDone = 1; states[i2cNum].readDone = 1;
} }
@ -953,8 +978,7 @@ void MXC_I2C_RevA_DMACallback(int ch, int error)
if (states[i].readDone) { if (states[i].readDone) {
if (temp_req->restart) { if (temp_req->restart) {
(temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART;
} } else {
else {
(temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP;
} }
@ -966,9 +990,7 @@ void MXC_I2C_RevA_DMACallback(int ch, int error)
temp_req->callback(temp_req, E_NO_ERROR); temp_req->callback(temp_req, E_NO_ERROR);
} }
} }
} } else if (states[i].channelRx == ch) {
else if (states[i].channelRx == ch) {
//save the request //save the request
states[i].readDone = 1; states[i].readDone = 1;
temp_req = states[i].req; temp_req = states[i].req;
@ -976,8 +998,7 @@ void MXC_I2C_RevA_DMACallback(int ch, int error)
if (states[i].writeDone) { if (states[i].writeDone) {
if (temp_req->restart) { if (temp_req->restart) {
(temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART;
} } else {
else {
(temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP;
} }
@ -993,7 +1014,8 @@ void MXC_I2C_RevA_DMACallback(int ch, int error)
} }
} }
int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck) int MXC_I2C_RevA_SlaveTransaction(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback,
uint32_t interruptCheck)
{ {
unsigned int interruptEnables = interruptCheck; unsigned int interruptEnables = interruptCheck;
int retVal = E_NO_ERROR; int retVal = E_NO_ERROR;
@ -1006,7 +1028,8 @@ int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_
return E_BAD_STATE; return E_BAD_STATE;
} }
MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK,
MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts
MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c);
MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c);
@ -1034,7 +1057,9 @@ int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_
return retVal; return retVal;
} }
int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck) int MXC_I2C_RevA_SlaveTransactionAsync(mxc_i2c_reva_regs_t *i2c,
mxc_i2c_reva_slave_handler_t callback,
uint32_t interruptCheck)
{ {
int i2cnum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); int i2cnum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c);
@ -1050,7 +1075,8 @@ int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_s
return E_BUSY; return E_BUSY;
} }
MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK,
MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts
MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c);
MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c);
MXC_I2C_SetTXThreshold((mxc_i2c_regs_t *)i2c, 1); // set TX threshold to 2 bytes MXC_I2C_SetTXThreshold((mxc_i2c_regs_t *)i2c, 1); // set TX threshold to 2 bytes
@ -1064,13 +1090,15 @@ int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_s
int MXC_I2C_RevA_SetRXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes) int MXC_I2C_RevA_SetRXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes)
{ {
unsigned int rxFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS; unsigned int rxFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH) >>
MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS;
if (numBytes > rxFIFOlen) { if (numBytes > rxFIFOlen) {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
i2c->rxctrl0 = (i2c->rxctrl0 & ~MXC_F_I2C_REVA_RXCTRL0_THD_LVL) | (numBytes << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS); i2c->rxctrl0 = (i2c->rxctrl0 & ~MXC_F_I2C_REVA_RXCTRL0_THD_LVL) |
(numBytes << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS);
return E_NO_ERROR; return E_NO_ERROR;
} }
@ -1081,13 +1109,15 @@ unsigned int MXC_I2C_RevA_GetRXThreshold (mxc_i2c_reva_regs_t* i2c)
int MXC_I2C_RevA_SetTXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes) int MXC_I2C_RevA_SetTXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes)
{ {
unsigned int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; unsigned int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >>
MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS;
if (numBytes > txFIFOlen) { if (numBytes > txFIFOlen) {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
i2c->txctrl0 = (i2c->txctrl0 & ~MXC_F_I2C_REVA_TXCTRL0_THD_LVL) | (numBytes << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS); i2c->txctrl0 = (i2c->txctrl0 & ~MXC_F_I2C_REVA_TXCTRL0_THD_LVL) |
(numBytes << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS);
return E_NO_ERROR; return E_NO_ERROR;
} }
@ -1100,7 +1130,8 @@ void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal)
{ {
// Don't need to check for return value as this function is not accessible to user // Don't need to check for return value as this function is not accessible to user
// i2c is already cheked for NULL from where this function is being called // i2c is already cheked for NULL from where this function is being called
mxc_i2c_reva_req_t* req = (mxc_i2c_reva_req_t*) AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)]; mxc_i2c_reva_req_t *req =
(mxc_i2c_reva_req_t *)AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)];
if (req->callback != NULL) { if (req->callback != NULL) {
req->callback(req, retVal); req->callback(req, retVal);
@ -1109,9 +1140,13 @@ void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal)
void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c) void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c)
{ {
/* Disable and clear interrupts */
i2c->inten0 = 0; i2c->inten0 = 0;
i2c->inten1 = 0; i2c->inten1 = 0;
i2c->intfl0 = i2c->intfl0;
i2c->intfl1 = i2c->intfl1;
// Don't need to check for return value as this function is not accessible to user // Don't need to check for return value as this function is not accessible to user
// i2c is already cheked for NULL from where this function is being called // i2c is already cheked for NULL from where this function is being called
AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL;
@ -1132,88 +1167,112 @@ void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum)
mxc_i2c_reva_regs_t *i2c = (mxc_i2c_reva_regs_t *)MXC_I2C_GET_BASE(i2cNum); mxc_i2c_reva_regs_t *i2c = (mxc_i2c_reva_regs_t *)MXC_I2C_GET_BASE(i2cNum);
mxc_i2c_reva_req_t *req = (mxc_i2c_reva_req_t *)AsyncRequests[i2cNum]; mxc_i2c_reva_req_t *req = (mxc_i2c_reva_req_t *)AsyncRequests[i2cNum];
/* Check for errors */
if (i2c->intfl0 & MXC_I2C_REVA_ERROR) {
/* Clear and disable interrupts */
i2c->intfl0 = i2c->intfl0;
i2c->intfl1 = i2c->intfl1;
i2c->inten0 = 0;
i2c->inten1 = 0;
MXC_I2C_Stop((mxc_i2c_regs_t *)i2c);
MXC_I2C_RevA_AsyncCallback(i2c, E_COMM_ERR);
MXC_I2C_RevA_AsyncStop(i2c);
return;
}
/* Write data to the TX FIFO */
if (req->tx_len > written) { if (req->tx_len > written) {
if (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_TX_THD) { if (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_TX_THD) {
written += MXC_I2C_WriteTXFIFO ((mxc_i2c_regs_t*) i2c, &req->tx_buf[written], req->tx_len - written); written += MXC_I2C_WriteTXFIFO((mxc_i2c_regs_t *)i2c, &req->tx_buf[written],
req->tx_len - written);
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD;
} }
if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { /* Enable the TX Threshold interrupt if we still need to write to the TX FIFO */
req->tx_len = written; if (written < req->tx_len) {
MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); i2c->inten0 |= MXC_F_I2C_REVA_INTEN0_TX_THD;
MXC_I2C_RevA_AsyncCallback (i2c, E_COMM_ERR); } else {
MXC_I2C_RevA_AsyncStop (i2c); i2c->inten0 &= ~(MXC_F_I2C_REVA_INTEN0_TX_THD);
}
/* Send a restart if we're reading after writing */
if ((req->tx_len == written) && (req->rx_len)) {
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE;
i2c->inten0 |= (MXC_F_I2C_REVA_INTEN0_DONE);
} }
} }
/* Read data in the RX FIFO */
if (req->rx_len > read) { if (req->rx_len > read) {
if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) { if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) {
read += MXC_I2C_ReadRXFIFO ((mxc_i2c_regs_t*) i2c, &req->rx_buf[read], req->rx_len - read); read +=
MXC_I2C_ReadRXFIFO((mxc_i2c_regs_t *)i2c, &req->rx_buf[read], req->rx_len - read);
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD;
} }
if (i2c->intfl0 & MXC_I2C_REVA_ERROR) {
req->rx_len = read;
MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c);
MXC_I2C_RevA_AsyncCallback (i2c, E_COMM_ERR);
MXC_I2C_RevA_AsyncStop (i2c);
} }
if ( (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) { /* Done writing, still reading */
if ((req->tx_len == written) && (req->rx_len - read) &&
(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)) {
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE;
/* First done interrupt after completing writes to the TX FIFO */
if (read == 0) {
i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit.
}
/* Set the number of bytes to read */
if ((req->rx_len - read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { if ((req->rx_len - read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) {
i2c->rxctrl1 = 0; i2c->rxctrl1 = 0;
} } else {
else {
i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read
} }
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; /* Enable RX Threshold interrupt for when the FIFO is full */
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE; if (read < req->rx_len) {
i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. i2c->inten0 |= (MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE);
} } else {
}
if ( (req->tx_len == written) && (read == 0)) {
i2c->inten0 &= ~MXC_F_I2C_REVA_INTEN0_TX_THD;
i2c->inten0 |= MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE;
if ( (req->rx_len) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) {
i2c->rxctrl1 = 0;
}
else {
i2c->rxctrl1 = (req->rx_len); // 0 for 256, otherwise number of bytes to read
}
MXC_I2C_Start ((mxc_i2c_regs_t*) i2c); // Start or Restart as needed
i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit.
}
if ( (req->tx_len == written) && (req->rx_len == read)) {
i2c->inten0 &= ~(MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE); i2c->inten0 &= ~(MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE);
}
}
/* Done reading and writing */
if ((req->tx_len == written) && (req->rx_len == read)) {
/* Disable and clear interrupts */
i2c->inten0 = 0;
i2c->inten1 = 0;
i2c->intfl0 = i2c->intfl0;
i2c->intfl1 = i2c->intfl1;
/* Send a restart or stop at the end of the transaction */
if (req->restart) { if (req->restart) {
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART;
} } else {
else {
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP;
} }
/* Call the callback */
if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { if (i2c->intfl0 & MXC_I2C_REVA_ERROR) {
MXC_I2C_RevA_AsyncCallback(i2c, E_COMM_ERR); MXC_I2C_RevA_AsyncCallback(i2c, E_COMM_ERR);
} } else {
else {
MXC_I2C_RevA_AsyncCallback(i2c, E_NO_ERROR); MXC_I2C_RevA_AsyncCallback(i2c, E_NO_ERROR);
} }
/* Clear the async state */
MXC_I2C_RevA_AsyncStop(i2c); MXC_I2C_RevA_AsyncStop(i2c);
}
} else {
AsyncWritten[i2cNum] = written; AsyncWritten[i2cNum] = written;
AsyncRead[i2cNum] = read; AsyncRead[i2cNum] = read;
} }
}
unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal) unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
mxc_i2c_reva_slave_handler_t callback,
unsigned int interruptEnables, int *retVal)
{ {
uint32_t tFlags = i2c->intfl0; uint32_t tFlags = i2c->intfl0;
*retVal = E_NO_ERROR; *retVal = E_NO_ERROR;
@ -1235,13 +1294,20 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_r
// I2C_EVT_TRANS_COMP // I2C_EVT_TRANS_COMP
// I2C_EVT_UNDERFLOW // I2C_EVT_UNDERFLOW
// I2C_EVT_OVERFLOW // I2C_EVT_OVERFLOW
if (!(interruptEnables & (MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH| MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) { if (!(interruptEnables &
(MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH |
MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) {
// The STOPERR/STARTERR interrupt that's enabled here could fire before we are addressed // The STOPERR/STARTERR interrupt that's enabled here could fire before we are addressed
// (fires anytime a stop/start is detected out of sequence). // (fires anytime a stop/start is detected out of sequence).
if (tFlags & MXC_I2C_REVA_ERROR) { if (tFlags & MXC_I2C_REVA_ERROR) {
*retVal = E_COMM_ERR; *retVal = E_COMM_ERR;
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal);
MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts }
MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK,
MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts
MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c);
MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c);
interruptEnables = 0; interruptEnables = 0;
@ -1250,30 +1316,47 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_r
if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV)) { if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV)) {
if (tFlags & MXC_F_I2C_REVA_INTFL0_RX_THD) { if (tFlags & MXC_F_I2C_REVA_INTFL0_RX_THD) {
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_RX_THRESH, NULL); callback(i2c, MXC_I2C_REVA_EVT_RX_THRESH, NULL);
}
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD;
} }
if (i2c->intfl1 & MXC_F_I2C_REVA_INTFL1_RX_OV) { if (i2c->intfl1 & MXC_F_I2C_REVA_INTFL1_RX_OV) {
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_OVERFLOW, NULL); callback(i2c, MXC_I2C_REVA_EVT_OVERFLOW, NULL);
}
i2c->intfl1 = MXC_F_I2C_REVA_INTFL1_RX_OV; i2c->intfl1 = MXC_F_I2C_REVA_INTFL1_RX_OV;
} }
} }
if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT)) { if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN |
MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT)) {
if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_THD) { if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_THD) {
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_TX_THRESH, NULL); callback(i2c, MXC_I2C_REVA_EVT_TX_THRESH, NULL);
}
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD;
} }
if (i2c->intfl1 & MXC_F_I2C_REVA_INTFL1_TX_UN) { if (i2c->intfl1 & MXC_F_I2C_REVA_INTFL1_TX_UN) {
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_UNDERFLOW, NULL); callback(i2c, MXC_I2C_REVA_EVT_UNDERFLOW, NULL);
}
i2c->intfl1 = MXC_F_I2C_REVA_INTFL1_TX_UN; i2c->intfl1 = MXC_F_I2C_REVA_INTFL1_TX_UN;
} }
if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT) { if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT) {
*retVal = E_NO_ERROR; *retVal = E_NO_ERROR;
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal);
}
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT;
interruptEnables = 0; interruptEnables = 0;
AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL;
@ -1282,7 +1365,11 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_r
if (tFlags & MXC_F_I2C_REVA_INTFL0_STOP) { if (tFlags & MXC_F_I2C_REVA_INTFL0_STOP) {
*retVal = E_NO_ERROR; *retVal = E_NO_ERROR;
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal);
}
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_STOP; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_STOP;
interruptEnables = 0; interruptEnables = 0;
AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL;
@ -1290,36 +1377,56 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_r
} }
if (tFlags & MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH) { if (tFlags & MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH) {
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL);
}
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | MXC_I2C_REVA_ERROR; interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV |
MXC_I2C_REVA_ERROR;
} }
if (tFlags & MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH) { if (tFlags & MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH) {
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL);
}
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN |
MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR;
} }
if (tFlags & MXC_F_I2C_REVA_INTFL0_ADDR_MATCH) { if (tFlags & MXC_F_I2C_REVA_INTFL0_ADDR_MATCH) {
if (readFlag & MXC_F_I2C_REVA_CTRL_READ) { if (readFlag & MXC_F_I2C_REVA_CTRL_READ) {
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL);
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR;
} }
else {
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN |
MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR;
} else {
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL);
}
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | MXC_I2C_REVA_ERROR; interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV |
MXC_I2C_REVA_ERROR;
} }
} else if (tFlags & MXC_I2C_REVA_ERROR) { } else if (tFlags & MXC_I2C_REVA_ERROR) {
*retVal = E_COMM_ERR; *retVal = E_COMM_ERR;
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal);
MXC_I2C_RevA_ClearFlags(i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // clear all i2c interrupts }
MXC_I2C_RevA_ClearFlags(i2c, MXC_I2C_REVA_INTFL0_MASK,
MXC_I2C_REVA_INTFL1_MASK); // clear all i2c interrupts
MXC_I2C_RevA_ClearTXFIFO(i2c); MXC_I2C_RevA_ClearTXFIFO(i2c);
MXC_I2C_RevA_ClearRXFIFO(i2c); MXC_I2C_RevA_ClearRXFIFO(i2c);
interruptEnables = 0; interruptEnables = 0;
@ -1340,8 +1447,7 @@ void MXC_I2C_RevA_AsyncHandler (mxc_i2c_reva_regs_t* i2c, uint32_t interruptChec
if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE) { if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE) {
MXC_I2C_RevA_MasterAsyncHandler(i2cNum); MXC_I2C_RevA_MasterAsyncHandler(i2cNum);
} } else {
else {
mxc_i2c_reva_slave_handler_t callback = (mxc_i2c_reva_slave_handler_t)AsyncRequests[i2cNum]; mxc_i2c_reva_slave_handler_t callback = (mxc_i2c_reva_slave_handler_t)AsyncRequests[i2cNum];
i2c->inten0 = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, i2c->inten0, &slaveRetVal); i2c->inten0 = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, i2c->inten0, &slaveRetVal);
} }

45
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h
View File

@ -1,5 +1,5 @@
/* **************************************************************************** /* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -31,8 +31,8 @@
* *
*************************************************************************** */ *************************************************************************** */
#ifndef _I2C_REVA_H_ #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_
#define _I2C_REVA_H_ #define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_
#include <stdio.h> #include <stdio.h>
#include <stddef.h> #include <stddef.h>
@ -46,7 +46,6 @@
#include "i2c_reva_regs.h" #include "i2c_reva_regs.h"
#include "dma.h" #include "dma.h"
/* **** Definitions **** */ /* **** Definitions **** */
#define MXC_I2C_REVA_MAX_ADDR_WIDTH 0x7F #define MXC_I2C_REVA_MAX_ADDR_WIDTH 0x7F
#define MXC_I2C_REVA_STD_MODE 100000 #define MXC_I2C_REVA_STD_MODE 100000
@ -59,8 +58,10 @@
#define MXC_I2C_REVA_MAX_FIFO_TRANSACTION 256 #define MXC_I2C_REVA_MAX_FIFO_TRANSACTION 256
#define MXC_I2C_REVA_ERROR (MXC_F_I2C_REVA_INTFL0_ARB_ERR | MXC_F_I2C_REVA_INTFL0_TO_ERR | MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR | \ #define MXC_I2C_REVA_ERROR \
MXC_F_I2C_REVA_INTFL0_DATA_ERR | MXC_F_I2C_REVA_INTFL0_DNR_ERR | MXC_F_I2C_REVA_INTFL0_START_ERR | \ (MXC_F_I2C_REVA_INTFL0_ARB_ERR | MXC_F_I2C_REVA_INTFL0_TO_ERR | \
MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR | MXC_F_I2C_REVA_INTFL0_DATA_ERR | \
MXC_F_I2C_REVA_INTFL0_DNR_ERR | MXC_F_I2C_REVA_INTFL0_START_ERR | \
MXC_F_I2C_REVA_INTFL0_STOP_ERR) MXC_F_I2C_REVA_INTFL0_STOP_ERR)
typedef struct _i2c_reva_req_t mxc_i2c_reva_req_t; typedef struct _i2c_reva_req_t mxc_i2c_reva_req_t;
@ -90,6 +91,8 @@ typedef int (*mxc_i2c_reva_slave_handler_t) (mxc_i2c_reva_regs_t* i2c,
mxc_i2c_reva_slave_event_t event, void *data); mxc_i2c_reva_slave_event_t event, void *data);
/* **** Variable Declaration **** */ /* **** Variable Declaration **** */
extern void *AsyncRequests[MXC_I2C_INSTANCES];
/* **** Function Prototypes **** */ /* **** Function Prototypes **** */
/* ************************************************************************* */ /* ************************************************************************* */
@ -111,14 +114,21 @@ int MXC_I2C_RevA_Start (mxc_i2c_reva_regs_t* i2c);
int MXC_I2C_RevA_Stop(mxc_i2c_reva_regs_t *i2c); int MXC_I2C_RevA_Stop(mxc_i2c_reva_regs_t *i2c);
int MXC_I2C_RevA_WriteByte(mxc_i2c_reva_regs_t *i2c, unsigned char byte); int MXC_I2C_RevA_WriteByte(mxc_i2c_reva_regs_t *i2c, unsigned char byte);
int MXC_I2C_RevA_ReadByte(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, int ack); int MXC_I2C_RevA_ReadByte(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, int ack);
int MXC_I2C_RevA_ReadByteInteractive (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, mxc_i2c_reva_getAck_t getAck); int MXC_I2C_RevA_ReadByteInteractive(mxc_i2c_reva_regs_t *i2c, unsigned char *byte,
mxc_i2c_reva_getAck_t getAck);
int MXC_I2C_RevA_Write(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len); int MXC_I2C_RevA_Write(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len);
int MXC_I2C_RevA_Read(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack); int MXC_I2C_RevA_Read(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack);
int MXC_I2C_RevA_ReadRXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len); int MXC_I2C_RevA_ReadRXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes,
int MXC_I2C_RevA_ReadRXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma); unsigned int len);
int MXC_I2C_RevA_ReadRXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len,
mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config,
mxc_dma_regs_t *dma);
int MXC_I2C_RevA_GetRXFIFOAvailable(mxc_i2c_reva_regs_t *i2c); int MXC_I2C_RevA_GetRXFIFOAvailable(mxc_i2c_reva_regs_t *i2c);
int MXC_I2C_RevA_WriteTXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len); int MXC_I2C_RevA_WriteTXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes,
int MXC_I2C_RevA_WriteTXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma); unsigned int len);
int MXC_I2C_RevA_WriteTXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len,
mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config,
mxc_dma_regs_t *dma);
int MXC_I2C_RevA_GetTXFIFOAvailable(mxc_i2c_reva_regs_t *i2c); int MXC_I2C_RevA_GetTXFIFOAvailable(mxc_i2c_reva_regs_t *i2c);
void MXC_I2C_RevA_ClearRXFIFO(mxc_i2c_reva_regs_t *i2c); void MXC_I2C_RevA_ClearRXFIFO(mxc_i2c_reva_regs_t *i2c);
void MXC_I2C_RevA_ClearTXFIFO(mxc_i2c_reva_regs_t *i2c); void MXC_I2C_RevA_ClearTXFIFO(mxc_i2c_reva_regs_t *i2c);
@ -140,8 +150,11 @@ int MXC_I2C_RevA_Recover (mxc_i2c_reva_regs_t* i2c, unsigned int retries);
int MXC_I2C_RevA_MasterTransaction(mxc_i2c_reva_req_t *req); int MXC_I2C_RevA_MasterTransaction(mxc_i2c_reva_req_t *req);
int MXC_I2C_RevA_MasterTransactionAsync(mxc_i2c_reva_req_t *req); int MXC_I2C_RevA_MasterTransactionAsync(mxc_i2c_reva_req_t *req);
int MXC_I2C_RevA_MasterTransactionDMA(mxc_i2c_reva_req_t *req, mxc_dma_regs_t *dma); int MXC_I2C_RevA_MasterTransactionDMA(mxc_i2c_reva_req_t *req, mxc_dma_regs_t *dma);
int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck); int MXC_I2C_RevA_SlaveTransaction(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback,
int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck); uint32_t interruptCheck);
int MXC_I2C_RevA_SlaveTransactionAsync(mxc_i2c_reva_regs_t *i2c,
mxc_i2c_reva_slave_handler_t callback,
uint32_t interruptCheck);
int MXC_I2C_RevA_SetRXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes); int MXC_I2C_RevA_SetRXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes);
unsigned int MXC_I2C_RevA_GetRXThreshold(mxc_i2c_reva_regs_t *i2c); unsigned int MXC_I2C_RevA_GetRXThreshold(mxc_i2c_reva_regs_t *i2c);
int MXC_I2C_RevA_SetTXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes); int MXC_I2C_RevA_SetTXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes);
@ -150,8 +163,10 @@ void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal);
void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c); void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c);
void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c); void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c);
void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum); void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum);
unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal); unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
mxc_i2c_reva_slave_handler_t callback,
unsigned int interruptEnables, int *retVal);
void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck); void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck);
void MXC_I2C_RevA_DMACallback(int ch, int error); void MXC_I2C_RevA_DMACallback(int ch, int error);
#endif /* _I2C_REVA_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_

9
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h
View File

@ -4,7 +4,7 @@
*/ */
/* **************************************************************************** /* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -37,8 +37,8 @@
* *
*************************************************************************** */ *************************************************************************** */
#ifndef _I2C_REVA_REGS_H_ #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_
#define _I2C_REVA_REGS_H_ #define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -577,4 +577,5 @@ typedef struct {
} }
#endif #endif
#endif /* _I2C_REGS_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_

47
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_me15.c
View File

@ -31,7 +31,6 @@
* *
*************************************************************************** */ *************************************************************************** */
#include <stdio.h> #include <stdio.h>
#include <stddef.h> #include <stddef.h>
#include <stdint.h> #include <stdint.h>
@ -46,7 +45,6 @@
#include "mxc_i2c.h" #include "mxc_i2c.h"
#include "i2c_reva.h" #include "i2c_reva.h"
/* **** Definitions **** */ /* **** Definitions **** */
#define MXC_I2C_FASTPLUS_SPEED 1000000 #define MXC_I2C_FASTPLUS_SPEED 1000000
@ -69,18 +67,15 @@ int MXC_I2C_Init(mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr)
if (i2c == MXC_I2C0) { if (i2c == MXC_I2C0) {
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C0); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C0);
MXC_GPIO_Config(&gpio_cfg_i2c0); MXC_GPIO_Config(&gpio_cfg_i2c0);
}
#if TARGET_NUM != 32675 #if TARGET_NUM != 32675
else if (i2c == MXC_I2C1) { } else if (i2c == MXC_I2C1) {
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C1); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C1);
MXC_GPIO_Config(&gpio_cfg_i2c1); MXC_GPIO_Config(&gpio_cfg_i2c1);
}
#endif #endif
else if (i2c == MXC_I2C2) { } else if (i2c == MXC_I2C2) {
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C2); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C2);
MXC_GPIO_Config(&gpio_cfg_i2c2); MXC_GPIO_Config(&gpio_cfg_i2c2);
} } else {
else {
return E_NO_DEVICE; return E_NO_DEVICE;
} }
@ -121,16 +116,13 @@ int MXC_I2C_Shutdown(mxc_i2c_regs_t* i2c)
if (i2c == MXC_I2C0) { if (i2c == MXC_I2C0) {
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C0); MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C0);
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I2C0); MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I2C0);
} } else if (i2c == MXC_I2C1) {
else if (i2c == MXC_I2C1) {
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1); MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1);
MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C1); MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C1);
} } else if (i2c == MXC_I2C2) {
else if (i2c == MXC_I2C2) {
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C2); MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C2);
MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C2); MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C2);
} } else {
else {
return E_NO_DEVICE; return E_NO_DEVICE;
} }
@ -142,14 +134,11 @@ int MXC_I2C_Reset (mxc_i2c_regs_t* i2c)
// Configure GPIO for I2C // Configure GPIO for I2C
if (i2c == MXC_I2C0) { if (i2c == MXC_I2C0) {
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I2C0); MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I2C0);
} } else if (i2c == MXC_I2C1) {
else if(i2c == MXC_I2C1) {
MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C1); MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C1);
} } else if (i2c == MXC_I2C2) {
else if(i2c == MXC_I2C2) {
MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C2); MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C2);
} } else {
else {
return E_NO_DEVICE; return E_NO_DEVICE;
} }
@ -226,7 +215,8 @@ int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, unsig
return MXC_I2C_RevA_ReadRXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len); return MXC_I2C_RevA_ReadRXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len);
} }
int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_dma_complete_cb_t callback) int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len,
mxc_i2c_dma_complete_cb_t callback)
{ {
uint8_t i2cNum; uint8_t i2cNum;
mxc_dma_config_t config; mxc_dma_config_t config;
@ -246,7 +236,8 @@ int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned in
return E_BAD_PARAM; return E_BAD_PARAM;
} }
return MXC_I2C_RevA_ReadRXFIFODMA ((mxc_i2c_reva_regs_t*) i2c, bytes, len, callback, config, MXC_DMA); return MXC_I2C_RevA_ReadRXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len, callback, config,
MXC_DMA);
} }
int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t *i2c) int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t *i2c)
@ -259,7 +250,8 @@ int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, unsi
return MXC_I2C_RevA_WriteTXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len); return MXC_I2C_RevA_WriteTXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len);
} }
int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_dma_complete_cb_t callback) int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len,
mxc_i2c_dma_complete_cb_t callback)
{ {
uint8_t i2cNum; uint8_t i2cNum;
mxc_dma_config_t config; mxc_dma_config_t config;
@ -279,7 +271,8 @@ int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned i
return E_BAD_PARAM; return E_BAD_PARAM;
} }
return MXC_I2C_RevA_WriteTXFIFODMA ((mxc_i2c_reva_regs_t*) i2c, bytes, len, callback, config, MXC_DMA); return MXC_I2C_RevA_WriteTXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len, callback, config,
MXC_DMA);
} }
int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t *i2c) int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t *i2c)
@ -373,12 +366,14 @@ int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t* req)
int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback) int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback)
{ {
return MXC_I2C_RevA_SlaveTransaction ((mxc_i2c_reva_regs_t*) i2c, (mxc_i2c_reva_slave_handler_t) callback, interruptCheck); return MXC_I2C_RevA_SlaveTransaction((mxc_i2c_reva_regs_t *)i2c,
(mxc_i2c_reva_slave_handler_t)callback, interruptCheck);
} }
int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback) int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback)
{ {
return MXC_I2C_RevA_SlaveTransactionAsync ((mxc_i2c_reva_regs_t*) i2c, (mxc_i2c_reva_slave_handler_t) callback, interruptCheck); return MXC_I2C_RevA_SlaveTransactionAsync(
(mxc_i2c_reva_regs_t *)i2c, (mxc_i2c_reva_slave_handler_t)callback, interruptCheck);
} }
int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes) int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes)

376
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c
View File

@ -66,7 +66,9 @@ void MXC_I2C_RevA_AsyncStop (mxc_i2c_reva_regs_t* i2c);
void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c); void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c);
void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum); void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum);
int MXC_I2C_RevA_DMAHandler(mxc_i2c_reva_req_t *req); int MXC_I2C_RevA_DMAHandler(mxc_i2c_reva_req_t *req);
unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal); unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
mxc_i2c_reva_slave_handler_t callback,
unsigned int interruptEnables, int *retVal);
/* ************************************************************************* */ /* ************************************************************************* */
/* Control/Configuration functions */ /* Control/Configuration functions */
@ -94,8 +96,7 @@ int MXC_I2C_RevA_Init (mxc_i2c_reva_regs_t* i2c, int masterMode, unsigned int sl
if (!masterMode) { if (!masterMode) {
MXC_I2C_SetSlaveAddr((mxc_i2c_regs_t *)i2c, slaveAddr, 0); MXC_I2C_SetSlaveAddr((mxc_i2c_regs_t *)i2c, slaveAddr, 0);
states[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)].master = 0; states[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)].master = 0;
} } else {
else {
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_MST_MODE; i2c->ctrl |= MXC_F_I2C_REVA_CTRL_MST_MODE;
states[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)].master = 1; states[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)].master = 1;
} }
@ -219,8 +220,7 @@ int MXC_I2C_RevA_SetClockStretching (mxc_i2c_reva_regs_t* i2c, int enable)
if (enable) { if (enable) {
i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_CLKSTR_DIS; i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_CLKSTR_DIS;
} } else {
else {
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_CLKSTR_DIS; i2c->ctrl |= MXC_F_I2C_REVA_CTRL_CLKSTR_DIS;
} }
@ -248,8 +248,7 @@ int MXC_I2C_RevA_Start (mxc_i2c_reva_regs_t* i2c)
// If we have an incomplete transfer, we need to do a restart // If we have an incomplete transfer, we need to do a restart
if (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_START) { if (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_START) {
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART;
} } else {
else {
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; // No check for start generation i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; // No check for start generation
} }
@ -264,7 +263,7 @@ int MXC_I2C_RevA_Stop (mxc_i2c_reva_regs_t* i2c)
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP;
while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_STOP); while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_STOP) {}
return E_NO_ERROR; return E_NO_ERROR;
} }
@ -284,7 +283,7 @@ int MXC_I2C_RevA_WriteByte (mxc_i2c_reva_regs_t* i2c, unsigned char byte)
MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK);
i2c->fifo = byte; i2c->fifo = byte;
while (! (i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)); while (!(i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)) {}
return i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DATA_ERR; return i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DATA_ERR;
} }
@ -295,7 +294,7 @@ int MXC_I2C_RevA_ReadByte (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, int ac
return E_NULL_PTR; return E_NULL_PTR;
} }
if (! (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM)) { if (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM) {
return E_UNDERFLOW; return E_UNDERFLOW;
} }
@ -310,7 +309,8 @@ int MXC_I2C_RevA_ReadByte (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, int ac
return E_NO_ERROR; return E_NO_ERROR;
} }
int MXC_I2C_RevA_ReadByteInteractive (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, mxc_i2c_reva_getAck_t getAck) int MXC_I2C_RevA_ReadByteInteractive(mxc_i2c_reva_regs_t *i2c, unsigned char *byte,
mxc_i2c_reva_getAck_t getAck)
{ {
if ((i2c == NULL) || (byte == NULL)) { if ((i2c == NULL) || (byte == NULL)) {
return E_NULL_PTR; return E_NULL_PTR;
@ -324,9 +324,9 @@ int MXC_I2C_RevA_ReadByteInteractive (mxc_i2c_reva_regs_t* i2c, unsigned char* b
if (getAck == NULL) { if (getAck == NULL) {
i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS; i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS;
} } else {
else { i2c->ctrl |= (!!getAck((mxc_i2c_reva_regs_t *)i2c, *byte))
i2c->ctrl |= (!!getAck ((mxc_i2c_reva_regs_t*) i2c, *byte)) << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS; << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS;
} }
return E_NO_ERROR; return E_NO_ERROR;
@ -350,8 +350,7 @@ int MXC_I2C_RevA_Write (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned
if (retVal >= 0) { if (retVal >= 0) {
notAcked += retVal; notAcked += retVal;
} } else {
else {
*len = written; *len = written;
return retVal; return retVal;
} }
@ -388,7 +387,8 @@ int MXC_I2C_RevA_Read (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned
return MXC_I2C_ReadByte((mxc_i2c_regs_t *)i2c, &(bytes[read]), ack); return MXC_I2C_ReadByte((mxc_i2c_regs_t *)i2c, &(bytes[read]), ack);
} }
int MXC_I2C_RevA_ReadRXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) int MXC_I2C_RevA_ReadRXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes,
unsigned int len)
{ {
unsigned read = 0; unsigned read = 0;
@ -403,8 +403,9 @@ int MXC_I2C_RevA_ReadRXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* b
return read; return read;
} }
int MXC_I2C_RevA_ReadRXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, \ int MXC_I2C_RevA_ReadRXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len,
mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma) mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config,
mxc_dma_regs_t *dma)
{ {
uint8_t i2cNum; uint8_t i2cNum;
uint8_t channel; uint8_t channel;
@ -439,9 +440,7 @@ int MXC_I2C_RevA_ReadRXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes,
if (states[i2cNum].master) { if (states[i2cNum].master) {
MXC_DMA_SetCallback(channel, MXC_I2C_RevA_DMACallback); MXC_DMA_SetCallback(channel, MXC_I2C_RevA_DMACallback);
} } else {
else {
MXC_DMA_SetCallback(channel, NULL); MXC_DMA_SetCallback(channel, NULL);
} }
@ -463,7 +462,8 @@ int MXC_I2C_RevA_GetRXFIFOAvailable (mxc_i2c_reva_regs_t* i2c)
return (i2c->rxctrl1 & MXC_F_I2C_REVA_RXCTRL1_LVL) >> MXC_F_I2C_REVA_RXCTRL1_LVL_POS; return (i2c->rxctrl1 & MXC_F_I2C_REVA_RXCTRL1_LVL) >> MXC_F_I2C_REVA_RXCTRL1_LVL_POS;
} }
int MXC_I2C_RevA_WriteTXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) int MXC_I2C_RevA_WriteTXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes,
unsigned int len)
{ {
unsigned written = 0; unsigned written = 0;
@ -478,8 +478,9 @@ int MXC_I2C_RevA_WriteTXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char*
return written; return written;
} }
int MXC_I2C_RevA_WriteTXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, \ int MXC_I2C_RevA_WriteTXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len,
mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma) mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config,
mxc_dma_regs_t *dma)
{ {
uint8_t i2cNum; uint8_t i2cNum;
uint8_t channel; uint8_t channel;
@ -516,8 +517,7 @@ int MXC_I2C_RevA_WriteTXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes,
if (states[i2cNum].master) { if (states[i2cNum].master) {
MXC_DMA_SetCallback(channel, MXC_I2C_RevA_DMACallback); MXC_DMA_SetCallback(channel, MXC_I2C_RevA_DMACallback);
} } else {
else {
MXC_DMA_SetCallback(channel, NULL); MXC_DMA_SetCallback(channel, NULL);
} }
@ -536,22 +536,24 @@ int MXC_I2C_RevA_GetTXFIFOAvailable (mxc_i2c_reva_regs_t* i2c)
return E_NULL_PTR; return E_NULL_PTR;
} }
int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >>
return txFIFOlen - ( (i2c->txctrl1 & MXC_F_I2C_REVA_TXCTRL1_LVL) >> MXC_F_I2C_REVA_TXCTRL1_LVL_POS); MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS;
return txFIFOlen -
((i2c->txctrl1 & MXC_F_I2C_REVA_TXCTRL1_LVL) >> MXC_F_I2C_REVA_TXCTRL1_LVL_POS);
} }
void MXC_I2C_RevA_ClearRXFIFO(mxc_i2c_reva_regs_t *i2c) void MXC_I2C_RevA_ClearRXFIFO(mxc_i2c_reva_regs_t *i2c)
{ {
i2c->rxctrl0 |= MXC_F_I2C_REVA_RXCTRL0_FLUSH; i2c->rxctrl0 |= MXC_F_I2C_REVA_RXCTRL0_FLUSH;
while (i2c->rxctrl0 & MXC_F_I2C_REVA_RXCTRL0_FLUSH); while (i2c->rxctrl0 & MXC_F_I2C_REVA_RXCTRL0_FLUSH) {}
} }
void MXC_I2C_RevA_ClearTXFIFO(mxc_i2c_reva_regs_t *i2c) void MXC_I2C_RevA_ClearTXFIFO(mxc_i2c_reva_regs_t *i2c)
{ {
i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_FLUSH; i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_FLUSH;
while (i2c->txctrl0 & MXC_F_I2C_REVA_TXCTRL0_FLUSH); while (i2c->txctrl0 & MXC_F_I2C_REVA_TXCTRL0_FLUSH) {}
} }
int MXC_I2C_RevA_GetFlags(mxc_i2c_reva_regs_t *i2c, unsigned int *flags0, unsigned int *flags1) int MXC_I2C_RevA_GetFlags(mxc_i2c_reva_regs_t *i2c, unsigned int *flags0, unsigned int *flags1)
@ -673,12 +675,12 @@ void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t* i2c)
void MXC_I2C_RevA_EnableGeneralCall(mxc_i2c_reva_regs_t *i2c) void MXC_I2C_RevA_EnableGeneralCall(mxc_i2c_reva_regs_t *i2c)
{ {
i2c->txctrl0 &= ~MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS; i2c->ctrl |= MXC_F_I2C_REVA_CTRL_GC_ADDR_EN;
} }
void MXC_I2C_RevA_DisableGeneralCall(mxc_i2c_reva_regs_t *i2c) void MXC_I2C_RevA_DisableGeneralCall(mxc_i2c_reva_regs_t *i2c)
{ {
i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS; i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_GC_ADDR_EN;
} }
void MXC_I2C_RevA_SetTimeout(mxc_i2c_reva_regs_t *i2c, unsigned int timeout) void MXC_I2C_RevA_SetTimeout(mxc_i2c_reva_regs_t *i2c, unsigned int timeout)
@ -729,7 +731,8 @@ int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req)
// stop or restart // stop or restart
// return good or error // return good or error
MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK,
MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts
MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c);
MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c);
i2c->inten0 = 0; i2c->inten0 = 0;
@ -743,7 +746,8 @@ int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req)
while (req->tx_len > written) { while (req->tx_len > written) {
if (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_TX_THD) { if (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_TX_THD) {
written += MXC_I2C_WriteTXFIFO ((mxc_i2c_regs_t*) i2c, &req->tx_buf[written], req->tx_len - written); written += MXC_I2C_WriteTXFIFO((mxc_i2c_regs_t *)i2c, &req->tx_buf[written],
req->tx_len - written);
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD;
} }
@ -754,26 +758,27 @@ int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req)
} }
} }
MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_RX_THD, 0); MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c,
MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_RX_THD, 0);
if (req->rx_len != 0) { if (req->rx_len != 0) {
if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) {
i2c->rxctrl1 = 0; i2c->rxctrl1 = 0;
} } else {
else {
i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read
} }
MXC_I2C_Start((mxc_i2c_regs_t *)i2c); // Start or Restart as needed MXC_I2C_Start((mxc_i2c_regs_t *)i2c); // Start or Restart as needed
while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART); while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART) {}
i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit.
} }
while (req->rx_len > read) { while (req->rx_len > read) {
if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) { if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) {
read += MXC_I2C_ReadRXFIFO ((mxc_i2c_regs_t*) i2c, &req->rx_buf[read], req->rx_len - read); read +=
MXC_I2C_ReadRXFIFO((mxc_i2c_regs_t *)i2c, &req->rx_buf[read], req->rx_len - read);
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD;
} }
@ -786,8 +791,7 @@ int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req)
if ((i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) { if ((i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) {
if ((req->rx_len - read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { if ((req->rx_len - read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) {
i2c->rxctrl1 = 0; i2c->rxctrl1 = 0;
} } else {
else {
i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read
} }
@ -799,13 +803,15 @@ int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req)
if (req->restart) { if (req->restart) {
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART;
} } else {
else {
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP;
while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_STOP)) {}
// Wait for Transaction to finish
} }
while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_STOP)); // Wait for Transaction to finish while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)) {}
while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)); // Wait for Transaction to finish // Wait for Transaction to finish
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_STOP; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_STOP;
@ -837,19 +843,39 @@ int MXC_I2C_RevA_MasterTransactionAsync (mxc_i2c_reva_req_t* req)
AsyncRequests[i2cNum] = (void *)req; AsyncRequests[i2cNum] = (void *)req;
AsyncWritten[i2cNum] = 0; AsyncWritten[i2cNum] = 0;
AsyncRead[i2cNum] = 0; AsyncRead[i2cNum] = 0;
MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK,
MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts
MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c);
MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c);
if ((req->rx_len == 0) || (req->tx_len != 0)) { i2c->inten0 = MXC_I2C_REVA_ERROR;
if (req->tx_len) {
i2c->fifo = (req->addr << 1) & ~0x1; // Load the slave address with write bit set i2c->fifo = (req->addr << 1) & ~0x1; // Load the slave address with write bit set
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; } else if (req->rx_len) {
i2c->fifo = (req->addr << 1) | 0x1; // Load the slave address with read bit set
/* Set the number of bytes to read */
if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) {
i2c->rxctrl1 = 0;
} else {
i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read
} }
i2c->inten0 = MXC_I2C_REVA_ERROR | MXC_F_I2C_REVA_INTEN0_TX_THD; /* Enable RX Threshold interrupt for when the FIFO is full */
return E_NO_ERROR; i2c->inten0 |= (MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE);
} else {
/* Must have tx_len and/or rx_len */
return E_BAD_PARAM;
} }
else {
MXC_I2C_Start((mxc_i2c_regs_t *)i2c);
/* Fill the FIFO as nessary */
MXC_I2C_RevA_MasterAsyncHandler(i2cNum);
return E_NO_ERROR;
} else {
return E_BUSY; return E_BUSY;
} }
} }
@ -877,7 +903,8 @@ int MXC_I2C_RevA_MasterTransactionDMA (mxc_i2c_reva_req_t* req, mxc_dma_regs_t*
return E_BAD_PARAM; return E_BAD_PARAM;
} }
MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK,
MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts
MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c);
MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c);
@ -904,25 +931,24 @@ int MXC_I2C_RevA_MasterTransactionDMA (mxc_i2c_reva_req_t* req, mxc_dma_regs_t*
#else #else
MXC_I2C_WriteTXFIFODMA((mxc_i2c_regs_t *)i2c, req->tx_buf, req->tx_len, NULL); MXC_I2C_WriteTXFIFODMA((mxc_i2c_regs_t *)i2c, req->tx_buf, req->tx_len, NULL);
#endif #endif
} } else {
else {
states[i2cNum].writeDone = 1; states[i2cNum].writeDone = 1;
} }
if (req->rx_buf != NULL) { if (req->rx_buf != NULL) {
while(states[i2cNum].writeDone != 1); //Ensure DMA transmit has finished before attempting to receive while (states[i2cNum].writeDone != 1) {}
//Ensure DMA transmit has finished before attempting to receive
if ((states[i2cNum].writeDone) && (!states[i2cNum].readDone)) { if ((states[i2cNum].writeDone) && (!states[i2cNum].readDone)) {
if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) {
i2c->rxctrl1 = 0; i2c->rxctrl1 = 0;
} } else {
else {
i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read
} }
MXC_I2C_Start((mxc_i2c_regs_t *)i2c); // Start or Restart as needed MXC_I2C_Start((mxc_i2c_regs_t *)i2c); // Start or Restart as needed
while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART); while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART) {}
i2c->fifo = ((req->addr) << 1) | 0x1; // Load the slave address with write bit set i2c->fifo = ((req->addr) << 1) | 0x1; // Load the slave address with write bit set
@ -932,8 +958,7 @@ int MXC_I2C_RevA_MasterTransactionDMA (mxc_i2c_reva_req_t* req, mxc_dma_regs_t*
MXC_I2C_ReadRXFIFODMA((mxc_i2c_regs_t *)i2c, req->rx_buf, req->rx_len, NULL); MXC_I2C_ReadRXFIFODMA((mxc_i2c_regs_t *)i2c, req->rx_buf, req->rx_len, NULL);
#endif #endif
} }
} } else {
else {
states[i2cNum].readDone = 1; states[i2cNum].readDone = 1;
} }
@ -953,8 +978,7 @@ void MXC_I2C_RevA_DMACallback(int ch, int error)
if (states[i].readDone) { if (states[i].readDone) {
if (temp_req->restart) { if (temp_req->restart) {
(temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART;
} } else {
else {
(temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP;
} }
@ -966,9 +990,7 @@ void MXC_I2C_RevA_DMACallback(int ch, int error)
temp_req->callback(temp_req, E_NO_ERROR); temp_req->callback(temp_req, E_NO_ERROR);
} }
} }
} } else if (states[i].channelRx == ch) {
else if (states[i].channelRx == ch) {
//save the request //save the request
states[i].readDone = 1; states[i].readDone = 1;
temp_req = states[i].req; temp_req = states[i].req;
@ -976,8 +998,7 @@ void MXC_I2C_RevA_DMACallback(int ch, int error)
if (states[i].writeDone) { if (states[i].writeDone) {
if (temp_req->restart) { if (temp_req->restart) {
(temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART;
} } else {
else {
(temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP;
} }
@ -993,7 +1014,8 @@ void MXC_I2C_RevA_DMACallback(int ch, int error)
} }
} }
int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck) int MXC_I2C_RevA_SlaveTransaction(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback,
uint32_t interruptCheck)
{ {
unsigned int interruptEnables = interruptCheck; unsigned int interruptEnables = interruptCheck;
int retVal = E_NO_ERROR; int retVal = E_NO_ERROR;
@ -1006,7 +1028,8 @@ int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_
return E_BAD_STATE; return E_BAD_STATE;
} }
MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK,
MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts
MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c);
MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c);
@ -1034,7 +1057,9 @@ int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_
return retVal; return retVal;
} }
int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck) int MXC_I2C_RevA_SlaveTransactionAsync(mxc_i2c_reva_regs_t *i2c,
mxc_i2c_reva_slave_handler_t callback,
uint32_t interruptCheck)
{ {
int i2cnum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); int i2cnum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c);
@ -1050,7 +1075,8 @@ int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_s
return E_BUSY; return E_BUSY;
} }
MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK,
MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts
MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c);
MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c);
MXC_I2C_SetTXThreshold((mxc_i2c_regs_t *)i2c, 1); // set TX threshold to 2 bytes MXC_I2C_SetTXThreshold((mxc_i2c_regs_t *)i2c, 1); // set TX threshold to 2 bytes
@ -1064,13 +1090,15 @@ int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_s
int MXC_I2C_RevA_SetRXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes) int MXC_I2C_RevA_SetRXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes)
{ {
unsigned int rxFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS; unsigned int rxFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH) >>
MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS;
if (numBytes > rxFIFOlen) { if (numBytes > rxFIFOlen) {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
i2c->rxctrl0 = (i2c->rxctrl0 & ~MXC_F_I2C_REVA_RXCTRL0_THD_LVL) | (numBytes << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS); i2c->rxctrl0 = (i2c->rxctrl0 & ~MXC_F_I2C_REVA_RXCTRL0_THD_LVL) |
(numBytes << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS);
return E_NO_ERROR; return E_NO_ERROR;
} }
@ -1081,13 +1109,15 @@ unsigned int MXC_I2C_RevA_GetRXThreshold (mxc_i2c_reva_regs_t* i2c)
int MXC_I2C_RevA_SetTXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes) int MXC_I2C_RevA_SetTXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes)
{ {
unsigned int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; unsigned int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >>
MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS;
if (numBytes > txFIFOlen) { if (numBytes > txFIFOlen) {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
i2c->txctrl0 = (i2c->txctrl0 & ~MXC_F_I2C_REVA_TXCTRL0_THD_LVL) | (numBytes << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS); i2c->txctrl0 = (i2c->txctrl0 & ~MXC_F_I2C_REVA_TXCTRL0_THD_LVL) |
(numBytes << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS);
return E_NO_ERROR; return E_NO_ERROR;
} }
@ -1100,7 +1130,8 @@ void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal)
{ {
// Don't need to check for return value as this function is not accessible to user // Don't need to check for return value as this function is not accessible to user
// i2c is already cheked for NULL from where this function is being called // i2c is already cheked for NULL from where this function is being called
mxc_i2c_reva_req_t* req = (mxc_i2c_reva_req_t*) AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)]; mxc_i2c_reva_req_t *req =
(mxc_i2c_reva_req_t *)AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)];
if (req->callback != NULL) { if (req->callback != NULL) {
req->callback(req, retVal); req->callback(req, retVal);
@ -1109,9 +1140,13 @@ void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal)
void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c) void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c)
{ {
/* Disable and clear interrupts */
i2c->inten0 = 0; i2c->inten0 = 0;
i2c->inten1 = 0; i2c->inten1 = 0;
i2c->intfl0 = i2c->intfl0;
i2c->intfl1 = i2c->intfl1;
// Don't need to check for return value as this function is not accessible to user // Don't need to check for return value as this function is not accessible to user
// i2c is already cheked for NULL from where this function is being called // i2c is already cheked for NULL from where this function is being called
AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL;
@ -1132,88 +1167,112 @@ void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum)
mxc_i2c_reva_regs_t *i2c = (mxc_i2c_reva_regs_t *)MXC_I2C_GET_BASE(i2cNum); mxc_i2c_reva_regs_t *i2c = (mxc_i2c_reva_regs_t *)MXC_I2C_GET_BASE(i2cNum);
mxc_i2c_reva_req_t *req = (mxc_i2c_reva_req_t *)AsyncRequests[i2cNum]; mxc_i2c_reva_req_t *req = (mxc_i2c_reva_req_t *)AsyncRequests[i2cNum];
/* Check for errors */
if (i2c->intfl0 & MXC_I2C_REVA_ERROR) {
/* Clear and disable interrupts */
i2c->intfl0 = i2c->intfl0;
i2c->intfl1 = i2c->intfl1;
i2c->inten0 = 0;
i2c->inten1 = 0;
MXC_I2C_Stop((mxc_i2c_regs_t *)i2c);
MXC_I2C_RevA_AsyncCallback(i2c, E_COMM_ERR);
MXC_I2C_RevA_AsyncStop(i2c);
return;
}
/* Write data to the TX FIFO */
if (req->tx_len > written) { if (req->tx_len > written) {
if (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_TX_THD) { if (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_TX_THD) {
written += MXC_I2C_WriteTXFIFO ((mxc_i2c_regs_t*) i2c, &req->tx_buf[written], req->tx_len - written); written += MXC_I2C_WriteTXFIFO((mxc_i2c_regs_t *)i2c, &req->tx_buf[written],
req->tx_len - written);
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD;
} }
if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { /* Enable the TX Threshold interrupt if we still need to write to the TX FIFO */
req->tx_len = written; if (written < req->tx_len) {
MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); i2c->inten0 |= MXC_F_I2C_REVA_INTEN0_TX_THD;
MXC_I2C_RevA_AsyncCallback (i2c, E_COMM_ERR); } else {
MXC_I2C_RevA_AsyncStop (i2c); i2c->inten0 &= ~(MXC_F_I2C_REVA_INTEN0_TX_THD);
}
/* Send a restart if we're reading after writing */
if ((req->tx_len == written) && (req->rx_len)) {
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE;
i2c->inten0 |= (MXC_F_I2C_REVA_INTEN0_DONE);
} }
} }
/* Read data in the RX FIFO */
if (req->rx_len > read) { if (req->rx_len > read) {
if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) { if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) {
read += MXC_I2C_ReadRXFIFO ((mxc_i2c_regs_t*) i2c, &req->rx_buf[read], req->rx_len - read); read +=
MXC_I2C_ReadRXFIFO((mxc_i2c_regs_t *)i2c, &req->rx_buf[read], req->rx_len - read);
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD;
} }
if (i2c->intfl0 & MXC_I2C_REVA_ERROR) {
req->rx_len = read;
MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c);
MXC_I2C_RevA_AsyncCallback (i2c, E_COMM_ERR);
MXC_I2C_RevA_AsyncStop (i2c);
} }
if ( (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) { /* Done writing, still reading */
if ((req->tx_len == written) && (req->rx_len - read) &&
(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)) {
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE;
/* First done interrupt after completing writes to the TX FIFO */
if (read == 0) {
i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit.
}
/* Set the number of bytes to read */
if ((req->rx_len - read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { if ((req->rx_len - read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) {
i2c->rxctrl1 = 0; i2c->rxctrl1 = 0;
} } else {
else {
i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read
} }
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; /* Enable RX Threshold interrupt for when the FIFO is full */
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE; if (read < req->rx_len) {
i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. i2c->inten0 |= (MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE);
} } else {
}
if ( (req->tx_len == written) && (read == 0)) {
i2c->inten0 &= ~MXC_F_I2C_REVA_INTEN0_TX_THD;
i2c->inten0 |= MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE;
if ( (req->rx_len) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) {
i2c->rxctrl1 = 0;
}
else {
i2c->rxctrl1 = (req->rx_len); // 0 for 256, otherwise number of bytes to read
}
MXC_I2C_Start ((mxc_i2c_regs_t*) i2c); // Start or Restart as needed
i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit.
}
if ( (req->tx_len == written) && (req->rx_len == read)) {
i2c->inten0 &= ~(MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE); i2c->inten0 &= ~(MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE);
}
}
/* Done reading and writing */
if ((req->tx_len == written) && (req->rx_len == read)) {
/* Disable and clear interrupts */
i2c->inten0 = 0;
i2c->inten1 = 0;
i2c->intfl0 = i2c->intfl0;
i2c->intfl1 = i2c->intfl1;
/* Send a restart or stop at the end of the transaction */
if (req->restart) { if (req->restart) {
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART;
} } else {
else {
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP;
} }
/* Call the callback */
if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { if (i2c->intfl0 & MXC_I2C_REVA_ERROR) {
MXC_I2C_RevA_AsyncCallback(i2c, E_COMM_ERR); MXC_I2C_RevA_AsyncCallback(i2c, E_COMM_ERR);
} } else {
else {
MXC_I2C_RevA_AsyncCallback(i2c, E_NO_ERROR); MXC_I2C_RevA_AsyncCallback(i2c, E_NO_ERROR);
} }
/* Clear the async state */
MXC_I2C_RevA_AsyncStop(i2c); MXC_I2C_RevA_AsyncStop(i2c);
}
} else {
AsyncWritten[i2cNum] = written; AsyncWritten[i2cNum] = written;
AsyncRead[i2cNum] = read; AsyncRead[i2cNum] = read;
} }
}
unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal) unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
mxc_i2c_reva_slave_handler_t callback,
unsigned int interruptEnables, int *retVal)
{ {
uint32_t tFlags = i2c->intfl0; uint32_t tFlags = i2c->intfl0;
*retVal = E_NO_ERROR; *retVal = E_NO_ERROR;
@ -1235,13 +1294,20 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_r
// I2C_EVT_TRANS_COMP // I2C_EVT_TRANS_COMP
// I2C_EVT_UNDERFLOW // I2C_EVT_UNDERFLOW
// I2C_EVT_OVERFLOW // I2C_EVT_OVERFLOW
if (!(interruptEnables & (MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH| MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) { if (!(interruptEnables &
(MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH |
MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) {
// The STOPERR/STARTERR interrupt that's enabled here could fire before we are addressed // The STOPERR/STARTERR interrupt that's enabled here could fire before we are addressed
// (fires anytime a stop/start is detected out of sequence). // (fires anytime a stop/start is detected out of sequence).
if (tFlags & MXC_I2C_REVA_ERROR) { if (tFlags & MXC_I2C_REVA_ERROR) {
*retVal = E_COMM_ERR; *retVal = E_COMM_ERR;
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal);
MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts }
MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK,
MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts
MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c);
MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c);
interruptEnables = 0; interruptEnables = 0;
@ -1250,30 +1316,47 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_r
if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV)) { if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV)) {
if (tFlags & MXC_F_I2C_REVA_INTFL0_RX_THD) { if (tFlags & MXC_F_I2C_REVA_INTFL0_RX_THD) {
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_RX_THRESH, NULL); callback(i2c, MXC_I2C_REVA_EVT_RX_THRESH, NULL);
}
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD;
} }
if (i2c->intfl1 & MXC_F_I2C_REVA_INTFL1_RX_OV) { if (i2c->intfl1 & MXC_F_I2C_REVA_INTFL1_RX_OV) {
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_OVERFLOW, NULL); callback(i2c, MXC_I2C_REVA_EVT_OVERFLOW, NULL);
}
i2c->intfl1 = MXC_F_I2C_REVA_INTFL1_RX_OV; i2c->intfl1 = MXC_F_I2C_REVA_INTFL1_RX_OV;
} }
} }
if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT)) { if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN |
MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT)) {
if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_THD) { if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_THD) {
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_TX_THRESH, NULL); callback(i2c, MXC_I2C_REVA_EVT_TX_THRESH, NULL);
}
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD;
} }
if (i2c->intfl1 & MXC_F_I2C_REVA_INTFL1_TX_UN) { if (i2c->intfl1 & MXC_F_I2C_REVA_INTFL1_TX_UN) {
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_UNDERFLOW, NULL); callback(i2c, MXC_I2C_REVA_EVT_UNDERFLOW, NULL);
}
i2c->intfl1 = MXC_F_I2C_REVA_INTFL1_TX_UN; i2c->intfl1 = MXC_F_I2C_REVA_INTFL1_TX_UN;
} }
if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT) { if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT) {
*retVal = E_NO_ERROR; *retVal = E_NO_ERROR;
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal);
}
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT;
interruptEnables = 0; interruptEnables = 0;
AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL;
@ -1282,7 +1365,11 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_r
if (tFlags & MXC_F_I2C_REVA_INTFL0_STOP) { if (tFlags & MXC_F_I2C_REVA_INTFL0_STOP) {
*retVal = E_NO_ERROR; *retVal = E_NO_ERROR;
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal);
}
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_STOP; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_STOP;
interruptEnables = 0; interruptEnables = 0;
AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL;
@ -1290,36 +1377,56 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_r
} }
if (tFlags & MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH) { if (tFlags & MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH) {
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL);
}
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | MXC_I2C_REVA_ERROR; interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV |
MXC_I2C_REVA_ERROR;
} }
if (tFlags & MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH) { if (tFlags & MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH) {
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL);
}
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN |
MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR;
} }
if (tFlags & MXC_F_I2C_REVA_INTFL0_ADDR_MATCH) { if (tFlags & MXC_F_I2C_REVA_INTFL0_ADDR_MATCH) {
if (readFlag & MXC_F_I2C_REVA_CTRL_READ) { if (readFlag & MXC_F_I2C_REVA_CTRL_READ) {
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL);
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR;
} }
else {
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN |
MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR;
} else {
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL);
}
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | MXC_I2C_REVA_ERROR; interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV |
MXC_I2C_REVA_ERROR;
} }
} else if (tFlags & MXC_I2C_REVA_ERROR) { } else if (tFlags & MXC_I2C_REVA_ERROR) {
*retVal = E_COMM_ERR; *retVal = E_COMM_ERR;
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal);
MXC_I2C_RevA_ClearFlags(i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // clear all i2c interrupts }
MXC_I2C_RevA_ClearFlags(i2c, MXC_I2C_REVA_INTFL0_MASK,
MXC_I2C_REVA_INTFL1_MASK); // clear all i2c interrupts
MXC_I2C_RevA_ClearTXFIFO(i2c); MXC_I2C_RevA_ClearTXFIFO(i2c);
MXC_I2C_RevA_ClearRXFIFO(i2c); MXC_I2C_RevA_ClearRXFIFO(i2c);
interruptEnables = 0; interruptEnables = 0;
@ -1340,8 +1447,7 @@ void MXC_I2C_RevA_AsyncHandler (mxc_i2c_reva_regs_t* i2c, uint32_t interruptChec
if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE) { if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE) {
MXC_I2C_RevA_MasterAsyncHandler(i2cNum); MXC_I2C_RevA_MasterAsyncHandler(i2cNum);
} } else {
else {
mxc_i2c_reva_slave_handler_t callback = (mxc_i2c_reva_slave_handler_t)AsyncRequests[i2cNum]; mxc_i2c_reva_slave_handler_t callback = (mxc_i2c_reva_slave_handler_t)AsyncRequests[i2cNum];
i2c->inten0 = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, i2c->inten0, &slaveRetVal); i2c->inten0 = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, i2c->inten0, &slaveRetVal);
} }

41
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h
View File

@ -31,8 +31,8 @@
* *
*************************************************************************** */ *************************************************************************** */
#ifndef _I2C_REVA_H_ #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_
#define _I2C_REVA_H_ #define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_
#include <stdio.h> #include <stdio.h>
#include <stddef.h> #include <stddef.h>
@ -46,7 +46,6 @@
#include "i2c_reva_regs.h" #include "i2c_reva_regs.h"
#include "dma.h" #include "dma.h"
/* **** Definitions **** */ /* **** Definitions **** */
#define MXC_I2C_REVA_MAX_ADDR_WIDTH 0x7F #define MXC_I2C_REVA_MAX_ADDR_WIDTH 0x7F
#define MXC_I2C_REVA_STD_MODE 100000 #define MXC_I2C_REVA_STD_MODE 100000
@ -59,8 +58,10 @@
#define MXC_I2C_REVA_MAX_FIFO_TRANSACTION 256 #define MXC_I2C_REVA_MAX_FIFO_TRANSACTION 256
#define MXC_I2C_REVA_ERROR (MXC_F_I2C_REVA_INTFL0_ARB_ERR | MXC_F_I2C_REVA_INTFL0_TO_ERR | MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR | \ #define MXC_I2C_REVA_ERROR \
MXC_F_I2C_REVA_INTFL0_DATA_ERR | MXC_F_I2C_REVA_INTFL0_DNR_ERR | MXC_F_I2C_REVA_INTFL0_START_ERR | \ (MXC_F_I2C_REVA_INTFL0_ARB_ERR | MXC_F_I2C_REVA_INTFL0_TO_ERR | \
MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR | MXC_F_I2C_REVA_INTFL0_DATA_ERR | \
MXC_F_I2C_REVA_INTFL0_DNR_ERR | MXC_F_I2C_REVA_INTFL0_START_ERR | \
MXC_F_I2C_REVA_INTFL0_STOP_ERR) MXC_F_I2C_REVA_INTFL0_STOP_ERR)
typedef struct _i2c_reva_req_t mxc_i2c_reva_req_t; typedef struct _i2c_reva_req_t mxc_i2c_reva_req_t;
@ -113,14 +114,21 @@ int MXC_I2C_RevA_Start (mxc_i2c_reva_regs_t* i2c);
int MXC_I2C_RevA_Stop(mxc_i2c_reva_regs_t *i2c); int MXC_I2C_RevA_Stop(mxc_i2c_reva_regs_t *i2c);
int MXC_I2C_RevA_WriteByte(mxc_i2c_reva_regs_t *i2c, unsigned char byte); int MXC_I2C_RevA_WriteByte(mxc_i2c_reva_regs_t *i2c, unsigned char byte);
int MXC_I2C_RevA_ReadByte(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, int ack); int MXC_I2C_RevA_ReadByte(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, int ack);
int MXC_I2C_RevA_ReadByteInteractive (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, mxc_i2c_reva_getAck_t getAck); int MXC_I2C_RevA_ReadByteInteractive(mxc_i2c_reva_regs_t *i2c, unsigned char *byte,
mxc_i2c_reva_getAck_t getAck);
int MXC_I2C_RevA_Write(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len); int MXC_I2C_RevA_Write(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len);
int MXC_I2C_RevA_Read(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack); int MXC_I2C_RevA_Read(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack);
int MXC_I2C_RevA_ReadRXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len); int MXC_I2C_RevA_ReadRXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes,
int MXC_I2C_RevA_ReadRXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma); unsigned int len);
int MXC_I2C_RevA_ReadRXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len,
mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config,
mxc_dma_regs_t *dma);
int MXC_I2C_RevA_GetRXFIFOAvailable(mxc_i2c_reva_regs_t *i2c); int MXC_I2C_RevA_GetRXFIFOAvailable(mxc_i2c_reva_regs_t *i2c);
int MXC_I2C_RevA_WriteTXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len); int MXC_I2C_RevA_WriteTXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes,
int MXC_I2C_RevA_WriteTXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma); unsigned int len);
int MXC_I2C_RevA_WriteTXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len,
mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config,
mxc_dma_regs_t *dma);
int MXC_I2C_RevA_GetTXFIFOAvailable(mxc_i2c_reva_regs_t *i2c); int MXC_I2C_RevA_GetTXFIFOAvailable(mxc_i2c_reva_regs_t *i2c);
void MXC_I2C_RevA_ClearRXFIFO(mxc_i2c_reva_regs_t *i2c); void MXC_I2C_RevA_ClearRXFIFO(mxc_i2c_reva_regs_t *i2c);
void MXC_I2C_RevA_ClearTXFIFO(mxc_i2c_reva_regs_t *i2c); void MXC_I2C_RevA_ClearTXFIFO(mxc_i2c_reva_regs_t *i2c);
@ -142,8 +150,11 @@ int MXC_I2C_RevA_Recover (mxc_i2c_reva_regs_t* i2c, unsigned int retries);
int MXC_I2C_RevA_MasterTransaction(mxc_i2c_reva_req_t *req); int MXC_I2C_RevA_MasterTransaction(mxc_i2c_reva_req_t *req);
int MXC_I2C_RevA_MasterTransactionAsync(mxc_i2c_reva_req_t *req); int MXC_I2C_RevA_MasterTransactionAsync(mxc_i2c_reva_req_t *req);
int MXC_I2C_RevA_MasterTransactionDMA(mxc_i2c_reva_req_t *req, mxc_dma_regs_t *dma); int MXC_I2C_RevA_MasterTransactionDMA(mxc_i2c_reva_req_t *req, mxc_dma_regs_t *dma);
int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck); int MXC_I2C_RevA_SlaveTransaction(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback,
int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck); uint32_t interruptCheck);
int MXC_I2C_RevA_SlaveTransactionAsync(mxc_i2c_reva_regs_t *i2c,
mxc_i2c_reva_slave_handler_t callback,
uint32_t interruptCheck);
int MXC_I2C_RevA_SetRXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes); int MXC_I2C_RevA_SetRXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes);
unsigned int MXC_I2C_RevA_GetRXThreshold(mxc_i2c_reva_regs_t *i2c); unsigned int MXC_I2C_RevA_GetRXThreshold(mxc_i2c_reva_regs_t *i2c);
int MXC_I2C_RevA_SetTXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes); int MXC_I2C_RevA_SetTXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes);
@ -152,8 +163,10 @@ void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal);
void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c); void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c);
void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c); void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c);
void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum); void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum);
unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal); unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
mxc_i2c_reva_slave_handler_t callback,
unsigned int interruptEnables, int *retVal);
void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck); void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck);
void MXC_I2C_RevA_DMACallback(int ch, int error); void MXC_I2C_RevA_DMACallback(int ch, int error);
#endif /* _I2C_REVA_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_

7
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h
View File

@ -37,8 +37,8 @@
* *
*************************************************************************** */ *************************************************************************** */
#ifndef _I2C_REVA_REGS_H_ #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_
#define _I2C_REVA_REGS_H_ #define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -577,4 +577,5 @@ typedef struct {
} }
#endif #endif
#endif /* _I2C_REGS_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_