Merge pull request #12176 from OpenNuvoton/nuvoton_usbd

Nuvoton: Support usbd
pull/12208/head
Martin Kojtal 2020-01-07 16:38:39 +01:00 committed by GitHub
commit fab9e3b6c7
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9 changed files with 2515 additions and 14 deletions

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@ -33,8 +33,8 @@
#include "HeapBlockDevice.h" #include "HeapBlockDevice.h"
#include "FATFileSystem.h" #include "FATFileSystem.h"
// TARGET_NANO100 SRAM 16KB can't afford mass-storage-disk test, so skip usb_msd_test.
#if !defined(DEVICE_USBDEVICE) || !DEVICE_USBDEVICE #if !defined(DEVICE_USBDEVICE) || !DEVICE_USBDEVICE || TARGET_NANO100
#error [NOT_SUPPORTED] USB Device not supported for this target #error [NOT_SUPPORTED] USB Device not supported for this target
#else #else

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@ -464,8 +464,8 @@ void USBCDC::_receive_isr_start()
{ {
if ((_rx_size == 0) && !_rx_in_progress) { if ((_rx_size == 0) && !_rx_in_progress) {
// Refill the buffer // Refill the buffer
read_start(_bulk_out, _rx_buffer, sizeof(_rx_buffer));
_rx_in_progress = true; _rx_in_progress = true;
read_start(_bulk_out, _rx_buffer, sizeof(_rx_buffer));
} }
} }

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@ -64,6 +64,7 @@ extern "C"
#define CLK_CLKSEL0_SDH0SEL_HCLK (0x02UL<<CLK_CLKSEL0_SDH0SEL_Pos) /*!< Setting SDH0 clock source as HCLK */ #define CLK_CLKSEL0_SDH0SEL_HCLK (0x02UL<<CLK_CLKSEL0_SDH0SEL_Pos) /*!< Setting SDH0 clock source as HCLK */
#define CLK_CLKSEL0_SDH0SEL_HIRC (0x03UL<<CLK_CLKSEL0_SDH0SEL_Pos) /*!< Setting SDH0 clock source as HIRC */ #define CLK_CLKSEL0_SDH0SEL_HIRC (0x03UL<<CLK_CLKSEL0_SDH0SEL_Pos) /*!< Setting SDH0 clock source as HIRC */
#define CLK_CLKSEL0_USBSEL_HIRC48 (0x00UL<<CLK_CLKSEL0_USBSEL_Pos) /*!< Setting USB clock source as HIRC48 */
#define CLK_CLKSEL0_USBSEL_PLL (0x01UL<<CLK_CLKSEL0_USBSEL_Pos) /*!< Setting USB clock source as PLL */ #define CLK_CLKSEL0_USBSEL_PLL (0x01UL<<CLK_CLKSEL0_USBSEL_Pos) /*!< Setting USB clock source as PLL */

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@ -9,7 +9,10 @@
******************************************************************************/ ******************************************************************************/
#ifndef __USBD_H__ #ifndef __USBD_H__
#define __USBD_H__ #define __USBD_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver /** @addtogroup NANO100_Device_Driver NANO100 Device Driver
@{ @{
@ -501,6 +504,9 @@ void USBD_LockEpStall(uint32_t u32EpBitmap);
/*@}*/ /* end of group NANO100_Device_Driver */ /*@}*/ /* end of group NANO100_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__USBD_H__ #endif //__USBD_H__

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@ -64,7 +64,7 @@ void mbed_sdk_init(void)
* T2. <1 ms with HIRC-clocked PLL as HCLK clock source * T2. <1 ms with HIRC-clocked PLL as HCLK clock source
* T1 will fail Greentea test which requires max 10 ms wake-up time. * T1 will fail Greentea test which requires max 10 ms wake-up time.
* *
* If we just call CLK_SetCoreClock(FREQ_42MHZ) to configure HCLK to 42 MHz, * If we just call CLK_SetCoreClock(FREQ_48MHZ) to configure HCLK to 48 MHz,
* it will go T1 with HXT already enabled in front. So we manually configure * it will go T1 with HXT already enabled in front. So we manually configure
* it to choose HXT/HIRC-clocked PLL. * it to choose HXT/HIRC-clocked PLL.
*/ */
@ -76,10 +76,10 @@ void mbed_sdk_init(void)
#endif #endif
#if (NU_CLOCK_PLL == NU_HXT_PLL) #if (NU_CLOCK_PLL == NU_HXT_PLL)
CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HXT, FREQ_42MHZ*2); CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HXT, FREQ_48MHZ*2);
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(2)); CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(2));
#elif (NU_CLOCK_PLL == NU_HIRC_PLL) #elif (NU_CLOCK_PLL == NU_HIRC_PLL)
CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HIRC, FREQ_42MHZ*2); CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HIRC, FREQ_48MHZ*2);
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(2)); CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(2));
#endif #endif

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@ -0,0 +1,41 @@
/* mbed Microcontroller Library
* Copyright (c) 2019-2020 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined(TARGET_M451)
#define NUMBER_OF_LOGICAL_ENDPOINTS (8)
#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS)
#elif defined (TARGET_M480)
#if (MBED_CONF_TARGET_USB_DEVICE_HSUSBD == 0)
#define NUMBER_OF_LOGICAL_ENDPOINTS (12)
#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS)
#else
#define NUMBER_OF_LOGICAL_ENDPOINTS (12)
#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS)
#endif
#elif defined (TARGET_M2351) || defined(TARGET_M261)
#define NUMBER_OF_LOGICAL_ENDPOINTS (12)
#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS)
#elif defined (TARGET_NANO100)
#define NUMBER_OF_LOGICAL_ENDPOINTS (8)
#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS)
#elif defined (TARGET_NUC472)
#define NUMBER_OF_LOGICAL_ENDPOINTS (12)
#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS)
#endif
#define ALLOW_ALL_EXCEPT_CRTL (USB_EP_ATTR_ALLOW_BULK | USB_EP_ATTR_ALLOW_INT | USB_EP_ATTR_ALLOW_ISO)
#define ALLOW_NO_ENDPOINTS 0

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@ -0,0 +1,71 @@
/* mbed Microcontroller Library
* Copyright (c) 2019-2020 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef USBPHYHW_H
#define USBPHYHW_H
#include "mbed.h"
#include "USBPhy.h"
class USBPhyHw : public USBPhy {
public:
USBPhyHw();
virtual ~USBPhyHw();
virtual void init(USBPhyEvents *events);
virtual void deinit();
virtual bool powered();
virtual void connect();
virtual void disconnect();
virtual void configure();
virtual void unconfigure();
virtual void sof_enable();
virtual void sof_disable();
virtual void set_address(uint8_t address);
virtual void remote_wakeup();
virtual const usb_ep_table_t *endpoint_table();
virtual uint32_t ep0_set_max_packet(uint32_t max_packet);
virtual void ep0_setup_read_result(uint8_t *buffer, uint32_t size);
virtual void ep0_read(uint8_t *data, uint32_t size);
virtual uint32_t ep0_read_result();
virtual void ep0_write(uint8_t *buffer, uint32_t size);
virtual void ep0_stall();
virtual bool endpoint_add(usb_ep_t endpoint, uint32_t max_packet, usb_ep_type_t type);
virtual void endpoint_remove(usb_ep_t endpoint);
virtual void endpoint_stall(usb_ep_t endpoint);
virtual void endpoint_unstall(usb_ep_t endpoint);
virtual bool endpoint_read(usb_ep_t endpoint, uint8_t *data, uint32_t size);
virtual uint32_t endpoint_read_result(usb_ep_t endpoint);
virtual bool endpoint_write(usb_ep_t endpoint, uint8_t *data, uint32_t size);
virtual void endpoint_abort(usb_ep_t endpoint);
virtual void process();
USBPhyEvents *events;
private:
uint8_t *read_buffers[16];
uint16_t read_sizes[16];
bool endpoint_read_core(usb_ep_t endpoint, uint32_t max_packet);
bool endpoint_read_result_core(usb_ep_t endpoint, uint8_t *data, uint32_t size, uint32_t *bytesRead);
};
#endif

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@ -7895,7 +7895,8 @@
"FLASH", "FLASH",
"EMAC", "EMAC",
"MPU", "MPU",
"WATCHDOG" "WATCHDOG",
"USBDEVICE"
], ],
"release_versions": ["5"], "release_versions": ["5"],
"device_name": "NUC472HI8AE", "device_name": "NUC472HI8AE",
@ -8027,7 +8028,8 @@
"FLASH", "FLASH",
"MPU", "MPU",
"WATCHDOG", "WATCHDOG",
"RESET_REASON" "RESET_REASON",
"USBDEVICE"
], ],
"components_add": ["FLASHIAP"], "components_add": ["FLASHIAP"],
"release_versions": ["2", "5"], "release_versions": ["2", "5"],
@ -8097,7 +8099,8 @@
"SPISLAVE", "SPISLAVE",
"SPI_ASYNCH", "SPI_ASYNCH",
"WATCHDOG", "WATCHDOG",
"RESET_REASON" "RESET_REASON",
"USBDEVICE"
], ],
"release_versions": ["5"], "release_versions": ["5"],
"device_name": "NANO130KE3BN", "device_name": "NANO130KE3BN",
@ -8514,7 +8517,7 @@
}, },
"usb-device-hsusbd": { "usb-device-hsusbd": {
"help": "Select high-speed USB device or not", "help": "Select high-speed USB device or not",
"value": 1 "value": 0
} }
}, },
"inherits": ["Target"], "inherits": ["Target"],
@ -8546,7 +8549,8 @@
"EMAC", "EMAC",
"MPU", "MPU",
"WATCHDOG", "WATCHDOG",
"RESET_REASON" "RESET_REASON",
"USBDEVICE"
], ],
"release_versions": ["5"], "release_versions": ["5"],
"bootloader_supported": true, "bootloader_supported": true,
@ -8796,7 +8800,8 @@
"SPI_ASYNCH", "SPI_ASYNCH",
"TRNG", "TRNG",
"FLASH", "FLASH",
"MPU" "MPU",
"USBDEVICE"
], ],
"detect_code": ["1305"], "detect_code": ["1305"],
"release_versions": ["5"], "release_versions": ["5"],
@ -9774,7 +9779,8 @@
"SPI_ASYNCH", "SPI_ASYNCH",
"TRNG", "TRNG",
"FLASH", "FLASH",
"MPU" "MPU",
"USBDEVICE"
], ],
"components_add": ["FLASHIAP"], "components_add": ["FLASHIAP"],
"detect_code": ["1310"], "detect_code": ["1310"],