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Make ARM test pass on mbed-os5 tests

pull/4650/head
adustm 2017-08-04 17:10:06 +02:00 committed by Pierre-Marie Ancele
parent 02df64b7d6
commit fa54e1ecba
2 changed files with 851 additions and 932 deletions
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targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l496xx.S
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@ -1,466 +1,434 @@
;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32l496xx.s ;* File Name : startup_stm32l496xx.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V1.7.0 ;* Version : V1.7.0
;* Date : 17-February-2017 ;* Date : 17-February-2017
;* Description : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain. ;* Description : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP
;* - Set the initial PC == Reset_Handler ;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address ;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually ;* - Branches to __main in the C library (which eventually
;* calls main()). ;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode, ;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main. ;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>> ;* <<< Use Configuration Wizard in Context Menu >>>
;******************************************************************************* ;*******************************************************************************
;* ;*
;* Redistribution and use in source and binary forms, with or without modification, ;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met: ;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice, ;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer. ;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice, ;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation ;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution. ;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software ;* may be used to endorse or promote products derived from this software
;* without specific prior written permission. ;* without specific prior written permission.
;* ;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;* ;*
;******************************************************************************* ;*******************************************************************************
;
; Amount of memory (in bytes) allocated for Stack AREA STACK, NOINIT, READWRITE, ALIGN=3
; Tailor this value to your application needs EXPORT __initial_sp
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> __initial_sp EQU 0x20050000 ; Top of RAM
; </h>
; <h> Heap Configuration
Stack_Size EQU 0x400 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size Heap_Size EQU 0x17800 ; 94KB (96KB, -2*1KB for main thread and scheduler)
__initial_sp
AREA HEAP, NOINIT, READWRITE, ALIGN=3
EXPORT __heap_base
; <h> Heap Configuration EXPORT __heap_limit
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h> __heap_base
Heap_Mem SPACE Heap_Size
Heap_Size EQU 0x200 __heap_limit
AREA HEAP, NOINIT, READWRITE, ALIGN=3 PRESERVE8
__heap_base THUMB
Heap_Mem SPACE Heap_Size
__heap_limit
; Vector Table Mapped to Address 0 at Reset
PRESERVE8 AREA RESET, DATA, READONLY
THUMB EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY __Vectors DCD __initial_sp ; Top of Stack
EXPORT __Vectors DCD Reset_Handler ; Reset Handler
EXPORT __Vectors_End DCD NMI_Handler ; NMI Handler
EXPORT __Vectors_Size DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
__Vectors DCD __initial_sp ; Top of Stack DCD BusFault_Handler ; Bus Fault Handler
DCD Reset_Handler ; Reset Handler DCD UsageFault_Handler ; Usage Fault Handler
DCD NMI_Handler ; NMI Handler DCD 0 ; Reserved
DCD HardFault_Handler ; Hard Fault Handler DCD 0 ; Reserved
DCD MemManage_Handler ; MPU Fault Handler DCD 0 ; Reserved
DCD BusFault_Handler ; Bus Fault Handler DCD 0 ; Reserved
DCD UsageFault_Handler ; Usage Fault Handler DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved DCD 0 ; Reserved
DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler
DCD 0 ; Reserved DCD SysTick_Handler ; SysTick Handler
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler ; External Interrupts
DCD 0 ; Reserved DCD WWDG_IRQHandler ; Window WatchDog
DCD PendSV_Handler ; PendSV Handler DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD SysTick_Handler ; SysTick Handler DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
; External Interrupts DCD FLASH_IRQHandler ; FLASH
DCD WWDG_IRQHandler ; Window WatchDog DCD RCC_IRQHandler ; RCC
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection DCD EXTI0_IRQHandler ; EXTI Line0
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line DCD EXTI1_IRQHandler ; EXTI Line1
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line DCD EXTI2_IRQHandler ; EXTI Line2
DCD FLASH_IRQHandler ; FLASH DCD EXTI3_IRQHandler ; EXTI Line3
DCD RCC_IRQHandler ; RCC DCD EXTI4_IRQHandler ; EXTI Line4
DCD EXTI0_IRQHandler ; EXTI Line0 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD EXTI1_IRQHandler ; EXTI Line1 DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD EXTI2_IRQHandler ; EXTI Line2 DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD EXTI3_IRQHandler ; EXTI Line3 DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD EXTI4_IRQHandler ; EXTI Line4 DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 DCD ADC1_2_IRQHandler ; ADC1, ADC2
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD ADC1_2_IRQHandler ; ADC1, ADC2 DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD CAN1_TX_IRQHandler ; CAN1 TX DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD CAN1_RX0_IRQHandler ; CAN1 RX0 DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD CAN1_RX1_IRQHandler ; CAN1 RX1 DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD CAN1_SCE_IRQHandler ; CAN1 SCE DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM2_IRQHandler ; TIM2
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 DCD TIM3_IRQHandler ; TIM3
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 DCD TIM4_IRQHandler ; TIM4
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD TIM2_IRQHandler ; TIM2 DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD TIM3_IRQHandler ; TIM3 DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD TIM4_IRQHandler ; TIM4 DCD SPI1_IRQHandler ; SPI1
DCD I2C1_EV_IRQHandler ; I2C1 Event DCD SPI2_IRQHandler ; SPI2
DCD I2C1_ER_IRQHandler ; I2C1 Error DCD USART1_IRQHandler ; USART1
DCD I2C2_EV_IRQHandler ; I2C2 Event DCD USART2_IRQHandler ; USART2
DCD I2C2_ER_IRQHandler ; I2C2 Error DCD USART3_IRQHandler ; USART3
DCD SPI1_IRQHandler ; SPI1 DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD SPI2_IRQHandler ; SPI2 DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USART1_IRQHandler ; USART1 DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
DCD USART2_IRQHandler ; USART2 DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
DCD USART3_IRQHandler ; USART3 DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD EXTI15_10_IRQHandler ; External Line[15:10] DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt DCD FMC_IRQHandler ; FMC
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt DCD TIM5_IRQHandler ; TIM5
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt DCD SPI3_IRQHandler ; SPI3
DCD ADC3_IRQHandler ; ADC3 global Interrupt DCD UART4_IRQHandler ; UART4
DCD FMC_IRQHandler ; FMC DCD UART5_IRQHandler ; UART5
DCD SDMMC1_IRQHandler ; SDMMC1 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM5_IRQHandler ; TIM5 DCD TIM7_IRQHandler ; TIM7
DCD SPI3_IRQHandler ; SPI3 DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD UART4_IRQHandler ; UART4 DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD UART5_IRQHandler ; UART5 DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD TIM7_IRQHandler ; TIM7 DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 DCD COMP_IRQHandler ; COMP Interrupt
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD COMP_IRQHandler ; COMP Interrupt DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 interrupt DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
DCD OTG_FS_IRQHandler ; USB OTG FS DCD I2C3_EV_IRQHandler ; I2C3 event
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 DCD I2C3_ER_IRQHandler ; I2C3 error
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD LPUART1_IRQHandler ; LP UART1 interrupt DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
DCD QUADSPI_IRQHandler ; Quad SPI global interrupt DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD I2C3_EV_IRQHandler ; I2C3 event DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
DCD I2C3_ER_IRQHandler ; I2C3 error DCD LCD_IRQHandler ; LCD global interrupt
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt DCD 0 ; Reserved
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt DCD RNG_IRQHandler ; RNG global interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt DCD FPU_IRQHandler ; FPU
DCD TSC_IRQHandler ; Touch Sense Controller global interrupt DCD CRS_IRQHandler ; CRS error
DCD LCD_IRQHandler ; LCD global interrupt DCD I2C4_EV_IRQHandler ; I2C4 event
DCD 0 ; Reserved DCD I2C4_ER_IRQHandler ; I2C4 error
DCD RNG_IRQHandler ; RNG global interrupt DCD DCMI_IRQHandler ; DCMI global interrupt
DCD FPU_IRQHandler ; FPU DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CRS_IRQHandler ; CRS error DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD I2C4_EV_IRQHandler ; I2C4 event DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD I2C4_ER_IRQHandler ; I2C4 error DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD DCMI_IRQHandler ; DCMI global interrupt DCD DMA2D_IRQHandler ; DMA2D global interrupt
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0 __Vectors_End
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE __Vectors_Size EQU __Vectors_End - __Vectors
DCD DMA2D_IRQHandler ; DMA2D global interrupt
AREA |.text|, CODE, READONLY
__Vectors_End
; Reset handler
__Vectors_Size EQU __Vectors_End - __Vectors Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
AREA |.text|, CODE, READONLY IMPORT SystemInit
IMPORT __main
; Reset handler
Reset_Handler PROC LDR R0, =SystemInit
EXPORT Reset_Handler [WEAK] BLX R0
IMPORT SystemInit LDR R0, =__main
IMPORT __main BX R0
ENDP
LDR R0, =SystemInit
BLX R0 ; Dummy Exception Handlers (infinite loops which can be modified)
LDR R0, =__main
BX R0 NMI_Handler PROC
ENDP EXPORT NMI_Handler [WEAK]
B .
; Dummy Exception Handlers (infinite loops which can be modified) ENDP
HardFault_Handler\
NMI_Handler PROC PROC
EXPORT NMI_Handler [WEAK] EXPORT HardFault_Handler [WEAK]
B . B .
ENDP ENDP
HardFault_Handler\ MemManage_Handler\
PROC PROC
EXPORT HardFault_Handler [WEAK] EXPORT MemManage_Handler [WEAK]
B . B .
ENDP ENDP
MemManage_Handler\ BusFault_Handler\
PROC PROC
EXPORT MemManage_Handler [WEAK] EXPORT BusFault_Handler [WEAK]
B . B .
ENDP ENDP
BusFault_Handler\ UsageFault_Handler\
PROC PROC
EXPORT BusFault_Handler [WEAK] EXPORT UsageFault_Handler [WEAK]
B . B .
ENDP ENDP
UsageFault_Handler\ SVC_Handler PROC
PROC EXPORT SVC_Handler [WEAK]
EXPORT UsageFault_Handler [WEAK] B .
B . ENDP
ENDP DebugMon_Handler\
SVC_Handler PROC PROC
EXPORT SVC_Handler [WEAK] EXPORT DebugMon_Handler [WEAK]
B . B .
ENDP ENDP
DebugMon_Handler\ PendSV_Handler PROC
PROC EXPORT PendSV_Handler [WEAK]
EXPORT DebugMon_Handler [WEAK] B .
B . ENDP
ENDP SysTick_Handler PROC
PendSV_Handler PROC EXPORT SysTick_Handler [WEAK]
EXPORT PendSV_Handler [WEAK] B .
B . ENDP
ENDP
SysTick_Handler PROC Default_Handler PROC
EXPORT SysTick_Handler [WEAK]
B . EXPORT WWDG_IRQHandler [WEAK]
ENDP EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
Default_Handler PROC EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT WWDG_IRQHandler [WEAK] EXPORT RCC_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK] EXPORT EXTI0_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK] EXPORT EXTI1_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK] EXPORT EXTI2_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK] EXPORT EXTI3_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK] EXPORT EXTI4_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK] EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK] EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK] EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK] EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK] EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK] EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK] EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK] EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK] EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK] EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK] EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK] EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK] EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK] EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK] EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] EXPORT TIM4_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK] EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK] EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK] EXPORT SPI1_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK] EXPORT SPI2_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK] EXPORT USART1_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK] EXPORT USART2_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK] EXPORT USART3_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK] EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK] EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK] EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK] EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK] EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK] EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK] EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DFSDM1_FLT3_IRQHandler [WEAK] EXPORT ADC3_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK] EXPORT FMC_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK] EXPORT SDMMC1_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK] EXPORT TIM5_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK] EXPORT UART5_IRQHandler [WEAK]
EXPORT SDMMC1_IRQHandler [WEAK] EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK] EXPORT TIM7_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK] EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK] EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK] EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK] EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK] EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK] EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK] EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK] EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK] EXPORT COMP_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK] EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT DFSDM1_FLT0_IRQHandler [WEAK] EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT DFSDM1_FLT1_IRQHandler [WEAK] EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DFSDM1_FLT2_IRQHandler [WEAK] EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK] EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK] EXPORT LPUART1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK] EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK] EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK] EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK] EXPORT SAI1_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK] EXPORT SAI2_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK] EXPORT SWPMI1_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK] EXPORT TSC_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK] EXPORT LCD_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK] EXPORT RNG_IRQHandler [WEAK]
EXPORT SAI2_IRQHandler [WEAK] EXPORT FPU_IRQHandler [WEAK]
EXPORT SWPMI1_IRQHandler [WEAK] EXPORT CRS_IRQHandler [WEAK]
EXPORT TSC_IRQHandler [WEAK] EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK] EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK] EXPORT DCMI_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK] EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK] EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK] EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK] EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK] EXPORT DMA2D_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK] WWDG_IRQHandler
EXPORT CAN2_RX1_IRQHandler [WEAK] PVD_PVM_IRQHandler
EXPORT CAN2_SCE_IRQHandler [WEAK] TAMP_STAMP_IRQHandler
EXPORT DMA2D_IRQHandler [WEAK] RTC_WKUP_IRQHandler
FLASH_IRQHandler
WWDG_IRQHandler RCC_IRQHandler
PVD_PVM_IRQHandler EXTI0_IRQHandler
TAMP_STAMP_IRQHandler EXTI1_IRQHandler
RTC_WKUP_IRQHandler EXTI2_IRQHandler
FLASH_IRQHandler EXTI3_IRQHandler
RCC_IRQHandler EXTI4_IRQHandler
EXTI0_IRQHandler DMA1_Channel1_IRQHandler
EXTI1_IRQHandler DMA1_Channel2_IRQHandler
EXTI2_IRQHandler DMA1_Channel3_IRQHandler
EXTI3_IRQHandler DMA1_Channel4_IRQHandler
EXTI4_IRQHandler DMA1_Channel5_IRQHandler
DMA1_Channel1_IRQHandler DMA1_Channel6_IRQHandler
DMA1_Channel2_IRQHandler DMA1_Channel7_IRQHandler
DMA1_Channel3_IRQHandler ADC1_2_IRQHandler
DMA1_Channel4_IRQHandler CAN1_TX_IRQHandler
DMA1_Channel5_IRQHandler CAN1_RX0_IRQHandler
DMA1_Channel6_IRQHandler CAN1_RX1_IRQHandler
DMA1_Channel7_IRQHandler CAN1_SCE_IRQHandler
ADC1_2_IRQHandler EXTI9_5_IRQHandler
CAN1_TX_IRQHandler TIM1_BRK_TIM15_IRQHandler
CAN1_RX0_IRQHandler TIM1_UP_TIM16_IRQHandler
CAN1_RX1_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
CAN1_SCE_IRQHandler TIM1_CC_IRQHandler
EXTI9_5_IRQHandler TIM2_IRQHandler
TIM1_BRK_TIM15_IRQHandler TIM3_IRQHandler
TIM1_UP_TIM16_IRQHandler TIM4_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler I2C1_EV_IRQHandler
TIM1_CC_IRQHandler I2C1_ER_IRQHandler
TIM2_IRQHandler I2C2_EV_IRQHandler
TIM3_IRQHandler I2C2_ER_IRQHandler
TIM4_IRQHandler SPI1_IRQHandler
I2C1_EV_IRQHandler SPI2_IRQHandler
I2C1_ER_IRQHandler USART1_IRQHandler
I2C2_EV_IRQHandler USART2_IRQHandler
I2C2_ER_IRQHandler USART3_IRQHandler
SPI1_IRQHandler EXTI15_10_IRQHandler
SPI2_IRQHandler RTC_Alarm_IRQHandler
USART1_IRQHandler DFSDM1_FLT3_IRQHandler
USART2_IRQHandler TIM8_BRK_IRQHandler
USART3_IRQHandler TIM8_UP_IRQHandler
EXTI15_10_IRQHandler TIM8_TRG_COM_IRQHandler
RTC_Alarm_IRQHandler TIM8_CC_IRQHandler
DFSDM1_FLT3_IRQHandler ADC3_IRQHandler
TIM8_BRK_IRQHandler FMC_IRQHandler
TIM8_UP_IRQHandler SDMMC1_IRQHandler
TIM8_TRG_COM_IRQHandler TIM5_IRQHandler
TIM8_CC_IRQHandler SPI3_IRQHandler
ADC3_IRQHandler UART4_IRQHandler
FMC_IRQHandler UART5_IRQHandler
SDMMC1_IRQHandler TIM6_DAC_IRQHandler
TIM5_IRQHandler TIM7_IRQHandler
SPI3_IRQHandler DMA2_Channel1_IRQHandler
UART4_IRQHandler DMA2_Channel2_IRQHandler
UART5_IRQHandler DMA2_Channel3_IRQHandler
TIM6_DAC_IRQHandler DMA2_Channel4_IRQHandler
TIM7_IRQHandler DMA2_Channel5_IRQHandler
DMA2_Channel1_IRQHandler DFSDM1_FLT0_IRQHandler
DMA2_Channel2_IRQHandler DFSDM1_FLT1_IRQHandler
DMA2_Channel3_IRQHandler DFSDM1_FLT2_IRQHandler
DMA2_Channel4_IRQHandler COMP_IRQHandler
DMA2_Channel5_IRQHandler LPTIM1_IRQHandler
DFSDM1_FLT0_IRQHandler LPTIM2_IRQHandler
DFSDM1_FLT1_IRQHandler OTG_FS_IRQHandler
DFSDM1_FLT2_IRQHandler DMA2_Channel6_IRQHandler
COMP_IRQHandler DMA2_Channel7_IRQHandler
LPTIM1_IRQHandler LPUART1_IRQHandler
LPTIM2_IRQHandler QUADSPI_IRQHandler
OTG_FS_IRQHandler I2C3_EV_IRQHandler
DMA2_Channel6_IRQHandler I2C3_ER_IRQHandler
DMA2_Channel7_IRQHandler SAI1_IRQHandler
LPUART1_IRQHandler SAI2_IRQHandler
QUADSPI_IRQHandler SWPMI1_IRQHandler
I2C3_EV_IRQHandler TSC_IRQHandler
I2C3_ER_IRQHandler LCD_IRQHandler
SAI1_IRQHandler RNG_IRQHandler
SAI2_IRQHandler FPU_IRQHandler
SWPMI1_IRQHandler CRS_IRQHandler
TSC_IRQHandler I2C4_EV_IRQHandler
LCD_IRQHandler I2C4_ER_IRQHandler
RNG_IRQHandler DCMI_IRQHandler
FPU_IRQHandler CAN2_TX_IRQHandler
CRS_IRQHandler CAN2_RX0_IRQHandler
I2C4_EV_IRQHandler CAN2_RX1_IRQHandler
I2C4_ER_IRQHandler CAN2_SCE_IRQHandler
DCMI_IRQHandler DMA2D_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler B .
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler ENDP
DMA2D_IRQHandler
ALIGN
B . END
ENDP ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

883
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_STD/startup_stm32l496xx.S
View File

@ -1,466 +1,417 @@
;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32l496xx.s ;* File Name : startup_stm32l496xx.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V1.7.0 ;* Version : V1.7.0
;* Date : 17-February-2017 ;* Date : 17-February-2017
;* Description : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain. ;* Description : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP
;* - Set the initial PC == Reset_Handler ;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address ;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually ;* - Branches to __main in the C library (which eventually
;* calls main()). ;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode, ;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main. ;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>> ;* <<< Use Configuration Wizard in Context Menu >>>
;******************************************************************************* ;*******************************************************************************
;* ;*
;* Redistribution and use in source and binary forms, with or without modification, ;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met: ;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice, ;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer. ;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice, ;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation ;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution. ;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software ;* may be used to endorse or promote products derived from this software
;* without specific prior written permission. ;* without specific prior written permission.
;* ;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;* ;*
;******************************************************************************* ;*******************************************************************************
;
; Amount of memory (in bytes) allocated for Stack __initial_sp EQU 0x20050000 ; Top of RAM
; Tailor this value to your application needs
; <h> Stack Configuration PRESERVE8
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> THUMB
; </h>
Stack_Size EQU 0x400 ; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
AREA STACK, NOINIT, READWRITE, ALIGN=3 EXPORT __Vectors
Stack_Mem SPACE Stack_Size EXPORT __Vectors_End
__initial_sp EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
; <h> Heap Configuration DCD Reset_Handler ; Reset Handler
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> DCD NMI_Handler ; NMI Handler
; </h> DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
Heap_Size EQU 0x200 DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
AREA HEAP, NOINIT, READWRITE, ALIGN=3 DCD 0 ; Reserved
__heap_base DCD 0 ; Reserved
Heap_Mem SPACE Heap_Size DCD 0 ; Reserved
__heap_limit DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
PRESERVE8 DCD DebugMon_Handler ; Debug Monitor Handler
THUMB DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY ; External Interrupts
EXPORT __Vectors DCD WWDG_IRQHandler ; Window WatchDog
EXPORT __Vectors_End DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
EXPORT __Vectors_Size DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
__Vectors DCD __initial_sp ; Top of Stack DCD FLASH_IRQHandler ; FLASH
DCD Reset_Handler ; Reset Handler DCD RCC_IRQHandler ; RCC
DCD NMI_Handler ; NMI Handler DCD EXTI0_IRQHandler ; EXTI Line0
DCD HardFault_Handler ; Hard Fault Handler DCD EXTI1_IRQHandler ; EXTI Line1
DCD MemManage_Handler ; MPU Fault Handler DCD EXTI2_IRQHandler ; EXTI Line2
DCD BusFault_Handler ; Bus Fault Handler DCD EXTI3_IRQHandler ; EXTI Line3
DCD UsageFault_Handler ; Usage Fault Handler DCD EXTI4_IRQHandler ; EXTI Line4
DCD 0 ; Reserved DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD 0 ; Reserved DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD 0 ; Reserved DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD 0 ; Reserved DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD SVC_Handler ; SVCall Handler DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DebugMon_Handler ; Debug Monitor Handler DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD 0 ; Reserved DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD PendSV_Handler ; PendSV Handler DCD ADC1_2_IRQHandler ; ADC1, ADC2
DCD SysTick_Handler ; SysTick Handler DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
; External Interrupts DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD WWDG_IRQHandler ; Window WatchDog DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD FLASH_IRQHandler ; FLASH DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD RCC_IRQHandler ; RCC DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD EXTI0_IRQHandler ; EXTI Line0 DCD TIM2_IRQHandler ; TIM2
DCD EXTI1_IRQHandler ; EXTI Line1 DCD TIM3_IRQHandler ; TIM3
DCD EXTI2_IRQHandler ; EXTI Line2 DCD TIM4_IRQHandler ; TIM4
DCD EXTI3_IRQHandler ; EXTI Line3 DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD EXTI4_IRQHandler ; EXTI Line4 DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 DCD SPI1_IRQHandler ; SPI1
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 DCD SPI2_IRQHandler ; SPI2
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 DCD USART1_IRQHandler ; USART1
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 DCD USART2_IRQHandler ; USART2
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 DCD USART3_IRQHandler ; USART3
DCD ADC1_2_IRQHandler ; ADC1, ADC2 DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD CAN1_TX_IRQHandler ; CAN1 TX DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD CAN1_RX0_IRQHandler ; CAN1 RX0 DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
DCD CAN1_RX1_IRQHandler ; CAN1 RX1 DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
DCD CAN1_SCE_IRQHandler ; CAN1 SCE DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 DCD FMC_IRQHandler ; FMC
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM2_IRQHandler ; TIM2 DCD TIM5_IRQHandler ; TIM5
DCD TIM3_IRQHandler ; TIM3 DCD SPI3_IRQHandler ; SPI3
DCD TIM4_IRQHandler ; TIM4 DCD UART4_IRQHandler ; UART4
DCD I2C1_EV_IRQHandler ; I2C1 Event DCD UART5_IRQHandler ; UART5
DCD I2C1_ER_IRQHandler ; I2C1 Error DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD I2C2_EV_IRQHandler ; I2C2 Event DCD TIM7_IRQHandler ; TIM7
DCD I2C2_ER_IRQHandler ; I2C2 Error DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD SPI1_IRQHandler ; SPI1 DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD SPI2_IRQHandler ; SPI2 DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD USART1_IRQHandler ; USART1 DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD USART2_IRQHandler ; USART2 DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD USART3_IRQHandler ; USART3 DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
DCD EXTI15_10_IRQHandler ; External Line[15:10] DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt DCD COMP_IRQHandler ; COMP Interrupt
DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt DCD OTG_FS_IRQHandler ; USB OTG FS
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD ADC3_IRQHandler ; ADC3 global Interrupt DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD FMC_IRQHandler ; FMC DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD SDMMC1_IRQHandler ; SDMMC1 DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
DCD TIM5_IRQHandler ; TIM5 DCD I2C3_EV_IRQHandler ; I2C3 event
DCD SPI3_IRQHandler ; SPI3 DCD I2C3_ER_IRQHandler ; I2C3 error
DCD UART4_IRQHandler ; UART4 DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD UART5_IRQHandler ; UART5 DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TIM7_IRQHandler ; TIM7 DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 DCD LCD_IRQHandler ; LCD global interrupt
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 DCD 0 ; Reserved
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 DCD RNG_IRQHandler ; RNG global interrupt
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 DCD FPU_IRQHandler ; FPU
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 DCD CRS_IRQHandler ; CRS error
DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt DCD I2C4_EV_IRQHandler ; I2C4 event
DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt DCD I2C4_ER_IRQHandler ; I2C4 error
DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt DCD DCMI_IRQHandler ; DCMI global interrupt
DCD COMP_IRQHandler ; COMP Interrupt DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD LPTIM2_IRQHandler ; LP TIM2 interrupt DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD OTG_FS_IRQHandler ; USB OTG FS DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 DCD DMA2D_IRQHandler ; DMA2D global interrupt
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD LPUART1_IRQHandler ; LP UART1 interrupt __Vectors_End
DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
DCD I2C3_EV_IRQHandler ; I2C3 event __Vectors_Size EQU __Vectors_End - __Vectors
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt AREA |.text|, CODE, READONLY
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt ; Reset handler
DCD TSC_IRQHandler ; Touch Sense Controller global interrupt Reset_Handler PROC
DCD LCD_IRQHandler ; LCD global interrupt EXPORT Reset_Handler [WEAK]
DCD 0 ; Reserved IMPORT SystemInit
DCD RNG_IRQHandler ; RNG global interrupt IMPORT __main
DCD FPU_IRQHandler ; FPU
DCD CRS_IRQHandler ; CRS error LDR R0, =SystemInit
DCD I2C4_EV_IRQHandler ; I2C4 event BLX R0
DCD I2C4_ER_IRQHandler ; I2C4 error LDR R0, =__main
DCD DCMI_IRQHandler ; DCMI global interrupt BX R0
DCD CAN2_TX_IRQHandler ; CAN2 TX ENDP
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1 ; Dummy Exception Handlers (infinite loops which can be modified)
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD DMA2D_IRQHandler ; DMA2D global interrupt NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
__Vectors_End B .
ENDP
__Vectors_Size EQU __Vectors_End - __Vectors HardFault_Handler\
PROC
AREA |.text|, CODE, READONLY EXPORT HardFault_Handler [WEAK]
B .
; Reset handler ENDP
Reset_Handler PROC MemManage_Handler\
EXPORT Reset_Handler [WEAK] PROC
IMPORT SystemInit EXPORT MemManage_Handler [WEAK]
IMPORT __main B .
ENDP
LDR R0, =SystemInit BusFault_Handler\
BLX R0 PROC
LDR R0, =__main EXPORT BusFault_Handler [WEAK]
BX R0 B .
ENDP ENDP
UsageFault_Handler\
; Dummy Exception Handlers (infinite loops which can be modified) PROC
EXPORT UsageFault_Handler [WEAK]
NMI_Handler PROC B .
EXPORT NMI_Handler [WEAK] ENDP
B . SVC_Handler PROC
ENDP EXPORT SVC_Handler [WEAK]
HardFault_Handler\ B .
PROC ENDP
EXPORT HardFault_Handler [WEAK] DebugMon_Handler\
B . PROC
ENDP EXPORT DebugMon_Handler [WEAK]
MemManage_Handler\ B .
PROC ENDP
EXPORT MemManage_Handler [WEAK] PendSV_Handler PROC
B . EXPORT PendSV_Handler [WEAK]
ENDP B .
BusFault_Handler\ ENDP
PROC SysTick_Handler PROC
EXPORT BusFault_Handler [WEAK] EXPORT SysTick_Handler [WEAK]
B . B .
ENDP ENDP
UsageFault_Handler\
PROC Default_Handler PROC
EXPORT UsageFault_Handler [WEAK]
B . EXPORT WWDG_IRQHandler [WEAK]
ENDP EXPORT PVD_PVM_IRQHandler [WEAK]
SVC_Handler PROC EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT SVC_Handler [WEAK] EXPORT RTC_WKUP_IRQHandler [WEAK]
B . EXPORT FLASH_IRQHandler [WEAK]
ENDP EXPORT RCC_IRQHandler [WEAK]
DebugMon_Handler\ EXPORT EXTI0_IRQHandler [WEAK]
PROC EXPORT EXTI1_IRQHandler [WEAK]
EXPORT DebugMon_Handler [WEAK] EXPORT EXTI2_IRQHandler [WEAK]
B . EXPORT EXTI3_IRQHandler [WEAK]
ENDP EXPORT EXTI4_IRQHandler [WEAK]
PendSV_Handler PROC EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT PendSV_Handler [WEAK] EXPORT DMA1_Channel2_IRQHandler [WEAK]
B . EXPORT DMA1_Channel3_IRQHandler [WEAK]
ENDP EXPORT DMA1_Channel4_IRQHandler [WEAK]
SysTick_Handler PROC EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT SysTick_Handler [WEAK] EXPORT DMA1_Channel6_IRQHandler [WEAK]
B . EXPORT DMA1_Channel7_IRQHandler [WEAK]
ENDP EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
Default_Handler PROC EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT WWDG_IRQHandler [WEAK] EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK] EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK] EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK] EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK] EXPORT TIM4_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK] EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK] EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK] EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK] EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK] EXPORT SPI1_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK] EXPORT SPI2_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK] EXPORT USART1_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK] EXPORT USART2_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK] EXPORT USART3_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK] EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK] EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK] EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK] EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK] EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK] EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] EXPORT ADC3_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] EXPORT FMC_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT SDMMC1_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK] EXPORT TIM5_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK] EXPORT UART5_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK] EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK] EXPORT TIM7_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK] EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK] EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK] EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK] EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK] EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK] EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK] EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK] EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
EXPORT DFSDM1_FLT3_IRQHandler [WEAK] EXPORT COMP_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK] EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK] EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK] EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK] EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK] EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK] EXPORT LPUART1_IRQHandler [WEAK]
EXPORT SDMMC1_IRQHandler [WEAK] EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK] EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK] EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK] EXPORT SAI1_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK] EXPORT SAI2_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK] EXPORT SWPMI1_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK] EXPORT TSC_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK] EXPORT LCD_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK] EXPORT RNG_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK] EXPORT FPU_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK] EXPORT CRS_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK] EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT DFSDM1_FLT0_IRQHandler [WEAK] EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT DFSDM1_FLT1_IRQHandler [WEAK] EXPORT DCMI_IRQHandler [WEAK]
EXPORT DFSDM1_FLT2_IRQHandler [WEAK] EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK] EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK] EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK] EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK] EXPORT DMA2D_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK] WWDG_IRQHandler
EXPORT LPUART1_IRQHandler [WEAK] PVD_PVM_IRQHandler
EXPORT QUADSPI_IRQHandler [WEAK] TAMP_STAMP_IRQHandler
EXPORT I2C3_EV_IRQHandler [WEAK] RTC_WKUP_IRQHandler
EXPORT I2C3_ER_IRQHandler [WEAK] FLASH_IRQHandler
EXPORT SAI1_IRQHandler [WEAK] RCC_IRQHandler
EXPORT SAI2_IRQHandler [WEAK] EXTI0_IRQHandler
EXPORT SWPMI1_IRQHandler [WEAK] EXTI1_IRQHandler
EXPORT TSC_IRQHandler [WEAK] EXTI2_IRQHandler
EXPORT LCD_IRQHandler [WEAK] EXTI3_IRQHandler
EXPORT RNG_IRQHandler [WEAK] EXTI4_IRQHandler
EXPORT FPU_IRQHandler [WEAK] DMA1_Channel1_IRQHandler
EXPORT CRS_IRQHandler [WEAK] DMA1_Channel2_IRQHandler
EXPORT I2C4_EV_IRQHandler [WEAK] DMA1_Channel3_IRQHandler
EXPORT I2C4_ER_IRQHandler [WEAK] DMA1_Channel4_IRQHandler
EXPORT DCMI_IRQHandler [WEAK] DMA1_Channel5_IRQHandler
EXPORT CAN2_TX_IRQHandler [WEAK] DMA1_Channel6_IRQHandler
EXPORT CAN2_RX0_IRQHandler [WEAK] DMA1_Channel7_IRQHandler
EXPORT CAN2_RX1_IRQHandler [WEAK] ADC1_2_IRQHandler
EXPORT CAN2_SCE_IRQHandler [WEAK] CAN1_TX_IRQHandler
EXPORT DMA2D_IRQHandler [WEAK] CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
WWDG_IRQHandler CAN1_SCE_IRQHandler
PVD_PVM_IRQHandler EXTI9_5_IRQHandler
TAMP_STAMP_IRQHandler TIM1_BRK_TIM15_IRQHandler
RTC_WKUP_IRQHandler TIM1_UP_TIM16_IRQHandler
FLASH_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
RCC_IRQHandler TIM1_CC_IRQHandler
EXTI0_IRQHandler TIM2_IRQHandler
EXTI1_IRQHandler TIM3_IRQHandler
EXTI2_IRQHandler TIM4_IRQHandler
EXTI3_IRQHandler I2C1_EV_IRQHandler
EXTI4_IRQHandler I2C1_ER_IRQHandler
DMA1_Channel1_IRQHandler I2C2_EV_IRQHandler
DMA1_Channel2_IRQHandler I2C2_ER_IRQHandler
DMA1_Channel3_IRQHandler SPI1_IRQHandler
DMA1_Channel4_IRQHandler SPI2_IRQHandler
DMA1_Channel5_IRQHandler USART1_IRQHandler
DMA1_Channel6_IRQHandler USART2_IRQHandler
DMA1_Channel7_IRQHandler USART3_IRQHandler
ADC1_2_IRQHandler EXTI15_10_IRQHandler
CAN1_TX_IRQHandler RTC_Alarm_IRQHandler
CAN1_RX0_IRQHandler DFSDM1_FLT3_IRQHandler
CAN1_RX1_IRQHandler TIM8_BRK_IRQHandler
CAN1_SCE_IRQHandler TIM8_UP_IRQHandler
EXTI9_5_IRQHandler TIM8_TRG_COM_IRQHandler
TIM1_BRK_TIM15_IRQHandler TIM8_CC_IRQHandler
TIM1_UP_TIM16_IRQHandler ADC3_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler FMC_IRQHandler
TIM1_CC_IRQHandler SDMMC1_IRQHandler
TIM2_IRQHandler TIM5_IRQHandler
TIM3_IRQHandler SPI3_IRQHandler
TIM4_IRQHandler UART4_IRQHandler
I2C1_EV_IRQHandler UART5_IRQHandler
I2C1_ER_IRQHandler TIM6_DAC_IRQHandler
I2C2_EV_IRQHandler TIM7_IRQHandler
I2C2_ER_IRQHandler DMA2_Channel1_IRQHandler
SPI1_IRQHandler DMA2_Channel2_IRQHandler
SPI2_IRQHandler DMA2_Channel3_IRQHandler
USART1_IRQHandler DMA2_Channel4_IRQHandler
USART2_IRQHandler DMA2_Channel5_IRQHandler
USART3_IRQHandler DFSDM1_FLT0_IRQHandler
EXTI15_10_IRQHandler DFSDM1_FLT1_IRQHandler
RTC_Alarm_IRQHandler DFSDM1_FLT2_IRQHandler
DFSDM1_FLT3_IRQHandler COMP_IRQHandler
TIM8_BRK_IRQHandler LPTIM1_IRQHandler
TIM8_UP_IRQHandler LPTIM2_IRQHandler
TIM8_TRG_COM_IRQHandler OTG_FS_IRQHandler
TIM8_CC_IRQHandler DMA2_Channel6_IRQHandler
ADC3_IRQHandler DMA2_Channel7_IRQHandler
FMC_IRQHandler LPUART1_IRQHandler
SDMMC1_IRQHandler QUADSPI_IRQHandler
TIM5_IRQHandler I2C3_EV_IRQHandler
SPI3_IRQHandler I2C3_ER_IRQHandler
UART4_IRQHandler SAI1_IRQHandler
UART5_IRQHandler SAI2_IRQHandler
TIM6_DAC_IRQHandler SWPMI1_IRQHandler
TIM7_IRQHandler TSC_IRQHandler
DMA2_Channel1_IRQHandler LCD_IRQHandler
DMA2_Channel2_IRQHandler RNG_IRQHandler
DMA2_Channel3_IRQHandler FPU_IRQHandler
DMA2_Channel4_IRQHandler CRS_IRQHandler
DMA2_Channel5_IRQHandler I2C4_EV_IRQHandler
DFSDM1_FLT0_IRQHandler I2C4_ER_IRQHandler
DFSDM1_FLT1_IRQHandler DCMI_IRQHandler
DFSDM1_FLT2_IRQHandler CAN2_TX_IRQHandler
COMP_IRQHandler CAN2_RX0_IRQHandler
LPTIM1_IRQHandler CAN2_RX1_IRQHandler
LPTIM2_IRQHandler CAN2_SCE_IRQHandler
OTG_FS_IRQHandler DMA2D_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler B .
LPUART1_IRQHandler
QUADSPI_IRQHandler ENDP
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler ALIGN
SAI1_IRQHandler END
SAI2_IRQHandler
SWPMI1_IRQHandler ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
TSC_IRQHandler
LCD_IRQHandler
RNG_IRQHandler
FPU_IRQHandler
CRS_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
DCMI_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
DMA2D_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****