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Update QSPI test to reflect fixes in QSPIFBlockDevice

pull/11894/head
Matthew Macovsky 2019-09-13 15:29:23 -07:00 committed by adbridge
parent 237db778a9
commit fa2ef8be96
2 changed files with 22 additions and 5 deletions
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1
TESTS/mbed_hal/qspi/main.cpp
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@ -84,6 +84,7 @@ static uint32_t gen_flash_address()
{ {
srand(ticker_read(get_us_ticker_data())); srand(ticker_read(get_us_ticker_data()));
uint32_t address = (((uint32_t)rand()) % QSPI_SECTOR_COUNT) * QSPI_SECTOR_SIZE; uint32_t address = (((uint32_t)rand()) % QSPI_SECTOR_COUNT) * QSPI_SECTOR_SIZE;
address &= 0xFFFFFF; // Ensure address is within 24 bits so as to not have to deal with 4-byte addressing
return address; return address;
} }

26
TESTS/mbed_hal/qspi/qspi_test_utils.cpp
View File

@ -58,7 +58,7 @@ void QspiCommand::set_dummy_cycles(int dummy_cycles)
void QspiCommand::build(int instruction, int address, int alt) void QspiCommand::build(int instruction, int address, int alt)
{ {
_cmd.instruction.disabled = (instruction == QSPI_NONE); _cmd.instruction.disabled = (instruction == QSPI_NO_INST);
if (!_cmd.instruction.disabled) { if (!_cmd.instruction.disabled) {
_cmd.instruction.value = instruction; _cmd.instruction.value = instruction;
} }
@ -127,17 +127,33 @@ void flash_init(Qspi &qspi)
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, status, QSPI_STATUS_REG_SIZE); ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, status, QSPI_STATUS_REG_SIZE);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret); TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
qspi.cmd.build(QSPI_CMD_RSTEN); // Only do reset enable if device needs it
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, NULL, 0); if (QSPI_CMD_RSTEN != 0) {
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret); qspi.cmd.build(QSPI_CMD_RSTEN);
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, NULL, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
WAIT_FOR(WRSR_MAX_TIME, qspi); WAIT_FOR(WRSR_MAX_TIME, qspi);
}
qspi.cmd.build(QSPI_CMD_RST); qspi.cmd.build(QSPI_CMD_RST);
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, NULL, 0); ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, NULL, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret); TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
WAIT_FOR(WAIT_MAX_TIME, qspi); WAIT_FOR(WAIT_MAX_TIME, qspi);
// Zero out status register to attempt to clear block protection bits
uint8_t blanks[QSPI_STATUS_REG_SIZE] = {0};
qspi.cmd.build(0x06);
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, NULL, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
qspi.cmd.build(0x01);
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), blanks, 1, NULL, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
WAIT_FOR(WRSR_MAX_TIME, qspi);
} }