mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #13692 from RyoheiHagimoto/gr_i2c_slave
Fix I2C slave bugs on Renesas RZ/A series.pull/13828/head
Martin Kojtal
GitHub
commit
f9e62fe615
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@ -1,5 +1,5 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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* Copyright (c) 2006-2020 ARM Limited
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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@ -50,9 +50,19 @@ volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST;
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/* RIICnSER */
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#define SER_SAR0E (1 << 0)
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#define SER_SAR1E (1 << 1)
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#define SER_SAR2E (1 << 2)
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#define SER_GCE (1 << 3)
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#define SER_DIDE (1 << 5)
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#define SER_HOAE (1 << 7)
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/* RIICnSR1 */
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#define SR1_AAS0 (1 << 0)
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#define SR1_AAS1 (1 << 1)
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#define SR1_AAS2 (1 << 2)
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#define SR1_GCA (1 << 3)
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#define SR1_DID (1 << 5)
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#define SR1_HOA (1 << 7)
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/* RIICnSR2 */
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#define SR2_START (1 << 2)
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@ -64,11 +74,13 @@ volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST;
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#define WAIT_TIMEOUT (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */
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static inline int i2c_status(i2c_t *obj) {
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static inline int i2c_status(i2c_t *obj)
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{
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return REG(SR2.UINT8[0]);
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}
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static void i2c_reg_reset(i2c_t *obj) {
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static void i2c_reg_reset(i2c_t *obj)
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{
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/* full reset */
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REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off
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REG(CR1.UINT8[0]) |= CR1_RST; // CR1.IICRST on
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@ -91,7 +103,8 @@ static void i2c_reg_reset(i2c_t *obj) {
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REG(CR1.UINT32) &= ~CR1_RST; // CR1.IICRST negate reset
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}
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static inline int i2c_wait_RDRF(i2c_t *obj) {
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static inline int i2c_wait_RDRF(i2c_t *obj)
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{
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int timeout = 0;
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/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
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@ -105,7 +118,8 @@ static inline int i2c_wait_RDRF(i2c_t *obj) {
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return 0;
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}
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static int i2c_wait_TDRE(i2c_t *obj) {
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static int i2c_wait_TDRE(i2c_t *obj)
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{
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int timeout = 0;
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/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
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@ -119,7 +133,8 @@ static int i2c_wait_TDRE(i2c_t *obj) {
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return 0;
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}
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static int i2c_wait_TEND(i2c_t *obj) {
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static int i2c_wait_TEND(i2c_t *obj)
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{
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int timeout = 0;
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/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
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@ -134,7 +149,8 @@ static int i2c_wait_TEND(i2c_t *obj) {
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}
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static int i2c_wait_START(i2c_t *obj) {
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static int i2c_wait_START(i2c_t *obj)
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{
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int timeout = 0;
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/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
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@ -148,7 +164,8 @@ static int i2c_wait_START(i2c_t *obj) {
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return 0;
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}
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static int i2c_wait_STOP(i2c_t *obj) {
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static int i2c_wait_STOP(i2c_t *obj)
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{
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int timeout = 0;
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/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
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@ -162,7 +179,8 @@ static int i2c_wait_STOP(i2c_t *obj) {
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return 0;
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}
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static int i2c_set_STOP(i2c_t *obj) {
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static int i2c_set_STOP(i2c_t *obj)
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{
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/* SR2.STOP = 0 */
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REG(SR2.UINT32) &= ~SR2_STOP;
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/* Stop condition */
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@ -171,28 +189,32 @@ static int i2c_set_STOP(i2c_t *obj) {
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return 0;
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}
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static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) {
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static void i2c_set_SR2_NACKF_STOP(i2c_t *obj)
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{
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/* SR2.NACKF = 0 */
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REG(SR2.UINT32) &= ~SR2_NACKF;
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/* SR2.STOP = 0 */
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REG(SR2.UINT32) &= ~SR2_STOP;
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}
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static void i2c_set_MR3_NACK(i2c_t *obj) {
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static void i2c_set_MR3_NACK(i2c_t *obj)
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{
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/* send a NOT ACK */
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REG(MR3.UINT32) |= MR3_ACKWP;
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REG(MR3.UINT32) |= MR3_ACKBT;
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REG(MR3.UINT32) &= ~MR3_ACKWP;
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}
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static void i2c_set_MR3_ACK(i2c_t *obj) {
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static void i2c_set_MR3_ACK(i2c_t *obj)
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{
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/* send a ACK */
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REG(MR3.UINT32) |= MR3_ACKWP;
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REG(MR3.UINT32) &= ~MR3_ACKBT;
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REG(MR3.UINT32) &= ~MR3_ACKWP;
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}
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static inline void i2c_power_enable(i2c_t *obj) {
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static inline void i2c_power_enable(i2c_t *obj)
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{
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volatile uint8_t dummy;
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switch ((int)obj->i2c.i2c) {
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case I2C_0:
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@ -212,7 +234,8 @@ static inline void i2c_power_enable(i2c_t *obj) {
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(void)dummy;
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}
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void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
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void i2c_init(i2c_t *obj, PinName sda, PinName scl)
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{
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/* determine the I2C to use */
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I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
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I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
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@ -231,7 +254,8 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
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obj->i2c.last_stop_flag = 1;
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}
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inline int i2c_start(i2c_t *obj) {
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inline int i2c_start(i2c_t *obj)
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{
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int timeout = 0;
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while ((REG(CR2.UINT32) & CR2_BBSY) != 0) {
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@ -246,7 +270,8 @@ inline int i2c_start(i2c_t *obj) {
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return 0;
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}
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static inline int i2c_restart(i2c_t *obj) {
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static inline int i2c_restart(i2c_t *obj)
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{
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/* SR2.START = 0 */
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REG(SR2.UINT32) &= ~SR2_START;
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/* ReStart condition */
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@ -255,7 +280,8 @@ static inline int i2c_restart(i2c_t *obj) {
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return 0;
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}
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inline int i2c_stop(i2c_t *obj) {
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inline int i2c_stop(i2c_t *obj)
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{
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(void)i2c_set_STOP(obj);
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(void)i2c_wait_STOP(obj);
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i2c_set_SR2_NACKF_STOP(obj);
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@ -263,14 +289,16 @@ inline int i2c_stop(i2c_t *obj) {
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return 0;
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}
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static void i2c_set_err_noslave(i2c_t *obj) {
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static void i2c_set_err_noslave(i2c_t *obj)
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{
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(void)i2c_set_STOP(obj);
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(void)i2c_wait_STOP(obj);
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i2c_set_SR2_NACKF_STOP(obj);
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obj->i2c.last_stop_flag = 1;
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}
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static inline int i2c_do_write(i2c_t *obj, int value) {
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static inline int i2c_do_write(i2c_t *obj, int value)
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{
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int timeout = 0;
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/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
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@ -286,7 +314,8 @@ static inline int i2c_do_write(i2c_t *obj, int value) {
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return 0;
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}
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static inline int i2c_read_address_write(i2c_t *obj, int value) {
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static inline int i2c_read_address_write(i2c_t *obj, int value)
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{
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int status;
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status = i2c_wait_TDRE(obj);
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@ -299,7 +328,8 @@ static inline int i2c_read_address_write(i2c_t *obj, int value) {
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}
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static inline int i2c_do_read(i2c_t *obj, int last) {
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static inline int i2c_do_read(i2c_t *obj, int last)
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{
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if (last == 2) {
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/* this time is befor last byte read */
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/* Set MR3 WAIT bit is 1 */;
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@ -314,7 +344,8 @@ static inline int i2c_do_read(i2c_t *obj, int last) {
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return (REG(DRR.UINT32) & 0xFF);
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}
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void i2c_frequency(i2c_t *obj, int hz) {
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void i2c_frequency(i2c_t *obj, int hz)
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{
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float64_t pclk_val;
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float64_t wait_utime;
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volatile float64_t bps;
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@ -400,7 +431,8 @@ void i2c_frequency(i2c_t *obj, int hz) {
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i2c_reg_reset(obj);
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}
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int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
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int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
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{
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int count = 0;
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int status;
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int value;
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@ -523,7 +555,8 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
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return length;
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}
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int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
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int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
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{
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int cnt;
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int status;
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@ -550,9 +583,9 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
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return I2C_ERROR_NO_SLAVE;
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}
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/* Send Write data */
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for (cnt=0; cnt<length; cnt++) {
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for (cnt = 0; cnt < length; cnt++) {
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status = i2c_do_write(obj, data[cnt]);
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if(status != 0) {
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if (status != 0) {
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i2c_set_err_noslave(obj);
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return cnt;
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} else {
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@ -581,13 +614,15 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
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return length;
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}
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void i2c_reset(i2c_t *obj) {
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void i2c_reset(i2c_t *obj)
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{
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(void)i2c_set_STOP(obj);
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(void)i2c_wait_STOP(obj);
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i2c_set_SR2_NACKF_STOP(obj);
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}
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int i2c_byte_read(i2c_t *obj, int last) {
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int i2c_byte_read(i2c_t *obj, int last)
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{
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int status;
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int data;
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@ -602,7 +637,8 @@ int i2c_byte_read(i2c_t *obj, int last) {
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return data;
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}
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int i2c_byte_write(i2c_t *obj, int data) {
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int i2c_byte_write(i2c_t *obj, int data)
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{
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int ack = 0;
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int status;
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int timeout = 0;
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@ -629,7 +665,8 @@ int i2c_byte_write(i2c_t *obj, int data) {
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return ack;
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}
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void i2c_slave_mode(i2c_t *obj, int enable_slave) {
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void i2c_slave_mode(i2c_t *obj, int enable_slave)
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{
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if (enable_slave != 0) {
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REG(SER.UINT32) |= SER_SAR0E; // only slave addr 0 is enabled
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} else {
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@ -637,47 +674,53 @@ void i2c_slave_mode(i2c_t *obj, int enable_slave) {
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}
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}
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int i2c_slave_receive(i2c_t *obj) {
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int status;
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int i2c_slave_receive(i2c_t *obj)
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{
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int retval;
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status = (REG(SR1.UINT8[0]) & SR1_AAS0);
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status |= (REG(CR2.UINT8[0]) & CR2_TRS) >> 4;
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switch(status) {
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case 0x01:
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/* the master is writing to this slave */
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retval = 3;
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break;
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case 0x02:
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/* the master is writing to all slave */
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retval = 2;
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break;
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case 0x03:
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/* detected general call address */
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if (0 != (REG(SR1.UINT8[0]) & SR1_GCA)) {
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/* the master is writing to all slave */
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retval = 2;
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}
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/* detected slave address */
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else if (0 != (REG(SR1.UINT8[0]) & SR1_AAS0)) {
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if (0 != (REG(CR2.UINT8[0]) & CR2_TRS)) {
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/* the master has requested a read from this slave */
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retval = 1;
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break;
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default :
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/* no data */
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retval = 0;
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break;
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} else {
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/* the master is writing to this slave */
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retval = 3;
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}
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}
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/* no data */
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else {
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retval = 0;
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}
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/* to detect restart-condition */
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if (0 != retval) {
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/* SR2.START = 0 */
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REG(SR2.UINT32) &= ~SR2_START;
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}
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return retval;
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}
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int i2c_slave_read(i2c_t *obj, char *data, int length) {
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int i2c_slave_read(i2c_t *obj, char *data, int length)
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{
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int timeout = 0;
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int count;
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int break_flg = 0;
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if(length <= 0) {
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if (length <= 0) {
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return 0;
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}
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for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) {
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/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
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while (((i2c_status(obj) & SR2_STOP) != 0) || ((i2c_status(obj) & SR2_RDRF) == 0)) {
|
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if ((i2c_status(obj) & SR2_STOP) != 0) {
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while (((i2c_status(obj) & (SR2_STOP | SR2_START)) != 0) || ((i2c_status(obj) & SR2_RDRF) == 0)) {
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/* received stop-condition or restart-condition */
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if ((i2c_status(obj) & (SR2_STOP | SR2_START)) != 0) {
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break_flg = 1;
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break;
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}
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@ -714,17 +757,18 @@ int i2c_slave_read(i2c_t *obj, char *data, int length) {
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return (count - 1);
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}
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int i2c_slave_write(i2c_t *obj, const char *data, int length) {
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int i2c_slave_write(i2c_t *obj, const char *data, int length)
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{
|
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int count = 0;
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int status = 0;
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if(length <= 0) {
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if (length <= 0) {
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return 0;
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}
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while ((count < length) && (status == 0)) {
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status = i2c_do_write(obj, data[count]);
|
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if(status == 0) {
|
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if (status == 0) {
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/* Wait send end */
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status = i2c_wait_TEND(obj);
|
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if ((status != 0) || ((count < (length - 1)) && ((REG(SR2.UINT32) & SR2_NACKF) != 0))) {
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|
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@ -742,7 +786,8 @@ int i2c_slave_write(i2c_t *obj, const char *data, int length) {
|
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return count;
|
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}
|
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|
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void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
|
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void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
|
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{
|
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REG(SAR0.UINT32) = (address & 0xfffffffe);
|
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}
|
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|
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|
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|
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|
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@ -48,9 +48,19 @@ static const volatile struct st_riic *RIIC[] = {
|
|||
|
||||
/* RIICnSER */
|
||||
#define SER_SAR0E (1 << 0)
|
||||
#define SER_SAR1E (1 << 1)
|
||||
#define SER_SAR2E (1 << 2)
|
||||
#define SER_GCE (1 << 3)
|
||||
#define SER_DIDE (1 << 5)
|
||||
#define SER_HOAE (1 << 7)
|
||||
|
||||
/* RIICnSR1 */
|
||||
#define SR1_AAS0 (1 << 0)
|
||||
#define SR1_AAS1 (1 << 1)
|
||||
#define SR1_AAS2 (1 << 2)
|
||||
#define SR1_GCA (1 << 3)
|
||||
#define SR1_DID (1 << 5)
|
||||
#define SR1_HOA (1 << 7)
|
||||
|
||||
/* RIICnSR2 */
|
||||
#define SR2_START (1 << 2)
|
||||
|
|
@ -666,29 +676,32 @@ void i2c_slave_mode(i2c_t *obj, int enable_slave)
|
|||
|
||||
int i2c_slave_receive(i2c_t *obj)
|
||||
{
|
||||
int status;
|
||||
int retval;
|
||||
|
||||
status = (obj->i2c.i2c->ICSR1.BYTE.LL & SR1_AAS0);
|
||||
status |= (obj->i2c.i2c->ICCR2.BYTE.LL & CR2_TRS) >> 4;
|
||||
|
||||
switch (status) {
|
||||
case 0x01:
|
||||
/* the master is writing to this slave */
|
||||
retval = 3;
|
||||
break;
|
||||
case 0x02:
|
||||
/* the master is writing to all slave */
|
||||
retval = 2;
|
||||
break;
|
||||
case 0x03:
|
||||
/* detected general call address */
|
||||
if (0 != (obj->i2c.i2c->ICSR1.BYTE.LL & SR1_GCA)) {
|
||||
/* the master is writing to all slave */
|
||||
retval = 2;
|
||||
}
|
||||
/* detected slave address */
|
||||
else if (0 != (obj->i2c.i2c->ICSR1.BYTE.LL & SR1_AAS0)) {
|
||||
if (0 != (obj->i2c.i2c->ICCR2.BYTE.LL & CR2_TRS)) {
|
||||
/* the master has requested a read from this slave */
|
||||
retval = 1;
|
||||
break;
|
||||
default :
|
||||
/* no data */
|
||||
retval = 0;
|
||||
break;
|
||||
} else {
|
||||
/* the master is writing to this slave */
|
||||
retval = 3;
|
||||
}
|
||||
}
|
||||
/* no data */
|
||||
else {
|
||||
retval = 0;
|
||||
}
|
||||
|
||||
/* to detect restart-condition */
|
||||
if (0 != retval) {
|
||||
/* SR2.START = 0 */
|
||||
obj->i2c.i2c->ICSR2.LONG &= ~SR2_START;
|
||||
}
|
||||
|
||||
return retval;
|
||||
|
|
@ -705,8 +718,9 @@ int i2c_slave_read(i2c_t *obj, char *data, int length)
|
|||
}
|
||||
for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) {
|
||||
/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
|
||||
while (((i2c_status(obj) & SR2_STOP) != 0) || ((i2c_status(obj) & SR2_RDRF) == 0)) {
|
||||
if ((i2c_status(obj) & SR2_STOP) != 0) {
|
||||
while (((i2c_status(obj) & (SR2_STOP | SR2_START)) != 0) || ((i2c_status(obj) & SR2_RDRF) == 0)) {
|
||||
/* received stop-condition or restart-condition */
|
||||
if ((i2c_status(obj) & (SR2_STOP | SR2_START)) != 0) {
|
||||
break_flg = 1;
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue