From f9a5120958a487d497cd7ae2d089a4fce1dceb66 Mon Sep 17 00:00:00 2001
From: toyowata <toyomasa.watarai@gmail.com>
Date: Tue, 8 Aug 2017 11:21:30 +0900
Subject: [PATCH] Fix mask bits for SPI clock rate

---
 targets/TARGET_NXP/TARGET_LPC176X/spi_api.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/targets/TARGET_NXP/TARGET_LPC176X/spi_api.c b/targets/TARGET_NXP/TARGET_LPC176X/spi_api.c
index ba2bde2989..cc30a264e8 100644
--- a/targets/TARGET_NXP/TARGET_LPC176X/spi_api.c
+++ b/targets/TARGET_NXP/TARGET_LPC176X/spi_api.c
@@ -98,7 +98,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
     
     int FRF = 0;                   // FRF (frame format) = SPI
     uint32_t tmp = obj->spi->CR0;
-    tmp &= ~(0xFFFF);
+    tmp &= ~(0x00FF);              // Clear DSS, FRF, CPOL and CPHA [7:0]
     tmp |= DSS << 0
         | FRF << 4
         | SPO << 6
@@ -146,7 +146,7 @@ void spi_frequency(spi_t *obj, int hz) {
             obj->spi->CPSR = prescaler;
             
             // divider
-            obj->spi->CR0 &= ~(0xFFFF << 8);
+            obj->spi->CR0 &= ~(0xFF00);  // Clear SCR: Serial clock rate [15:8]
             obj->spi->CR0 |= (divider - 1) << 8;
             ssp_enable(obj);
             return;