diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
index 5016bbb8a4..01655f83d9 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
@@ -4,10 +4,10 @@
* Description:
* Wrapper function to initialize all generated code.
* This file was automatically generated and should not be modified.
-* Tools Package 2.1.0.1260
-* psoc6pdl 1.6.0.3875
+* Tools Package 2.2.0.1747
+* psoc6pdl 1.6.0.4172
* personalities_2.0 2.0.0.0
-* udd 1.2.0.300
+* udd 1.2.0.370
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
index d1342ebfb9..e7918199cd 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
@@ -4,10 +4,10 @@
* Description:
* Simple wrapper header containing all generated files.
* This file was automatically generated and should not be modified.
-* Tools Package 2.1.0.1260
-* psoc6pdl 1.6.0.3875
+* Tools Package 2.2.0.1747
+* psoc6pdl 1.6.0.4172
* personalities_2.0 2.0.0.0
-* udd 1.2.0.300
+* udd 1.2.0.370
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
index 1636a83269..d6ff9ce659 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
@@ -4,10 +4,10 @@
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
-* Tools Package 2.1.0.1260
-* psoc6pdl 1.6.0.3875
+* Tools Package 2.2.0.1747
+* psoc6pdl 1.6.0.4172
* personalities_2.0 2.0.0.0
-* udd 1.2.0.300
+* udd 1.2.0.370
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
index a689c632ae..fbe87bea6f 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
@@ -4,10 +4,10 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
-* Tools Package 2.1.0.1260
-* psoc6pdl 1.6.0.3875
+* Tools Package 2.2.0.1747
+* psoc6pdl 1.6.0.4172
* personalities_2.0 2.0.0.0
-* udd 1.2.0.300
+* udd 1.2.0.370
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
index c41dd25cac..7e966a2564 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
@@ -4,10 +4,10 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
-* Tools Package 2.1.0.1260
-* psoc6pdl 1.6.0.3875
+* Tools Package 2.2.0.1747
+* psoc6pdl 1.6.0.4172
* personalities_2.0 2.0.0.0
-* udd 1.2.0.300
+* udd 1.2.0.370
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
index 242fcbc028..d547cbb15c 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
@@ -5,10 +5,10 @@
* Contains warnings and errors that occurred while generating code for the
* design.
* This file was automatically generated and should not be modified.
-* Tools Package 2.1.0.1260
-* psoc6pdl 1.6.0.3875
+* Tools Package 2.2.0.1747
+* psoc6pdl 1.6.0.4172
* personalities_2.0 2.0.0.0
-* udd 1.2.0.300
+* udd 1.2.0.370
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
index d11e638cff..bed2bd8555 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
@@ -4,10 +4,10 @@
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
-* Tools Package 2.1.0.1260
-* psoc6pdl 1.6.0.3875
+* Tools Package 2.2.0.1747
+* psoc6pdl 1.6.0.4172
* personalities_2.0 2.0.0.0
-* udd 1.2.0.300
+* udd 1.2.0.370
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
index e44ec27574..98c6b484e0 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
@@ -4,10 +4,10 @@
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
-* Tools Package 2.1.0.1260
-* psoc6pdl 1.6.0.3875
+* Tools Package 2.2.0.1747
+* psoc6pdl 1.6.0.4172
* personalities_2.0 2.0.0.0
-* udd 1.2.0.300
+* udd 1.2.0.370
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
index 9db17d0ab1..ed39d783ba 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
@@ -4,10 +4,10 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
-* Tools Package 2.1.0.1260
-* psoc6pdl 1.6.0.3875
+* Tools Package 2.2.0.1747
+* psoc6pdl 1.6.0.4172
* personalities_2.0 2.0.0.0
-* udd 1.2.0.300
+* udd 1.2.0.370
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
index 3d5ee16c4b..76bf8debba 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
@@ -4,10 +4,10 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
-* Tools Package 2.1.0.1260
-* psoc6pdl 1.6.0.3875
+* Tools Package 2.2.0.1747
+* psoc6pdl 1.6.0.4172
* personalities_2.0 2.0.0.0
-* udd 1.2.0.300
+* udd 1.2.0.370
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
index 5513818699..cd1687d96a 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
@@ -4,10 +4,10 @@
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
-* Tools Package 2.1.0.1260
-* psoc6pdl 1.6.0.3875
+* Tools Package 2.2.0.1747
+* psoc6pdl 1.6.0.4172
* personalities_2.0 2.0.0.0
-* udd 1.2.0.300
+* udd 1.2.0.370
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
index 1f3abd0a83..e97ec70409 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
@@ -4,10 +4,10 @@
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
-* Tools Package 2.1.0.1260
-* psoc6pdl 1.6.0.3875
+* Tools Package 2.2.0.1747
+* psoc6pdl 1.6.0.4172
* personalities_2.0 2.0.0.0
-* udd 1.2.0.300
+* udd 1.2.0.370
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
@@ -38,20 +38,20 @@ void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
-#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
-#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
#if defined(__cplusplus)
}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
index a7d83b82b3..a0e508fc3b 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
@@ -4,10 +4,10 @@
* Description:
* System configuration
* This file was automatically generated and should not be modified.
-* Tools Package 2.1.0.1260
-* psoc6pdl 1.6.0.3875
+* Tools Package 2.2.0.1747
+* psoc6pdl 1.6.0.4172
* personalities_2.0 2.0.0.0
-* udd 1.2.0.300
+* udd 1.2.0.370
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
@@ -709,7 +709,7 @@ void init_cycfg_system(void)
Cy_SysClk_ClkSlowInit();
#endif
- #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == 0U))
+ #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U))
/* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
@@ -773,7 +773,7 @@ void init_cycfg_system(void)
Cy_SysClk_ClkHf0Init();
- #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == 0U))
+ #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U))
#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
/* Apply the ClkPath1 user setting */
Cy_SysClk_ClkPath1Init();
@@ -891,13 +891,10 @@ void init_cycfg_system(void)
Cy_SysClk_ClkBakInit();
#endif
- /* Configure default enabled clocks */
- #ifdef CY_CFG_SYSCLK_ILO_ENABLED
- Cy_SysClk_IloInit();
- #else
- Cy_SysClk_IloDisable();
- Cy_SysClk_IloHibernateOn(false);
- #endif
+ /* Configure default enabled clocks */
+ #ifdef CY_CFG_SYSCLK_ILO_ENABLED
+ Cy_SysClk_IloInit();
+ #endif
#ifndef CY_CFG_SYSCLK_IMO_ENABLED
#error the IMO must be enabled for proper chip operation
@@ -921,6 +918,15 @@ void init_cycfg_system(void)
/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
SystemCoreClockUpdate();
+ #ifndef CY_CFG_SYSCLK_ILO_ENABLED
+ #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
+ /* Wait 4 ILO cycles in case of unfinished CLKLF clock source transition */
+ Cy_SysLib_DelayUs(200U);
+ #endif
+ Cy_SysClk_IloDisable();
+ Cy_SysClk_IloHibernateOn(false);
+ #endif
+
#endif /* ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
index 429b031bb9..65ccfd3376 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
@@ -4,10 +4,10 @@
* Description:
* System configuration
* This file was automatically generated and should not be modified.
-* Tools Package 2.1.0.1260
-* psoc6pdl 1.6.0.3875
+* Tools Package 2.2.0.1747
+* psoc6pdl 1.6.0.4172
* personalities_2.0 2.0.0.0
-* udd 1.2.0.300
+* udd 1.2.0.370
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c
index 7e634e2f31..c58b712a10 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c
@@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
-* \version 2.70.1
+* \version 2.80
*
* The device system-source file.
*
@@ -40,6 +40,10 @@
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+#if defined(CY_DEVICE_SECURE)
+ #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
/*******************************************************************************
* SystemCoreClockUpdate()
@@ -160,7 +164,7 @@ void SystemInit(void)
#ifdef __CM0P_PRESENT
#if (__CM0P_PRESENT == 0)
/* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
- REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
+ REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
CY_STARTUP_IPC7_DP_OFFSET);
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
@@ -233,6 +237,11 @@ void SystemInit(void)
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+#if defined(CY_DEVICE_SECURE)
+ /* Initialize Protected Register Access driver */
+ Cy_PRA_Init();
+#endif /* defined(CY_DEVICE_SECURE) */
}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/system_psoc6.h
index 58550faf74..bd27b72ad6 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/system_psoc6.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/system_psoc6.h
@@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6.h
-* \version 2.70.1
+* \version 2.80
*
* \brief Device system header file.
*
@@ -321,6 +321,16 @@
* | Reason for Change |
*
*
+* | 2.80 |
+* Updated linker scripts for PSoC 64 Secure MCU devices. |
+* Updated FLASH and SRAM memory area definitions in cyb0xxx linker script templates
+* in accordance with the PSoC 64 Secure Boot SDK policies. |
+*
+*
+* | Added \ref Cy_PRA_Init() function call to \ref SystemInit() API for CM0+ core of PSoC 64 Secure MCU. |
+* Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver. |
+*
+*
* | 2.70.1 |
* Updated documentation for the better description of the existing startup implementation. |
* User experience enhancement. |
@@ -538,11 +548,7 @@ extern "C" {
* \addtogroup group_system_config_system_functions
* \{
*/
-#if defined(__ARMCC_VERSION)
- extern void SystemInit(void) __attribute__((constructor));
-#else
- extern void SystemInit(void);
-#endif /* (__ARMCC_VERSION) */
+extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/** \} group_system_config_system_functions */