From f90b6c9cb0c675d0f422b0ca3f3ed3daa335b24e Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 10 Dec 2019 10:00:05 +0800 Subject: [PATCH] NANO130: Support dynamic heap configuration on IAR On IAR, configure heap to 1KiB at a minimum and expandable, dependent on available SRAM. This requires IAR 8.x. --- .../TARGET_NANO100/device/TOOLCHAIN_IAR/NANO130.icf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_IAR/NANO130.icf b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_IAR/NANO130.icf index e87a2a7851..d7468abd8e 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_IAR/NANO130.icf +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_IAR/NANO130.icf @@ -11,7 +11,7 @@ define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000; define symbol __ICFEDIT_region_IRAM_end__ = 0x20004000 - 1; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0xB00; +define symbol __ICFEDIT_size_heap__ = 0x400; /**** End of ICF editor section. ###ICF###*/ @@ -21,7 +21,7 @@ define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFED define block ROMVEC with alignment = 8 { readonly section .intvec }; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; initialize by copy with packing = none { readwrite };