From f75905a89a7649e78c9134f17d29b196b1cecf85 Mon Sep 17 00:00:00 2001 From: bcostm Date: Wed, 3 May 2017 09:50:54 +0200 Subject: [PATCH] DISCO_L475VG_IOT01A: change comment for 8-byte aligned adress for IAR .icf file --- .../TARGET_STM32L475xG/device/TOOLCHAIN_IAR/stm32l475xx.icf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/stm32l475xx.icf b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/stm32l475xx.icf index d1f1eba3ee..10ae3e5766 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/stm32l475xx.icf +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/stm32l475xx.icf @@ -6,8 +6,8 @@ define symbol __region_ROM_end__ = 0x080FFFFF; /* [RAM = 128kb = 96kb + 32kb = 0x20000] */ /* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */ define symbol __NVIC_start__ = 0x10000000; -define symbol __NVIC_end__ = 0x10000187; /* Aligned on 8 bytes (392 = 49 x 8) */ -define symbol __region_SRAM2_start__ = 0x10000188; +define symbol __NVIC_end__ = 0x10000187; +define symbol __region_SRAM2_start__ = 0x10000188; /* This adress is 8-byte aligned */ define symbol __region_SRAM2_end__ = 0x10007FFF; define symbol __region_SRAM1_start__ = 0x20000000; define symbol __region_SRAM1_end__ = 0x20017FFF;