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Check timer active flag after enabling timer counting in us_ticker/lp_ticker

pull/6579/head
ccli8 2018-03-26 09:42:53 +08:00 committed by adbridge
parent 85a1139056
commit f6ac93a1c1
8 changed files with 127 additions and 70 deletions
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23
targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c
View File

@ -63,8 +63,10 @@ void lp_ticker_init(void)
// Enable IP clock // Enable IP clock
CLK_EnableModuleClock(TIMER_MODINIT.clkidx); CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
// Configure clock // Configure clock
uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
@ -72,19 +74,24 @@ void lp_ticker_init(void)
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
// Continuous mode // Continuous mode
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default. // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/; timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
timer_base->CMP = cmp_timer;
// Set vector // Set vector
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
NVIC_EnableIRQ(TIMER_MODINIT.irq_n); NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); TIMER_EnableInt(timer_base);
TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
/* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */ TIMER_EnableWakeup(timer_base);
wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
TIMER_Start(timer_base);
/* Wait for timer to start counting and raise active flag */
while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
} }
timestamp_t lp_ticker_read() timestamp_t lp_ticker_read()
@ -114,6 +121,7 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
* (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
timer_base->CMP = cmp_timer; timer_base->CMP = cmp_timer;
wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
} }
@ -147,6 +155,7 @@ const ticker_info_t* lp_ticker_get_info()
static void tmr1_vec(void) static void tmr1_vec(void)
{ {
TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
// NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler(); // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();

15
targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c
View File

@ -58,23 +58,28 @@ void us_ticker_init(void)
// Enable IP clock // Enable IP clock
CLK_EnableModuleClock(TIMER_MODINIT.clkidx); CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
// Timer for normal counter // Timer for normal counter
uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
uint32_t cmp_timer = TMR_CMP_MAX; uint32_t cmp_timer = TMR_CMP_MAX;
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default. // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/; timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer; timer_base->CMP = cmp_timer;
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
NVIC_EnableIRQ(TIMER_MODINIT.irq_n); NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); TIMER_EnableInt(timer_base);
TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
TIMER_Start(timer_base);
/* Wait for timer to start counting and raise active flag */
while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
} }
uint32_t us_ticker_read() uint32_t us_ticker_read()

23
targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c
View File

@ -63,8 +63,10 @@ void lp_ticker_init(void)
// Enable IP clock // Enable IP clock
CLK_EnableModuleClock(TIMER_MODINIT.clkidx); CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
// Configure clock // Configure clock
uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
@ -72,19 +74,24 @@ void lp_ticker_init(void)
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
// Continuous mode // Continuous mode
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default. // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/; timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
timer_base->CMP = cmp_timer;
// Set vector // Set vector
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
NVIC_EnableIRQ(TIMER_MODINIT.irq_n); NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); TIMER_EnableInt(timer_base);
TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
/* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */ TIMER_EnableWakeup(timer_base);
wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
TIMER_Start(timer_base);
/* Wait for timer to start counting and raise active flag */
while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
} }
timestamp_t lp_ticker_read() timestamp_t lp_ticker_read()
@ -114,6 +121,7 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
* (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
timer_base->CMP = cmp_timer; timer_base->CMP = cmp_timer;
wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
} }
@ -147,6 +155,7 @@ const ticker_info_t* lp_ticker_get_info()
static void tmr1_vec(void) static void tmr1_vec(void)
{ {
TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
// NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler(); // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();

15
targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c
View File

@ -58,23 +58,28 @@ void us_ticker_init(void)
// Enable IP clock // Enable IP clock
CLK_EnableModuleClock(TIMER_MODINIT.clkidx); CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
// Timer for normal counter // Timer for normal counter
uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
uint32_t cmp_timer = TMR_CMP_MAX; uint32_t cmp_timer = TMR_CMP_MAX;
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default. // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/; timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer; timer_base->CMP = cmp_timer;
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
NVIC_EnableIRQ(TIMER_MODINIT.irq_n); NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); TIMER_EnableInt(timer_base);
TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
TIMER_Start(timer_base);
/* Wait for timer to start counting and raise active flag */
while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
} }
uint32_t us_ticker_read() uint32_t us_ticker_read()

26
targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c
View File

@ -65,28 +65,36 @@ void lp_ticker_init(void)
// Enable IP clock // Enable IP clock
CLK_EnableModuleClock(TIMER_MODINIT.clkidx); CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
// Configure clock // Configure clock
uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
uint32_t cmp_timer = TMR_CMP_MAX; uint32_t cmp_timer = TMR_CMP_MAX;
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
// Continuous mode // Continuous mode
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE; timer_base->CTL = TIMER_CONTINUOUS_MODE;
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->PRECNT = prescale_timer;
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMPR = cmp_timer; timer_base->PRECNT = prescale_timer;
timer_base->CMPR = cmp_timer;
// Set vector // Set vector
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
NVIC_EnableIRQ(TIMER_MODINIT.irq_n); NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); TIMER_EnableInt(timer_base);
TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
/* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */ TIMER_EnableWakeup(timer_base);
wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
TIMER_Start(timer_base);
/* Wait for timer to start counting and raise active flag */
while(! (timer_base->CTL & TIMER_CTL_TMR_ACT_Msk));
} }
timestamp_t lp_ticker_read() timestamp_t lp_ticker_read()
@ -116,6 +124,7 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
* (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
timer_base->CMPR = cmp_timer; timer_base->CMPR = cmp_timer;
wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
} }
@ -149,6 +158,7 @@ const ticker_info_t* lp_ticker_get_info()
void TMR1_IRQHandler(void) void TMR1_IRQHandler(void)
{ {
TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
// NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler(); // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();

17
targets/TARGET_NUVOTON/TARGET_NANO100/us_ticker.c
View File

@ -60,23 +60,28 @@ void us_ticker_init(void)
// Enable IP clock // Enable IP clock
CLK_EnableModuleClock(TIMER_MODINIT.clkidx); CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
// Timer for normal counter // Timer for normal counter
uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
uint32_t cmp_timer = TMR_CMP_MAX; uint32_t cmp_timer = TMR_CMP_MAX;
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE; timer_base->CTL = TIMER_CONTINUOUS_MODE;
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->PRECNT = prescale_timer; timer_base->PRECNT = prescale_timer;
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMPR = cmp_timer; timer_base->CMPR = cmp_timer;
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
NVIC_EnableIRQ(TIMER_MODINIT.irq_n); NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); TIMER_EnableInt(timer_base);
TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
TIMER_Start(timer_base);
/* Wait for timer to start counting and raise active flag */
while(! (timer_base->CTL & TIMER_CTL_TMR_ACT_Msk));
} }
uint32_t us_ticker_read() uint32_t us_ticker_read()

23
targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c
View File

@ -63,27 +63,34 @@ void lp_ticker_init(void)
// Enable IP clock // Enable IP clock
CLK_EnableModuleClock(TIMER_MODINIT.clkidx); CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
// Configure clock // Configure clock
uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
uint32_t cmp_timer = TMR_CMP_MAX; uint32_t cmp_timer = TMR_CMP_MAX;
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
// Continuous mode // Continuous mode
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer | TIMER_CTL_CNTDATEN_Msk; timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer | TIMER_CTL_CNTDATEN_Msk;
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
timer_base->CMP = cmp_timer;
// Set vector // Set vector
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
NVIC_EnableIRQ(TIMER_MODINIT.irq_n); NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); TIMER_EnableInt(timer_base);
TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
/* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */ TIMER_EnableWakeup(timer_base);
wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
TIMER_Start(timer_base);
/* Wait for timer to start counting and raise active flag */
while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
} }
timestamp_t lp_ticker_read() timestamp_t lp_ticker_read()
@ -113,6 +120,7 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
* (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
timer_base->CMP = cmp_timer; timer_base->CMP = cmp_timer;
wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
} }
@ -146,6 +154,7 @@ const ticker_info_t* lp_ticker_get_info()
static void tmr1_vec(void) static void tmr1_vec(void)
{ {
TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
// NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler(); // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();

15
targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c
View File

@ -58,22 +58,27 @@ void us_ticker_init(void)
// Enable IP clock // Enable IP clock
CLK_EnableModuleClock(TIMER_MODINIT.clkidx); CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
// Timer for normal counter // Timer for normal counter
uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
uint32_t cmp_timer = TMR_CMP_MAX; uint32_t cmp_timer = TMR_CMP_MAX;
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer | TIMER_CTL_CNTDATEN_Msk; timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer | TIMER_CTL_CNTDATEN_Msk;
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer; timer_base->CMP = cmp_timer;
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
NVIC_EnableIRQ(TIMER_MODINIT.irq_n); NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); TIMER_EnableInt(timer_base);
TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
TIMER_Start(timer_base);
/* Wait for timer to start counting and raise active flag */
while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
} }
uint32_t us_ticker_read() uint32_t us_ticker_read()