diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/sleep.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/sleep.c
index 0ce8fa0236..82016bfdf1 100644
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/sleep.c
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/sleep.c
@@ -38,10 +38,10 @@ static volatile uint8_t wk_CPGSTBREQ1;
 static volatile uint8_t wk_CPGSTBREQ2;
 
 typedef struct {
-    volatile uint8_t * p_wk_stbcr;
-    volatile uint8_t * p_stbcr;
-    volatile uint8_t * p_stbreq;
-    volatile uint8_t * p_stback;
+    volatile uint8_t *p_wk_stbcr;
+    volatile uint8_t *p_stbcr;
+    volatile uint8_t *p_stbreq;
+    volatile uint8_t *p_stback;
     uint8_t mstp;
     uint8_t stbrq;
 } module_stanby_t;
@@ -63,10 +63,11 @@ static const module_stanby_t module_stanby[] = {
     {0, 0, 0, 0, 0}  /* None */
 };
 
-static void module_standby_in(void) {
+static void module_standby_in(void)
+{
     volatile uint32_t cnt;
     volatile uint8_t dummy_8;
-    const module_stanby_t * p_module = &module_stanby[0];
+    const module_stanby_t *p_module = &module_stanby[0];
 
     while (p_module->p_wk_stbcr != 0) {
         if ((*p_module->p_wk_stbcr & p_module->mstp) == 0) {
@@ -85,10 +86,11 @@ static void module_standby_in(void) {
     (void)dummy_8;
 }
 
-static void module_standby_out(void) {
+static void module_standby_out(void)
+{
     volatile uint32_t cnt;
     volatile uint8_t dummy_8;
-    const module_stanby_t * p_module = &module_stanby[0];
+    const module_stanby_t *p_module = &module_stanby[0];
 
     while (p_module->p_wk_stbcr != 0) {
         if ((*p_module->p_wk_stbcr & p_module->mstp) == 0) {
@@ -105,14 +107,28 @@ static void module_standby_out(void) {
     (void)dummy_8;
 }
 
-void hal_sleep(void) {
+void hal_sleep(void)
+{
     // Transition to Sleep Mode
     __WFI();
 }
 
-void hal_deepsleep(void) {
+void hal_deepsleep(void)
+{
     volatile uint8_t dummy_8;
 
+    /* Waits for the serial transmission to complete */
+    const struct st_scif *SCIF[SCIF_COUNT] = SCIF_ADDRESS_LIST;
+
+    for (int uart = 0; uart < SCIF_COUNT; uart++) {
+        if ((wk_CPGSTBCR4 & (1 << (7 - uart))) == 0) {     // Is the power turned on?
+            if ((SCIF[uart]->SCSCR & 0x00A0) == 0x00A0) {  // Is transmission enabled? (TE = 1, TIE = 1)
+                /* Waits for the transmission to complete (TEND = 1) */
+                while ((SCIF[uart]->SCFSR & 0x0040) == 0); // Waits for the transmission to complete (TEND = 1)
+            }
+        }
+    }
+
     core_util_critical_section_enter();
     /* For powerdown the peripheral module, save current standby control register values(just in case) */
     wk_CPGSTBCR3  = CPGSTBCR3;
@@ -129,17 +145,6 @@ void hal_deepsleep(void) {
     wk_CPGSTBCR13 = CPGSTBCR13;
 #endif
 
-    /* Waits for the serial transmission to complete */
-    const struct st_scif *SCIF[SCIF_COUNT] = SCIF_ADDRESS_LIST;
-
-    for (int uart = 0; uart < SCIF_COUNT; uart++) {
-        if ((wk_CPGSTBCR4 & (1 << (7 - uart))) == 0) {     // Is the power turned on?
-            if ((SCIF[uart]->SCSCR & 0x00A0) == 0x00A0) {  // Is transmission enabled? (TE = 1, TIE = 1)
-                while ((SCIF[uart]->SCFSR & 0x0040) == 0); // Waits for the transmission to complete (TEND = 1)
-            }
-        }
-    }
-
     /* MTU2 (for low power ticker) */
     CPGSTBCR3  |= ~(CPG_STBCR3_BIT_MSTP33);
     dummy_8    = CPGSTBCR3;
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/os_tick_ostm.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/os_tick_ostm.c
index c04bb4b1de..1448635ea3 100644
--- a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/os_tick_ostm.c
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/os_tick_ostm.c
@@ -22,9 +22,6 @@
  * limitations under the License.
  */
 
-#ifdef MBED_CONF_RTOS_PRESENT
-
-#include "os_tick.h"
 #include "irq_ctrl.h"
 
 #include <MBRZA2M.h>
@@ -41,6 +38,9 @@
 #define OSTM                        (OSTM0)
 #define OSTM_IRQn                   ((IRQn_ID_t)OSTMI0_IRQn)
 
+#ifdef MBED_CONF_RTOS_PRESENT
+
+#include "os_tick.h"
 
 static uint32_t OSTM_Clock;         // Timer tick frequency
 static uint8_t  OSTM_PendIRQ;       // Timer interrupt pending flag
@@ -188,11 +188,11 @@ uint32_t OS_Tick_GetOverflow(void)
 {
     return (IRQ_GetPending(OSTM_IRQn));
 }
+#endif
 
 // Get Cortex-A9 OS Timer interrupt number
 IRQn_ID_t mbed_get_a9_tick_irqn()
 {
     return OSTM_IRQn;
 }
-#endif
 
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/sleep.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/sleep.c
index 787a5a1478..7b17627eea 100644
--- a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/sleep.c
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/sleep.c
@@ -59,6 +59,16 @@ static const module_stanby_t module_stanby[] = {
     {0, 0, 0, 0, 0}  /* None */
 };
 
+/* Channel array defines of SCIF */
+/*(Sample) value = SCIF[ channel ]->SCSMR; */
+#define SCIFA_COUNT  (5)
+#define SCIFA_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCIFA0, &SCIFA1, &SCIFA2, &SCIFA3, &SCIFA4 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of SCIF */
+
 static void module_standby_in(void)
 {
     volatile uint32_t cnt;
@@ -113,6 +123,20 @@ void hal_deepsleep(void)
 {
     volatile uint8_t dummy_8;
 
+    /* Waits for the serial transmission to complete */
+    volatile const struct st_scifa *SCIFA[SCIFA_COUNT] = SCIFA_ADDRESS_LIST;
+
+    for (int uart = 0; uart < SCIFA_COUNT; uart++) {
+        /* Is the power turned on? */
+        if ((wk_CPGSTBCR4 & (1 << (7 - uart))) == 0) {
+            /* Is transmission enabled? (TE = 1, TIE = 1) */
+            if ((SCIFA[uart]->SCR.WORD & 0x00A0) == 0x00A0) {
+                /* Waits for the transmission to complete (TEND = 1) */
+                while ((SCIFA[uart]->FSR.WORD & 0x0040) == 0);
+            }
+        }
+    }
+
     core_util_critical_section_enter();
     /* For powerdown the peripheral module, save current standby control register values(just in case) */
     wk_CPGSTBCR3  = CPG.STBCR3.BYTE;