Adding STM32_F429 + S2_LP (WiSUN) as a new MTB target

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_MTB_STM_S2LP/PeripheralNames.h

@@ -1,4 +1,5 @@
 /* mbed Microcontroller Library
+* SPDX-License-Identifier: BSD-3-Clause
  *******************************************************************************
  * Copyright (c) 2016, STMicroelectronics
  * All rights reserved.
@@ -57,6 +58,7 @@ typedef enum {
     UART_8 = (int)UART8_BASE
 } UARTName;
 
+#define SPI_COUNT 6
 typedef enum {
     SPI_1 = (int)SPI1_BASE,
     SPI_2 = (int)SPI2_BASE,

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_MTB_STM_S2LP/PeripheralPins.c

@@ -1,4 +1,5 @@
 /* mbed Microcontroller Library
+* SPDX-License-Identifier: BSD-3-Clause
  *******************************************************************************
  * Copyright (c) 2018, STMicroelectronics
  * All rights reserved.

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_MTB_STM_S2LP/PinNames.h

@@ -1,4 +1,5 @@
 /* mbed Microcontroller Library
+* SPDX-License-Identifier: BSD-3-Clause
  *******************************************************************************
  * Copyright (c) 2018, STMicroelectronics
  * All rights reserved.

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_MTB_STM_S2LP/system_clock.c

@@ -30,7 +30,7 @@
 **/
 
 #include "stm32f4xx.h"
-
+#include "nvic_addr.h"
 #include "mbed_error.h"
 
 // clock source is selected with CLOCK_SOURCE in json config
@@ -56,6 +56,10 @@ uint8_t SetSysClock_PLL_HSI(void);
   */
 void SystemInit(void)
 {
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
     /* Reset the RCC clock configuration to the default reset state ------------*/
     /* Set HSION bit */
     RCC->CR |= (uint32_t)0x00000001;
@@ -79,6 +83,13 @@ void SystemInit(void)
     SystemInit_ExtMemCtl();
 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
 }
 
 /**

targets/targets.json

@@ -2834,8 +2834,8 @@
         "core": "Cortex-M4F",
         "config": {
             "clock_source": {
-                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (8MHz) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI|USE_PLL_HSE_XTAL",
+                "value": "USE_PLL_HSE_XTAL",
                 "macro_name": "CLOCK_SOURCE"
             },
             "clock_source_usb": {
@@ -2846,10 +2846,10 @@
         },
         "extra_labels_add": ["STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xx", "STM32F429xI"],
         "macros_add": ["USB_STM_HAL"],
-        "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "TRNG", "FLASH", "MPU"],
         "detect_code": ["0467"],
         "release_versions": ["5"],
-        "device_name": "STM32F429VI",
+        "device_name": "STM32F429ZI",
         "bootloader_supported": true
     },
     "NUCLEO_F439ZI": {