diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/system_MK64F12.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/system_MK64F12.c index 21d23f3ade..849c58c74f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/system_MK64F12.c +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/system_MK64F12.c @@ -1,21 +1,48 @@ /* ** ################################################################### ** Processor: MK64FN1M0VMD12 -** Compilers: ARM Compiler +** Compilers: Keil ARM C/C++ Compiler ** Freescale C/C++ for Embedded ARM ** GNU C Compiler ** GNU C Compiler - CodeSourcery Sourcery G++ ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K64P144M120SF5RM, Rev.1, July 2013 -** Version: rev. 2.1, 2013-10-29 +** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 +** Version: rev. 2.5, 2014-02-10 +** Build: b140611 ** ** Abstract: ** Provides a system configuration function and a global variable that ** contains the system frequency. It configures the device and initializes ** the oscillator (PLL) that is part of the microcontroller device. ** -** Copyright: 2013 Freescale, Inc. All Rights Reserved. +** Copyright (c) 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.freescale.com ** mail: support@freescale.com @@ -30,16 +57,29 @@ ** System initialization updated. ** MCG - registers updated. ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-29) +** - rev. 2.1 (2013-10-30) ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-09) +** DMA - EARS register removed. +** AIPS0, AIPS1 - MPRA register updated. +** - rev. 2.3 (2014-01-24) +** Update according to reference manual rev. 2 +** ENET, MCG, MCM, SIM, USB - registers updated +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK64F12.h +** Update of SystemInit() and SystemCoreClockUpdate() functions. +** - rev. 2.5 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK64F12.h +** Update of SystemInit() and SystemCoreClockUpdate() functions. +** Module access macro module_BASES replaced by module_BASE_PTRS. ** ** ################################################################### */ /*! * @file MK64F12 - * @version 2.1 - * @date 2013-10-29 + * @version 2.5 + * @date 2014-02-10 * @brief Device specific configuration file for MK64F12 (implementation file) * * Provides a system configuration function and a global variable that contains @@ -48,72 +88,8 @@ */ #include -#include "MK64F12.h" +#include "cmsis.h" -#define DISABLE_WDOG 1 - -#ifndef CLOCK_SETUP -#define CLOCK_SETUP 4 -#endif -/* Predefined clock setups - 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode - Default part configuration. - Reference clock source for MCG module is the slow internal clock source 32.768kHz - Core clock = 20.97MHz, BusClock = 20.97MHz - 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode - Maximum achievable clock frequency configuration. - Reference clock source for MCG module is an external clock source 50MHz - Core clock = 120MHz, BusClock = 60MHz - 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power Internal (BLPI) mode - Core clock/Bus clock derived directly from an fast internal clock 4MHz with no multiplication - The clock settings is ready for Very Low Power Run mode. - Core clock = 4MHz, BusClock = 4MHz - 3 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode - Core clock/Bus clock derived directly from the RTC oscillator clock source 32.768kHz - The clock settings is ready for Very Low Power Run mode. - Core clock = 32.768kHz, BusClock = 32.768kHz - 4 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode - USB clock setup - USB clock divider is set for USB to receive 48MHz input clock. - Reference clock source for MCG module is an external clock source 50MHz - USB clock divider is set for USB to receive 48MHz input clock. - Core clock = 120MHz, BusClock = 60MHz -*/ - -/*---------------------------------------------------------------------------- - Define clock source values - *----------------------------------------------------------------------------*/ -#if (CLOCK_SETUP == 0) - #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */ - #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ - #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ - #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ - #define DEFAULT_SYSTEM_CLOCK 20485760u /* Default System clock value */ -#elif (CLOCK_SETUP == 1) - #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */ - #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ - #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ - #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ - #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */ -#elif (CLOCK_SETUP == 2) - #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */ - #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ - #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ - #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ - #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */ -#elif (CLOCK_SETUP == 3) - #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */ - #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ - #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ - #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ - #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */ -#elif (CLOCK_SETUP == 4) - #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */ - #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ - #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ - #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ - #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */ -#endif /* (CLOCK_SETUP == 4) */ /* ---------------------------------------------------------------------------- @@ -131,7 +107,6 @@ void SystemInit (void) { SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ #if (DISABLE_WDOG) - /* Disable the WDOG module */ /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */ WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */ /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */ @@ -144,197 +119,165 @@ void SystemInit (void) { WDOG_STCTRLH_CLKSRC_MASK | 0x0100U; #endif /* (DISABLE_WDOG) */ - - /* - * Release hold with ACKISO: Only has an effect if recovering from VLLSx. - * if ACKISO is set you must clear ackiso before initializing the PLL - * if osc enabled in low power modes - enable it first before ack - */ - if (PMC->REGSC & PMC_REGSC_ACKISO_MASK) + if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U) { - PMC->REGSC |= PMC_REGSC_ACKISO_MASK; + if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U) + { + PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/ + } + } else { +#ifdef SYSTEM_RTC_CR_VALUE + SIM_SCGC6 |= SIM_SCGC6_RTC_MASK; + if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */ + RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE); + RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK; + RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK; + } +#endif } -#if (CLOCK_SETUP == 0) - /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */ - SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | - SIM_CLKDIV1_OUTDIV2(0x00) | - SIM_CLKDIV1_OUTDIV3(0x01) | - SIM_CLKDIV1_OUTDIV4(0x01); /* Update system prescalers */ - /* SIM->SOPT2: PLLFLLSEL=0 */ - SIM->SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */ - /* SIM->SOPT1: OSC32KSEL=3 */ - SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */ - /* Switch to FEI Mode */ - /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = MCG_C1_CLKS(0x00) | - MCG_C1_FRDIV(0x00) | - MCG_C1_IREFS_MASK | - MCG_C1_IRCLKEN_MASK; - /* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */ - MCG->C2 = MCG_C2_RANGE0(0x00); - /* MCG->C4: DMX32=0,DRST_DRS=0 */ - MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); - /* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - OSC->CR = OSC_CR_ERCLKEN_MASK; - /* MCG->C7: OSCSEL=0 */ - MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK); - /* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ - MCG->C5 = MCG_C5_PRDIV0(0x00); - /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ - MCG->C6 = MCG_C6_VDIV0(0x00); - while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */ - } - while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */ - } -#elif (CLOCK_SETUP == 1) || (CLOCK_SETUP == 4) - /* SIM->SCGC5: PORTA=1 */ - SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */ - /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */ - SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | - SIM_CLKDIV1_OUTDIV2(0x01) | - SIM_CLKDIV1_OUTDIV3(0x02) | - SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */ - /* SIM->SOPT2: PLLFLLSEL=1 */ - SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */ - /* SIM->SOPT1: OSC32KSEL=3 */ - SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */ - /* PORTA->PCR[18]: ISF=0,MUX=0 */ - PORTA->PCR[18] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); - /* Switch to FBE Mode */ - /* MCG->C2: LOCRE0=0,?=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */ - MCG->C2 = MCG_C2_RANGE0(0x02); - /* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - OSC->CR = OSC_CR_ERCLKEN_MASK; - /* MCG->C7: OSCSEL=0 */ - MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK); - /* MCG->C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x07) | MCG_C1_IRCLKEN_MASK); - /* MCG->C4: DMX32=0,DRST_DRS=0 */ - MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); - /* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */ - MCG->C5 = MCG_C5_PRDIV0(0x13); - /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0x18 */ - MCG->C6 = MCG_C6_VDIV0(0x18); - while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ - } - while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ - } - /* Switch to PBE Mode */ - /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */ - MCG->C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x18)); - while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ - } - while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */ - } - /* Switch to PEE Mode */ - /* MCG->C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x05) | MCG_C1_IRCLKEN_MASK); - while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */ - } - #if (CLOCK_SETUP == 4) - /* Set USB input clock to 48MHz */ - /* SIM->CLKDIV2: USBDIV=4,USBFRAC=1 */ - SIM->CLKDIV2 = (uint32_t)((SIM->CLKDIV2 & (uint32_t)~(uint32_t)( - SIM_CLKDIV2_USBDIV(0x03) - )) | (uint32_t)( - SIM_CLKDIV2_USBDIV(0x04) | - SIM_CLKDIV2_USBFRAC_MASK - )); + /* Power mode protection initialization */ +#ifdef SYSTEM_SMC_PMPROT_VALUE + SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE; +#endif + + /* System clock initialization */ + /* Internal reference clock trim initialization */ +#if defined(SLOW_TRIM_ADDRESS) + if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) { /* Skip if non-volatile flash memory is erased */ + MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS); + #endif /* defined(SLOW_TRIM_ADDRESS) */ + #if defined(SLOW_FINE_TRIM_ADDRESS) + MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK); #endif -#elif (CLOCK_SETUP == 2) - /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */ - SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | - SIM_CLKDIV1_OUTDIV2(0x00) | - SIM_CLKDIV1_OUTDIV3(0x00) | - SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */ - /* SIM->SOPT2: PLLFLLSEL=0 */ - SIM->SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */ - /* SIM->SOPT1: OSC32KSEL=3 */ - SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */ - /* MCG->SC: FCRDIV=0 */ - MCG->SC &= (uint8_t)~(uint8_t)(MCG_SC_FCRDIV(0x07)); - /* Switch to FBI Mode */ - /* MCG->C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = MCG_C1_CLKS(0x01) | - MCG_C1_FRDIV(0x00) | - MCG_C1_IREFS_MASK | - MCG_C1_IRCLKEN_MASK; - /* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=1 */ - MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_IRCS_MASK); - /* MCG->C4: DMX32=0,DRST_DRS=0 */ - MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); - /* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - OSC->CR = OSC_CR_ERCLKEN_MASK; - /* MCG->C7: OSCSEL=0 */ - MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK); - /* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ - MCG->C5 = MCG_C5_PRDIV0(0x00); - /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ - MCG->C6 = MCG_C6_VDIV0(0x00); - while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */ + #if defined(FAST_TRIM_ADDRESS) + MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK); + #endif + #if defined(FAST_FINE_TRIM_ADDRESS) + MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK); + #endif /* defined(FAST_FINE_TRIM_ADDRESS) */ +#if defined(SLOW_TRIM_ADDRESS) } - while((MCG->S & 0x0CU) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */ - } - /* Switch to BLPI Mode */ - /* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=1,IRCS=1 */ - MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_LP_MASK | MCG_C2_IRCS_MASK); - while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */ - } - while((MCG->S & MCG_S_IRCST_MASK) == 0x00U) { /* Check that the fast external reference clock is selected. */ - } -#elif (CLOCK_SETUP == 3) - /* SIM->SCGC6: RTC=1 */ - SIM->SCGC6 |= SIM_SCGC6_RTC_MASK; - if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the OSCILLATOR is not already enabled */ - /* RTC->CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - RTC->CR &= (uint32_t)~(uint32_t)( - RTC_CR_SC2P_MASK | - RTC_CR_SC4P_MASK | - RTC_CR_SC8P_MASK | - RTC_CR_SC16P_MASK - ); - /* RTC->CR: OSCE=1 */ - RTC->CR |= RTC_CR_OSCE_MASK; - /* RTC->CR: CLKO=0 */ - RTC->CR &= (uint32_t)~(uint32_t)(RTC_CR_CLKO_MASK); - } - /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */ - SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | - SIM_CLKDIV1_OUTDIV2(0x00) | - SIM_CLKDIV1_OUTDIV3(0x00) | - SIM_CLKDIV1_OUTDIV4(0x00); /* Update system prescalers */ - /* SIM->SOPT1: OSC32KSEL=2 */ - SIM->SOPT1 = (uint32_t)((SIM->SOPT1 & (uint32_t)~(uint32_t)( - SIM_SOPT1_OSC32KSEL(0x01) - )) | (uint32_t)( - SIM_SOPT1_OSC32KSEL(0x02) - )); /* System oscillator drives 32 kHz clock for various peripherals */ - /* Switch to FBE Mode */ - /* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */ - MCG->C2 = MCG_C2_RANGE0(0x00); - /* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - OSC->CR = OSC_CR_ERCLKEN_MASK; - /* MCG->C7: OSCSEL=1 */ - MCG->C7 |= MCG_C7_OSCSEL_MASK; - /* MCG->C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK); - /* MCG->C4: DMX32=0,DRST_DRS=0 */ - MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); - /* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ - MCG->C5 = MCG_C5_PRDIV0(0x00); - /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ - MCG->C6 = MCG_C6_VDIV0(0x00); - while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ - } - while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ - } - /* Switch to BLPE Mode */ - /* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=1,IRCS=0 */ - MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_LP_MASK); - while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ + #endif /* defined(SLOW_TRIM_ADDRESS) */ + + /* Set system prescalers and clock sources */ + SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */ + SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */ + SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */ +#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI)) + /* Set MCG and OSC */ +#if ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U))) + /* SIM_SCGC5: PORTA=1 */ + SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; + /* PORTA_PCR18: ISF=0,MUX=0 */ + PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); + if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) { + /* PORTA_PCR19: ISF=0,MUX=0 */ + PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); } #endif + MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */ + MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */ + /* Check that the source of the FLL reference clock is the requested one. */ + if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) { + while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { + } + } else { + while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { + } + } + MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */ + MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */ + OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */ + MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */ + #if (MCG_MODE == MCG_MODE_BLPI) + /* BLPI specific */ + MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */ + #endif + +#else /* MCG_MODE */ + /* Set MCG and OSC */ +#if (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U) + /* SIM_SCGC5: PORTA=1 */ + SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; + /* PORTA_PCR18: ISF=0,MUX=0 */ + PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); + if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) { + /* PORTA_PCR19: ISF=0,MUX=0 */ + PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); + } +#endif + MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */ + MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */ + OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */ + MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */ + #if (MCG_MODE == MCG_MODE_PEE) + MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/ + #else + MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */ + #endif + if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) { + while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */ + } + } + /* Check that the source of the FLL reference clock is the requested one. */ + if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) { + while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { + } + } else { + while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { + } + } + MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */ +#endif /* MCG_MODE */ + + /* Common for all MCG modes */ + + /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */ + MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */ + MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */ + if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) { + MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */ + } + /* BLPE, PEE and PBE MCG mode specific */ + +#if (MCG_MODE == MCG_MODE_BLPE) + MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */ +#elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE)) + MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */ + while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/ + } + #if (MCG_MODE == MCG_MODE_PEE) + MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK); + #endif +#endif +#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE)) + while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */ + } +#elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI)) + while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */ + } +#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE)) + while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ + } +#elif (MCG_MODE == MCG_MODE_PEE) + while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */ + } +#endif +#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT)) + SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */ + while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */ + } +#endif + +#if defined(SYSTEM_SIM_CLKDIV2_VALUE) + SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */ +#endif + + /* PLL loss of lock interrupt request initialization */ + if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) { + NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */ + } } /* ---------------------------------------------------------------------------- @@ -342,81 +285,107 @@ void SystemInit (void) { ---------------------------------------------------------------------------- */ void SystemCoreClockUpdate (void) { - uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ - uint8_t Divider; + uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ + uint16_t Divider; - if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) { + if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { /* Output of FLL or PLL is selected */ - if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { + if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) { /* FLL is selected */ - if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) { + if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { /* External reference clock is selected */ - if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { - MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ - } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ - MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ - } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ - Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); - MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ - if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) { - MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */ - } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */ - } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ - MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ - } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ + switch (MCG->C7 & MCG_C7_OSCSEL_MASK) { + case 0x00U: + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + break; + case 0x01U: + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + break; + case 0x02U: + default: + MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */ + break; + } + if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { + switch (MCG->C1 & MCG_C1_FRDIV_MASK) { + case 0x38U: + Divider = 1536U; + break; + case 0x30U: + Divider = 1280U; + break; + default: + Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + break; + } + } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */ + Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + } + MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ + } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ + } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ /* Select correct multiplier to calculate the MCG output clock */ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { - case 0x0u: - MCGOUTClock *= 640u; + case 0x00U: + MCGOUTClock *= 640U; break; - case 0x20u: - MCGOUTClock *= 1280u; + case 0x20U: + MCGOUTClock *= 1280U; break; - case 0x40u: - MCGOUTClock *= 1920u; + case 0x40U: + MCGOUTClock *= 1920U; break; - case 0x60u: - MCGOUTClock *= 2560u; + case 0x60U: + MCGOUTClock *= 2560U; break; - case 0x80u: - MCGOUTClock *= 732u; + case 0x80U: + MCGOUTClock *= 732U; break; - case 0xA0u: - MCGOUTClock *= 1464u; + case 0xA0U: + MCGOUTClock *= 1464U; break; - case 0xC0u: - MCGOUTClock *= 2197u; + case 0xC0U: + MCGOUTClock *= 2197U; break; - case 0xE0u: - MCGOUTClock *= 2929u; + case 0xE0U: + MCGOUTClock *= 2929U; break; default: break; } - } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ + } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ /* PLL is selected */ - Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK)); - MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ - Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u); - MCGOUTClock *= Divider; /* Calculate the MCG output clock */ - } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ - } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) { + Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); + MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ + Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); + MCGOUTClock *= Divider; /* Calculate the MCG output clock */ + } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { /* Internal reference clock is selected */ - if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) { - MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ - } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ - MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */ - } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ - } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) { + if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ + } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ + Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); + MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */ + } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { /* External reference clock is selected */ - if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { - MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ - } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ - MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ - } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ - } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ + switch (MCG->C7 & MCG_C7_OSCSEL_MASK) { + case 0x00U: + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + break; + case 0x01U: + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + break; + case 0x02U: + default: + MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */ + break; + } + } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ /* Reserved value */ return; - } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ - SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); + } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ + SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); }