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Merge pull request #13643 from OpenNuvoton/nuvoton_m2351_gcc_iar_5.15 

M2351: Support GCC and IAR
pull/13758/head
Martin Kojtal 2020-10-13 11:21:52 +01:00 committed by GitHub
parent f5633c4a04 a76e49c843
commit f1e304bb0b
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
18 changed files with 1306 additions and 928 deletions
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60
targets/TARGET_NUVOTON/TARGET_M2351/TARGET_M23_NS/device/TOOLCHAIN_ARMC6/M2351.sct Normal file
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#! armclang -E
/*
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "../../../device/partition_M2351_mem.h"
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
LR_IROM1 MBED_APP_START
{
/* load address = execution address */
ER_IROM1 +0
{
*(RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE
{
}
/* Reserve for vectors
*
* Vector table base address is required to be 128-byte aligned at a minimum.
* A PE might impose further restrictions on it. */
ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
{
}
RW_IRAM1 AlignExpr(+0, 16)
{
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
{
}
}
ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= MBED_RAM_APP_START + MBED_RAM_APP_SIZE)

212
targets/TARGET_NUVOTON/TARGET_M2351/TARGET_M23_NS/device/TOOLCHAIN_GCC_ARM/M2351.ld Normal file
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/*
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Nuvoton M2351 GCC linker script file
*/
#include "../../../device/partition_M2351_mem.h"
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
StackSize = MBED_BOOT_STACK_SIZE;
MEMORY
{
VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400
RAM_INTERN (rwx) : ORIGIN = MBED_RAM_APP_START, LENGTH = MBED_RAM_APP_SIZE
}
/**
* Must match cmsis_nvic.h
*/
__vector_size = 4 * (16 + 102);
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
. = ALIGN(8);
} > VECTORS
.copy.table : ALIGN(4)
{
__copy_table_start__ = .;
LONG (LOADADDR(.data))
LONG (ADDR(.data))
LONG (SIZEOF(.data))
__copy_table_end__ = .;
} > FLASH
.zero.table : ALIGN(4)
{
__zero_table_start__ = .;
LONG (ADDR(.bss))
LONG (SIZEOF(.bss))
__zero_table_end__ = .;
} > FLASH
.text :
{
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.stack (NOLOAD) :
{
. = ALIGN(8);
__StackLimit = .;
. += StackSize;
__StackTop = .;
} > RAM_INTERN
PROVIDE(__stack = __StackTop);
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > FLASH
/* Relocate vector table in SRAM */
.isr_vector.reloc (NOLOAD) :
{
. = ALIGN(1 << LOG2CEIL(__vector_size));
PROVIDE(__start_vector_table__ = .);
. += __vector_size;
PROVIDE(__end_vector_table__ = .);
} > RAM_INTERN
.data :
{
PROVIDE( __etext = LOADADDR(.data) );
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
/* All data end */
. = ALIGN(32);
__data_end__ = .;
} >RAM_INTERN AT>FLASH
.bss (NOLOAD):
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM_INTERN
.heap (NOLOAD) :
{
. = ALIGN(8);
__end__ = .;
end = __end__;
*(.heap*);
. += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
__HeapLimit = .;
} > RAM_INTERN
Image$$ARM_LIB_HEAP$$ZI$$Base = ADDR(.heap);
Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap);
PROVIDE(__heap_size = SIZEOF(.heap));
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
}

64
targets/TARGET_NUVOTON/TARGET_M2351/TARGET_M23_NS/device/TOOLCHAIN_IAR/M2351.icf Normal file
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/*
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
include "../../../device/partition_M2351_mem.icf.h";
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START;
define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
define symbol __ICFEDIT_size_intvec__ = 4 * (16 + 102);
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
define block IRAMVEC with alignment = 1024, size = __ICFEDIT_size_intvec__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem: __ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place at start of IRAM_region { block CSTACK };
place in IRAM_region { block IRAMVEC };
place in IRAM_region { readwrite };
place in IRAM_region { block HEAP };

72
targets/TARGET_NUVOTON/TARGET_M2351/TARGET_M23_S/device/TOOLCHAIN_ARMC6/M2351.sct Normal file
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#! armclang -E
/*
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "../../../device/partition_M2351_mem.h"
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
LR_IROM1 MBED_APP_START
{
/* load address = execution address */
ER_IROM1 +0
{
*(RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE
{
}
/* Reserve for vectors
*
* Vector table base address is required to be 128-byte aligned at a minimum.
* A PE might impose further restrictions on it. */
ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
{
}
/* 16 byte-aligned */
RW_IRAM1 AlignExpr(+0, 16)
{
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
{
}
}
LR_IROM_NSC NU_TZ_NSC_START NU_TZ_NSC_SIZE
{
ER_IROM_NSC NU_TZ_NSC_START FIXED PADVALUE 0xFFFFFFFF NU_TZ_NSC_SIZE
{
*(Veneer$$CMSE)
}
}
/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. */
ScatterAssert(ImageBase(ER_IROM_NSC) >= 0x4000)
/* Heap must be allocated in RAM. */
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_APP_START + MBED_RAM_APP_SIZE))

234
targets/TARGET_NUVOTON/TARGET_M2351/TARGET_M23_S/device/TOOLCHAIN_GCC_ARM/M2351.ld Normal file
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/*
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Nuvoton M2351 GCC linker script file
*/
#include "../../../device/partition_M2351_mem.h"
#ifndef MBED_BOOT_STACK_SIZE
#define MBED_BOOT_STACK_SIZE 0x400
#endif
StackSize = MBED_BOOT_STACK_SIZE;
MEMORY
{
VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400
FLASH_NSC (rx) : ORIGIN = NU_TZ_NSC_START, LENGTH = NU_TZ_NSC_SIZE
RAM_INTERN (rwx) : ORIGIN = MBED_RAM_APP_START, LENGTH = MBED_RAM_APP_SIZE
}
/**
* Must match cmsis_nvic.h
*/
__vector_size = 4 * (16 + 102);
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
. = ALIGN(8);
} > VECTORS
.copy.table : ALIGN(4)
{
__copy_table_start__ = .;
LONG (LOADADDR(.data))
LONG (ADDR(.data))
LONG (SIZEOF(.data))
__copy_table_end__ = .;
} > FLASH
.zero.table : ALIGN(4)
{
__zero_table_start__ = .;
LONG (ADDR(.bss))
LONG (SIZEOF(.bss))
__zero_table_end__ = .;
} > FLASH
.text :
{
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.stack (NOLOAD) :
{
. = ALIGN(8);
__StackLimit = .;
. += StackSize;
__StackTop = .;
} > RAM_INTERN
PROVIDE(__stack = __StackTop);
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > FLASH
/* Relocate vector table in SRAM */
.isr_vector.reloc (NOLOAD) :
{
. = ALIGN(1 << LOG2CEIL(__vector_size));
PROVIDE(__start_vector_table__ = .);
. += __vector_size;
PROVIDE(__end_vector_table__ = .);
} > RAM_INTERN
.data :
{
PROVIDE( __etext = LOADADDR(.data) );
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
/* All data end */
. = ALIGN(32);
__data_end__ = .;
} >RAM_INTERN AT>FLASH
.bss (NOLOAD):
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM_INTERN
/* Veneer$$CMSE : */
.gnu.sgstubs NU_TZ_NSC_START :
{
. = ALIGN(32);
__sgstubs_start = .;
*(.gnu.sgstubs.*)
__sgstubs_end = .;
. = ALIGN(32);
} > FLASH_NSC
/* NOTE: __sgstubs_end is not updated with *(.gnu.sgstubs.*). __sgstubs_start and
* __sgstubs_end are the same. GCC bug? */
Image$$ER_IROM_NSC$$Base = ADDR(.gnu.sgstubs);
ASSERT(SIZEOF(.gnu.sgstubs) <= NU_TZ_NSC_SIZE, "Size of .gnu.sgstubs region cannot exceed NU_TZ_NSC_SIZE.")
/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. */
ASSERT(((__sgstubs_start % 32) == 0), "Requested by SAU, NSC region must start at 32 byte-aligned boundary.")
ASSERT(__sgstubs_start >= 0x4000, "By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.")
.heap (NOLOAD) :
{
. = ALIGN(8);
__end__ = .;
end = __end__;
*(.heap*);
. += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
__HeapLimit = .;
} > RAM_INTERN
Image$$ARM_LIB_HEAP$$ZI$$Base = ADDR(.heap);
Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap);
PROVIDE(__heap_size = SIZEOF(.heap));
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
}

74
targets/TARGET_NUVOTON/TARGET_M2351/TARGET_M23_S/device/TOOLCHAIN_IAR/M2351.icf Normal file
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/*
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
include "../../../device/partition_M2351_mem.icf.h";
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
/* FIXME: Check NSC area requirement */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START;
define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
define symbol __ICFEDIT_size_intvec__ = 4 * (16 + 102);
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
/* IAR has something wrong with "$$" in section/block name. So unlike other toolchains,
* we name "ER_IROM_NSC" instead of "Image$$ER_IROM_NSC". */
define block ER_IROM_NSC with alignment = 32 { readonly section Veneer$$CMSE };
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
define block IRAMVEC with alignment = 1024, size = __ICFEDIT_size_intvec__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem: __ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place at address mem: NU_TZ_NSC_START { block ER_IROM_NSC };
place at start of IRAM_region { block CSTACK };
place in IRAM_region { block IRAMVEC };
place in IRAM_region { readwrite };
place in IRAM_region { block HEAP };
define exported symbol Image$$ER_IROM_NSC$$Base = NU_TZ_NSC_START;

173
targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARMC6/M2351.sct
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@ -1,173 +0,0 @@
#! armclang -E
/*
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "../partition_M2351_mem.h"
#ifndef NU_TZ_NSC_SIZE
#define NU_TZ_NSC_SIZE (0x1000)
#endif
#if defined(DOMAIN_NS) && DOMAIN_NS
#ifndef MBED_APP_START
#define MBED_APP_START NU_ROM_START_NS
#endif
#ifndef MBED_APP_SIZE
#define MBED_APP_SIZE NU_ROM_SIZE_NS
#endif
#ifndef MBED_RAM_APP_START
#define MBED_RAM_APP_START NU_RAM_START_NS
#endif
#ifndef MBED_RAM_APP_SIZE
#define MBED_RAM_APP_SIZE NU_RAM_SIZE_NS
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#else
#ifndef MBED_APP_START
#define MBED_APP_START NU_ROM_START_S
#endif
#ifndef MBED_APP_SIZE
#define MBED_APP_SIZE NU_ROM_SIZE_S
#endif
#ifndef MBED_RAM_APP_START
#define MBED_RAM_APP_START NU_RAM_START_S
#endif
#ifndef MBED_RAM_APP_SIZE
#define MBED_RAM_APP_SIZE NU_RAM_SIZE_S
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#endif
/* Requirements for NSC location
*
* 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
* 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
* 3. Greentea NVSTORE uses last 2 sectors or 4KiB x 2 for its test. Avoid this range.
* 4. NSC region size defaults to 4KiB if not defined.
*/
#define NU_TZ_NSC_START (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE)
#if defined(DOMAIN_NS) && DOMAIN_NS
LR_IROM1 MBED_APP_START
{
/* load address = execution address */
ER_IROM1 +0
{
*(RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE
{
}
/* Reserve for vectors
*
* Vector table base address is required to be 128-byte aligned at a minimum.
* A PE might impose further restrictions on it. */
ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
{
}
/* 16 byte-aligned */
RW_IRAM1 AlignExpr(+0, 16)
{
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
{
}
}
ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= MBED_RAM_APP_START + MBED_RAM_APP_SIZE)
#else
LR_IROM1 MBED_APP_START
{
/* load address = execution address */
ER_IROM1 +0
{
*(RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE
{
}
/* Reserve for vectors
*
* Vector table base address is required to be 128-byte aligned at a minimum.
* A PE might impose further restrictions on it. */
ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
{
}
/* 16 byte-aligned */
RW_IRAM1 AlignExpr(+0, 16)
{
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
{
}
}
LR_IROM_NSC NU_TZ_NSC_START NU_TZ_NSC_SIZE
{
ER_IROM_NSC +0
{
*(Veneer$$CMSE)
}
ER_IROM_NSC_PAD +0 FILL 0xFFFFFFFF (NU_TZ_NSC_START + NU_TZ_NSC_SIZE - ImageLimit(ER_IROM_NSC))
{
}
}
ScatterAssert(LoadLimit(LR_IROM1) <= NU_TZ_NSC_START)
ScatterAssert(LoadLimit(LR_IROM_NSC) <= (NU_TZ_NSC_START + NU_TZ_NSC_SIZE))
/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000 */
ScatterAssert(LoadBase(LR_IROM_NSC) >= 0x4000)
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_APP_START + MBED_RAM_APP_SIZE))
#endif

368
targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/M2351.ld
View File

@ -1,368 +0,0 @@
/*
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Nuvoton M2351 GCC linker script file
*/
#include "../partition_M2351_mem.h"
#ifndef NU_TZ_NSC_SIZE
#define NU_TZ_NSC_SIZE (0x1000)
#endif
#if defined(DOMAIN_NS) && DOMAIN_NS
#ifndef MBED_APP_START
#define MBED_APP_START NU_ROM_START_NS
#endif
#ifndef MBED_APP_SIZE
#define MBED_APP_SIZE NU_ROM_SIZE_NS
#endif
#ifndef MBED_RAM_APP_START
#define MBED_RAM_APP_START NU_RAM_START_NS
#endif
#ifndef MBED_RAM_APP_SIZE
#define MBED_RAM_APP_SIZE NU_RAM_SIZE_NS
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#else
#ifndef MBED_APP_START
#define MBED_APP_START NU_ROM_START_S
#endif
#ifndef MBED_APP_SIZE
#define MBED_APP_SIZE NU_ROM_SIZE_S
#endif
#ifndef MBED_RAM_APP_START
#define MBED_RAM_APP_START NU_RAM_START_S
#endif
#ifndef MBED_RAM_APP_SIZE
#define MBED_RAM_APP_SIZE NU_RAM_SIZE_S
#endif
#ifndef MBED_BOOT_STACK_SIZE
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#endif
StackSize = MBED_BOOT_STACK_SIZE;
/* Requirements for NSC location
*
* 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
* 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
* 3. Greentea NVSTORE uses last 2 sectors or 4KiB x 2 for its test. Avoid this range.
* 4. NSC region size defaults to 4KiB if not defined.
*/
#ifndef NU_TZ_NSC_START
#define NU_TZ_NSC_START (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE)
#endif
#if defined(DOMAIN_NS) && DOMAIN_NS
MEMORY
{
VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400
RAM_INTERN (rwx) : ORIGIN = MBED_RAM_APP_START, LENGTH = MBED_RAM_APP_SIZE
}
#else
MEMORY
{
VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = NU_TZ_NSC_START - MBED_APP_START - 0x400
NSC_FLASH (rx) : ORIGIN = NU_TZ_NSC_START, LENGTH = NU_TZ_NSC_SIZE
RAM_INTERN (rwx) : ORIGIN = MBED_RAM_APP_START, LENGTH = MBED_RAM_APP_SIZE
}
#endif
/**
* Must match cmsis_nvic.h
*/
__vector_size = 4 * (16 + 102);
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
. = ALIGN(8);
} > VECTORS
/* ensure that uvisor bss is at the beginning of memory */
.uvisor.bss (NOLOAD):
{
. = ALIGN(32);
__uvisor_bss_start = .;
/* protected uvisor main bss */
. = ALIGN(32);
__uvisor_bss_main_start = .;
KEEP(*(.keep.uvisor.bss.main))
. = ALIGN(32);
__uvisor_bss_main_end = .;
/* protected uvisor secure boxes bss */
. = ALIGN(32);
__uvisor_bss_boxes_start = .;
KEEP(*(.keep.uvisor.bss.boxes))
. = ALIGN(32);
__uvisor_bss_boxes_end = .;
/* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. */
. = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));
__uvisor_bss_end = .;
} > RAM_INTERN
.text :
{
/* uVisor code and data */
. = ALIGN(8);
__uvisor_main_start = .;
*(.uvisor.main)
__uvisor_main_end = .;
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
#if (! defined(DOMAIN_NS)) || (! DOMAIN_NS)
/* Veneer$$CMSE : */
.gnu.sgstubs :
{
__sgstubs_start = .;
*(.gnu.sgstubs.*)
__sgstubs_end = .;
} > NSC_FLASH
__nu_tz_nsc_start = NU_TZ_NSC_START;
__nu_tz_nsc_size = NU_TZ_NSC_SIZE;
/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. */
ASSERT(__sgstubs_start >= 0x4000, "By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.")
#endif
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > FLASH
/* .stack section doesn't contains any symbols. It is only
* used for linker to reserve space for the main stack section
* WARNING: .stack should come immediately after the last secure memory
* section. This provides stack overflow detection. */
.stack (NOLOAD):
{
__StackLimit = .;
*(.stack*);
. += StackSize - (. - __StackLimit);
} > RAM_INTERN
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ADDR(.stack) + SIZEOF(.stack);
__StackLimit = ADDR(.stack);
PROVIDE(__stack = __StackTop);
/* Relocate vector table in SRAM */
.isr_vector.reloc (NOLOAD) :
{
. = ALIGN(1 << LOG2CEIL(__vector_size));
PROVIDE(__start_vector_table__ = .);
. += __vector_size;
PROVIDE(__end_vector_table__ = .);
} > RAM_INTERN
.data :
{
PROVIDE( __etext = LOADADDR(.data) );
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
/* All data end */
. = ALIGN(32);
__data_end__ = .;
} >RAM_INTERN AT>FLASH
/* uvisor configuration data */
.uvisor.secure :
{
. = ALIGN(32);
__uvisor_secure_start = .;
/* uvisor secure boxes configuration tables */
. = ALIGN(32);
__uvisor_cfgtbl_start = .;
KEEP(*(.keep.uvisor.cfgtbl))
. = ALIGN(32);
__uvisor_cfgtbl_end = .;
/* pointers to uvisor secure boxes configuration tables */
/* note: no further alignment here, we need to have the exact list of pointers */
__uvisor_cfgtbl_ptr_start = .;
KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
KEEP(*(.keep.uvisor.cfgtbl_ptr))
__uvisor_cfgtbl_ptr_end = .;
/* the following symbols are kept for backward compatibility and will be soon
* deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)
* will need to use uVisor 0.8.x or above, or the security assertions will halt the
* system */
/************************/
__uvisor_data_src = .;
__uvisor_data_start = .;
__uvisor_data_end = .;
/************************/
. = ALIGN(32);
__uvisor_secure_end = .;
} >FLASH
.uninitialized (NOLOAD):
{
. = ALIGN(32);
__uninitialized_start = .;
*(.uninitialized)
KEEP(*(.keep.uninitialized))
. = ALIGN(32);
__uninitialized_end = .;
} > RAM_INTERN
.bss (NOLOAD):
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM_INTERN
.heap (NOLOAD):
{
__end__ = .;
end = __end__;
*(.heap*);
. += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
__HeapLimit = .;
} > RAM_INTERN
PROVIDE(__heap_size = SIZEOF(.heap));
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
/* Provide physical memory boundaries for uVisor. */
__uvisor_flash_start = ORIGIN(VECTORS);
__uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
__uvisor_sram_start = ORIGIN(RAM_INTERN);
__uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);
}

138
targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_IAR/M2351.icf
View File

@ -1,138 +0,0 @@
/*
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
include "../partition_M2351_mem.icf";
if (! isdefinedsymbol(NU_TZ_NSC_SIZE)) {
define symbol NU_TZ_NSC_SIZE = 0x1000;
}
if (isdefinedsymbol(DOMAIN_NS)) {
if (! isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = NU_ROM_START_NS;
}
if (! isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = NU_ROM_SIZE_NS;
}
if (! isdefinedsymbol(MBED_RAM_APP_START)) {
define symbol MBED_RAM_APP_START = NU_RAM_START_NS;
}
if (! isdefinedsymbol(MBED_RAM_APP_SIZE)) {
define symbol MBED_RAM_APP_SIZE = NU_RAM_SIZE_NS;
}
if (! isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START;
define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
define symbol __ICFEDIT_size_heap__ = 0x8000;
} else {
if (! isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = NU_ROM_START_S;
}
if (! isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = NU_ROM_SIZE_S;
}
if (! isdefinedsymbol(MBED_RAM_APP_START)) {
define symbol MBED_RAM_APP_START = NU_RAM_START_S;
}
if (! isdefinedsymbol(MBED_RAM_APP_SIZE)) {
define symbol MBED_RAM_APP_SIZE = NU_RAM_SIZE_S;
}
if (! isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
/* Requirements for NSC location
*
* 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
* 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
* 3. Greentea NVSTORE uses last 2 sectors or 4KiB x 2 for its test. Avoid this range.
* 4. NSC region size defaults to 4KiB if not defined.
*/
if (! isdefinedsymbol(NU_TZ_NSC_START)) {
define symbol NU_TZ_NSC_START = MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE;
}
define exported symbol __NU_TZ_NSC_start__ = NU_TZ_NSC_START;
define exported symbol __NU_TZ_NSC_size__ = NU_TZ_NSC_SIZE;
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol __ICFEDIT_region_NSCROM_start__ = NU_TZ_NSC_START;
define symbol __ICFEDIT_region_NSCROM_end__ = NU_TZ_NSC_START + NU_TZ_NSC_SIZE - 1;
define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START;
define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
define symbol __ICFEDIT_size_heap__ = 0x4000;
}
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
define block IRAMVEC with alignment = 1024, size = 4 * (16 + 102) { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
if (! isdefinedsymbol(DOMAIN_NS)) {
place at address mem:__ICFEDIT_region_NSCROM_start__ { readonly section Veneer$$CMSE };
}
place at start of IRAM_region { block CSTACK };
place in IRAM_region { block IRAMVEC };
place in IRAM_region { readwrite };
place in IRAM_region { block HEAP };

6
targets/TARGET_NUVOTON/TARGET_M2351/device/cmsis.h
View File

@ -23,8 +23,8 @@
#include "partition_M2351.h"
/* Check relevant macro has been defined */
#if (! defined(NU_TZ_SECURE_FLASH_SIZE))
#error("NU_TZ_SECURE_FLASH_SIZE not defined")
#if (! defined(NU_ROM_SIZE_S))
#error("NU_ROM_SIZE_S not defined")
#endif
// Support linker-generated symbol as start of relocated vector table.
@ -38,7 +38,7 @@ extern uint32_t __start_vector_table__;
/* TZ_START_NS: Start address of non-secure application */
#ifndef TZ_START_NS
#define TZ_START_NS (NS_OFFSET + NU_TZ_SECURE_FLASH_SIZE)
#define TZ_START_NS (NS_OFFSET + NU_ROM_SIZE_S)
#endif
#endif

53
targets/TARGET_NUVOTON/TARGET_M2351/device/partition_M2351.h
View File

@ -21,48 +21,31 @@
#include "partition_M2351_mem.h"
#define NU_TZ_SECURE_FLASH_SIZE NU_ROM_SIZE_S
#define NU_TZ_SECURE_SRAM_SIZE NU_RAM_SIZE_S
#ifdef __cplusplus
extern "C"
{
#endif
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#if defined(__ARMCC_VERSION)
extern int Load$$LR$$LR_IROM_NSC$$Base;
extern int Load$$LR$$LR_IROM_NSC$$Length;
#define NU_TZ_NSC_REGION_START ((uint32_t) &Load$$LR$$LR_IROM_NSC$$Base)
#define NU_TZ_NSC_REGION_SIZE ((uint32_t) &Load$$LR$$LR_IROM_NSC$$Length)
extern int Image$$ER_IROM_NSC$$Base;
#define NU_TZ_NSC_REGION_START ((uint32_t) &Image$$ER_IROM_NSC$$Base)
#define NU_TZ_NSC_REGION_SIZE (NU_TZ_NSC_SIZE)
#elif defined(__ICCARM__)
extern int __NU_TZ_NSC_start__;
extern int __NU_TZ_NSC_size__;
#define NU_TZ_NSC_REGION_START ((uint32_t) &__NU_TZ_NSC_start__)
#define NU_TZ_NSC_REGION_SIZE ((uint32_t) &__NU_TZ_NSC_size__)
extern int Image$$ER_IROM_NSC$$Base;
#define NU_TZ_NSC_REGION_START ((uint32_t) &Image$$ER_IROM_NSC$$Base)
#define NU_TZ_NSC_REGION_SIZE (NU_TZ_NSC_SIZE)
#elif defined(__GNUC__)
extern int __nu_tz_nsc_start;
extern int __nu_tz_nsc_size;
#define NU_TZ_NSC_REGION_START ((uint32_t) &__nu_tz_nsc_start)
#define NU_TZ_NSC_REGION_SIZE ((uint32_t) &__nu_tz_nsc_size)
extern int Image$$ER_IROM_NSC$$Base;
#define NU_TZ_NSC_REGION_START ((uint32_t) &Image$$ER_IROM_NSC$$Base)
#define NU_TZ_NSC_REGION_SIZE (NU_TZ_NSC_SIZE)
#endif
/* Check relevant macros have been defined */
#if (! defined(NU_TZ_SECURE_FLASH_SIZE))
#error("NU_TZ_SECURE_FLASH_SIZE not defined")
#endif
#if (! defined(NU_TZ_SECURE_SRAM_SIZE))
#error("NU_TZ_SECURE_SRAM_SIZE not defined")
#endif
#if (! defined(NU_TZ_NSC_REGION_START))
#error("NU_TZ_NSC_REGION_START not defined")
#endif
#if (! defined(NU_TZ_NSC_REGION_SIZE))
#error("NU_TZ_NSC_REGION_SIZE not defined")
#endif
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
@ -88,7 +71,7 @@ extern int __nu_tz_nsc_size;
// <0x16000=> 88KB
// <0x18000=> 96KB
*/
#define SCU_SECURE_SRAM_SIZE NU_TZ_SECURE_SRAM_SIZE
#define SCU_SECURE_SRAM_SIZE NU_RAM_SIZE_S
#define NON_SECURE_SRAM_BASE (0x30000000 + SCU_SECURE_SRAM_SIZE)
@ -103,7 +86,7 @@ extern int __nu_tz_nsc_size;
// <o>Secure Flash ROM Size <0x800-0x7FFFF:0x800>
*/
#define FMC_SECURE_ROM_SIZE NU_TZ_SECURE_FLASH_SIZE
#define FMC_SECURE_ROM_SIZE NU_ROM_SIZE_S
#define FMC_NON_SECURE_BASE (0x10000000 + FMC_SECURE_ROM_SIZE)
@ -867,5 +850,9 @@ __STATIC_INLINE void TZ_SAU_Setup(void)
#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
#ifdef __cplusplus
}
#endif
#endif /* PARTITION_M2351 */

126
targets/TARGET_NUVOTON/TARGET_M2351/device/partition_M2351_mem.h
View File

@ -19,12 +19,18 @@
#ifndef __PARTITION_M2351_MEM_H__
#define __PARTITION_M2351_MEM_H__
/* About partition_M2351_mem.h/partition_M2351_mem.icf
/* About partition_M2351_mem.h/partition_M2351_mem.icf.h
*
* 1. partition_M2351_mem.h is created for centralizing memory partition configuration. It will be
* included by C/C++ files and linker files (except IAR linker file).
* 2. IAR linker doesn't support preprocessor, so partition_M2351_mem.icf, duplicate of partition_M2351_mem.h
* 2. IAR linker doesn't support preprocessor, so partition_M2351_mem.icf.h, duplicate of partition_M2351_mem.h
* is created for IAR linker file.
* 3. To continue above, we name partition_M2351_mem.icf.h instead of partition_M2351_mem.icf because:
* (1) Mbed OS build tool may mis-regard partition_M2351_mem.icf as the main linker configuration file.
* (2) *.icf files may not be present in search directories for "include" directive. Per observation,
* the search directories are inconsistent among normal example build and test code build. To address
* it, we name partition_M2351_mem.icf.h instead because *.h files are always present in these builds
* (already there or via copy).
*/
/* Default flash/SRAM partition
@ -39,34 +45,38 @@
*/
#if defined(DOMAIN_NS) && DOMAIN_NS
/* Default non-secure ROM layout */
/* Resolve non-secure ROM start */
#ifndef MBED_ROM_START
#define MBED_ROM_START (0x10040000)
#endif
/* Resolve non-secure ROM size */
#ifndef MBED_ROM_SIZE
#define MBED_ROM_SIZE (0x40000)
#endif
/* Default non-secure RAM layout */
/* Resolve non-secure RAM start */
#ifndef MBED_RAM_START
#define MBED_RAM_START (0x30008000)
#endif
/* Resolve non-secure RAM size */
#ifndef MBED_RAM_SIZE
#define MBED_RAM_SIZE (0x10000)
#endif
#else
/* Default secure ROM layout */
/* Resolve secure ROM start */
#ifndef MBED_ROM_START
#define MBED_ROM_START (0x0)
#endif
/* Resolve secure ROM size */
#ifndef MBED_ROM_SIZE
#define MBED_ROM_SIZE (0x40000)
#endif
/* Default secure RAM layout */
/* Resolve secure RAM start */
#ifndef MBED_RAM_START
#define MBED_RAM_START (0x20000000)
#endif
/* Resolve secure RAM size */
#ifndef MBED_RAM_SIZE
#define MBED_RAM_SIZE (0x8000)
#endif
@ -108,4 +118,108 @@
#endif
/* Mbed build tool passes just APPLICATION_xxx macros to C/C++ files and just
* MBED_APP_xxx macros to linker files even though they mean the same thing.
* Because this file is to include by both C/C++ files and linker files, we add
* these macros according to the others for consistency when they are missing
* in compile or link stage. */
#ifndef APPLICATION_ADDR
#ifdef MBED_APP_START
#define APPLICATION_ADDR MBED_APP_START
#else
#define APPLICATION_ADDR MBED_ROM_START
#endif
#endif
#ifndef APPLICATION_SIZE
#ifdef MBED_APP_SIZE
#define APPLICATION_SIZE MBED_APP_SIZE
#else
#define APPLICATION_SIZE MBED_ROM_SIZE
#endif
#endif
#ifndef APPLICATION_RAM_ADDR
#ifdef MBED_RAM_APP_START
#define APPLICATION_RAM_ADDR MBED_RAM_APP_START
#else
#define APPLICATION_RAM_ADDR MBED_RAM_START
#endif
#endif
#ifndef APPLICATION_RAM_SIZE
#ifdef MBED_RAM_APP_SIZE
#define APPLICATION_RAM_SIZE MBED_RAM_APP_SIZE
#else
#define APPLICATION_RAM_SIZE MBED_RAM_SIZE
#endif
#endif
#ifndef MBED_APP_START
#define MBED_APP_START APPLICATION_ADDR
#endif
#ifndef MBED_APP_SIZE
#define MBED_APP_SIZE APPLICATION_SIZE
#endif
#ifndef MBED_RAM_APP_START
#define MBED_RAM_APP_START APPLICATION_RAM_ADDR
#endif
#ifndef MBED_RAM_APP_SIZE
#define MBED_RAM_APP_SIZE APPLICATION_RAM_SIZE
#endif
#if (APPLICATION_ADDR != MBED_APP_START)
#error("APPLICATION_ADDR and MBED_APP_START are not the same!!!")
#endif
#if (APPLICATION_SIZE != MBED_APP_SIZE)
#error("APPLICATION_SIZE and MBED_APP_SIZE are not the same!!!")
#endif
#if (APPLICATION_RAM_ADDR != MBED_RAM_APP_START)
#error("APPLICATION_RAM_ADDR and MBED_RAM_APP_START are not the same!!!")
#endif
#if (APPLICATION_RAM_SIZE != MBED_RAM_APP_SIZE)
#error("APPLICATION_RAM_SIZE and MBED_RAM_APP_SIZE are not the same!!!")
#endif
/* Determine NSC area
*
* Requirements for NSC area:
* 1. Requested by SAU, NSC area must start at 32 byte-aligned boundary.
* 2. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
* 3. Greentea flash IAP uses last 2 sectors for its test. Avoid this range.
* 4. Greentea NVSTORE uses last 2 sectors or 4 KiB x 2 for its test. Avoid this range.
* 5. KVStore uses last a few KiB. Avoid this range.
* 6. Due to TFM build process, TFM and its tests must generate the same cmse_lib.o.
* To this end, TZ NSC location must fix at a well-known location and cannot place
* arbitrarily.
*
* Configurable for NSC area:
* We cannot configure NSC location via configuration parameter because the generated
* configuration macros are just passed to C/C++ files but not to linker files. So
* we can only hardcode NSC location here as constants (to be included by linker file).
*
* Locate NSC area at end of secure flash:
* We decide to locate NSC area at end of secure flash. To avoid this area
* accidentally erased by flash IAP operation, flash IAP must configure to exclude
* this area.
*/
/* TZ NSC area defaults to from secure ROM end */
#define NU_TZ_NSC_START (NU_ROM_START_S + NU_ROM_SIZE_S - NU_TZ_NSC_SIZE)
/* TZ NSC area defaults to 4KiB. */
#define NU_TZ_NSC_SIZE 0x1000
/* Configuration of flash IAP area */
#define NU_FLASHIAP_SECURE_START NU_ROM_START_S
/* Exclude NSC area to avoid accidentally erased */
#define NU_FLASHIAP_SECURE_SIZE (NU_ROM_SIZE_S - NU_TZ_NSC_SIZE)
#define NU_FLASHIAP_NONSECURE_START NU_ROM_START_NS
#define NU_FLASHIAP_NONSECURE_SIZE NU_ROM_SIZE_NS
#endif /* __PARTITION_M2351_MEM_H__ */

100
targets/TARGET_NUVOTON/TARGET_M2351/device/partition_M2351_mem.icf
View File

@ -1,100 +0,0 @@
/*
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* See partition_M2351_mem.h for documentation */
/* Default flash/SRAM partition
*
* Default flash partition:
* Secure: 256KiB
* Non-secure: 256KiB
*
* Default SRAM partition:
* Secure: 32KiB
* Non-secure: 64KiB
*/
#if defined(DOMAIN_NS) && DOMAIN_NS
/* Default non-secure ROM layout */
if (! isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10040000;
}
if (! isdefinedsymbol(MBED_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = 0x40000;
}
/* Default non-secure RAM layout */
if (! isdefinedsymbol(MBED_RAM_START)) {
define symbol MBED_RAM_START = 0x30008000;
}
if (! isdefinedsymbol(MBED_RAM_SIZE)) {
define symbol MBED_RAM_SIZE = 0x10000;
}
#else
/* Default secure ROM layout */
if (! isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x0;
}
if (! isdefinedsymbol(MBED_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = 0x40000;
}
/* Default secure RAM layout */
if (! isdefinedsymbol(MBED_RAM_START)) {
define symbol MBED_RAM_START = 0x20000000;
}
if (! isdefinedsymbol(MBED_RAM_SIZE)) {
define symbol MBED_RAM_SIZE = 0x8000;
}
#endif
/* Resolved flash/SRAM partition */
#if defined(DOMAIN_NS) && DOMAIN_NS
/* Resolved secure ROM layout */
define symbol NU_ROM_START_S = 0x0;
define symbol NU_ROM_SIZE_S = (0x80000 - MBED_ROM_SIZE);
/* Resolved secure RAM layout */
define symbol NU_RAM_START_S = 0x20000000;
define symbol NU_RAM_SIZE_S = (0x18000 - MBED_RAM_SIZE);
/* Resolved non-secure ROM layout */
define symbol NU_ROM_START_NS = MBED_ROM_START;
define symbol NU_ROM_SIZE_NS = MBED_ROM_SIZE;
/* Resolved non-secure RAM layout */
define symbol NU_RAM_START_NS = MBED_RAM_START;
define symbol NU_RAM_SIZE_NS = MBED_RAM_SIZE;
#else
/* Resolved secure ROM layout */
define symbol NU_ROM_START_S = MBED_ROM_START;
define symbol NU_ROM_SIZE_S = MBED_ROM_SIZE;
/* Resolved secure RAM layout */
define symbol NU_RAM_START_S = MBED_RAM_START;
define symbol NU_RAM_SIZE_S = MBED_RAM_SIZE;
/* Resolved non-secure ROM layout */
define symbol NU_ROM_START_NS = (0x10000000 + MBED_ROM_SIZE);
define symbol NU_ROM_SIZE_NS = (0x80000 - MBED_ROM_SIZE);
/* Resolved non-secure RAM layout */
define symbol NU_RAM_START_NS = (0x30000000 + MBED_RAM_SIZE);
define symbol NU_RAM_SIZE_NS = (0x18000 - MBED_RAM_SIZE);
#endif

252
targets/TARGET_NUVOTON/TARGET_M2351/device/partition_M2351_mem.icf.h Normal file
View File

@ -0,0 +1,252 @@
/*
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* See partition_M2351_mem.h for documentation */
/* IAR doesn't support short-circuit evaluation in boolean operator and fails when
* evaluating undefined symbol. Define it explicitly. */
if (!isdefinedsymbol(DOMAIN_NS)) {
define symbol DOMAIN_NS = 0;
}
/* Default flash/SRAM partition
*
* Default flash partition:
* Secure: 256KiB
* Non-secure: 256KiB
*
* Default SRAM partition:
* Secure: 32KiB
* Non-secure: 64KiB
*/
if (DOMAIN_NS) {
/* Resolve non-secure ROM start */
if (! isdefinedsymbol(MBED_ROM_START)) {
if (isdefinedsymbol(PSA_NON_SECURE_ROM_START)) {
define symbol MBED_ROM_START = PSA_NON_SECURE_ROM_START;
} else {
define symbol MBED_ROM_START = 0x10040000;
}
}
/* Resolve non-secure ROM size */
if (! isdefinedsymbol(MBED_ROM_SIZE)) {
if (isdefinedsymbol(PSA_NON_SECURE_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = PSA_NON_SECURE_ROM_SIZE;
} else {
define symbol MBED_ROM_SIZE = 0x40000;
}
}
/* Resolve non-secure RAM start */
if (! isdefinedsymbol(MBED_RAM_START)) {
if (isdefinedsymbol(PSA_NON_SECURE_RAM_START)) {
define symbol MBED_RAM_START = PSA_NON_SECURE_RAM_START;
} else {
define symbol MBED_RAM_START = 0x30008000;
}
}
/* Resolve non-secure RAM size */
if (! isdefinedsymbol(MBED_RAM_SIZE)) {
if (isdefinedsymbol(PSA_NON_SECURE_RAM_SIZE)) {
define symbol MBED_RAM_SIZE = PSA_NON_SECURE_RAM_SIZE;
} else {
define symbol MBED_RAM_SIZE = 0x10000;
}
}
} else {
/* Resolve secure ROM start */
if (! isdefinedsymbol(MBED_ROM_START)) {
if (isdefinedsymbol(PSA_SECURE_ROM_START)) {
define symbol MBED_ROM_START = PSA_SECURE_ROM_START;
} else {
define symbol MBED_ROM_START = 0x0;
}
}
/* Resolve secure ROM size */
if (! isdefinedsymbol(MBED_ROM_SIZE)) {
if (isdefinedsymbol(PSA_SECURE_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = PSA_SECURE_ROM_SIZE;
} else {
define symbol MBED_ROM_SIZE = 0x40000;
}
}
/* Resolve secure RAM start */
if (! isdefinedsymbol(MBED_RAM_START)) {
if (isdefinedsymbol(PSA_SECURE_RAM_START)) {
define symbol MBED_RAM_START = PSA_SECURE_RAM_START;
} else {
define symbol MBED_RAM_START = 0x20000000;
}
}
/* Resolve secure RAM size */
if (! isdefinedsymbol(MBED_RAM_SIZE)) {
if (isdefinedsymbol(PSA_SECURE_RAM_SIZE)) {
define symbol MBED_RAM_SIZE = PSA_SECURE_RAM_SIZE;
} else {
define symbol MBED_RAM_SIZE = 0x8000;
}
}
}
/* Resolved flash/SRAM partition */
if (DOMAIN_NS) {
/* Resolved secure ROM layout */
define symbol NU_ROM_START_S = 0x0;
define symbol NU_ROM_SIZE_S = (0x80000 - MBED_ROM_SIZE);
/* Resolved secure RAM layout */
define symbol NU_RAM_START_S = 0x20000000;
define symbol NU_RAM_SIZE_S = (0x18000 - MBED_RAM_SIZE);
/* Resolved non-secure ROM layout */
define symbol NU_ROM_START_NS = MBED_ROM_START;
define symbol NU_ROM_SIZE_NS = MBED_ROM_SIZE;
/* Resolved non-secure RAM layout */
define symbol NU_RAM_START_NS = MBED_RAM_START;
define symbol NU_RAM_SIZE_NS = MBED_RAM_SIZE;
} else {
/* Resolved secure ROM layout */
define symbol NU_ROM_START_S = MBED_ROM_START;
define symbol NU_ROM_SIZE_S = MBED_ROM_SIZE;
/* Resolved secure RAM layout */
define symbol NU_RAM_START_S = MBED_RAM_START;
define symbol NU_RAM_SIZE_S = MBED_RAM_SIZE;
/* Resolved non-secure ROM layout */
define symbol NU_ROM_START_NS = (0x10000000 + MBED_ROM_SIZE);
define symbol NU_ROM_SIZE_NS = (0x80000 - MBED_ROM_SIZE);
/* Resolved non-secure RAM layout */
define symbol NU_RAM_START_NS = (0x30000000 + MBED_RAM_SIZE);
define symbol NU_RAM_SIZE_NS = (0x18000 - MBED_RAM_SIZE);
}
/* Mbed build tool passes just APPLICATION_xxx macros to C/C++ files and just
* MBED_APP_xxx macros to linker files even though they mean the same thing.
* Because this file is to include by both C/C++ files and linker files, we add
* these macros according to the others for consistency when they are missing
* in compile or link stage. */
if (!isdefinedsymbol(APPLICATION_ADDR)) {
if (isdefinedsymbol(MBED_APP_START)) {
define symbol APPLICATION_ADDR = MBED_APP_START;
} else {
define symbol APPLICATION_ADDR = MBED_ROM_START;
}
}
if (!isdefinedsymbol(APPLICATION_SIZE)) {
if (isdefinedsymbol(MBED_APP_SIZE)) {
define symbol APPLICATION_SIZE = MBED_APP_SIZE;
} else {
define symbol APPLICATION_SIZE = MBED_ROM_SIZE;
}
}
if (!isdefinedsymbol(APPLICATION_RAM_ADDR)) {
if (isdefinedsymbol(MBED_RAM_APP_START)) {
define symbol APPLICATION_RAM_ADDR = MBED_RAM_APP_START;
} else {
define symbol APPLICATION_RAM_ADDR = MBED_RAM_START;
}
}
if (!isdefinedsymbol(APPLICATION_RAM_SIZE)) {
if (isdefinedsymbol(MBED_RAM_APP_SIZE)) {
define symbol APPLICATION_RAM_SIZE = MBED_RAM_APP_SIZE;
} else {
define symbol APPLICATION_RAM_SIZE = MBED_RAM_SIZE;
}
}
if (!isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = APPLICATION_ADDR;
}
if (!isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = APPLICATION_SIZE;
}
if (!isdefinedsymbol(MBED_RAM_APP_START)) {
define symbol MBED_RAM_APP_START = APPLICATION_RAM_ADDR;
}
if (!isdefinedsymbol(MBED_RAM_APP_SIZE)) {
define symbol MBED_RAM_APP_SIZE = APPLICATION_RAM_SIZE;
}
if (APPLICATION_ADDR != MBED_APP_START) {
error "APPLICATION_ADDR and MBED_APP_START are not the same!!!";
}
if (APPLICATION_SIZE != MBED_APP_SIZE) {
error "APPLICATION_SIZE and MBED_APP_SIZE are not the same!!!";
}
if (APPLICATION_RAM_ADDR != MBED_RAM_APP_START) {
error "APPLICATION_RAM_ADDR and MBED_RAM_APP_START are not the same!!!";
}
if (APPLICATION_RAM_SIZE != MBED_RAM_APP_SIZE) {
error "APPLICATION_RAM_SIZE and MBED_RAM_APP_SIZE are not the same!!!";
}
/* Determine NSC area
*
* Requirements for NSC area:
* 1. Requested by SAU, NSC area must start at 32 byte-aligned boundary.
* 2. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
* 3. Greentea flash IAP uses last 2 sectors for its test. Avoid this range.
* 4. Greentea NVSTORE uses last 2 sectors or 4 KiB x 2 for its test. Avoid this range.
* 5. KVStore uses last a few KiB. Avoid this range.
* 6. Due to TFM build process, TFM and its tests must generate the same cmse_lib.o.
* To this end, TZ NSC location must fix at a well-known location and cannot place
* arbitrarily.
*
* Configurable for NSC area:
* We cannot configure NSC location via configuration parameter because the generated
* configuration macros are just passed to C/C++ files but not to linker files. So
* we can only hardcode NSC location here as constants (to be included by linker file).
*
* Locate NSC area at end of secure flash:
* We decide to locate NSC area at end of secure flash. To avoid this area
* accidentally erased by flash IAP operation, flash IAP must configure to exclude
* this area.
*/
/* TZ NSC area defaults to 4KiB. */
define symbol NU_TZ_NSC_SIZE = 0x1000;
/* TZ NSC area defaults to from secure ROM end */
define symbol NU_TZ_NSC_START = (NU_ROM_START_S + NU_ROM_SIZE_S - NU_TZ_NSC_SIZE);
/* Configuration of flash IAP area */
define symbol NU_FLASHIAP_SECURE_START = NU_ROM_START_S;
/* Exclude NSC area to avoid accidentally erased */
define symbol NU_FLASHIAP_SECURE_SIZE = (NU_ROM_SIZE_S - NU_TZ_NSC_SIZE);
define symbol NU_FLASHIAP_NONSECURE_START = NU_ROM_START_NS;
define symbol NU_FLASHIAP_NONSECURE_SIZE = NU_ROM_SIZE_NS;

196
targets/TARGET_NUVOTON/TARGET_M2351/device/startup_M2351.c
View File

@ -1,27 +1,35 @@
/**************************************************************************//**
* @file startup_M2351.c
* @version V2.00
* $Revision: 9 $
* $Date: 16/08/27 12:33p $
* @brief Startup Source File
/*
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
*
* @note
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
******************************************************************************/
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "M2351.h"
/* Suppress warning messages */
#if defined(__CC_ARM)
// Suppress warning message: extended constant initialiser used
#if defined(__ARMCC_VERSION)
// Suppress warning message: extended constant initializer used
#pragma diag_suppress 1296
#elif defined(__ICCARM__)
// Suppress warning message Pe1665
#pragma diag_suppress=Pe1665
#elif defined(__GNUC__)
#endif
/* Macro Definitions */
#if defined(__CC_ARM)
#if defined(__ARMCC_VERSION)
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias(#f)))
@ -46,22 +54,22 @@ void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS)));
#endif
/* Initialize segments */
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#if defined(__ARMCC_VERSION)
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
extern void __main(void);
#elif defined(__ICCARM__)
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
extern uint32_t CSTACK$$Limit;
void __iar_program_start(void);
#elif defined(__GNUC__)
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
extern uint32_t __StackTop;
extern uint32_t __etext;
extern uint32_t __data_start__;
extern uint32_t __data_end__;
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __copy_table_start__;
extern uint32_t __copy_table_end__;
extern uint32_t __zero_table_start__;
extern uint32_t __zero_table_end__;
extern void uvisor_init(void);
#if defined(TOOLCHAIN_GCC_ARM)
extern void _start(void);
#else
@ -87,7 +95,7 @@ WEAK_ALIAS_FUNC(SysTick_Handler, Default_Handler)
WEAK_ALIAS_FUNC(BOD_IRQHandler, Default_Handler) // 0: Brown Out detection
WEAK_ALIAS_FUNC(IRC_IRQHandler, Default_Handler) // 1: Internal RC
WEAK_ALIAS_FUNC(PWRWU_IRQHandler, Default_Handler) // 2: Power down wake up
WEAK_ALIAS_FUNC(SRAM_IRQHandler, Default_Handler) // 3: SRAM
WEAK_ALIAS_FUNC(SRAM_IRQHandler, Default_Handler) // 3: SRAM
WEAK_ALIAS_FUNC(CLKFAIL_IRQHandler, Default_Handler) // 4: Clock detection fail
// 5: Reserved
WEAK_ALIAS_FUNC(RTC_IRQHandler, Default_Handler) // 6: Real Time Clock
@ -106,16 +114,16 @@ WEAK_ALIAS_FUNC(GPC_IRQHandler, Default_Handler) // 18: GPIO Port C
WEAK_ALIAS_FUNC(GPD_IRQHandler, Default_Handler) // 19: GPIO Port D
WEAK_ALIAS_FUNC(GPE_IRQHandler, Default_Handler) // 20: GPIO Port E
WEAK_ALIAS_FUNC(GPF_IRQHandler, Default_Handler) // 21: GPIO Port F
WEAK_ALIAS_FUNC(QSPI0_IRQHandler, Default_Handler) // 22: SPI0
WEAK_ALIAS_FUNC(QSPI0_IRQHandler, Default_Handler) // 22: SPI0
WEAK_ALIAS_FUNC(SPI0_IRQHandler, Default_Handler) // 23: SPI1
WEAK_ALIAS_FUNC(BRAKE0_IRQHandler, Default_Handler) // 24:
WEAK_ALIAS_FUNC(EPWM0_P0_IRQHandler, Default_Handler) // 25:
WEAK_ALIAS_FUNC(EPWM0_P1_IRQHandler, Default_Handler) // 26:
WEAK_ALIAS_FUNC(EPWM0_P2_IRQHandler, Default_Handler) // 27:
WEAK_ALIAS_FUNC(EPWM0_P0_IRQHandler, Default_Handler) // 25:
WEAK_ALIAS_FUNC(EPWM0_P1_IRQHandler, Default_Handler) // 26:
WEAK_ALIAS_FUNC(EPWM0_P2_IRQHandler, Default_Handler) // 27:
WEAK_ALIAS_FUNC(BRAKE1_IRQHandler, Default_Handler) // 28:
WEAK_ALIAS_FUNC(EPWM1_P0_IRQHandler, Default_Handler) // 29:
WEAK_ALIAS_FUNC(EPWM1_P1_IRQHandler, Default_Handler) // 30:
WEAK_ALIAS_FUNC(EPWM1_P2_IRQHandler, Default_Handler) // 31:
WEAK_ALIAS_FUNC(EPWM1_P0_IRQHandler, Default_Handler) // 29:
WEAK_ALIAS_FUNC(EPWM1_P1_IRQHandler, Default_Handler) // 30:
WEAK_ALIAS_FUNC(EPWM1_P2_IRQHandler, Default_Handler) // 31:
WEAK_ALIAS_FUNC(TMR0_IRQHandler, Default_Handler) // 32: Timer 0
WEAK_ALIAS_FUNC(TMR1_IRQHandler, Default_Handler) // 33: Timer 1
WEAK_ALIAS_FUNC(TMR2_IRQHandler, Default_Handler) // 34: Timer 2
@ -124,7 +132,7 @@ WEAK_ALIAS_FUNC(UART0_IRQHandler, Default_Handler) // 36: UART0
WEAK_ALIAS_FUNC(UART1_IRQHandler, Default_Handler) // 37: UART1
WEAK_ALIAS_FUNC(I2C0_IRQHandler, Default_Handler) // 38: I2C0
WEAK_ALIAS_FUNC(I2C1_IRQHandler, Default_Handler) // 39: I2C1
WEAK_ALIAS_FUNC(PDMA0_IRQHandler, Default_Handler) // 40: Peripheral DMA
WEAK_ALIAS_FUNC(PDMA0_IRQHandler, Default_Handler) // 40: Peripheral DMA
WEAK_ALIAS_FUNC(DAC_IRQHandler, Default_Handler) // 41: DAC
WEAK_ALIAS_FUNC(EADC0_IRQHandler, Default_Handler) // 42: ADC0 interrupt source 0
WEAK_ALIAS_FUNC(EADC1_IRQHandler, Default_Handler) // 43: ADC0 interrupt source 1
@ -177,15 +185,14 @@ WEAK_ALIAS_FUNC(DSRC_IRQHandler, Default_Handler) // 97:
WEAK_ALIAS_FUNC(PDMA1_IRQHandler, Default_Handler) // 98:
WEAK_ALIAS_FUNC(SCU_IRQHandler, Default_Handler) // 99:
// 100: Reserved
WEAK_ALIAS_FUNC(TRNG_IRQHandler, Default_Handler) // 101:
WEAK_ALIAS_FUNC(TRNG_IRQHandler, Default_Handler) // 101:
/* Vector table */
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
__attribute__ ((section("RESET")))
#if defined(__ARMCC_VERSION)
__attribute__ ((section("RESET"), used))
const uint32_t __vector_handlers[] = {
#elif defined(__ICCARM__)
extern uint32_t CSTACK$$Limit;
const uint32_t __vector_table[] @ ".intvec" = {
#elif defined(__GNUC__)
__attribute__ ((section(".vector_table")))
@ -193,10 +200,9 @@ const uint32_t __vector_handlers[] = {
#endif
/* Configure Initial Stack Pointer, using linker-generated symbols */
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#if defined(__ARMCC_VERSION)
(uint32_t) &Image$$ARM_LIB_STACK$$ZI$$Limit,
#elif defined(__ICCARM__)
//(uint32_t) __sfe("CSTACK"),
(uint32_t) &CSTACK$$Limit,
#elif defined(__GNUC__)
(uint32_t) &__StackTop,
@ -323,12 +329,48 @@ const uint32_t __vector_handlers[] = {
(uint32_t) TRNG_IRQHandler, // 101:
};
/**
* \brief This is the code that gets called on processor reset.
/* Some reset handler code cannot implement in pure C. Implement it in inline/embedded assembly.
*
* Reset_Handler:
* For non-secure PSA/non-secure non-PSA/secure non-PSA, jump directly to Reset_Handler_1
* For secure PSA, switch from MSP to PSP, then jump to Reset_Handler_1
*
* Reset_Handler_1:
* Platform initialization
* C/C++ runtime initialization
*/
void Reset_Handler(void)
/* Forward declaration */
void Reset_Handler_1(void);
/* Add '__attribute__((naked))' here to make sure compiler does not generate prologue and
* epilogue sequences for Reset_Handler. We don't want MSP is updated by compiler-generated
* code during stack switch.
*
* Don't allow extended assembly in naked functions:
* The compiler only supports basic __asm statements in __attribute__((naked))
* functions. Using extended assembly, parameter references or mixing C code with
* __asm statements might not work reliably.
*/
__attribute__((naked)) void Reset_Handler(void)
{
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if defined(__GNUC__)
__asm(".syntax unified \n");
#endif
/* Jump to Reset_Handler_1 */
#if !defined(__ICCARM__)
__asm("movw r0, #:lower16:Reset_Handler_1 \n");
__asm("movt r0, #:upper16:Reset_Handler_1 \n");
#else
__asm("mov32 r0, Reset_Handler_1 \n");
#endif
__asm("bx r0 \n");
}
void Reset_Handler_1(void)
{
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Disable register write-protection function */
SYS_UnlockReg();
@ -339,38 +381,61 @@ void Reset_Handler(void)
SYS_LockReg();
#endif
/**
* SystemInit() must be called at the very start.
*/
/* SystemInit() must be called at the very start. */
SystemInit();
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#if defined(__ARMCC_VERSION)
__main();
#elif defined(__ICCARM__)
__iar_program_start();
#elif defined(__GNUC__)
uint32_t *src_ind = (uint32_t *) &__etext;
uint32_t *dst_ind = (uint32_t *) &__data_start__;
uint32_t *dst_end = (uint32_t *) &__data_end__;
/* Move (multiple) .data section(s) from ROM to RAM */
{
/* Struct of copy table entry which must match linker script */
typedef struct copy_table_entry_ {
uint32_t src; // Address to copy from
uint32_t dst; // Address to copy to
uint32_t size; // Copy size in bytes
} copy_table_entry;
/* Move .data section from ROM to RAM */
if (src_ind != dst_ind) {
for (; dst_ind < dst_end;) {
*dst_ind ++ = *src_ind ++;
copy_table_entry *copy_table_ind = (copy_table_entry *) &__copy_table_start__;
copy_table_entry *copy_table_end = (copy_table_entry *) &__copy_table_end__;
for (; copy_table_ind != copy_table_end; copy_table_ind ++) {
uint32_t *src_ind = (uint32_t *) copy_table_ind->src;
uint32_t *src_end = (uint32_t *) (copy_table_ind->src + copy_table_ind->size);
uint32_t *dst_ind = (uint32_t *) copy_table_ind->dst;
if (src_ind != dst_ind) {
for (; src_ind < src_end;) {
*dst_ind ++ = *src_ind ++;
}
}
}
}
/* Initialize .bss section to zero */
dst_ind = (uint32_t *) &__bss_start__;
dst_end = (uint32_t *) &__bss_end__;
if (dst_ind != dst_end) {
for (; dst_ind < dst_end;) {
*dst_ind ++ = 0;
/* Initialize (multiple) .bss sections to zero */
{
/* Struct of zero table entry which must match linker script */
typedef struct zero_table_entry_ {
uint32_t start; // Address to start zero'ing
uint32_t size; // Zero size in bytes
} zero_table_entry;
zero_table_entry *zero_table_ind = (zero_table_entry *) &__zero_table_start__;
zero_table_entry *zero_table_end = (zero_table_entry *) &__zero_table_end__;
for (; zero_table_ind != zero_table_end; zero_table_ind ++) {
uint32_t *dst_ind = (uint32_t *) zero_table_ind->start;
uint32_t *dst_end = (uint32_t *) (zero_table_ind->start + zero_table_ind->size);
for (; dst_ind < dst_end; ) {
*dst_ind ++ = 0;
}
}
}
_start();
#endif
@ -386,18 +451,3 @@ void Default_Handler(void)
{
while (1);
}
#if 0
#if defined(__CC_ARM)
uint32_t GetPC(void)
{
uint32_t val=0;
__asm {
MOV R0, #0 // dumy
//MOV R0, LR // Except R0~R12, SP/LR/PC cannot be read or directly modified in inline assembly code
MOV val, R0
}
return val;
}
#endif
#endif

12
targets/TARGET_NUVOTON/TARGET_M2351/flash_api.c
View File

@ -87,7 +87,7 @@ static const flash_algo_t flash_algo_config = {
/* Secure flash */
static const sector_info_t sectors_info[] = {
{NU_ROM_START_S, 0x800}, // (start, sector size)
{NU_FLASHIAP_SECURE_START, 0x800}, // (start, sector size)
};
/* Secure flash */
@ -95,15 +95,15 @@ static const flash_target_config_t flash_target_config = {
.page_size = 4, // 4 bytes
// Here page_size is program unit, which is different
// than FMC definition.
.flash_start = NU_ROM_START_S,
.flash_size = NU_ROM_SIZE_S,
.flash_start = NU_FLASHIAP_SECURE_START,
.flash_size = NU_FLASHIAP_SECURE_SIZE,
.sectors = sectors_info,
.sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t)
};
/* Non-secure flash */
static const sector_info_t sectors_info_ns[] = {
{NU_ROM_START_NS, 0x800}, // (start, sector size)
{NU_FLASHIAP_NONSECURE_START, 0x800}, // (start, sector size)
};
/* Non-secure flash */
@ -111,8 +111,8 @@ static const flash_target_config_t flash_target_config_ns = {
.page_size = 4, // 4 bytes
// Here page_size is program unit, which is different
// than FMC definition.
.flash_start = NU_ROM_START_NS,
.flash_size = NU_ROM_SIZE_NS,
.flash_start = NU_FLASHIAP_NONSECURE_START,
.flash_size = NU_FLASHIAP_NONSECURE_SIZE,
.sectors = sectors_info_ns,
.sector_info_count = sizeof(sectors_info_ns) / sizeof(sector_info_t)
};

92
targets/TARGET_NUVOTON/TARGET_M2351/rtc_api.c
View File

@ -26,10 +26,13 @@
#include "partition_M2351.h"
#include "hal_secure.h"
/* NOTE: BSP RTC driver judges secure/non-secure RTC by PC. This implementation cannot support non-secure RTC
* controlled by secure executable. A better way would be that secure/non-secure RTC base is passed
* to RTC API as an argument like most other APIs. With BSP RTC driver unchanged, we must enforce
* secure RTC. */
/* Secure attribution of RTC
*
* We need RTC to be secure for security concern.
*
* On M2351, configured to secure
* On M2354, hard-wired to secure
*/
#if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 1))
#error("Limited by BSP/RTC, we can only support secure RTC.")
#endif
@ -67,7 +70,7 @@ void rtc_write(time_t t)
*
* NOTE: This dependents on real hardware.
*/
#define NU_RTCCLK_PER_SEC ((CLK->CLKSEL3 & CLK_CLKSEL3_SC0SEL_Msk) ? __LIRC : __LXT)
#define NU_RTCCLK_PER_SEC (__LXT)
/* Strategy for implementation of RTC HAL
*
@ -121,35 +124,37 @@ static time_t t_write = 0;
/* Convert date time from H/W RTC to struct TM */
static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc);
static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, 0, 0, 0, RTC_IRQn, NULL};
static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, CLK_CLKSEL3_RTCSEL_LXT, 0, 0, RTC_IRQn, NULL};
__NONSECURE_ENTRY
void rtc_init_s(void)
static void rtc_init_impl(void);
static void rtc_free_impl(void);
static int32_t rtc_isenabled_impl(void);
static int64_t rtc_read_impl(void);
static void rtc_write_impl(int64_t t);
static void rtc_init_impl(void)
{
if (rtc_isenabled()) {
if (rtc_isenabled_impl()) {
return;
}
RTC_Open(NULL);
/* POSIX time origin (00:00:00 UTC, Thursday, 1 January 1970) */
rtc_write(0);
rtc_write_impl(0);
}
__NONSECURE_ENTRY
void rtc_free_s(void)
static void rtc_free_impl(void)
{
CLK_DisableModuleClock_S(rtc_modinit.clkidx);
}
__NONSECURE_ENTRY
int32_t rtc_isenabled_s(void)
static int32_t rtc_isenabled_impl(void)
{
// NOTE: To access (RTC) registers, clock must be enabled first.
if (! (CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk)) {
// Enable IP clock
CLK_EnableModuleClock_S(rtc_modinit.clkidx);
}
// To access (RTC) registers, clock must be enabled first.
// For TZ, with RTC being secure, we needn't call the secure gateway versions.
CLK_EnableModuleClock(rtc_modinit.clkidx);
CLK_SetModuleClock(rtc_modinit.clkidx, rtc_modinit.clksrc, rtc_modinit.clkdiv);
RTC_T *rtc_base = (RTC_T *) NU_MODBASE(rtc_modinit.modname);
@ -157,16 +162,15 @@ int32_t rtc_isenabled_s(void)
return !! (rtc_base->INIT & RTC_INIT_ACTIVE_Msk);
}
__NONSECURE_ENTRY
int64_t rtc_read_s(void)
static int64_t rtc_read_impl(void)
{
/* NOTE: After boot, RTC time registers are not synced immediately, about 1 sec latency.
* RTC time got (through RTC_GetDateAndTime()) in this sec would be last-synced and incorrect.
* NUC472/M453: Known issue
* M487: Fixed
*/
if (! rtc_isenabled()) {
rtc_init();
if (! rtc_isenabled_impl()) {
rtc_init_impl();
}
/* Used for intermediary between date time of H/W RTC and POSIX time */
@ -206,11 +210,10 @@ int64_t rtc_read_s(void)
return t_present;
}
__NONSECURE_ENTRY
void rtc_write_s(int64_t t)
static void rtc_write_impl(int64_t t)
{
if (! rtc_isenabled()) {
rtc_init();
if (! rtc_isenabled_impl()) {
rtc_init_impl();
}
t_write = t;
@ -255,4 +258,39 @@ static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC
}
#endif
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__NONSECURE_ENTRY
void rtc_init_s(void)
{
rtc_init_impl();
}
__NONSECURE_ENTRY
void rtc_free_s(void)
{
rtc_free_impl();
}
__NONSECURE_ENTRY
int32_t rtc_isenabled_s(void)
{
return rtc_isenabled_impl();
}
__NONSECURE_ENTRY
int64_t rtc_read_s(void)
{
return rtc_read_impl();
}
__NONSECURE_ENTRY
void rtc_write_s(int64_t t)
{
rtc_write_impl(t);
}
#endif
#endif

2
targets/targets.json
View File

@ -8943,7 +8943,7 @@
"inherits": ["NU_PFM_M2351"],
"core": "Cortex-M23-NS",
"trustzone": true,
"supported_toolchains": ["ARMC6"],
"supported_toolchains": ["ARMC6", "GCC_ARM", "IAR"],
"extra_labels_add": [
"M23_NS",
"NU_PREBUILD_SECURE"