Add FUTURE_SEQUANA_PSA target

* Modify linker scripts to be compatible with bootloader and PSA
* Add memory protection
* Modify original post-build step to allow link with PSA binaries
* Config kvstore for ITS on FUTURE_SEQUANA_PSA
* Enable PSA-Crypto on PSoC6 with NVSeed

features/storage/kvstore/conf/mbed_lib.json

@@ -14,6 +14,9 @@
         "K64F": {
             "storage_type": "TDB_INTERNAL"
         },
+        "FUTURE_SEQUANA_M0_PSA": {
+            "storage_type": "TDB_INTERNAL"
+        },
         "K66F": {
             "storage_type": "TDB_INTERNAL"
         }

features/storage/kvstore/conf/tdb_internal/mbed_lib.json

@@ -9,5 +9,11 @@
             "help": "If default, the base address is set to the first sector after the application code ends.",
             "value": "0"
         }
+    },
+    "target_overrides": {
+        "FUTURE_SEQUANA_M0_PSA": {
+            "internal_size": "0x8000",
+            "internal_base_address": "0x10078000"
+        }
     }
 }

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/cy8c6xx7_cm0plus.sct

@@ -30,6 +30,22 @@
 ;* SPDX-License-Identifier: Apache-2.0
 ;******************************************************************************/
 
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x80000
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x10000
+#endif
+
 ; The defines below describe the location and size of blocks of memory in the target.
 ; Use these defines to specify the memory regions available for allocation.
 
@@ -39,14 +55,14 @@
 ; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
 ; RAM
 ; RAM
-#define RAM_START               0x08000000
+#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                0x00010000
+#define RAM_SIZE                MBED_RAM_SIZE
 ; Flash
 ; Flash
-#define FLASH_START             0x10000000
+#define FLASH_START             MBED_ROM_START
-#define FLASH_SIZE              0x00078000
+#define FLASH_SIZE              MBED_ROM_SIZE
 
-; The following defines describe a 32K flash region used for EEPROM emulation. 
+; The following defines describe a 32K flash region used for EEPROM emulation.
 ; This region can also be used as the general purpose flash.
 ; You can assign sections to this memory region for only one of the cores.
 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
@@ -84,7 +100,7 @@
 #define EFUSE_SIZE              0x100000
 
 
-LR_IROM1 FLASH_START FLASH_SIZE
+LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
 {
     .cy_app_header +0
     {

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld

@@ -28,6 +28,21 @@ SEARCH_DIR(.)
 GROUP(-lgcc -lc -lnosys)
 ENTRY(Reset_Handler)
 
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x80000
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x10000
+#endif
 
 /* Force symbol to be entered in the output file as an undefined symbol. Doing
 * this may, for example, trigger linking of additional modules from standard
@@ -47,8 +62,8 @@ MEMORY
      * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld',
      * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'.
      */
-    ram               (rwx)   : ORIGIN = 0x08000000, LENGTH = 0x10000
+    ram               (rwx)   : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
-    flash             (rx)    : ORIGIN = 0x10000000, LENGTH = 0x78000
+    flash             (rx)    : ORIGIN = MBED_ROM_START, LENGTH = (MBED_ROM_SIZE - 0x8000)
 
     /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
      * You can assign sections to this memory region for only one of the cores.
@@ -333,7 +348,7 @@ SECTIONS
         KEEP(*(.cy_toc_part2))
     } > sflash_toc_2
 
-    
+
     /* Supervisory Flash: Table of Content # 2 Copy */
     .cy_rtoc_part2 :
     {

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf

@@ -29,6 +29,22 @@
 /*-Specials-*/
 define symbol __ICFEDIT_intvec_start__ = 0x00000000;
 
+if (!isdefinedsymbol(MBED_ROM_START)) {
+  define symbol MBED_ROM_START = 0x10000000;
+}
+
+if (!isdefinedsymbol(MBED_ROM_SIZE)) {
+  define symbol MBED_ROM_SIZE = 0x80000;
+}
+
+if (!isdefinedsymbol(MBED_RAM_START)) {
+  define symbol MBED_RAM_START = 0x08000000;
+}
+
+if (!isdefinedsymbol(MBED_RAM_SIZE)) {
+  define symbol MBED_RAM_SIZE = 0x10000;
+}
+
 /* The symbols below define the location and size of blocks of memory in the target.
  * Use these symbols to specify the memory regions available for allocation.
  */
@@ -39,11 +55,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000;
  * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
  */
 /* RAM */
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
+define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
-define symbol __ICFEDIT_region_IRAM1_end__   = 0x08010000;
+define symbol __ICFEDIT_region_IRAM1_end__   = (MBED_RAM_START + MBED_RAM_SIZE);
 /* Flash */
-define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+define symbol __ICFEDIT_region_IROM1_start__ = MBED_ROM_START;
-define symbol __ICFEDIT_region_IROM1_end__   = 0x10078000;
+define symbol __ICFEDIT_region_IROM1_end__   = (MBED_ROM_START + MBED_ROM_SIZE - 0x8000);
 
 /* The following symbols define a 32K flash region used for EEPROM emulation.
  * This region can also be used as the general purpose flash.

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/system_psoc63_cm0plus.c

@@ -153,6 +153,9 @@ void mbed_sdk_init(void)
     ipcrpc_init();
 }
 
+#if defined(COMPONENT_SPM_MAILBOX)
+void mailbox_init(void);
+#endif
 
 /*******************************************************************************
 * Function Name: SystemInit
@@ -189,6 +192,10 @@ void SystemInit(void)
     Cy_SystemInit();
     SystemCoreClockUpdate();
 
+#if defined(COMPONENT_SPM_MAILBOX)
+    mailbox_init();
+#endif
+
 #if defined(CY_DEVICE_PSOC6ABLE2)
     #if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
         /* Allocate and initialize semaphores for the system operations. */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_ARM_STD/cy8c6xx7_cm4_dual.sct

@@ -30,6 +30,22 @@
 ;* SPDX-License-Identifier: Apache-2.0
 ;******************************************************************************/
 
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10080000
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x78000
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08010000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x37800
+#endif
+
 ; The defines below describe the location and size of blocks of memory in the target.
 ; Use these defines to specify the memory regions available for allocation.
 
@@ -41,12 +57,12 @@
 ; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
 ; RAM
 ; RAM
-#define RAM_START               0x08010000
+#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                0x00037800
+#define RAM_SIZE                MBED_RAM_SIZE
 ; Flash
 ; Flash
-#define FLASH_START             0x10080000
+#define FLASH_START             MBED_ROM_START
-#define FLASH_SIZE              0x00078000
+#define FLASH_SIZE              MBED_ROM_SIZE
 
 ; The following defines describe a 32K flash region used for EEPROM emulation.
 ; This region can also be used as the general purpose flash.

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld

@@ -28,6 +28,21 @@ SEARCH_DIR(.)
 GROUP(-lgcc -lc -lnosys)
 ENTRY(Reset_Handler)
 
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10080000
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x78000
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08010000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x37800
+#endif
 
 /* Force symbol to be entered in the output file as an undefined symbol. Doing
 * this may, for example, trigger linking of additional modules from standard
@@ -49,8 +64,8 @@ MEMORY
      * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
      * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
      */
-    ram               (rwx)   : ORIGIN = 0x08010000, LENGTH = 0x37800
+    ram               (rwx)   : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
-    flash             (rx)    : ORIGIN = 0x10080000, LENGTH = 0x78000
+    flash             (rx)    : ORIGIN = MBED_ROM_START, LENGTH = MBED_ROM_SIZE
 
     /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
      * You can assign sections to this memory region for only one of the cores.
@@ -339,7 +354,7 @@ SECTIONS
         KEEP(*(.cy_toc_part2))
     } > sflash_toc_2
 
-    
+
     /* Supervisory Flash: Table of Content # 2 Copy */
     .cy_rtoc_part2 :
     {

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf

@@ -29,6 +29,22 @@
 /*-Specials-*/
 define symbol __ICFEDIT_intvec_start__ = 0x00000000;
 
+if (!isdefinedsymbol(MBED_ROM_START)) {
+  define symbol MBED_ROM_START = 0x10080000;
+}
+
+if (!isdefinedsymbol(MBED_ROM_SIZE)) {
+  define symbol MBED_ROM_SIZE = 0x78000;
+}
+
+if (!isdefinedsymbol(MBED_RAM_START)) {
+  define symbol MBED_RAM_START = 0x08010000;
+}
+
+if (!isdefinedsymbol(MBED_RAM_SIZE)) {
+  define symbol MBED_RAM_SIZE = 0x37800;
+}
+
 /* The symbols below define the location and size of blocks of memory in the target.
  * Use these symbols to specify the memory regions available for allocation.
  */
@@ -41,11 +57,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000;
  * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
  */
 /* RAM */
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x08010000;
+define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
-define symbol __ICFEDIT_region_IRAM1_end__   = 0x08047800;
+define symbol __ICFEDIT_region_IRAM1_end__   = (MBED_RAM_START + MBED_RAM_SIZE);
 /* Flash */
-define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000;
+define symbol __ICFEDIT_region_IROM1_start__ = MBED_ROM_START;
-define symbol __ICFEDIT_region_IROM1_end__   = 0x100F8000;
+define symbol __ICFEDIT_region_IROM1_end__   = (MBED_ROM_START + MBED_ROM_SIZE);
 
 /* The following symbols define a 32K flash region used for EEPROM emulation. 
  * This region can also be used as the general purpose flash.

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/system_psoc63_cm4.c

@@ -124,6 +124,9 @@ uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
     #define CY_ROOT_PATH_SRC_DSI_MUX_PILO   (19UL)
 #endif /* (SRSS_PILO_PRESENT == 1U) */
 
+#if defined(COMPONENT_SPM_MAILBOX)
+void mailbox_init(void);
+#endif
 
 /*******************************************************************************
 * Function Name: SystemInit
@@ -161,6 +164,10 @@ void SystemInit(void)
 
     Cy_SystemInit();
     SystemCoreClockUpdate();
+
+#if defined(COMPONENT_SPM_MAILBOX)
+    mailbox_init();
+#endif
 }
 
 

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA_M0_PSA/cyprotection.h

@@ -0,0 +1,189 @@
+/***************************************************************************//**
+* \file cyprotection.h
+* \version 1.0
+*
+* \brief
+*  This is the header file for the protection configuration structures
+*  and functions.
+*
+********************************************************************************
+* \copyright
+*
+* <EFBFBD> 2018, Cypress Semiconductor Corporation
+* or a subsidiary of Cypress Semiconductor Corporation. All rights
+* reserved.
+*
+* This software, including source code, documentation and related
+* materials (<EFBFBD>Software<EFBFBD>), is owned by Cypress Semiconductor
+* Corporation or one of its subsidiaries (<EFBFBD>Cypress<EFBFBD>) and is protected by
+* and subject to worldwide patent protection (United States and foreign),
+* United States copyright laws and international treaty provisions.
+* Therefore, you may use this Software only as provided in the license
+* agreement accompanying the software package from which you
+* obtained this Software (<EFBFBD>EULA<EFBFBD>).
+*
+* If no EULA applies, Cypress hereby grants you a personal, non-
+* exclusive, non-transferable license to copy, modify, and compile the
+* Software source code solely for use in connection with Cypress<EFBFBD>s
+* integrated circuit products. Any reproduction, modification, translation,
+* compilation, or representation of this Software except as specified
+* above is prohibited without the express written permission of Cypress.
+*
+* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO
+* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING,
+* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+* PARTICULAR PURPOSE. Cypress reserves the right to make
+* changes to the Software without notice. Cypress does not assume any
+* liability arising out of the application or use of the Software or any
+* product or circuit described in the Software. Cypress does not
+* authorize its products for use in any products where a malfunction or
+* failure of the Cypress product may reasonably be expected to result in
+* significant property damage, injury or death (<EFBFBD>High Risk Product<EFBFBD>). By
+* including Cypress<EFBFBD>s product in a High Risk Product, the manufacturer
+* of such system or application assumes all risk of such use and in doing
+* so agrees to indemnify Cypress against all liability.
+*
+******************************************************************************/
+
+#ifndef _CYPROTECTION_H_
+#define _CYPROTECTION_H_
+
+#include "cy_prot.h"
+
+#define MPU_SMPU_SUBREGIONS_NUMB (8u)
+/* MPU is not used yet */
+#define CPUSS_PROT_MPU_STRUCT_NR (0u)
+
+#define CPUSS_PROT_PPU_GR_STRUCT_NR (16u)
+#define CPUSS_PROT_PPU_PROG_STRUCT_NR (16u)
+#define CPUSS_PROT_PPU_FX_SL_STRUCT_NR (16u)
+#define CPUSS_PROT_PPU_FX_RG_STRUCT_NR (29u)
+
+#define CPUSS_PROT_PPU_FX_RG_START_ADDR (0x40201000UL)
+
+#define PRIVILEGED_MODE (1u)
+#define UNPRIVILEGED_MODE (0u)
+#define NONSECURE_MODE (1u)
+#define SECURE_MODE (0u)
+
+/* PPU Group existing bitmask - 11001011111 */
+#define PERI_PPU_GR_MMIO_EXIST_BITMASK 0x65F
+/* PPU MMIO1 Group Fixed Region existing bitmask - 10 */
+#define PERI_PPU_GR_MMIO1_EXIST_BITMASK 0x2
+/* PPU MMIO2 Group Fixed Region existing bitmask - 11001111111111 */
+#define PERI_PPU_GR_MMIO2_EXIST_BITMASK 0x33FF
+/* PPU MMIO3 Group Fixed Region existing bitmask - 1111101111111 */
+#define PERI_PPU_GR_MMIO3_EXIST_BITMASK 0x1F7F
+/* PPU MMIO4 Group Fixed Region existing bitmask - 101 */
+#define PERI_PPU_GR_MMIO4_EXIST_BITMASK 0x5
+/* PPU MMIO6 Group Fixed Region existing bitmask - 1111111111 */
+#define PERI_PPU_GR_MMIO6_EXIST_BITMASK 0x3FF
+/* PPU MMIO9 Group Fixed Region existing bitmask - 11 */
+#define PERI_PPU_GR_MMIO9_EXIST_BITMASK 0x3
+/* PPU MMIO10 Group Fixed Region existing bitmask - 111 */
+#define PERI_PPU_GR_MMIO10_EXIST_BITMASK 0x7
+
+
+/* TODO: There is no SWPU configuration part */
+typedef struct {
+    uint32_t*         address;          /**< Base address of the memory region (Only applicable to slave) */
+    cy_en_prot_size_t regionSize;       /**< Size of the memory region (Only applicable to slave) */
+    uint8_t           subregions;       /**< Mask of the 8 subregions to disable (Only applicable to slave) */
+    cy_en_prot_perm_t userPermission;   /**< User permissions for the region */
+    cy_en_prot_perm_t privPermission;   /**< Privileged permissions for the region */
+    bool              secure;           /**< Non Secure = 0, Secure = 1 */
+    bool              pcMatch;          /**< Access evaluation = 0, Matching = 1  */
+    uint16_t          pcMask;           /**< Mask of allowed protection context(s) */
+    PROT_SMPU_SMPU_STRUCT_Type* prot_region; /* protection region */
+    cy_en_prot_perm_t userMstPermission;   /**< User permissions for the region */
+    cy_en_prot_perm_t privMstPermission;   /**< Privileged permissions for the region */
+} cy_smpu_region_config_t;
+
+/*
+* See Cy_Prot_ConfigBusMaster function description for parameters meaning
+*
+* act_pcMask specifies active PC for Cy_Prot_SetActivePC function
+*/
+typedef struct {
+    en_prot_master_t busMaster;
+    bool privileged;
+    bool secure;
+    uint32_t pcMask;
+    uint32_t act_pc;
+} cy_bus_master_config_t;
+
+/** Configuration structure for Fixed Group (GR) PPU (PPU_GR) struct initialization */
+typedef struct
+{
+    cy_en_prot_perm_t   userPermission;   /**< User permissions for the region */
+    cy_en_prot_perm_t   privPermission;   /**< Privileged permissions for the region */
+    bool                secure;           /**< Non Secure = 0, Secure = 1 */
+    bool                pcMatch;          /**< Access evaluation = 0, Matching = 1  */
+    uint16_t            pcMask;           /**< Mask of allowed protection context(s) */
+    cy_en_prot_perm_t   userMstPermission;   /**< Master User permissions for the region */
+    cy_en_prot_perm_t   privMstPermission;   /**< Master Privileged permissions for the region */
+    bool                secureMst;           /**< Non Secure = 0, Secure = 1 Master */
+    uint16_t            pcMstMask;           /**< Master Mask of allowed protection context(s) */
+    PERI_PPU_GR_Type    *pPpuStr;           /**< Ppu structure address */
+} cy_ppu_fixed_gr_cfg_t;
+/** Configuration structure for Fixed Region (RG) PPU (PPU_RG) struct initialization */
+typedef struct
+{
+    cy_en_prot_perm_t   userPermission;   /**< User permissions for the region */
+    cy_en_prot_perm_t   privPermission;   /**< Privileged permissions for the region */
+    bool                secure;           /**< Non Secure = 0, Secure = 1 */
+    bool                pcMatch;          /**< Access evaluation = 0, Matching = 1  */
+    uint16_t            pcMask;           /**< Mask of allowed protection context(s) */
+    cy_en_prot_perm_t   userMstPermission;   /**< Master User permissions for the region */
+    cy_en_prot_perm_t   privMstPermission;   /**< Master Privileged permissions for the region */
+    bool                secureMst;           /**< Non Secure = 0, Secure = 1 Master */
+    uint16_t            pcMstMask;           /**< Master Mask of allowed protection context(s) */
+    PERI_GR_PPU_RG_Type *pPpuStr;           /**< Ppu structure address */
+} cy_ppu_fixed_rg_cfg_t;
+/** Configuration structure for Fixed Slave (SL) PPU (PPU_SL) struct initialization */
+typedef struct
+{
+    cy_en_prot_perm_t   userPermission;   /**< User permissions for the region */
+    cy_en_prot_perm_t   privPermission;   /**< Privileged permissions for the region */
+    bool                secure;           /**< Non Secure = 0, Secure = 1 */
+    bool                pcMatch;          /**< Access evaluation = 0, Matching = 1  */
+    uint16_t            pcMask;           /**< Mask of allowed protection context(s) */
+    cy_en_prot_perm_t   userMstPermission;   /**< Master User permissions for the region */
+    cy_en_prot_perm_t   privMstPermission;   /**< Master Privileged permissions for the region */
+    bool                secureMst;           /**< Non Secure = 0, Secure = 1 Master */
+    uint16_t            pcMstMask;           /**< Master Mask of allowed protection context(s) */
+    PERI_GR_PPU_SL_Type *pPpuStr;           /**< Ppu structure address */
+} cy_ppu_fixed_sl_cfg_t;
+
+/** Configuration structure for Programmable (PROG) PPU (PPU_PR) struct initialization */
+typedef struct
+{
+    uint32_t*         address;          /**< Base address of the memory region (Only applicable to slave) */
+    cy_en_prot_size_t regionSize;       /**< Size of the memory region (Only applicable to slave) */
+    uint8_t           subregions;       /**< Mask of the 8 subregions to disable (Only applicable to slave) */
+    cy_en_prot_perm_t userPermission;   /**< User permissions for the region */
+    cy_en_prot_perm_t privPermission;   /**< Privileged permissions for the region */
+    bool              secure;           /**< Non Secure = 0, Secure = 1 */
+    bool              pcMatch;          /**< Access evaluation = 0, Matching = 1  */
+    uint16_t          pcMask;           /**< Mask of allowed protection context(s) */
+    cy_en_prot_perm_t userMstPermission;   /**< Master User permissions for the region */
+    cy_en_prot_perm_t privMstPermission;   /**< Master Privileged permissions for the region */
+    bool              secureMst;           /**< Non Secure = 0, Secure = 1 Master */
+    uint16_t          pcMstMask;           /**< Master Mask of allowed protection context(s) */
+    PERI_PPU_PR_Type              *pPpuStr;           /**< Ppu structure address */
+} cy_ppu_prog_cfg_t;
+
+cy_en_prot_status_t smpu_protect(cy_smpu_region_config_t smpu_config_arr[], uint32_t arr_length);
+cy_en_prot_status_t ppu_fixed_rg_protect(cy_ppu_fixed_rg_cfg_t ppu_config_arr[], uint32_t arr_length);
+cy_en_prot_status_t ppu_fixed_sl_protect(cy_ppu_fixed_sl_cfg_t ppu_config_arr[], uint32_t arr_length);
+cy_en_prot_status_t ppu_prog_protect(cy_ppu_prog_cfg_t ppu_config_arr[], uint32_t arr_length);
+cy_en_prot_status_t ppu_fixed_gr_protect(cy_ppu_fixed_gr_cfg_t ppu_config_arr[], uint32_t arr_length);
+cy_en_prot_status_t bus_masters_protect(cy_bus_master_config_t bus_masters_config_arr[], uint32_t arr_length);
+
+uint8_t isPeriferalAccessAllowed(uint32_t perStartAddr, uint32_t perSize,
+    uint8_t privModeFlag, uint8_t nsecureFlag, enum cy_en_prot_pc_t protectionCtx, cy_en_prot_perm_t accessType);
+uint8_t isMemoryAccessAllowed(uint32_t memStartAddr, uint32_t memSize,
+    uint8_t privModeFlag, uint8_t nsecureFlag, enum cy_en_prot_pc_t protectionCtx, cy_en_prot_perm_t accessType);
+
+#endif /* _CYPROTECTION_H_ */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA_M0_PSA/spm_hal_api.c

@@ -0,0 +1,78 @@
+/* Copyright (c) 2017-2018 ARM Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+/* -------------------------------------- Includes ----------------------------------- */
+
+#include "cy_sysint.h"
+#include "spm_internal.h"
+
+#ifdef PU_ENABLE
+#include "cyprotection_config.h"
+#endif // PU_ENABLE
+
+
+/* -------------------------------------- HAL API ------------------------------------ */
+
+// These implementations are meant to be used only for SPM running on PSoC6 M0+ core.
+
+void spm_hal_start_nspe(void)
+{
+    Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR);
+}
+
+void spm_hal_memory_protection_init(void)
+{
+#ifdef PU_ENABLE
+    cy_en_prot_status_t status;
+
+    /* smpu */
+    status = smpu_protect((cy_smpu_region_config_t *)flash_spm_smpu_config, sizeof(flash_spm_smpu_config) / sizeof(flash_spm_smpu_config[0]));
+    CY_ASSERT(status == CY_PROT_SUCCESS);  // TODO: Panic instead
+    status = smpu_protect((cy_smpu_region_config_t *)sram_spm_smpu_config, sizeof(sram_spm_smpu_config) / sizeof(sram_spm_smpu_config[0]));
+    CY_ASSERT(status == CY_PROT_SUCCESS);  // TODO: Panic instead
+
+    /* fixed region ppu */
+    status = ppu_fixed_rg_protect((cy_ppu_fixed_rg_cfg_t *)fixed_rg_pc0_ppu_config, sizeof(fixed_rg_pc0_ppu_config) / sizeof(fixed_rg_pc0_ppu_config[0]));
+    CY_ASSERT(status == CY_PROT_SUCCESS);  // TODO: Panic instead
+    status = ppu_fixed_rg_protect((cy_ppu_fixed_rg_cfg_t *)fixed_rg_spm_ppu_config, sizeof(fixed_rg_spm_ppu_config) / sizeof(fixed_rg_spm_ppu_config[0]));
+    CY_ASSERT(status == CY_PROT_SUCCESS);  // TODO: Panic instead
+    status = ppu_fixed_rg_protect((cy_ppu_fixed_rg_cfg_t *)fixed_rg_any_ppu_config, sizeof(fixed_rg_any_ppu_config) / sizeof(fixed_rg_any_ppu_config[0]));
+    CY_ASSERT(status == CY_PROT_SUCCESS);  // TODO: Panic instead
+    /* fixed slave ppu */
+    status = ppu_fixed_sl_protect((cy_ppu_fixed_sl_cfg_t *)fixed_sl_pc0_ppu_config, sizeof(fixed_sl_pc0_ppu_config) / sizeof(fixed_sl_pc0_ppu_config[0]));
+    CY_ASSERT(status == CY_PROT_SUCCESS);  // TODO: Panic instead
+    status = ppu_fixed_sl_protect((cy_ppu_fixed_sl_cfg_t *)fixed_sl_spm_ppu_config, sizeof(fixed_sl_spm_ppu_config) / sizeof(fixed_sl_spm_ppu_config[0]));
+    CY_ASSERT(status == CY_PROT_SUCCESS);  // TODO: Panic instead
+    status = ppu_fixed_sl_protect((cy_ppu_fixed_sl_cfg_t *)fixed_sl_any_ppu_config, sizeof(fixed_sl_any_ppu_config) / sizeof(fixed_sl_any_ppu_config[0]));
+    CY_ASSERT(status == CY_PROT_SUCCESS);  // TODO: Panic instead
+    /* programmable ppu */
+    status = ppu_prog_protect((cy_ppu_prog_cfg_t *)prog_pc0_ppu_config, sizeof(prog_pc0_ppu_config) / sizeof(prog_pc0_ppu_config[0]));
+    CY_ASSERT(status == CY_PROT_SUCCESS);  // TODO: Panic instead
+    status = ppu_prog_protect((cy_ppu_prog_cfg_t *)prog_spm_ppu_config, sizeof(prog_spm_ppu_config) / sizeof(prog_spm_ppu_config[0]));
+    CY_ASSERT(status == CY_PROT_SUCCESS);  // TODO: Panic instead
+    /* fixed group ppu */
+    status = ppu_fixed_gr_protect((cy_ppu_fixed_gr_cfg_t *)fixed_gr_pc0_ppu_config, sizeof(fixed_gr_pc0_ppu_config) / sizeof(fixed_gr_pc0_ppu_config[0]));
+    CY_ASSERT(status == CY_PROT_SUCCESS);  // TODO: Panic instead
+    status = ppu_fixed_gr_protect((cy_ppu_fixed_gr_cfg_t *)fixed_gr_spm_ppu_config, sizeof(fixed_gr_spm_ppu_config) / sizeof(fixed_gr_spm_ppu_config[0]));
+    CY_ASSERT(status == CY_PROT_SUCCESS);  // TODO: Panic instead
+
+    /* bus masters */
+    status = bus_masters_protect((cy_bus_master_config_t *)bus_masters_config, sizeof(bus_masters_config) / sizeof(bus_masters_config[0]));
+    CY_ASSERT(status == CY_PROT_SUCCESS);  // TODO: Panic instead
+#endif // PU_ENABLE
+}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA_M0_PSA/spm_init_api.c

@@ -0,0 +1,94 @@
+/* Copyright (c) 2017-2018 ARM Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+/* -------------------------------------- Includes ----------------------------------- */
+
+#include "spm_api.h"
+
+#include "cmsis.h"
+#include "cyip_ipc.h"
+#include "cy_ipc_drv.h"
+#include "cy_syslib.h"
+#include "cy_sysint.h"
+
+
+
+/* ------------------------------------ Definitions ---------------------------------- */
+
+#define SPM_IPC_CHANNEL 8u
+#define SPM_IPC_NOTIFY_CM0P_INTR    (CY_IPC_INTR_SPARE + 2) // CM4 to CM0+ notify interrupt number
+#define SPM_IPC_NOTIFY_CM4_INTR     (CY_IPC_INTR_SPARE + 1) // CM0+ to CM4 notify interrupt number
+
+
+
+/* ---------------------------------- Static Globals --------------------------------- */
+
+static IPC_STRUCT_Type      *ipc_channel_handle;
+static IPC_INTR_STRUCT_Type *ipc_interrupt_ptr;
+
+
+
+/* ------------------------ Platform's Functions Implementation ---------------------- */
+
+void ipc_interrupt_handler(void)
+{
+    // Call ARM's interrupt handler
+    spm_mailbox_irq_callback();
+
+    // Clear the interrupt and make a dummy read to avoid double interrupt occurrence:
+    // - The double interrupt’s triggering is caused by buffered write operations on bus
+    // - The dummy read of the status register is indeed required to make sure previous write completed before leaving ISR
+    // Note: This is a direct clear using the IPC interrupt register and not clear of an NVIC register
+    Cy_IPC_Drv_ClearInterrupt(ipc_interrupt_ptr, CY_IPC_NO_NOTIFICATION, (1uL << SPM_IPC_CHANNEL));
+}
+
+void mailbox_init(void)
+{
+    // Interrupts configuration for CM0+
+    // * See ce216795_common.h for occupied interrupts
+    // -----------------------------------------------
+
+    // Configure interrupts ISR / MUX and priority
+    cy_stc_sysint_t ipc_intr_Config;
+    ipc_intr_Config.intrSrc = (IRQn_Type)NvicMux3_IRQn; // Can be any Mux we choose
+    ipc_intr_Config.cm0pSrc = (cy_en_intr_t)cpuss_interrupts_ipc_0_IRQn + SPM_IPC_NOTIFY_CM0P_INTR;    // Must match the interrupt we trigger using NOTIFY on CM4
+    ipc_intr_Config.intrPriority = 1;
+    (void)Cy_SysInt_Init(&ipc_intr_Config, ipc_interrupt_handler);
+
+    // Set specific NOTIFY interrupt mask only.
+    // Only the interrupt sources with their masks enabled can trigger the interrupt.
+    ipc_interrupt_ptr = Cy_IPC_Drv_GetIntrBaseAddr(SPM_IPC_NOTIFY_CM0P_INTR);
+    CY_ASSERT(ipc_interrupt_ptr != NULL);
+    Cy_IPC_Drv_SetInterruptMask(ipc_interrupt_ptr, 0x0, 1 << SPM_IPC_CHANNEL);
+
+    // Enable the interrupt
+    NVIC_EnableIRQ(ipc_intr_Config.intrSrc);
+
+    ipc_channel_handle = Cy_IPC_Drv_GetIpcBaseAddress(SPM_IPC_CHANNEL);
+    CY_ASSERT(ipc_channel_handle != NULL);
+}
+
+
+
+/* -------------------------------------- HAL API ------------------------------------ */
+
+void spm_hal_mailbox_notify(void)
+{
+    CY_ASSERT(ipc_channel_handle != NULL);
+    Cy_IPC_Drv_AcquireNotify(ipc_channel_handle, (1uL << SPM_IPC_NOTIFY_CM4_INTR));
+}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA_PSA/spm_init_api.c

@@ -0,0 +1,93 @@
+/* Copyright (c) 2017-2018 ARM Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+/* -------------------------------------- Includes ----------------------------------- */
+
+#include "spm_api.h"
+
+#include "cmsis.h"
+#include "cyip_ipc.h"
+#include "cy_ipc_drv.h"
+#include "cy_syslib.h"
+#include "cy_sysint.h"
+
+
+
+/* ------------------------------------ Definitions ---------------------------------- */
+
+#define SPM_IPC_CHANNEL 8u
+#define SPM_IPC_NOTIFY_CM0P_INTR    (CY_IPC_INTR_SPARE + 2) // CM4 to CM0+ notify interrupt number
+#define SPM_IPC_NOTIFY_CM4_INTR     (CY_IPC_INTR_SPARE + 1) // CM0+ to CM4 notify interrupt number
+
+
+
+/* ---------------------------------- Static Globals --------------------------------- */
+
+static IPC_STRUCT_Type      *ipc_channel_handle;
+static IPC_INTR_STRUCT_Type *ipc_interrupt_ptr;
+
+
+
+/* ------------------------ Platform's Functions Implementation ---------------------- */
+
+void ipc_interrupt_handler(void)
+{
+    // Call ARM's interrupt handler
+    spm_mailbox_irq_callback();
+
+    // Clear the interrupt and make a dummy read to avoid double interrupt occurrence:
+    // - The double interrupt’s triggering is caused by buffered write operations on bus
+    // - The dummy read of the status register is indeed required to make sure previous write completed before leaving ISR
+    // Note: This is a direct clear using the IPC interrupt register and not clear of an NVIC register
+    Cy_IPC_Drv_ClearInterrupt(ipc_interrupt_ptr, CY_IPC_NO_NOTIFICATION, (1uL << SPM_IPC_CHANNEL));
+}
+
+void mailbox_init(void)
+{
+    // Interrupts configuration for CM4
+    // * See ce216795_common.h for occupied interrupts
+    // -----------------------------------------------
+
+    // Configure interrupts ISR / MUX and priority
+    cy_stc_sysint_t ipc_intr_Config;
+    ipc_intr_Config.intrSrc = (IRQn_Type)cpuss_interrupts_ipc_0_IRQn + SPM_IPC_NOTIFY_CM4_INTR;
+    ipc_intr_Config.intrPriority = 1;
+    (void)Cy_SysInt_Init(&ipc_intr_Config, ipc_interrupt_handler);
+
+    // Set specific NOTIFY interrupt mask only.
+    // Only the interrupt sources with their masks enabled can trigger the interrupt.
+    ipc_interrupt_ptr = Cy_IPC_Drv_GetIntrBaseAddr(SPM_IPC_NOTIFY_CM4_INTR);
+    CY_ASSERT(ipc_interrupt_ptr != NULL);
+    Cy_IPC_Drv_SetInterruptMask(ipc_interrupt_ptr, 0x0, 1 << SPM_IPC_CHANNEL);
+
+    // Enable the interrupt
+    NVIC_EnableIRQ(ipc_intr_Config.intrSrc);
+
+    ipc_channel_handle = Cy_IPC_Drv_GetIpcBaseAddress(SPM_IPC_CHANNEL);
+    CY_ASSERT(ipc_channel_handle != NULL);
+}
+
+
+
+/* -------------------------------------- HAL API ------------------------------------ */
+
+void spm_hal_mailbox_notify(void)
+{
+    CY_ASSERT(ipc_channel_handle != NULL);
+    Cy_IPC_Drv_AcquireNotify(ipc_channel_handle, (1uL << SPM_IPC_NOTIFY_CM0P_INTR));
+}

targets/TARGET_Cypress/TARGET_PSOC6/psoc6_utils.c

@@ -100,6 +100,7 @@ do {                                                            \
 #define SRM_TCPWM(num)                     {(num), (0)}
 
 #define DEFAULT_PORT_RES        0xff
+#define DEFAULT_DIVIDER8_RES    0xff
 #define DEFAULT_DIVIDER_RES     0xffff
 #define DEFAULT_SCM_RES         1
 #define DEFAULT_TCPWM_RES       1

targets/targets.json

@@ -7658,6 +7658,52 @@
             }
         }
     },
+    "FUTURE_SEQUANA_M0_PSA": {
+        "inherits": ["SPE_Target", "FUTURE_SEQUANA_M0"],
+        "components_add": ["SPM_MAILBOX", "FLASHIAP"],
+        "extra_labels_add": ["PSA"],
+        "macros_add": [
+            "PSOC6_DYNSRM_DISABLE=1",
+            "MBEDTLS_PSA_CRYPTO_SPM",
+            "MBEDTLS_PSA_CRYPTO_C",
+            "MBEDTLS_ENTROPY_NV_SEED",
+            "MBEDTLS_PLATFORM_NV_SEED_READ_MACRO=mbed_default_seed_read",
+            "MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO=mbed_default_seed_write"
+        ],
+        "deliver_to_target": "FUTURE_SEQUANA_PSA",
+        "overrides": {
+            "secure-rom-start": "0x10000000",
+            "secure-rom-size": "0x80000",
+            "non-secure-rom-start": "0x10080000",
+            "non-secure-rom-size": "0x78000",
+            "secure-ram-start": "0x08000000",
+            "secure-ram-size": "0x10000",
+            "non-secure-ram-start": "0x08010000",
+            "non-secure-ram-size": "0x37700",
+            "shared-ram-start": "0x08047700",
+            "shared-ram-size": "0x100"
+        }
+    },
+    "FUTURE_SEQUANA_PSA": {
+        "inherits": ["NSPE_Target", "FUTURE_SEQUANA"],
+        "sub_target": "FUTURE_SEQUANA_M0_PSA",
+        "extra_labels_add": ["PSA"],
+        "extra_labels_remove": ["CORDIO"],
+        "components_add": ["SPM_MAILBOX"],
+        "macros_add": ["PSOC6_DYNSRM_DISABLE=1", "MBEDTLS_PSA_CRYPTO_C"],
+        "overrides": {
+            "secure-rom-start": "0x10000000",
+            "secure-rom-size": "0x80000",
+            "non-secure-rom-start": "0x10080000",
+            "non-secure-rom-size": "0x78000",
+            "secure-ram-start": "0x08000000",
+            "secure-ram-size": "0x10000",
+            "non-secure-ram-start": "0x08010000",
+            "non-secure-ram-size": "0x37700",
+            "shared-ram-start": "0x08047700",
+            "shared-ram-size": "0x100"
+        }
+    },
     "TMPM3HQ": {
         "inherits": ["Target"],
         "core": "Cortex-M3",

tools/targets/PSOC6.py

@@ -98,7 +98,10 @@ def find_cm0_image(toolchain, resources, elf, hexf):
     # Locate user-specified image
     from tools.resources import FileType
     hex_files = resources.get_file_paths(FileType.HEX)
-    m0hexf = next((f for f in hex_files if os.path.basename(f) == toolchain.target.m0_core_img), None)
+    if toolchain.target.name.endswith('_PSA'):
+        m0hexf = next((f for f in hex_files if os.path.basename(f) == os.path.basename(hexf)), None)
+    else:
+        m0hexf = next((f for f in hex_files if os.path.basename(f) == toolchain.target.m0_core_img), None)
 
     if m0hexf:
         toolchain.notify.debug("M0 core image file found %s." % os.path.basename(m0hexf))