mirror of https://github.com/ARMmbed/mbed-os.git
Merge remote-tracking branch 'mbed-nordic/epr_integration' into nrf52_nrf51_unified_integration
Vincent Coubard
commit
f10cf7fe16
114
hal/targets.json
114
hal/targets.json
|
|
@ -1487,7 +1487,7 @@
|
|||
"extra_labels_add": ["DELTA_DFCM_NNN40"],
|
||||
"macros_add": ["TARGET_DELTA_DFCM_NNN40", "TARGET_NRF_LFCLK_RC"]
|
||||
},
|
||||
"NRF51_DK": {
|
||||
"NRF51_DK_LEGACY": {
|
||||
"supported_form_factors": ["ARDUINO"],
|
||||
"inherits": ["MCU_NRF51_32K"],
|
||||
"progen": {"target": "nrf51-dk"},
|
||||
|
|
@ -1868,6 +1868,118 @@
|
|||
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
|
||||
"default_build": "standard"
|
||||
},
|
||||
"MCU_NRF51_UNIFIED": {
|
||||
"inherits": ["Target"],
|
||||
"core": "Cortex-M0",
|
||||
"OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex",
|
||||
"macros": [
|
||||
"NRF51",
|
||||
"TARGET_NRF51822",
|
||||
"BLE_STACK_SUPPORT_REQD",
|
||||
"SOFTDEVICE_PRESENT",
|
||||
"S130",
|
||||
"TARGET_MCU_NRF51822"
|
||||
],
|
||||
"MERGE_BOOTLOADER": false,
|
||||
"extra_labels": ["NORDIC", "MCU_NRF51", "MCU_NRF51822_UNIFIED", "NRF5"],
|
||||
"OUTPUT_EXT": "hex",
|
||||
"is_disk_virtual": true,
|
||||
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
|
||||
"public": false,
|
||||
"MERGE_SOFT_DEVICE": true,
|
||||
"EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
|
||||
{
|
||||
"boot": "",
|
||||
"name": "s130_nrf51_2.0.0_softdevice.hex",
|
||||
"offset": 110592
|
||||
}
|
||||
],
|
||||
"detect_code": ["1070"],
|
||||
"post_binary_hook": {
|
||||
"function": "MCU_NRF51Code.binary_hook",
|
||||
"toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
|
||||
},
|
||||
"program_cycle_s": 6,
|
||||
"default_build": "small",
|
||||
"features": ["BLE"],
|
||||
"config":{
|
||||
"lf_clock_src": {
|
||||
"value": "NRF_LF_SRC_XTAL",
|
||||
"macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MCU_NRF51_32K_UNIFIED": {
|
||||
"inherits": ["MCU_NRF51_UNIFIED"],
|
||||
"extra_labels_add": ["MCU_NORDIC_32K", "MCU_NRF51_32K"],
|
||||
"macros_add": ["TARGET_MCU_NORDIC_32K", "TARGET_MCU_NRF51_32K"],
|
||||
"public": false
|
||||
},
|
||||
"NRF51_DK": {
|
||||
"supported_form_factors": ["ARDUINO"],
|
||||
"inherits": ["MCU_NRF51_32K_UNIFIED"],
|
||||
"progen": {"target": "nrf51-dk"},
|
||||
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"]
|
||||
},
|
||||
"MCU_NRF52": {
|
||||
"inherits": ["Target"],
|
||||
"core": "Cortex-M4F",
|
||||
"macros": ["NRF52", "TARGET_NRF52832", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S132"],
|
||||
"extra_labels": ["NORDIC", "MCU_NRF52", "MCU_NRF52832", "NRF5"],
|
||||
"OUTPUT_EXT": "hex",
|
||||
"is_disk_virtual": true,
|
||||
"supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
|
||||
"public": false,
|
||||
"detect_code": ["1101"],
|
||||
"program_cycle_s": 6,
|
||||
"MERGE_SOFT_DEVICE": true,
|
||||
"EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
|
||||
{
|
||||
"boot": "",
|
||||
"name": "s132_nrf52_2.0.0_softdevice.hex",
|
||||
"offset": 114688
|
||||
}
|
||||
],
|
||||
"post_binary_hook": {
|
||||
"function": "MCU_NRF51Code.binary_hook",
|
||||
"toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
|
||||
},
|
||||
"MERGE_BOOTLOADER": false,
|
||||
"features": ["BLE"],
|
||||
"config":{
|
||||
"lf_clock_src": {
|
||||
"value": "NRF_LF_SRC_XTAL",
|
||||
"macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC"
|
||||
}
|
||||
}
|
||||
},
|
||||
"NRF52_DK": {
|
||||
"supported_form_factors": ["ARDUINO"],
|
||||
"inherits": ["MCU_NRF52"],
|
||||
"progen": {"target": "nrf52-dk"},
|
||||
"macros_add": [
|
||||
"BOARD_PCA10040",
|
||||
"NRF52_PAN_12",
|
||||
"NRF52_PAN_15",
|
||||
"NRF52_PAN_58",
|
||||
"NRF52_PAN_55",
|
||||
"NRF52_PAN_54",
|
||||
"NRF52_PAN_31",
|
||||
"NRF52_PAN_30",
|
||||
"NRF52_PAN_51",
|
||||
"NRF52_PAN_36",
|
||||
"NRF52_PAN_53",
|
||||
"S132",
|
||||
"CONFIG_GPIO_AS_PINRESET",
|
||||
"BLE_STACK_SUPPORT_REQD",
|
||||
"SWI_DISABLE0",
|
||||
"NRF52_PAN_20",
|
||||
"NRF52_PAN_64",
|
||||
"NRF52_PAN_62",
|
||||
"NRF52_PAN_63"
|
||||
],
|
||||
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"]
|
||||
},
|
||||
"BLUEPILL_F103C8": {
|
||||
"core": "Cortex-M3",
|
||||
"default_toolchain": "GCC_ARM",
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -1,109 +0,0 @@
|
|||
/* Copyright (c) 2013, Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef _COMPILER_ABSTRACTION_H
|
||||
#define _COMPILER_ABSTRACTION_H
|
||||
|
||||
/*lint ++flb "Enter library region" */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak /*!< weak keyword for ARM Compiler */
|
||||
#endif
|
||||
|
||||
#define GET_SP() __current_sp() /*!> read current SP function for ARM Compiler */
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak /*!> define weak function for IAR Compiler */
|
||||
#endif
|
||||
|
||||
#define GET_SP() __get_SP() /*!> read current SP function for IAR Compiler */
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak)) /*!< weak keyword for GNU Compiler */
|
||||
#endif
|
||||
|
||||
#define GET_SP() gcc_current_sp() /*!> read current SP function for GNU Compiler */
|
||||
|
||||
static inline unsigned int gcc_current_sp(void)
|
||||
{
|
||||
register unsigned sp asm("sp");
|
||||
return sp;
|
||||
}
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak)) /*!< weak keyword for TASKING Compiler */
|
||||
#endif
|
||||
|
||||
#define GET_SP() __get_MSP() /*!> read current SP function for TASKING Compiler */
|
||||
|
||||
#endif
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif
|
||||
|
|
@ -1,74 +0,0 @@
|
|||
#ifndef _NRF_DELAY_H
|
||||
#define _NRF_DELAY_H
|
||||
|
||||
// #include "nrf.h"
|
||||
|
||||
/*lint --e{438, 522} "Variable not used" "Function lacks side-effects" */
|
||||
#if defined ( __CC_ARM )
|
||||
static __ASM void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
|
||||
{
|
||||
loop
|
||||
SUBS R0, R0, #1
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
BNE loop
|
||||
BX LR
|
||||
}
|
||||
#elif defined ( __ICCARM__ )
|
||||
static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
|
||||
{
|
||||
__ASM (
|
||||
"loop:\n\t"
|
||||
" SUBS R0, R0, #1\n\t"
|
||||
" NOP\n\t"
|
||||
" NOP\n\t"
|
||||
" NOP\n\t"
|
||||
" NOP\n\t"
|
||||
" NOP\n\t"
|
||||
" NOP\n\t"
|
||||
" NOP\n\t"
|
||||
" NOP\n\t"
|
||||
" NOP\n\t"
|
||||
" NOP\n\t"
|
||||
" NOP\n\t"
|
||||
" NOP\n\t"
|
||||
" BNE loop\n\t");
|
||||
}
|
||||
#elif defined ( __GNUC__ )
|
||||
__INLINE static void nrf_delay_us(uint32_t volatile number_of_us)
|
||||
{
|
||||
do
|
||||
{
|
||||
__ASM volatile (
|
||||
"NOP\n\t"
|
||||
"NOP\n\t"
|
||||
"NOP\n\t"
|
||||
"NOP\n\t"
|
||||
"NOP\n\t"
|
||||
"NOP\n\t"
|
||||
"NOP\n\t"
|
||||
"NOP\n\t"
|
||||
"NOP\n\t"
|
||||
"NOP\n\t"
|
||||
"NOP\n\t"
|
||||
"NOP\n\t"
|
||||
"NOP\n\t"
|
||||
"NOP\n\t"
|
||||
);
|
||||
} while (--number_of_us);
|
||||
}
|
||||
#endif
|
||||
|
||||
void nrf_delay_ms(uint32_t volatile number_of_ms);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,187 +0,0 @@
|
|||
/* Copyright (c) 2013, Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
/* NOTE: Template files (including this one) are application specific and therefore expected to
|
||||
be copied into the application project folder prior to its use! */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "nrf.h"
|
||||
#include "nrf_delay.h"
|
||||
#include "system_nrf51.h"
|
||||
|
||||
/*lint ++flb "Enter library region" */
|
||||
|
||||
#define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */
|
||||
|
||||
static bool is_manual_peripheral_setup_needed(void);
|
||||
static bool is_disabled_in_debug_needed(void);
|
||||
static void init_clock(void);
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
|
||||
#elif defined ( __ICCARM__ )
|
||||
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK;
|
||||
#elif defined ( __GNUC__ )
|
||||
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
|
||||
#endif
|
||||
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
}
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
#if defined(TARGET_NRF_32MHZ_XTAL)
|
||||
/* For 32MHz HFCLK XTAL such as Taiyo Yuden
|
||||
Physically, tiny footprint XTAL oscillate higher freq. To make BLE modules smaller, some modules
|
||||
are using 32MHz XTAL.
|
||||
This code wriging the value 0xFFFFFF00 to the UICR (User Information Configuration Register)
|
||||
at address 0x10001008, to make nRF51 works with 32MHz system clock. This register will be overwritten
|
||||
by SoftDevice to 0xFFFFFFFF, the default value. Each hex files built with mbed classic online compiler
|
||||
contain SoftDevice, so that, this code run once just after the hex file will be flashed onto nRF51.
|
||||
After changing the value, nRF51 need to reboot. */
|
||||
if (*(uint32_t *)0x10001008 == 0xFFFFFFFF)
|
||||
{
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
*(uint32_t *)0x10001008 = 0xFFFFFF00;
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NVIC_SystemReset();
|
||||
while (true){}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* If desired, switch off the unused RAM to lower consumption by the use of RAMON register.
|
||||
It can also be done in the application main() function. */
|
||||
|
||||
/* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required
|
||||
to enable the use of peripherals" found at Product Anomaly document for your device found at
|
||||
https://www.nordicsemi.com/. The side effect of executing these instructions in the devices
|
||||
that do not need it is that the new peripherals in the second generation devices (LPCOMP for
|
||||
example) will not be available. */
|
||||
if (is_manual_peripheral_setup_needed())
|
||||
{
|
||||
*(uint32_t volatile *)0x40000504 = 0xC007FFDF;
|
||||
*(uint32_t volatile *)0x40006C18 = 0x00008000;
|
||||
}
|
||||
|
||||
/* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG
|
||||
register is incorrect" found at Product Anomaly document four your device found at
|
||||
https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */
|
||||
if (is_disabled_in_debug_needed())
|
||||
{
|
||||
NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos;
|
||||
}
|
||||
|
||||
// Start the external 32khz crystal oscillator.
|
||||
init_clock();
|
||||
}
|
||||
|
||||
void init_clock(void)
|
||||
{
|
||||
/* For compatibility purpose, the default behaviour is to first attempt to initialise an
|
||||
external clock, and after a timeout, use the internal RC one. To avoid this wait, boards that
|
||||
don't have an external oscillator can set TARGET_NRF_LFCLK_RC directly. */
|
||||
uint32_t i = 0;
|
||||
const uint32_t polling_period = 200;
|
||||
const uint32_t timeout = 1000000;
|
||||
|
||||
#if defined(TARGET_NRF_LFCLK_RC)
|
||||
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_RC << CLOCK_LFCLKSRC_SRC_Pos);
|
||||
#else
|
||||
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos);
|
||||
#endif
|
||||
NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
|
||||
NRF_CLOCK->TASKS_LFCLKSTART = 1;
|
||||
|
||||
/* Wait for the external oscillator to start up.
|
||||
nRF51822 product specification (8.1.5) gives a typical value of 300ms for external clock
|
||||
startup duration, and a maximum value of 1s. When using the internal RC source, typical delay
|
||||
will be 390µs, so we use a polling period of 200µs.
|
||||
|
||||
We can't use us_ticker at this point, so we have to rely on a less precise method for
|
||||
measuring our timeout. Because of this, the actual timeout will be slightly longer than 1
|
||||
second, which isn't an issue at all, since this fallback should only be used as a safety net.
|
||||
*/
|
||||
for (i = 0; i < (timeout / polling_period); i++) {
|
||||
if (NRF_CLOCK->EVENTS_LFCLKSTARTED != 0)
|
||||
return;
|
||||
nrf_delay_us(polling_period);
|
||||
}
|
||||
|
||||
/* Fallback to internal clock. Belt and braces, since the internal clock is used by default
|
||||
whilst no external source is running. This is not only a sanity check, but it also allows
|
||||
code down the road (e.g. ble initialisation) to directly know which clock is used. */
|
||||
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_RC << CLOCK_LFCLKSRC_SRC_Pos);
|
||||
NRF_CLOCK->TASKS_LFCLKSTART = 1;
|
||||
while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {
|
||||
// Do nothing.
|
||||
}
|
||||
}
|
||||
|
||||
static bool is_manual_peripheral_setup_needed(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
|
||||
{
|
||||
return true;
|
||||
}
|
||||
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
|
||||
{
|
||||
return true;
|
||||
}
|
||||
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool is_disabled_in_debug_needed(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
|
@ -1,68 +0,0 @@
|
|||
/* Copyright (c) 2013, Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#ifndef SYSTEM_NRF51_H
|
||||
#define SYSTEM_NRF51_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_NRF51_H */
|
||||
|
|
@ -12,13 +12,13 @@
|
|||
;
|
||||
;WITH SOFTDEVICE:
|
||||
|
||||
LR_IROM1 0x1C000 0x0024000 {
|
||||
ER_IROM1 0x1C000 0x0024000 {
|
||||
LR_IROM1 0x0001B000 0x0025000 {
|
||||
ER_IROM1 0x0001B000 0x0025000 {
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20002800 0x00005800 {
|
||||
RW_IRAM1 0x20002ef8 0x5108 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
|
@ -12,13 +12,13 @@
|
|||
;
|
||||
;WITH SOFTDEVICE:
|
||||
|
||||
LR_IROM1 0x1C000 0x0024000 {
|
||||
ER_IROM1 0x1C000 0x0024000 {
|
||||
LR_IROM1 0x0001B000 0x0025000 {
|
||||
ER_IROM1 0x0001B000 0x0025000 {
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20002800 0x00001800 {
|
||||
RW_IRAM1 0x20002ef8 0x1108 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
;WITHOUT SOFTDEVICE:
|
||||
;LR_IROM1 0x00000000 0x00040000 {
|
||||
; ER_IROM1 0x00000000 0x00040000 {
|
||||
; *.o (RESET, +First)
|
||||
; *(InRoot$$Sections)
|
||||
; .ANY (+RO)
|
||||
; }
|
||||
; RW_IRAM1 0x20000000 0x00004000 {
|
||||
; .ANY (+RW +ZI)
|
||||
; }
|
||||
;}
|
||||
;
|
||||
;WITH SOFTDEVICE:
|
||||
|
||||
LR_IROM1 0x0001B000 0x0025000 {
|
||||
ER_IROM1 0x0001B000 0x0025000 {
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20002ef8 0x1108 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x0001C000, LENGTH = 0x24000
|
||||
RAM (rwx) : ORIGIN = 0x20002800, LENGTH = 0x5800
|
||||
FLASH (rx) : ORIGIN = 0x0001B000, LENGTH = 0x25000
|
||||
RAM (rwx) : ORIGIN = 0x20002ef8, LENGTH = 0x5108
|
||||
}
|
||||
|
||||
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
|
||||
|
|
@ -114,6 +114,15 @@ SECTIONS
|
|||
|
||||
} > RAM
|
||||
|
||||
__edata = .;
|
||||
|
||||
.fs_data :
|
||||
{
|
||||
PROVIDE(__start_fs_data = .);
|
||||
KEEP(*(.fs_data))
|
||||
PROVIDE(__stop_fs_data = .);
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
|
|
@ -1,32 +1,41 @@
|
|||
/*
|
||||
Copyright (c) 2013, Nordic Semiconductor ASA
|
||||
All rights reserved.
|
||||
/*
|
||||
* Copyright (c) 2013 Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
|
||||
* integrated circuit in a product or a software update for such product, must reproduce
|
||||
* the above copyright notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary or object form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
* Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
NOTE: Template files (including this one) are application specific and therefore
|
||||
|
|
@ -117,8 +126,9 @@ __Vectors:
|
|||
|
||||
/* Reset Handler */
|
||||
|
||||
.equ NRF_POWER_RAMON_ADDRESS, 0x40000524
|
||||
.equ NRF_POWER_RAMON_RAMxON_ONMODE_Msk, 0x3
|
||||
.equ NRF_POWER_RAMON_ADDRESS, 0x40000524
|
||||
.equ NRF_POWER_RAMONB_ADDRESS, 0x40000554
|
||||
.equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3
|
||||
|
||||
.text
|
||||
.thumb
|
||||
|
|
@ -129,10 +139,14 @@ __Vectors:
|
|||
Reset_Handler:
|
||||
.fnstart
|
||||
|
||||
/* Make sure ALL RAM banks are powered on */
|
||||
MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
|
||||
LDR R0, =NRF_POWER_RAMON_ADDRESS
|
||||
LDR R2, [R0]
|
||||
MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
|
||||
ORRS R2, R1
|
||||
STR R2, [R0]
|
||||
|
||||
LDR R0, =NRF_POWER_RAMONB_ADDRESS
|
||||
LDR R2, [R0]
|
||||
ORRS R2, R1
|
||||
STR R2, [R0]
|
||||
|
||||
|
|
@ -2,11 +2,11 @@
|
|||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00016000;
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x0001b000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x000160c0;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x0001b0c0;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20002000;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20002ef8;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
|
|
@ -2,12 +2,12 @@
|
|||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00016000;
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x0001b000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x000160c0;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20002000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x0001b0c0;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20002ef8;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
||||
/*-Sizes-*/
|
||||
/*Heap 1/4 of ram and stack 1/8*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0xc00;
|
||||
|
|
@ -0,0 +1,171 @@
|
|||
/*
|
||||
* Copyright (c) 2015 Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
|
||||
* integrated circuit in a product or a software update for such product, must reproduce
|
||||
* the above copyright notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary or object form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
/* NOTE: Template files (including this one) are application specific and therefore expected to
|
||||
be copied into the application project folder prior to its use! */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "nrf.h"
|
||||
#include "system_nrf51.h"
|
||||
#include "nrf5x_lf_clk_helper.h"
|
||||
|
||||
/*lint ++flb "Enter library region" */
|
||||
|
||||
|
||||
#define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */
|
||||
|
||||
static bool is_manual_peripheral_setup_needed(void);
|
||||
static bool is_disabled_in_debug_needed(void);
|
||||
static bool is_peripheral_domain_setup_needed(void);
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
|
||||
#elif defined ( __ICCARM__ )
|
||||
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK;
|
||||
#elif defined ( __GNUC__ )
|
||||
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
|
||||
#endif
|
||||
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
}
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* If desired, switch off the unused RAM to lower consumption by the use of RAMON register.
|
||||
It can also be done in the application main() function. */
|
||||
|
||||
/* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required
|
||||
to enable the use of peripherals" found at Product Anomaly document for your device found at
|
||||
https://www.nordicsemi.com/. The side effect of executing these instructions in the devices
|
||||
that do not need it is that the new peripherals in the second generation devices (LPCOMP for
|
||||
example) will not be available. */
|
||||
if (is_manual_peripheral_setup_needed())
|
||||
{
|
||||
*(uint32_t volatile *)0x40000504 = 0xC007FFDF;
|
||||
*(uint32_t volatile *)0x40006C18 = 0x00008000;
|
||||
}
|
||||
|
||||
/* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG
|
||||
register is incorrect" found at Product Anomaly document for your device found at
|
||||
https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */
|
||||
if (is_disabled_in_debug_needed())
|
||||
{
|
||||
NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos;
|
||||
}
|
||||
|
||||
/* Execute the following code to eliminate excessive current in sleep mode with RAM retention in nRF51802 devices,
|
||||
as indicated by PAN 76 "System: Excessive current in sleep mode with retention" found at Product Anomaly document
|
||||
for your device found at https://www.nordicsemi.com/. */
|
||||
if (is_peripheral_domain_setup_needed()){
|
||||
if (*(uint32_t volatile *)0x4006EC00 != 1){
|
||||
*(uint32_t volatile *)0x4006EC00 = 0x9375;
|
||||
while (*(uint32_t volatile *)0x4006EC00 != 1){
|
||||
}
|
||||
}
|
||||
*(uint32_t volatile *)0x4006EC14 = 0xC0;
|
||||
}
|
||||
|
||||
// Start the LF oscilator according to the mbed configuration (over the nrf5x_lf_clk_helper.h file)
|
||||
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_TO_USE << CLOCK_LFCLKSRC_SRC_Pos);
|
||||
NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
|
||||
NRF_CLOCK->TASKS_LFCLKSTART = 1;
|
||||
|
||||
// Wait for the external oscillator to start up.
|
||||
while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {
|
||||
// Do nothing.
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static bool is_manual_peripheral_setup_needed(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
|
||||
{
|
||||
return true;
|
||||
}
|
||||
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
|
||||
{
|
||||
return true;
|
||||
}
|
||||
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool is_disabled_in_debug_needed(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool is_peripheral_domain_setup_needed(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0xA0) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
|
||||
{
|
||||
return true;
|
||||
}
|
||||
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0xD0) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Copyright (c) 2015 Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
|
||||
* integrated circuit in a product or a software update for such product, must reproduce
|
||||
* the above copyright notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary or object form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#ifndef SYSTEM_NRF51_H
|
||||
#define SYSTEM_NRF51_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_NRF51_H */
|
||||
|
|
@ -12,13 +12,13 @@
|
|||
;
|
||||
;WITH SOFTDEVICE:
|
||||
|
||||
LR_IROM1 0x18000 0x0028000 {
|
||||
ER_IROM1 0x18000 0x0028000 {
|
||||
LR_IROM1 0x1C000 0x0064000 {
|
||||
ER_IROM1 0x1C000 0x0064000 {
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20002000 0x00002000 {
|
||||
RW_IRAM1 0x20002EF8 0x0000D108 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,443 @@
|
|||
;/* Copyright (c) 2012 ARM LIMITED
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
; ---------------------------------------------------------------------------*/
|
||||
|
||||
__initial_sp EQU 0x20008000
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMonitor_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD POWER_CLOCK_IRQHandler
|
||||
DCD RADIO_IRQHandler
|
||||
DCD UARTE0_UART0_IRQHandler
|
||||
DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
DCD NFCT_IRQHandler
|
||||
DCD GPIOTE_IRQHandler
|
||||
DCD SAADC_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD RTC0_IRQHandler
|
||||
DCD TEMP_IRQHandler
|
||||
DCD RNG_IRQHandler
|
||||
DCD ECB_IRQHandler
|
||||
DCD CCM_AAR_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD QDEC_IRQHandler
|
||||
DCD COMP_LPCOMP_IRQHandler
|
||||
DCD SWI0_EGU0_IRQHandler
|
||||
DCD SWI1_EGU1_IRQHandler
|
||||
DCD SWI2_EGU2_IRQHandler
|
||||
DCD SWI3_EGU3_IRQHandler
|
||||
DCD SWI4_EGU4_IRQHandler
|
||||
DCD SWI5_EGU5_IRQHandler
|
||||
DCD TIMER3_IRQHandler
|
||||
DCD TIMER4_IRQHandler
|
||||
DCD PWM0_IRQHandler
|
||||
DCD PDM_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD MWU_IRQHandler
|
||||
DCD PWM1_IRQHandler
|
||||
DCD PWM2_IRQHandler
|
||||
DCD SPIM2_SPIS2_SPI2_IRQHandler
|
||||
DCD RTC2_IRQHandler
|
||||
DCD I2S_IRQHandler
|
||||
DCD FPU_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemoryManagement_Handler\
|
||||
PROC
|
||||
EXPORT MemoryManagement_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMonitor_Handler\
|
||||
PROC
|
||||
EXPORT DebugMonitor_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT POWER_CLOCK_IRQHandler [WEAK]
|
||||
EXPORT RADIO_IRQHandler [WEAK]
|
||||
EXPORT UARTE0_UART0_IRQHandler [WEAK]
|
||||
EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK]
|
||||
EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK]
|
||||
EXPORT NFCT_IRQHandler [WEAK]
|
||||
EXPORT GPIOTE_IRQHandler [WEAK]
|
||||
EXPORT SAADC_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT RTC0_IRQHandler [WEAK]
|
||||
EXPORT TEMP_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT ECB_IRQHandler [WEAK]
|
||||
EXPORT CCM_AAR_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT RTC1_IRQHandler [WEAK]
|
||||
EXPORT QDEC_IRQHandler [WEAK]
|
||||
EXPORT COMP_LPCOMP_IRQHandler [WEAK]
|
||||
EXPORT SWI0_EGU0_IRQHandler [WEAK]
|
||||
EXPORT SWI1_EGU1_IRQHandler [WEAK]
|
||||
EXPORT SWI2_EGU2_IRQHandler [WEAK]
|
||||
EXPORT SWI3_EGU3_IRQHandler [WEAK]
|
||||
EXPORT SWI4_EGU4_IRQHandler [WEAK]
|
||||
EXPORT SWI5_EGU5_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT TIMER4_IRQHandler [WEAK]
|
||||
EXPORT PWM0_IRQHandler [WEAK]
|
||||
EXPORT PDM_IRQHandler [WEAK]
|
||||
EXPORT MWU_IRQHandler [WEAK]
|
||||
EXPORT PWM1_IRQHandler [WEAK]
|
||||
EXPORT PWM2_IRQHandler [WEAK]
|
||||
EXPORT SPIM2_SPIS2_SPI2_IRQHandler [WEAK]
|
||||
EXPORT RTC2_IRQHandler [WEAK]
|
||||
EXPORT I2S_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
POWER_CLOCK_IRQHandler
|
||||
RADIO_IRQHandler
|
||||
UARTE0_UART0_IRQHandler
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
NFCT_IRQHandler
|
||||
GPIOTE_IRQHandler
|
||||
SAADC_IRQHandler
|
||||
TIMER0_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
RTC0_IRQHandler
|
||||
TEMP_IRQHandler
|
||||
RNG_IRQHandler
|
||||
ECB_IRQHandler
|
||||
CCM_AAR_IRQHandler
|
||||
WDT_IRQHandler
|
||||
RTC1_IRQHandler
|
||||
QDEC_IRQHandler
|
||||
COMP_LPCOMP_IRQHandler
|
||||
SWI0_EGU0_IRQHandler
|
||||
SWI1_EGU1_IRQHandler
|
||||
SWI2_EGU2_IRQHandler
|
||||
SWI3_EGU3_IRQHandler
|
||||
SWI4_EGU4_IRQHandler
|
||||
SWI5_EGU5_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
TIMER4_IRQHandler
|
||||
PWM0_IRQHandler
|
||||
PDM_IRQHandler
|
||||
MWU_IRQHandler
|
||||
PWM1_IRQHandler
|
||||
PWM2_IRQHandler
|
||||
SPIM2_SPIS2_SPI2_IRQHandler
|
||||
RTC2_IRQHandler
|
||||
I2S_IRQHandler
|
||||
FPU_IRQHandler
|
||||
B .
|
||||
ENDP
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* mbed Microcontroller Library - stackheap
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
/*
|
||||
* Copyright (c) 2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x1C000, LENGTH = 0x64000
|
||||
RAM (rwx) : ORIGIN = 0x20002ef8, LENGTH = 0xd108
|
||||
}
|
||||
|
||||
|
||||
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with the other linker script that defines memory regions FLASH and RAM.
|
||||
* It references the following symbols that must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines the following symbols that the code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.Vectors))
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(4);
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
. = ALIGN(4);
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
__etext = .;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
*(.jcr)
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
__edata = .;
|
||||
|
||||
.fs_data :
|
||||
{
|
||||
PROVIDE(__start_fs_data = .);
|
||||
KEEP(*(.fs_data))
|
||||
PROVIDE(__stop_fs_data = .);
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*);
|
||||
|
||||
/* Expand the heap to reach the stack boundary. */
|
||||
ASSERT(. <= (ORIGIN(RAM) + LENGTH(RAM) - 0x800), "heap region overflowed into stack");
|
||||
. += (ORIGIN(RAM) + LENGTH(RAM) - 0x800) - .;
|
||||
} > RAM
|
||||
PROVIDE(__heap_start = ADDR(.heap));
|
||||
PROVIDE(__heap_size = SIZEOF(.heap));
|
||||
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
|
||||
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
|
||||
|
||||
/* .stack_dummy section does not contain any symbols. It is only
|
||||
* used for the linker script to calculate the size of stack sections
|
||||
* and assign values to stack symbols later. */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
__StackLimit = .;
|
||||
*(.stack*)
|
||||
. += (ORIGIN(RAM) + LENGTH(RAM) - .);
|
||||
} > RAM
|
||||
|
||||
/* Set the stack top to the end of RAM and move down the stack limit by
|
||||
* the size of the stack_dummy section. */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
}
|
||||
|
|
@ -0,0 +1,467 @@
|
|||
/*
|
||||
* Copyright (c) 2013 Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
|
||||
* integrated circuit in a product or a software update for such product, must reproduce
|
||||
* the above copyright notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary or object form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
NOTE: Template files (including this one) are application specific and therefore
|
||||
expected to be copied into the application project folder prior to its use!
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.arch armv7e-m
|
||||
|
||||
.section .Vectors
|
||||
.align 2
|
||||
.globl __Vectors
|
||||
__Vectors:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler
|
||||
.long NMI_Handler
|
||||
.long HardFault_Handler
|
||||
.long MemoryManagement_Handler
|
||||
.long BusFault_Handler
|
||||
.long UsageFault_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long SVC_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long PendSV_Handler
|
||||
.long SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.long POWER_CLOCK_IRQHandler
|
||||
.long RADIO_IRQHandler
|
||||
.long UARTE0_UART0_IRQHandler
|
||||
.long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
.long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
.long NFCT_IRQHandler
|
||||
.long GPIOTE_IRQHandler
|
||||
.long SAADC_IRQHandler
|
||||
.long TIMER0_IRQHandler
|
||||
.long TIMER1_IRQHandler
|
||||
.long TIMER2_IRQHandler
|
||||
.long RTC0_IRQHandler
|
||||
.long TEMP_IRQHandler
|
||||
.long RNG_IRQHandler
|
||||
.long ECB_IRQHandler
|
||||
.long CCM_AAR_IRQHandler
|
||||
.long WDT_IRQHandler
|
||||
.long RTC1_IRQHandler
|
||||
.long QDEC_IRQHandler
|
||||
.long COMP_LPCOMP_IRQHandler
|
||||
.long SWI0_EGU0_IRQHandler
|
||||
.long SWI1_EGU1_IRQHandler
|
||||
.long SWI2_EGU2_IRQHandler
|
||||
.long SWI3_EGU3_IRQHandler
|
||||
.long SWI4_EGU4_IRQHandler
|
||||
.long SWI5_EGU5_IRQHandler
|
||||
.long TIMER3_IRQHandler
|
||||
.long TIMER4_IRQHandler
|
||||
.long PWM0_IRQHandler
|
||||
.long PDM_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long MWU_IRQHandler
|
||||
.long PWM1_IRQHandler
|
||||
.long PWM2_IRQHandler
|
||||
.long SPIM2_SPIS2_SPI2_IRQHandler
|
||||
.long RTC2_IRQHandler
|
||||
.long I2S_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
|
||||
.size __Vectors, . - __Vectors
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 1
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
.fnstart
|
||||
|
||||
|
||||
/* Loop to copy data from read only memory to RAM. The ranges
|
||||
* of copy from/to are specified by following symbols evaluated in
|
||||
* linker script.
|
||||
* __etext: End of code section, i.e., begin of data sections to copy from.
|
||||
* __data_start__/__data_end__: RAM address range that data should be
|
||||
* copied to. Both must be aligned to 4 bytes boundary. */
|
||||
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
subs r3, r2
|
||||
ble .LC0
|
||||
|
||||
.LC1:
|
||||
subs r3, 4
|
||||
ldr r0, [r1,r3]
|
||||
str r0, [r2,r3]
|
||||
bgt .LC1
|
||||
.LC0:
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =_start
|
||||
BX R0
|
||||
|
||||
.pool
|
||||
.cantunwind
|
||||
.fnend
|
||||
.size Reset_Handler,.-Reset_Handler
|
||||
|
||||
.section ".text"
|
||||
|
||||
|
||||
/* Dummy Exception Handlers (infinite loops which can be modified) */
|
||||
|
||||
.weak NMI_Handler
|
||||
.type NMI_Handler, %function
|
||||
NMI_Handler:
|
||||
B .
|
||||
.size NMI_Handler, . - NMI_Handler
|
||||
|
||||
|
||||
.weak HardFault_Handler
|
||||
.type HardFault_Handler, %function
|
||||
HardFault_Handler:
|
||||
B .
|
||||
.size HardFault_Handler, . - HardFault_Handler
|
||||
|
||||
|
||||
.weak MemoryManagement_Handler
|
||||
.type MemoryManagement_Handler, %function
|
||||
MemoryManagement_Handler:
|
||||
B .
|
||||
.size MemoryManagement_Handler, . - MemoryManagement_Handler
|
||||
|
||||
|
||||
.weak BusFault_Handler
|
||||
.type BusFault_Handler, %function
|
||||
BusFault_Handler:
|
||||
B .
|
||||
.size BusFault_Handler, . - BusFault_Handler
|
||||
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.type UsageFault_Handler, %function
|
||||
UsageFault_Handler:
|
||||
B .
|
||||
.size UsageFault_Handler, . - UsageFault_Handler
|
||||
|
||||
|
||||
.weak SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
B .
|
||||
.size SVC_Handler, . - SVC_Handler
|
||||
|
||||
|
||||
.weak PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
B .
|
||||
.size PendSV_Handler, . - PendSV_Handler
|
||||
|
||||
|
||||
.weak SysTick_Handler
|
||||
.type SysTick_Handler, %function
|
||||
SysTick_Handler:
|
||||
B .
|
||||
.size SysTick_Handler, . - SysTick_Handler
|
||||
|
||||
|
||||
/* IRQ Handlers */
|
||||
|
||||
.globl Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
B .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
.macro IRQ handler
|
||||
.weak \handler
|
||||
.set \handler, Default_Handler
|
||||
.endm
|
||||
|
||||
IRQ POWER_CLOCK_IRQHandler
|
||||
IRQ RADIO_IRQHandler
|
||||
IRQ UARTE0_UART0_IRQHandler
|
||||
IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
IRQ NFCT_IRQHandler
|
||||
IRQ GPIOTE_IRQHandler
|
||||
IRQ SAADC_IRQHandler
|
||||
IRQ TIMER0_IRQHandler
|
||||
IRQ TIMER1_IRQHandler
|
||||
IRQ TIMER2_IRQHandler
|
||||
IRQ RTC0_IRQHandler
|
||||
IRQ TEMP_IRQHandler
|
||||
IRQ RNG_IRQHandler
|
||||
IRQ ECB_IRQHandler
|
||||
IRQ CCM_AAR_IRQHandler
|
||||
IRQ WDT_IRQHandler
|
||||
IRQ RTC1_IRQHandler
|
||||
IRQ QDEC_IRQHandler
|
||||
IRQ COMP_LPCOMP_IRQHandler
|
||||
IRQ SWI0_EGU0_IRQHandler
|
||||
IRQ SWI1_EGU1_IRQHandler
|
||||
IRQ SWI2_EGU2_IRQHandler
|
||||
IRQ SWI3_EGU3_IRQHandler
|
||||
IRQ SWI4_EGU4_IRQHandler
|
||||
IRQ SWI5_EGU5_IRQHandler
|
||||
IRQ TIMER3_IRQHandler
|
||||
IRQ TIMER4_IRQHandler
|
||||
IRQ PWM0_IRQHandler
|
||||
IRQ PDM_IRQHandler
|
||||
IRQ MWU_IRQHandler
|
||||
IRQ PWM1_IRQHandler
|
||||
IRQ PWM2_IRQHandler
|
||||
IRQ SPIM2_SPIS2_SPI2_IRQHandler
|
||||
IRQ RTC2_IRQHandler
|
||||
IRQ I2S_IRQHandler
|
||||
|
||||
.end
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x1c000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x1c000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x7ffff;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20002ef8;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2000ffff;
|
||||
export symbol __ICFEDIT_region_RAM_start__;
|
||||
export symbol __ICFEDIT_region_RAM_end__;
|
||||
/*-Sizes-*/
|
||||
/*Heap 1/4 of ram and stack 1/8*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x800;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x1800;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __code_start_soft_device__ = 0x0;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
keep { section .intvec };
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK,
|
||||
block HEAP };
|
||||
|
||||
/*This is used for mbed applications build inside the Embedded workbench
|
||||
Applications build with the python scritps use a hex merge so need to merge it
|
||||
inside the linker. The linker can only use binary files so the hex merge is not possible
|
||||
through the linker. That is why a binary is used instead of a hex image for the embedded project.
|
||||
*/
|
||||
if(isdefinedsymbol(SOFT_DEVICE_BIN))
|
||||
{
|
||||
place at address mem:__code_start_soft_device__ { section .noinit_softdevice };
|
||||
}
|
||||
|
|
@ -0,0 +1,578 @@
|
|||
;/* Copyright (c) 2012 ARM LIMITED
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
; ---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
|
||||
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMonitor_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD POWER_CLOCK_IRQHandler
|
||||
DCD RADIO_IRQHandler
|
||||
DCD UARTE0_UART0_IRQHandler
|
||||
DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
DCD NFCT_IRQHandler
|
||||
DCD GPIOTE_IRQHandler
|
||||
DCD SAADC_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD RTC0_IRQHandler
|
||||
DCD TEMP_IRQHandler
|
||||
DCD RNG_IRQHandler
|
||||
DCD ECB_IRQHandler
|
||||
DCD CCM_AAR_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD QDEC_IRQHandler
|
||||
DCD COMP_LPCOMP_IRQHandler
|
||||
DCD SWI0_EGU0_IRQHandler
|
||||
DCD SWI1_EGU1_IRQHandler
|
||||
DCD SWI2_EGU2_IRQHandler
|
||||
DCD SWI3_EGU3_IRQHandler
|
||||
DCD SWI4_EGU4_IRQHandler
|
||||
DCD SWI5_EGU5_IRQHandler
|
||||
DCD TIMER3_IRQHandler
|
||||
DCD TIMER4_IRQHandler
|
||||
DCD PWM0_IRQHandler
|
||||
DCD PDM_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD MWU_IRQHandler
|
||||
DCD PWM1_IRQHandler
|
||||
DCD PWM2_IRQHandler
|
||||
DCD SPIM2_SPIS2_SPI2_IRQHandler
|
||||
DCD RTC2_IRQHandler
|
||||
DCD I2S_IRQHandler
|
||||
DCD FPU_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
; Default handlers.
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
; Dummy exception handlers
|
||||
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
NMI_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK MemoryManagement_Handler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
MemoryManagement_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
BusFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
UsageFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
SVC_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK DebugMonitor_Handler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
DebugMonitor_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B .
|
||||
|
||||
|
||||
; Dummy interrupt handlers
|
||||
|
||||
PUBWEAK POWER_CLOCK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
POWER_CLOCK_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RADIO_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
RADIO_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK UARTE0_UART0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
UARTE0_UART0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK NFCT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
NFCT_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK GPIOTE_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
GPIOTE_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SAADC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
SAADC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
TIMER0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
TIMER1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
TIMER2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
RTC0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TEMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
TEMP_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
RNG_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK ECB_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
ECB_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK CCM_AAR_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
CCM_AAR_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK WDT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
WDT_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
RTC1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK QDEC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
QDEC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK COMP_LPCOMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
COMP_LPCOMP_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI0_EGU0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
SWI0_EGU0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI1_EGU1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
SWI1_EGU1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI2_EGU2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
SWI2_EGU2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI3_EGU3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
SWI3_EGU3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI4_EGU4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
SWI4_EGU4_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI5_EGU5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
SWI5_EGU5_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
TIMER3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
TIMER4_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
PWM0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PDM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
PDM_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK MWU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
MWU_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
PWM1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
PWM2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM2_SPIS2_SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
SPIM2_SPIS2_SPI2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
RTC2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK I2S_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
I2S_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT(1)
|
||||
FPU_IRQHandler
|
||||
B .
|
||||
|
||||
|
||||
END
|
||||
|
||||
|
||||
|
|
@ -1,5 +1,6 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
/*
|
||||
* PackageLicenseDeclared: Apache-2.0
|
||||
* Copyright (c) 2016 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
|
|
@ -13,18 +14,11 @@
|
|||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PORTNAMES_H
|
||||
#define MBED_PORTNAMES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#ifndef MBED_CMSIS_H
|
||||
#define MBED_CMSIS_H
|
||||
|
||||
typedef enum {
|
||||
Port0 = 0 //GPIO pins 0-31
|
||||
} PortName;
|
||||
#include "nrf.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
/* mbed Microcontroller Library
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2016 ARM Limited. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of SRAM2
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *) SCB->VTOR;
|
||||
uint32_t i;
|
||||
|
||||
/* Copy and switch to dynamic vectors if the first time called */
|
||||
if (SCB->VTOR != NVIC_RAM_VECTOR_ADDRESS) {
|
||||
uint32_t *old_vectors = (uint32_t *) NVIC_FLASH_VECTOR_ADDRESS;
|
||||
vectors = (uint32_t *) NVIC_RAM_VECTOR_ADDRESS;
|
||||
for (i = 0; i < NVIC_NUM_VECTORS; i++) {
|
||||
vectors[i] = old_vectors[i];
|
||||
}
|
||||
SCB->VTOR = (uint32_t) NVIC_RAM_VECTOR_ADDRESS;
|
||||
}
|
||||
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||
}
|
||||
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *) SCB->VTOR;
|
||||
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/* mbed Microcontroller Library
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2016 ARM Limited. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
#define NVIC_NUM_VECTORS (16 + 38) // CORE + MCU Peripherals
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
#include "nrf52.h"
|
||||
#include "cmsis.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,321 @@
|
|||
/*
|
||||
* Copyright (c) 2015 Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
|
||||
* integrated circuit in a product or a software update for such product, must reproduce
|
||||
* the above copyright notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary or object form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "nrf.h"
|
||||
#include "system_nrf52.h"
|
||||
#include "nrf5x_lf_clk_helper.h"
|
||||
|
||||
/*lint ++flb "Enter library region" */
|
||||
|
||||
#define __SYSTEM_CLOCK_64M (64000000UL)
|
||||
|
||||
static bool errata_16(void);
|
||||
static bool errata_31(void);
|
||||
static bool errata_32(void);
|
||||
static bool errata_36(void);
|
||||
static bool errata_37(void);
|
||||
static bool errata_57(void);
|
||||
static bool errata_66(void);
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
|
||||
#elif defined ( __ICCARM__ )
|
||||
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
|
||||
#elif defined ( __GNUC__ )
|
||||
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
|
||||
#endif
|
||||
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
SystemCoreClock = __SYSTEM_CLOCK_64M;
|
||||
}
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_16()){
|
||||
*(volatile uint32_t *)0x4007C074 = 3131961357ul;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_31()){
|
||||
*(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_32()){
|
||||
CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_36()){
|
||||
NRF_CLOCK->EVENTS_DONE = 0;
|
||||
NRF_CLOCK->EVENTS_CTTO = 0;
|
||||
NRF_CLOCK->CTIV = 0;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_37()){
|
||||
*(volatile uint32_t *)0x400005A0 = 0x3;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_57()){
|
||||
*(volatile uint32_t *)0x40005610 = 0x00000005;
|
||||
*(volatile uint32_t *)0x40005688 = 0x00000001;
|
||||
*(volatile uint32_t *)0x40005618 = 0x00000000;
|
||||
*(volatile uint32_t *)0x40005614 = 0x0000003F;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_66()){
|
||||
NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
|
||||
NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
|
||||
NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
|
||||
NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
|
||||
NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
|
||||
NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
|
||||
NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
|
||||
NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
|
||||
NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
|
||||
NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
|
||||
NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
|
||||
NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
|
||||
NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
|
||||
NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
|
||||
NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
|
||||
NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
|
||||
NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
|
||||
}
|
||||
|
||||
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
|
||||
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
|
||||
* operations are not used in your code. */
|
||||
#if (__FPU_USED == 1)
|
||||
SCB->CPACR |= (3UL << 20) | (3UL << 22);
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
/* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
|
||||
two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
|
||||
normal GPIOs. */
|
||||
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
|
||||
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
|
||||
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
|
||||
reserved for PinReset and not available as normal GPIO. */
|
||||
#if defined (CONFIG_GPIO_AS_PINRESET)
|
||||
if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
|
||||
((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_UICR->PSELRESET[0] = 21;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_UICR->PSELRESET[1] = 21;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
|
||||
Specification to see which one). */
|
||||
#if defined (ENABLE_SWO)
|
||||
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
|
||||
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
|
||||
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
#endif
|
||||
|
||||
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
|
||||
Specification to see which ones). */
|
||||
#if defined (ENABLE_TRACE)
|
||||
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
|
||||
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
|
||||
NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
#endif
|
||||
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
// Start the LF oscilator according to the mbed configuration (over the nrf5x_lf_clk_helper.h file)
|
||||
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_TO_USE << CLOCK_LFCLKSRC_SRC_Pos);
|
||||
NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
|
||||
NRF_CLOCK->TASKS_LFCLKSTART = 1;
|
||||
|
||||
// Wait for the external oscillator to start up.
|
||||
while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {
|
||||
// Do nothing.
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static bool errata_16(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
|
||||
{
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool errata_31(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
|
||||
{
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool errata_32(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
|
||||
{
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool errata_36(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
|
||||
{
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool errata_37(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
|
||||
{
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool errata_57(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
|
||||
{
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool errata_66(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
|
||||
{
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Copyright (c) 2015 Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
|
||||
* integrated circuit in a product or a software update for such product, must reproduce
|
||||
* the above copyright notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary or object form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#ifndef SYSTEM_NRF52_H
|
||||
#define SYSTEM_NRF52_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_NRF52_H */
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
|
||||
* integrated circuit in a product or a software update for such product, must reproduce
|
||||
* the above copyright notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary or object form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __NRF5X_LF_CLK_HELPER_H_
|
||||
|
||||
#ifndef MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC
|
||||
#define MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC (NRF_LF_SRC_XTAL)
|
||||
#warning No configuration for LF clock source. Xtal source will be used as a default configuration.
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#define NRF_LF_SRC_XTAL 2
|
||||
#define NRF_LF_SRC_SYNTH 3
|
||||
#define NRF_LF_SRC_RC 4
|
||||
|
||||
#if MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_SYNTH
|
||||
#define CLOCK_LFCLKSRC_SRC_TO_USE (CLOCK_LFCLKSRC_SRC_Synth)
|
||||
#elif MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_XTAL
|
||||
#define CLOCK_LFCLKSRC_SRC_TO_USE (CLOCK_LFCLKSRC_SRC_Xtal)
|
||||
#elif MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_RC
|
||||
#define CLOCK_LFCLKSRC_SRC_TO_USE (CLOCK_LFCLKSRC_SRC_RC)
|
||||
#else
|
||||
#error Bad LFCLK configuration. Declare proper source through mbed configuration.
|
||||
#endif
|
||||
|
||||
#undef NRF_LF_SRC_XTAL
|
||||
#undef NRF_LF_SRC_SYNTH
|
||||
#undef NRF_LF_SRC_RC
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,135 @@
|
|||
/*
|
||||
* Copyright (c) 2015 Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
|
||||
* integrated circuit in a product or a software update for such product, must reproduce
|
||||
* the above copyright notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary or object form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _COMPILER_ABSTRACTION_H
|
||||
#define _COMPILER_ABSTRACTION_H
|
||||
|
||||
/*lint ++flb "Enter library region" */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGN
|
||||
#define __ALIGN(n) __align(n)
|
||||
#endif
|
||||
|
||||
#define GET_SP() __current_sp()
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
|
||||
/* Not defined for IAR since it requires a new line to work, and C preprocessor does not allow that. */
|
||||
#ifndef __ALIGN
|
||||
#define __ALIGN(n)
|
||||
#endif
|
||||
|
||||
#define GET_SP() __get_SP()
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGN
|
||||
#define __ALIGN(n) __attribute__((aligned(n)))
|
||||
#endif
|
||||
|
||||
#define GET_SP() gcc_current_sp()
|
||||
|
||||
static inline unsigned int gcc_current_sp(void)
|
||||
{
|
||||
register unsigned sp __ASM("sp");
|
||||
return sp;
|
||||
}
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGN
|
||||
#define __ALIGN(n) __align(n)
|
||||
#endif
|
||||
|
||||
#define GET_SP() __get_MSP()
|
||||
|
||||
#endif
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif
|
||||
|
|
@ -1,22 +1,28 @@
|
|||
/*
|
||||
* Copyright (c) Nordic Semiconductor ASA
|
||||
/*
|
||||
* Copyright (c) 2015 Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
|
||||
* integrated circuit in a product or a software update for such product, must reproduce
|
||||
* the above copyright notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
|
||||
* contributors to this software may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary or object form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
|
|
@ -27,12 +33,18 @@
|
|||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#ifndef NRF_H
|
||||
#define NRF_H
|
||||
|
||||
/* MDK version */
|
||||
#define MDK_MAJOR_VERSION 8
|
||||
#define MDK_MINOR_VERSION 5
|
||||
#define MDK_MICRO_VERSION 0
|
||||
|
||||
#if defined(_WIN32)
|
||||
/* Do not include nrf51 specific files when building for PC host */
|
||||
#elif defined(__unix)
|
||||
|
|
@ -50,6 +62,7 @@
|
|||
#include "nrf52.h"
|
||||
#include "nrf52_bitfields.h"
|
||||
#include "nrf51_to_nrf52.h"
|
||||
#include "nrf52_name_change.h"
|
||||
#else
|
||||
#error "Device family must be defined. See nrf.h."
|
||||
#endif /* NRF51, NRF52 */
|
||||
|
|
@ -59,3 +72,4 @@
|
|||
#endif /* _WIN32 || __unix || __APPLE__ */
|
||||
|
||||
#endif /* NRF_H */
|
||||
|
||||
|
|
@ -1,34 +1,56 @@
|
|||
/*
|
||||
* Copyright (c) Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
|
||||
/****************************************************************************************************//**
|
||||
* @file nrf51.h
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
|
||||
* nrf51 from Nordic Semiconductor.
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
* @version V522
|
||||
* @date 23. February 2016
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
* @note Generated with SVDConv V2.81d
|
||||
* from CMSIS SVD File 'nrf51.svd' Version 522,
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
|
||||
* contributors to this software may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
* @par Copyright (c) 2013, Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
*******************************************************************************************************/
|
||||
|
||||
|
||||
|
||||
/** @addtogroup Nordic Semiconductor
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup nrf51
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef NRF51_H
|
||||
#define NRF51_H
|
||||
|
|
@ -843,8 +865,8 @@ typedef struct { /*!< AAR Structure
|
|||
__IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
|
||||
__I uint32_t RESERVED5;
|
||||
__IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
|
||||
__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
|
||||
during resolution. A minimum of 3 bytes must be reserved. */
|
||||
__IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during
|
||||
resolution. A minimum of 3 bytes must be reserved. */
|
||||
__I uint32_t RESERVED6[697];
|
||||
__IO uint32_t POWER; /*!< Peripheral power control. */
|
||||
} NRF_AAR_Type;
|
||||
|
|
@ -882,8 +904,8 @@ typedef struct { /*!< CCM Structure
|
|||
__IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
|
||||
__IO uint32_t INPTR; /*!< Pointer to the input packet. */
|
||||
__IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
|
||||
__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
|
||||
during resolution. A minimum of 43 bytes must be reserved. */
|
||||
__IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during
|
||||
resolution. A minimum of 43 bytes must be reserved. */
|
||||
__I uint32_t RESERVED5[697];
|
||||
__IO uint32_t POWER; /*!< Peripheral power control. */
|
||||
} NRF_CCM_Type;
|
||||
|
|
@ -1031,7 +1053,7 @@ typedef struct { /*!< NVMC Structure
|
|||
__I uint32_t READY; /*!< Ready flag. */
|
||||
__I uint32_t RESERVED1[64];
|
||||
__IO uint32_t CONFIG; /*!< Configuration register. */
|
||||
|
||||
|
||||
union {
|
||||
__IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
|
||||
__IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
|
||||
|
|
@ -1082,7 +1104,7 @@ typedef struct { /*!< FICR Structure
|
|||
__I uint32_t PPFC; /*!< Pre-programmed factory code present. */
|
||||
__I uint32_t RESERVED2;
|
||||
__I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
|
||||
|
||||
|
||||
union {
|
||||
__I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
|
||||
kept for backward compatinility purposes. Use SIZERAMBLOCKS
|
||||
|
|
@ -1121,7 +1143,7 @@ typedef struct { /*!< UICR Structure
|
|||
__IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
|
||||
__I uint32_t RESERVED0;
|
||||
__I uint32_t FWID; /*!< Firmware ID. */
|
||||
|
||||
|
||||
union {
|
||||
__IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
|
||||
__IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
|
||||
|
|
@ -1260,3 +1282,4 @@ typedef struct { /*!< GPIO Structure
|
|||
|
||||
|
||||
#endif /* nrf51_H */
|
||||
|
||||
|
|
@ -1,22 +1,28 @@
|
|||
/*
|
||||
* Copyright (c) Nordic Semiconductor ASA
|
||||
/*
|
||||
* Copyright (c) 2015 Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
|
||||
* integrated circuit in a product or a software update for such product, must reproduce
|
||||
* the above copyright notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
|
||||
* contributors to this software may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary or object form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
|
|
@ -27,8 +33,9 @@
|
|||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __NRF51_BITS_H
|
||||
#define __NRF51_BITS_H
|
||||
|
||||
|
|
@ -1,22 +1,28 @@
|
|||
/*
|
||||
* Copyright (c) Nordic Semiconductor ASA
|
||||
/*
|
||||
* Copyright (c) 2015 Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
|
||||
* integrated circuit in a product or a software update for such product, must reproduce
|
||||
* the above copyright notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
|
||||
* contributors to this software may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary or object form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
|
|
@ -27,9 +33,10 @@
|
|||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#ifndef NRF51_DEPRECATED_H
|
||||
#define NRF51_DEPRECATED_H
|
||||
|
||||
|
|
@ -0,0 +1,944 @@
|
|||
/*
|
||||
* Copyright (c) 2015 Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
|
||||
* integrated circuit in a product or a software update for such product, must reproduce
|
||||
* the above copyright notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary or object form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#ifndef NRF51_TO_NRF52_H
|
||||
#define NRF51_TO_NRF52_H
|
||||
|
||||
/*lint ++flb "Enter library region */
|
||||
|
||||
/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices.
|
||||
* It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the
|
||||
* functionality is gone, there old names are not define, so compilation will fail. Note that also includes macros
|
||||
* from the nrf51_deprecated.h file. */
|
||||
|
||||
|
||||
/* IRQ */
|
||||
/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */
|
||||
#define UART0_IRQHandler UARTE0_UART0_IRQHandler
|
||||
#define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
#define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
#define ADC_IRQHandler SAADC_IRQHandler
|
||||
#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler
|
||||
#define SWI0_IRQHandler SWI0_EGU0_IRQHandler
|
||||
#define SWI1_IRQHandler SWI1_EGU1_IRQHandler
|
||||
#define SWI2_IRQHandler SWI2_EGU2_IRQHandler
|
||||
#define SWI3_IRQHandler SWI3_EGU3_IRQHandler
|
||||
#define SWI4_IRQHandler SWI4_EGU4_IRQHandler
|
||||
#define SWI5_IRQHandler SWI5_EGU5_IRQHandler
|
||||
|
||||
#define UART0_IRQn UARTE0_UART0_IRQn
|
||||
#define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
|
||||
#define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
|
||||
#define ADC_IRQn SAADC_IRQn
|
||||
#define LPCOMP_IRQn COMP_LPCOMP_IRQn
|
||||
#define SWI0_IRQn SWI0_EGU0_IRQn
|
||||
#define SWI1_IRQn SWI1_EGU1_IRQn
|
||||
#define SWI2_IRQn SWI2_EGU2_IRQn
|
||||
#define SWI3_IRQn SWI3_EGU3_IRQn
|
||||
#define SWI4_IRQn SWI4_EGU4_IRQn
|
||||
#define SWI5_IRQn SWI5_EGU5_IRQn
|
||||
|
||||
|
||||
/* UICR */
|
||||
/* Register RBPCONF was renamed to APPROTECT. */
|
||||
#define RBPCONF APPROTECT
|
||||
|
||||
#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos
|
||||
#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk
|
||||
#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled
|
||||
#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled
|
||||
|
||||
|
||||
/* GPIO */
|
||||
/* GPIO port was renamed to P0. */
|
||||
#define NRF_GPIO NRF_P0
|
||||
#define NRF_GPIO_BASE NRF_P0_BASE
|
||||
|
||||
|
||||
/* SPIS */
|
||||
/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */
|
||||
#define PSELSCK PSEL.SCK
|
||||
#define PSELMISO PSEL.MISO
|
||||
#define PSELMOSI PSEL.MOSI
|
||||
#define PSELCSN PSEL.CSN
|
||||
|
||||
/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */
|
||||
#define RXDPTR RXD.PTR
|
||||
#define MAXRX RXD.MAXCNT
|
||||
#define AMOUNTRX RXD.AMOUNT
|
||||
|
||||
#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos
|
||||
#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk
|
||||
|
||||
#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos
|
||||
#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk
|
||||
|
||||
/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */
|
||||
#define TXDPTR TXD.PTR
|
||||
#define MAXTX TXD.MAXCNT
|
||||
#define AMOUNTTX TXD.AMOUNT
|
||||
|
||||
#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos
|
||||
#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk
|
||||
|
||||
#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos
|
||||
#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk
|
||||
|
||||
|
||||
/* MPU */
|
||||
/* Part of MPU module was renamed BPROT, while the rest was eliminated. */
|
||||
#define NRF_MPU NRF_BPROT
|
||||
|
||||
/* Register DISABLEINDEBUG macros were affected. */
|
||||
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos
|
||||
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk
|
||||
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled
|
||||
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled
|
||||
|
||||
/* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */
|
||||
#define PROTENSET0 CONFIG0
|
||||
#define PROTENSET1 CONFIG1
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos
|
||||
#define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk
|
||||
#define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos
|
||||
#define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk
|
||||
#define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos
|
||||
#define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk
|
||||
#define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos
|
||||
#define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk
|
||||
#define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos
|
||||
#define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk
|
||||
#define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos
|
||||
#define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk
|
||||
#define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos
|
||||
#define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk
|
||||
#define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos
|
||||
#define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk
|
||||
#define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos
|
||||
#define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk
|
||||
#define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos
|
||||
#define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk
|
||||
#define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos
|
||||
#define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk
|
||||
#define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos
|
||||
#define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk
|
||||
#define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos
|
||||
#define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk
|
||||
#define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos
|
||||
#define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk
|
||||
#define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos
|
||||
#define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk
|
||||
#define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos
|
||||
#define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk
|
||||
#define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos
|
||||
#define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk
|
||||
#define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos
|
||||
#define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk
|
||||
#define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos
|
||||
#define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk
|
||||
#define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos
|
||||
#define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk
|
||||
#define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos
|
||||
#define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk
|
||||
#define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos
|
||||
#define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk
|
||||
#define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos
|
||||
#define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk
|
||||
#define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos
|
||||
#define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk
|
||||
#define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos
|
||||
#define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk
|
||||
#define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos
|
||||
#define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk
|
||||
#define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos
|
||||
#define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk
|
||||
#define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos
|
||||
#define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk
|
||||
#define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos
|
||||
#define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk
|
||||
#define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos
|
||||
#define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk
|
||||
#define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos
|
||||
#define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk
|
||||
#define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled
|
||||
|
||||
#define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos
|
||||
#define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk
|
||||
#define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled
|
||||
#define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled
|
||||
#define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos
|
||||
#define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk
|
||||
#define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos
|
||||
#define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk
|
||||
#define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos
|
||||
#define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk
|
||||
#define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos
|
||||
#define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk
|
||||
#define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos
|
||||
#define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk
|
||||
#define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos
|
||||
#define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk
|
||||
#define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos
|
||||
#define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk
|
||||
#define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos
|
||||
#define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk
|
||||
#define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos
|
||||
#define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk
|
||||
#define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos
|
||||
#define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk
|
||||
#define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos
|
||||
#define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk
|
||||
#define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos
|
||||
#define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk
|
||||
#define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos
|
||||
#define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk
|
||||
#define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos
|
||||
#define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk
|
||||
#define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos
|
||||
#define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk
|
||||
#define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos
|
||||
#define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk
|
||||
#define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos
|
||||
#define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk
|
||||
#define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos
|
||||
#define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk
|
||||
#define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos
|
||||
#define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk
|
||||
#define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos
|
||||
#define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk
|
||||
#define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos
|
||||
#define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk
|
||||
#define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos
|
||||
#define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk
|
||||
#define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos
|
||||
#define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk
|
||||
#define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos
|
||||
#define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk
|
||||
#define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos
|
||||
#define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk
|
||||
#define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos
|
||||
#define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk
|
||||
#define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos
|
||||
#define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk
|
||||
#define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos
|
||||
#define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk
|
||||
#define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos
|
||||
#define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk
|
||||
#define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos
|
||||
#define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk
|
||||
#define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos
|
||||
#define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk
|
||||
#define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled
|
||||
|
||||
#define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos
|
||||
#define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk
|
||||
#define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled
|
||||
#define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled
|
||||
#define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled
|
||||
|
||||
|
||||
/* From nrf51_deprecated.h */
|
||||
|
||||
/* NVMC */
|
||||
/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */
|
||||
#define ERASEPROTECTEDPAGE ERASEPCR0
|
||||
|
||||
|
||||
/* IRQ */
|
||||
/* COMP module was eliminated. Adapted to nrf52 headers. */
|
||||
#define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler
|
||||
#define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn
|
||||
|
||||
|
||||
/* RADIO */
|
||||
/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip
|
||||
|
||||
|
||||
/* FICR */
|
||||
/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
|
||||
#define DEVICEID0 DEVICEID[0]
|
||||
#define DEVICEID1 DEVICEID[1]
|
||||
|
||||
/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
|
||||
#define ER0 ER[0]
|
||||
#define ER1 ER[1]
|
||||
#define ER2 ER[2]
|
||||
#define ER3 ER[3]
|
||||
|
||||
/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
|
||||
#define IR0 IR[0]
|
||||
#define IR1 IR[1]
|
||||
#define IR2 IR[2]
|
||||
#define IR3 IR[3]
|
||||
|
||||
/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
|
||||
#define DEVICEADDR0 DEVICEADDR[0]
|
||||
#define DEVICEADDR1 DEVICEADDR[1]
|
||||
|
||||
|
||||
/* PPI */
|
||||
/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
|
||||
#define TASKS_CHG0EN TASKS_CHG[0].EN
|
||||
#define TASKS_CHG0DIS TASKS_CHG[0].DIS
|
||||
#define TASKS_CHG1EN TASKS_CHG[1].EN
|
||||
#define TASKS_CHG1DIS TASKS_CHG[1].DIS
|
||||
#define TASKS_CHG2EN TASKS_CHG[2].EN
|
||||
#define TASKS_CHG2DIS TASKS_CHG[2].DIS
|
||||
#define TASKS_CHG3EN TASKS_CHG[3].EN
|
||||
#define TASKS_CHG3DIS TASKS_CHG[3].DIS
|
||||
|
||||
/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
|
||||
#define CH0_EEP CH[0].EEP
|
||||
#define CH0_TEP CH[0].TEP
|
||||
#define CH1_EEP CH[1].EEP
|
||||
#define CH1_TEP CH[1].TEP
|
||||
#define CH2_EEP CH[2].EEP
|
||||
#define CH2_TEP CH[2].TEP
|
||||
#define CH3_EEP CH[3].EEP
|
||||
#define CH3_TEP CH[3].TEP
|
||||
#define CH4_EEP CH[4].EEP
|
||||
#define CH4_TEP CH[4].TEP
|
||||
#define CH5_EEP CH[5].EEP
|
||||
#define CH5_TEP CH[5].TEP
|
||||
#define CH6_EEP CH[6].EEP
|
||||
#define CH6_TEP CH[6].TEP
|
||||
#define CH7_EEP CH[7].EEP
|
||||
#define CH7_TEP CH[7].TEP
|
||||
#define CH8_EEP CH[8].EEP
|
||||
#define CH8_TEP CH[8].TEP
|
||||
#define CH9_EEP CH[9].EEP
|
||||
#define CH9_TEP CH[9].TEP
|
||||
#define CH10_EEP CH[10].EEP
|
||||
#define CH10_TEP CH[10].TEP
|
||||
#define CH11_EEP CH[11].EEP
|
||||
#define CH11_TEP CH[11].TEP
|
||||
#define CH12_EEP CH[12].EEP
|
||||
#define CH12_TEP CH[12].TEP
|
||||
#define CH13_EEP CH[13].EEP
|
||||
#define CH13_TEP CH[13].TEP
|
||||
#define CH14_EEP CH[14].EEP
|
||||
#define CH14_TEP CH[14].TEP
|
||||
#define CH15_EEP CH[15].EEP
|
||||
#define CH15_TEP CH[15].TEP
|
||||
|
||||
/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
|
||||
#define CHG0 CHG[0]
|
||||
#define CHG1 CHG[1]
|
||||
#define CHG2 CHG[2]
|
||||
#define CHG3 CHG[3]
|
||||
|
||||
/* All bitfield macros for the CHGx registers therefore changed name. */
|
||||
#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included
|
||||
|
||||
#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included
|
||||
|
||||
#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included
|
||||
|
||||
#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included
|
||||
|
||||
#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included
|
||||
|
||||
#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included
|
||||
|
||||
#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included
|
||||
|
||||
#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included
|
||||
|
||||
#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included
|
||||
|
||||
#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included
|
||||
|
||||
#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included
|
||||
|
||||
#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included
|
||||
|
||||
#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included
|
||||
|
||||
#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included
|
||||
|
||||
#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included
|
||||
|
||||
#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
|
||||
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF51_TO_NRF52_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* Copyright (c) 2015 Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
|
||||
* integrated circuit in a product or a software update for such product, must reproduce
|
||||
* the above copyright notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary or object form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#ifndef NRF52_NAME_CHANGE_H
|
||||
#define NRF52_NAME_CHANGE_H
|
||||
|
||||
/*lint ++flb "Enter library region */
|
||||
|
||||
/* This file is given to prevent your SW from not compiling with the updates made to nrf52.h and
|
||||
* nrf52_bitfields.h. The macros defined in this file were available previously. Do not use these
|
||||
* macros on purpose. Use the ones defined in nrf52.h and nrf52_bitfields.h instead.
|
||||
*/
|
||||
|
||||
/* I2S */
|
||||
/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
|
||||
#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled
|
||||
#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled
|
||||
#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master
|
||||
#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave
|
||||
#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled
|
||||
#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled
|
||||
#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled
|
||||
#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled
|
||||
#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled
|
||||
#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled
|
||||
#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit
|
||||
#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit
|
||||
#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit
|
||||
#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left
|
||||
#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right
|
||||
#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned
|
||||
#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
|
||||
#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left
|
||||
#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF52_NAME_CHANGE_H */
|
||||
|
||||
|
|
@ -1,51 +0,0 @@
|
|||
/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
|
||||
*
|
||||
* The information contained herein is property of Nordic Semiconductor ASA.
|
||||
* Terms and conditions of usage are described in detail in NORDIC
|
||||
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* Licensees are granted free, non-transferable use of the information. NO
|
||||
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
|
||||
* the file.
|
||||
*
|
||||
*/
|
||||
|
||||
/** @file
|
||||
*
|
||||
* @defgroup crc_compute CRC compute
|
||||
* @{
|
||||
* @ingroup hci_transport
|
||||
*
|
||||
* @brief This module implements the CRC-16 calculation in the blocks.
|
||||
*/
|
||||
|
||||
#ifndef CRC16_H__
|
||||
#define CRC16_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**@brief Function for calculating CRC-16 in blocks.
|
||||
*
|
||||
* Feed each consecutive data block into this function, along with the current value of p_crc as
|
||||
* returned by the previous call of this function. The first call of this function should pass NULL
|
||||
* as the initial value of the crc in p_crc.
|
||||
*
|
||||
* @param[in] p_data The input data block for computation.
|
||||
* @param[in] size The size of the input data block in bytes.
|
||||
* @param[in] p_crc The previous calculated CRC-16 value or NULL if first call.
|
||||
*
|
||||
* @return The updated CRC-16 value, based on the input supplied.
|
||||
*/
|
||||
uint16_t crc16_compute(const uint8_t * p_data, uint32_t size, const uint16_t * p_crc);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // CRC16_H__
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,92 +0,0 @@
|
|||
/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
|
||||
*
|
||||
* The information contained herein is property of Nordic Semiconductor ASA.
|
||||
* Terms and conditions of usage are described in detail in NORDIC
|
||||
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* Licensees are granted free, non-transferable use of the information. NO
|
||||
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
|
||||
* the file.
|
||||
*
|
||||
*/
|
||||
|
||||
/** @file
|
||||
*
|
||||
* @defgroup app_error Common application error handler
|
||||
* @{
|
||||
* @ingroup app_common
|
||||
*
|
||||
* @brief Common application error handler and macros for utilizing a common error handler.
|
||||
*/
|
||||
|
||||
#ifndef APP_ERROR_H__
|
||||
#define APP_ERROR_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "nrf_error.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**@brief Function for error handling, which is called when an error has occurred.
|
||||
*
|
||||
* @param[in] error_code Error code supplied to the handler.
|
||||
* @param[in] line_num Line number where the handler is called.
|
||||
* @param[in] p_file_name Pointer to the file name.
|
||||
*/
|
||||
void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**@brief Macro for calling error handler function.
|
||||
*
|
||||
* @param[in] ERR_CODE Error code supplied to the error handler.
|
||||
*/
|
||||
#ifdef DEBUG
|
||||
#define APP_ERROR_HANDLER(ERR_CODE) \
|
||||
do \
|
||||
{ \
|
||||
app_error_handler((ERR_CODE), __LINE__, (uint8_t*) __FILE__); \
|
||||
} while (0)
|
||||
#else
|
||||
#define APP_ERROR_HANDLER(ERR_CODE) \
|
||||
do \
|
||||
{ \
|
||||
app_error_handler((ERR_CODE), 0, 0); \
|
||||
} while (0)
|
||||
#endif
|
||||
/**@brief Macro for calling error handler function if supplied error code any other than NRF_SUCCESS.
|
||||
*
|
||||
* @param[in] ERR_CODE Error code supplied to the error handler.
|
||||
*/
|
||||
#define APP_ERROR_CHECK(ERR_CODE) \
|
||||
do \
|
||||
{ \
|
||||
const uint32_t LOCAL_ERR_CODE = (ERR_CODE); \
|
||||
if (LOCAL_ERR_CODE != NRF_SUCCESS) \
|
||||
{ \
|
||||
APP_ERROR_HANDLER(LOCAL_ERR_CODE); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
/**@brief Macro for calling error handler function if supplied boolean value is false.
|
||||
*
|
||||
* @param[in] BOOLEAN_VALUE Boolean value to be evaluated.
|
||||
*/
|
||||
#define APP_ERROR_CHECK_BOOL(BOOLEAN_VALUE) \
|
||||
do \
|
||||
{ \
|
||||
const uint32_t LOCAL_BOOLEAN_VALUE = (BOOLEAN_VALUE); \
|
||||
if (!LOCAL_BOOLEAN_VALUE) \
|
||||
{ \
|
||||
APP_ERROR_HANDLER(0); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#endif // APP_ERROR_H__
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,234 +0,0 @@
|
|||
/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
|
||||
*
|
||||
* The information contained herein is property of Nordic Semiconductor ASA.
|
||||
* Terms and conditions of usage are described in detail in NORDIC
|
||||
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* Licensees are granted free, non-transferable use of the information. NO
|
||||
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
|
||||
* the file.
|
||||
*
|
||||
*/
|
||||
|
||||
/** @file
|
||||
*
|
||||
* @defgroup app_util Utility Functions and Definitions
|
||||
* @{
|
||||
* @ingroup app_common
|
||||
*
|
||||
* @brief Various types and definitions available to all applications.
|
||||
*/
|
||||
|
||||
#ifndef APP_UTIL_H__
|
||||
#define APP_UTIL_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "compiler_abstraction.h"
|
||||
|
||||
enum
|
||||
{
|
||||
UNIT_0_625_MS = 625, /**< Number of microseconds in 0.625 milliseconds. */
|
||||
UNIT_1_25_MS = 1250, /**< Number of microseconds in 1.25 milliseconds. */
|
||||
UNIT_10_MS = 10000 /**< Number of microseconds in 10 milliseconds. */
|
||||
};
|
||||
|
||||
/**@brief Macro for doing static (i.e. compile time) assertion.
|
||||
*
|
||||
* @note If the assertion fails when compiling using Keil, the compiler will report error message
|
||||
* "error: #94: the size of an array must be greater than zero" (while gcc will list the
|
||||
* symbol static_assert_failed, making the error message more readable).
|
||||
* If the supplied expression can not be evaluated at compile time, Keil will report
|
||||
* "error: #28: expression must have a constant value".
|
||||
*
|
||||
* @note The macro is intentionally implemented not using do while(0), allowing it to be used
|
||||
* outside function blocks (e.g. close to global type- and variable declarations).
|
||||
* If used in a code block, it must be used before any executable code in this block.
|
||||
*
|
||||
* @param[in] EXPR Constant expression to be verified.
|
||||
*/
|
||||
|
||||
#if defined(__GNUC__)
|
||||
#define STATIC_ASSERT(EXPR) typedef char __attribute__((unused)) static_assert_failed[(EXPR) ? 1 : -1]
|
||||
#elif defined(__ICCARM__)
|
||||
#define STATIC_ASSERT(EXPR) extern char static_assert_failed[(EXPR) ? 1 : -1]
|
||||
#else
|
||||
#define STATIC_ASSERT(EXPR) typedef char static_assert_failed[(EXPR) ? 1 : -1]
|
||||
#endif
|
||||
|
||||
|
||||
/**@brief type for holding an encoded (i.e. little endian) 16 bit unsigned integer. */
|
||||
typedef uint8_t uint16_le_t[2];
|
||||
|
||||
/**@brief type for holding an encoded (i.e. little endian) 32 bit unsigned integer. */
|
||||
typedef uint8_t uint32_le_t[4];
|
||||
|
||||
/**@brief Byte array type. */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t size; /**< Number of array entries. */
|
||||
uint8_t * p_data; /**< Pointer to array entries. */
|
||||
} uint8_array_t;
|
||||
|
||||
/**@brief Perform rounded integer division (as opposed to truncating the result).
|
||||
*
|
||||
* @param[in] A Numerator.
|
||||
* @param[in] B Denominator.
|
||||
*
|
||||
* @return Rounded (integer) result of dividing A by B.
|
||||
*/
|
||||
#define ROUNDED_DIV(A, B) (((A) + ((B) / 2)) / (B))
|
||||
|
||||
/**@brief Check if the integer provided is a power of two.
|
||||
*
|
||||
* @param[in] A Number to be tested.
|
||||
*
|
||||
* @return true if value is power of two.
|
||||
* @return false if value not power of two.
|
||||
*/
|
||||
#define IS_POWER_OF_TWO(A) ( ((A) != 0) && ((((A) - 1) & (A)) == 0) )
|
||||
|
||||
/**@brief To convert milliseconds to ticks.
|
||||
* @param[in] TIME Number of milliseconds to convert.
|
||||
* @param[in] RESOLUTION Unit to be converted to in [us/ticks].
|
||||
*/
|
||||
#define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION))
|
||||
|
||||
|
||||
/**@brief Perform integer division, making sure the result is rounded up.
|
||||
*
|
||||
* @details One typical use for this is to compute the number of objects with size B is needed to
|
||||
* hold A number of bytes.
|
||||
*
|
||||
* @param[in] A Numerator.
|
||||
* @param[in] B Denominator.
|
||||
*
|
||||
* @return Integer result of dividing A by B, rounded up.
|
||||
*/
|
||||
#define CEIL_DIV(A, B) \
|
||||
/*lint -save -e573 */ \
|
||||
((((A) - 1) / (B)) + 1) \
|
||||
/*lint -restore */
|
||||
|
||||
/**@brief Function for encoding a uint16 value.
|
||||
*
|
||||
* @param[in] value Value to be encoded.
|
||||
* @param[out] p_encoded_data Buffer where the encoded data is to be written.
|
||||
*
|
||||
* @return Number of bytes written.
|
||||
*/
|
||||
static __INLINE uint8_t uint16_encode(uint16_t value, uint8_t * p_encoded_data)
|
||||
{
|
||||
p_encoded_data[0] = (uint8_t) ((value & 0x00FF) >> 0);
|
||||
p_encoded_data[1] = (uint8_t) ((value & 0xFF00) >> 8);
|
||||
return sizeof(uint16_t);
|
||||
}
|
||||
|
||||
/**@brief Function for encoding a uint32 value.
|
||||
*
|
||||
* @param[in] value Value to be encoded.
|
||||
* @param[out] p_encoded_data Buffer where the encoded data is to be written.
|
||||
*
|
||||
* @return Number of bytes written.
|
||||
*/
|
||||
static __INLINE uint8_t uint32_encode(uint32_t value, uint8_t * p_encoded_data)
|
||||
{
|
||||
p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0);
|
||||
p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8);
|
||||
p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16);
|
||||
p_encoded_data[3] = (uint8_t) ((value & 0xFF000000) >> 24);
|
||||
return sizeof(uint32_t);
|
||||
}
|
||||
|
||||
/**@brief Function for decoding a uint16 value.
|
||||
*
|
||||
* @param[in] p_encoded_data Buffer where the encoded data is stored.
|
||||
*
|
||||
* @return Decoded value.
|
||||
*/
|
||||
static __INLINE uint16_t uint16_decode(const uint8_t * p_encoded_data)
|
||||
{
|
||||
return ( (((uint16_t)((uint8_t *)p_encoded_data)[0])) |
|
||||
(((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 ));
|
||||
}
|
||||
|
||||
/**@brief Function for decoding a uint32 value.
|
||||
*
|
||||
* @param[in] p_encoded_data Buffer where the encoded data is stored.
|
||||
*
|
||||
* @return Decoded value.
|
||||
*/
|
||||
static __INLINE uint32_t uint32_decode(const uint8_t * p_encoded_data)
|
||||
{
|
||||
return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) |
|
||||
(((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) |
|
||||
(((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) |
|
||||
(((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 ));
|
||||
}
|
||||
|
||||
/** @brief Function for converting the input voltage (in milli volts) into percentage of 3.0 Volts.
|
||||
*
|
||||
* @details The calculation is based on a linearized version of the battery's discharge
|
||||
* curve. 3.0V returns 100% battery level. The limit for power failure is 2.1V and
|
||||
* is considered to be the lower boundary.
|
||||
*
|
||||
* The discharge curve for CR2032 is non-linear. In this model it is split into
|
||||
* 4 linear sections:
|
||||
* - Section 1: 3.0V - 2.9V = 100% - 42% (58% drop on 100 mV)
|
||||
* - Section 2: 2.9V - 2.74V = 42% - 18% (24% drop on 160 mV)
|
||||
* - Section 3: 2.74V - 2.44V = 18% - 6% (12% drop on 300 mV)
|
||||
* - Section 4: 2.44V - 2.1V = 6% - 0% (6% drop on 340 mV)
|
||||
*
|
||||
* These numbers are by no means accurate. Temperature and
|
||||
* load in the actual application is not accounted for!
|
||||
*
|
||||
* @param[in] mvolts The voltage in mV
|
||||
*
|
||||
* @return Battery level in percent.
|
||||
*/
|
||||
static __INLINE uint8_t battery_level_in_percent(const uint16_t mvolts)
|
||||
{
|
||||
uint8_t battery_level;
|
||||
|
||||
if (mvolts >= 3000)
|
||||
{
|
||||
battery_level = 100;
|
||||
}
|
||||
else if (mvolts > 2900)
|
||||
{
|
||||
battery_level = 100 - ((3000 - mvolts) * 58) / 100;
|
||||
}
|
||||
else if (mvolts > 2740)
|
||||
{
|
||||
battery_level = 42 - ((2900 - mvolts) * 24) / 160;
|
||||
}
|
||||
else if (mvolts > 2440)
|
||||
{
|
||||
battery_level = 18 - ((2740 - mvolts) * 12) / 300;
|
||||
}
|
||||
else if (mvolts > 2100)
|
||||
{
|
||||
battery_level = 6 - ((2440 - mvolts) * 6) / 340;
|
||||
}
|
||||
else
|
||||
{
|
||||
battery_level = 0;
|
||||
}
|
||||
|
||||
return battery_level;
|
||||
}
|
||||
|
||||
/**@brief Function for checking if a pointer value is aligned to a 4 byte boundary.
|
||||
*
|
||||
* @param[in] p Pointer value to be checked.
|
||||
*
|
||||
* @return TRUE if pointer is aligned to a 4 byte boundary, FALSE otherwise.
|
||||
*/
|
||||
static __INLINE bool is_word_aligned(void * p)
|
||||
{
|
||||
return (((uintptr_t)p & 0x03) == 0);
|
||||
}
|
||||
|
||||
#endif // APP_UTIL_H__
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,90 +0,0 @@
|
|||
S110/S120/S130 license agreement
|
||||
|
||||
NORDIC SEMICONDUCTOR ASA SOFTDEVICE LICENSE AGREEMENT
|
||||
|
||||
License Agreement for the Nordic Semiconductor ASA ("Nordic") S110, S120 and S130 Bluetooth SoftDevice software packages ("SoftDevice").
|
||||
You ("You" "Licensee") must carefully and thoroughly read this License Agreement ("Agreement"), and accept to adhere to this Agreement before
|
||||
downloading, installing and/or using any software or content in the SoftDevice provided herewith.
|
||||
|
||||
YOU ACCEPT THIS LICENSE AGREEMENT BY (A) CLICKING ACCEPT OR AGREE TO THIS LICENSE AGREEMENT, WHERE THIS
|
||||
OPTION IS MADE AVAILABLE TO YOU; OR (B) BY ACTUALLY USING THE SOFTDEVICE, IN THIS CASE YOU AGREE THAT THE USE OF
|
||||
THE SOFTDEVICE CONSTITUTES ACCEPTANCE OF THE LICENSING AGREEMENT FROM THAT POINT ONWARDS.
|
||||
|
||||
IF YOU DO NOT AGREE TO BE BOUND BY THE TERMS OF THIS AGREEMENT, THEN DO NOT DOWNLOAD, INSTALL/COMPLETE
|
||||
INSTALLATION OF, OR IN ANY OTHER WAY MAKE USE OF THE SOFTDEVICE.
|
||||
|
||||
1. Grant of License
|
||||
Subject to the terms in this Agreement Nordic grants Licensee a limited, non-exclusive, non-transferable, non-sub licensable, revocable license
|
||||
("License"): (a) to use the SoftDevice solely in connection with a Nordic integrated circuit, and (b) to distribute the SoftDevice solely as integrated
|
||||
in Licensee Product. Licensee shall not use the SoftDevice for any purpose other than specifically authorized herein. It is a material breach of this
|
||||
agreement to use or modify the SoftDevice for use on any wireless connectivity integrated circuit other than a Nordic integrated circuit.
|
||||
|
||||
2. Title
|
||||
Nordic retains full rights, title, and ownership to the SoftDevice and any and all patents, copyrights, trade secrets, trade names, trademarks, and
|
||||
other intellectual property rights in and to the SoftDevice.
|
||||
|
||||
3. No Modifications or Reverse Engineering
|
||||
Licensee shall not, modify, reverse engineer, disassemble, decompile or otherwise attempt to discover the source code of any non-source code
|
||||
parts of the SoftDevice including, but not limited to pre-compiled hex files, binaries and object code.
|
||||
|
||||
4. Distribution Restrictions
|
||||
Except as set forward in Section 1 above, the Licensee may not disclose or distribute any or all parts of the SoftDevice to any third party.
|
||||
Licensee agrees to provide reasonable security precautions to prevent unauthorized access to or use of the SoftDevice as proscribed herein.
|
||||
Licensee also agrees that use of and access to the SoftDevice will be strictly limited to the employees and subcontractors of the Licensee
|
||||
necessary for the performance of development, verification and production tasks under this Agreement. The Licensee is responsible for making
|
||||
such employees and subcontractors comply with the obligations concerning use and non-disclosure of the SoftDevice.
|
||||
|
||||
5. No Other Rights
|
||||
Licensee shall use the SoftDevice only in compliance with this Agreement and shall refrain from using the SoftDevice in any way that may be
|
||||
contrary to this Agreement.
|
||||
|
||||
6. Fees
|
||||
Nordic grants the License to the Licensee free of charge provided that the Licensee undertakes the obligations in the Agreement and warrants to
|
||||
comply with the Agreement.
|
||||
|
||||
7. DISCLAIMER OF WARRANTY
|
||||
THE SOFTDEVICE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND EXPRESS OR IMPLIED AND NEITHER NORDIC, ITS
|
||||
LICENSORS OR AFFILIATES NOR THE COPYRIGHT HOLDERS MAKE ANY REPRESENTATIONS OR WARRANTIES, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR
|
||||
THAT THE SOFTDEVICE WILL NOT INFRINGE ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADEMARKS OR OTHER RIGHTS. THERE
|
||||
IS NO WARRANTY BY NORDIC OR BY ANY OTHER PARTY THAT THE FUNCTIONS CONTAINED IN THE SOFTDEVICE WILL MEET THE
|
||||
REQUIREMENTS OF LICENSEE OR THAT THE OPERATION OF THE SOFTDEVICE WILL BE UNINTERRUPTED OR ERROR-FREE.
|
||||
LICENSEE ASSUMES ALL RESPONSIBILITY AND RISK FOR THE SELECTION OF THE SOFTDEVICE TO ACHIEVE LICENSEE’S
|
||||
INTENDED RESULTS AND FOR THE INSTALLATION, USE AND RESULTS OBTAINED FROM IT.
|
||||
|
||||
8. No Support
|
||||
Nordic is not obligated to furnish or make available to Licensee any further information, software, technical information, know-how, show-how,
|
||||
bug-fixes or support. Nordic reserves the right to make changes to the SoftDevice without further notice.
|
||||
|
||||
9. Limitation of Liability
|
||||
In no event shall Nordic, its employees or suppliers, licensors or affiliates be liable for any lost profits, revenue, sales, data or costs of
|
||||
procurement of substitute goods or services, property damage, personal injury, interruption of business, loss of business information or for any
|
||||
special, direct, indirect, incidental, economic, punitive, special or consequential damages, however caused and whether arising under contract,
|
||||
tort, negligence, or other theory of liability arising out of the use of or inability to use the SoftDevice, even if Nordic or its employees or suppliers,
|
||||
licensors or affiliates are advised of the possibility of such damages. Because some countries/states/jurisdictions do not allow the exclusion or
|
||||
limitation of liability, but may allow liability to be limited, in such cases, Nordic, its employees or licensors or affiliates’ liability shall be limited to
|
||||
USD 50.
|
||||
|
||||
10. Breach of Contract
|
||||
Upon a breach of contract by the Licensee, Nordic and its licensor are entitled to damages in respect of any direct loss which can be reasonably
|
||||
attributed to the breach by the Licensee. If the Licensee has acted with gross negligence or willful misconduct, the Licensee shall cover both
|
||||
direct and indirect costs for Nordic and its licensors.
|
||||
|
||||
11. Indemnity
|
||||
Licensee undertakes to indemnify, hold harmless and defend Nordic and its directors, officers, affiliates, shareholders, licensors, employees and
|
||||
agents from and against any claims or lawsuits, including attorney's fees, that arise or result of the Licensee’s execution of the License and which
|
||||
is not due to causes for which Nordic is responsible.
|
||||
|
||||
12. Governing Law
|
||||
This Agreement shall be construed according to the laws of Norway, and hereby submits to the exclusive jurisdiction of the Oslo tingrett.
|
||||
|
||||
13. Assignment
|
||||
Licensee shall not assign this Agreement or any rights or obligations hereunder without the prior written consent of Nordic.
|
||||
|
||||
14. Termination
|
||||
Without prejudice to any other rights, Nordic may cancel this Agreement if Licensee does not abide by the terms and conditions of this
|
||||
Agreement. Upon termination Licensee must promptly cease the use of the License and destroy all copies of the Licensed Technology and any
|
||||
other material provided by Nordic or its affiliate, or produced by the Licensee in connection with the Agreement or the Licensed Technology.
|
||||
|
||||
15. Third party beneficiaries
|
||||
Nordic’s licensors are intended third party beneficiaries under this Agreement.
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,90 +0,0 @@
|
|||
S110/S120/S130 license agreement
|
||||
|
||||
NORDIC SEMICONDUCTOR ASA SOFTDEVICE LICENSE AGREEMENT
|
||||
|
||||
License Agreement for the Nordic Semiconductor ASA ("Nordic") S110, S120 and S130 Bluetooth SoftDevice software packages ("SoftDevice").
|
||||
You ("You" "Licensee") must carefully and thoroughly read this License Agreement ("Agreement"), and accept to adhere to this Agreement before
|
||||
downloading, installing and/or using any software or content in the SoftDevice provided herewith.
|
||||
|
||||
YOU ACCEPT THIS LICENSE AGREEMENT BY (A) CLICKING ACCEPT OR AGREE TO THIS LICENSE AGREEMENT, WHERE THIS
|
||||
OPTION IS MADE AVAILABLE TO YOU; OR (B) BY ACTUALLY USING THE SOFTDEVICE, IN THIS CASE YOU AGREE THAT THE USE OF
|
||||
THE SOFTDEVICE CONSTITUTES ACCEPTANCE OF THE LICENSING AGREEMENT FROM THAT POINT ONWARDS.
|
||||
|
||||
IF YOU DO NOT AGREE TO BE BOUND BY THE TERMS OF THIS AGREEMENT, THEN DO NOT DOWNLOAD, INSTALL/COMPLETE
|
||||
INSTALLATION OF, OR IN ANY OTHER WAY MAKE USE OF THE SOFTDEVICE.
|
||||
|
||||
1. Grant of License
|
||||
Subject to the terms in this Agreement Nordic grants Licensee a limited, non-exclusive, non-transferable, non-sub licensable, revocable license
|
||||
("License"): (a) to use the SoftDevice solely in connection with a Nordic integrated circuit, and (b) to distribute the SoftDevice solely as integrated
|
||||
in Licensee Product. Licensee shall not use the SoftDevice for any purpose other than specifically authorized herein. It is a material breach of this
|
||||
agreement to use or modify the SoftDevice for use on any wireless connectivity integrated circuit other than a Nordic integrated circuit.
|
||||
|
||||
2. Title
|
||||
Nordic retains full rights, title, and ownership to the SoftDevice and any and all patents, copyrights, trade secrets, trade names, trademarks, and
|
||||
other intellectual property rights in and to the SoftDevice.
|
||||
|
||||
3. No Modifications or Reverse Engineering
|
||||
Licensee shall not, modify, reverse engineer, disassemble, decompile or otherwise attempt to discover the source code of any non-source code
|
||||
parts of the SoftDevice including, but not limited to pre-compiled hex files, binaries and object code.
|
||||
|
||||
4. Distribution Restrictions
|
||||
Except as set forward in Section 1 above, the Licensee may not disclose or distribute any or all parts of the SoftDevice to any third party.
|
||||
Licensee agrees to provide reasonable security precautions to prevent unauthorized access to or use of the SoftDevice as proscribed herein.
|
||||
Licensee also agrees that use of and access to the SoftDevice will be strictly limited to the employees and subcontractors of the Licensee
|
||||
necessary for the performance of development, verification and production tasks under this Agreement. The Licensee is responsible for making
|
||||
such employees and subcontractors comply with the obligations concerning use and non-disclosure of the SoftDevice.
|
||||
|
||||
5. No Other Rights
|
||||
Licensee shall use the SoftDevice only in compliance with this Agreement and shall refrain from using the SoftDevice in any way that may be
|
||||
contrary to this Agreement.
|
||||
|
||||
6. Fees
|
||||
Nordic grants the License to the Licensee free of charge provided that the Licensee undertakes the obligations in the Agreement and warrants to
|
||||
comply with the Agreement.
|
||||
|
||||
7. DISCLAIMER OF WARRANTY
|
||||
THE SOFTDEVICE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND EXPRESS OR IMPLIED AND NEITHER NORDIC, ITS
|
||||
LICENSORS OR AFFILIATES NOR THE COPYRIGHT HOLDERS MAKE ANY REPRESENTATIONS OR WARRANTIES, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR
|
||||
THAT THE SOFTDEVICE WILL NOT INFRINGE ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADEMARKS OR OTHER RIGHTS. THERE
|
||||
IS NO WARRANTY BY NORDIC OR BY ANY OTHER PARTY THAT THE FUNCTIONS CONTAINED IN THE SOFTDEVICE WILL MEET THE
|
||||
REQUIREMENTS OF LICENSEE OR THAT THE OPERATION OF THE SOFTDEVICE WILL BE UNINTERRUPTED OR ERROR-FREE.
|
||||
LICENSEE ASSUMES ALL RESPONSIBILITY AND RISK FOR THE SELECTION OF THE SOFTDEVICE TO ACHIEVE LICENSEE’S
|
||||
INTENDED RESULTS AND FOR THE INSTALLATION, USE AND RESULTS OBTAINED FROM IT.
|
||||
|
||||
8. No Support
|
||||
Nordic is not obligated to furnish or make available to Licensee any further information, software, technical information, know-how, show-how,
|
||||
bug-fixes or support. Nordic reserves the right to make changes to the SoftDevice without further notice.
|
||||
|
||||
9. Limitation of Liability
|
||||
In no event shall Nordic, its employees or suppliers, licensors or affiliates be liable for any lost profits, revenue, sales, data or costs of
|
||||
procurement of substitute goods or services, property damage, personal injury, interruption of business, loss of business information or for any
|
||||
special, direct, indirect, incidental, economic, punitive, special or consequential damages, however caused and whether arising under contract,
|
||||
tort, negligence, or other theory of liability arising out of the use of or inability to use the SoftDevice, even if Nordic or its employees or suppliers,
|
||||
licensors or affiliates are advised of the possibility of such damages. Because some countries/states/jurisdictions do not allow the exclusion or
|
||||
limitation of liability, but may allow liability to be limited, in such cases, Nordic, its employees or licensors or affiliates’ liability shall be limited to
|
||||
USD 50.
|
||||
|
||||
10. Breach of Contract
|
||||
Upon a breach of contract by the Licensee, Nordic and its licensor are entitled to damages in respect of any direct loss which can be reasonably
|
||||
attributed to the breach by the Licensee. If the Licensee has acted with gross negligence or willful misconduct, the Licensee shall cover both
|
||||
direct and indirect costs for Nordic and its licensors.
|
||||
|
||||
11. Indemnity
|
||||
Licensee undertakes to indemnify, hold harmless and defend Nordic and its directors, officers, affiliates, shareholders, licensors, employees and
|
||||
agents from and against any claims or lawsuits, including attorney's fees, that arise or result of the Licensee’s execution of the License and which
|
||||
is not due to causes for which Nordic is responsible.
|
||||
|
||||
12. Governing Law
|
||||
This Agreement shall be construed according to the laws of Norway, and hereby submits to the exclusive jurisdiction of the Oslo tingrett.
|
||||
|
||||
13. Assignment
|
||||
Licensee shall not assign this Agreement or any rights or obligations hereunder without the prior written consent of Nordic.
|
||||
|
||||
14. Termination
|
||||
Without prejudice to any other rights, Nordic may cancel this Agreement if Licensee does not abide by the terms and conditions of this
|
||||
Agreement. Upon termination Licensee must promptly cease the use of the License and destroy all copies of the Licensed Technology and any
|
||||
other material provided by Nordic or its affiliate, or produced by the Licensee in connection with the Agreement or the Licensed Technology.
|
||||
|
||||
15. Third party beneficiaries
|
||||
Nordic’s licensors are intended third party beneficiaries under this Agreement.
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,58 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PERIPHERALNAMES_H
|
||||
#define MBED_PERIPHERALNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define STDIO_UART_TX TX_PIN_NUMBER
|
||||
#define STDIO_UART_RX RX_PIN_NUMBER
|
||||
#define STDIO_UART UART_0
|
||||
|
||||
typedef enum {
|
||||
UART_0 = (int)NRF_UART0_BASE
|
||||
} UARTName;
|
||||
|
||||
|
||||
typedef enum {
|
||||
SPI_0 = (int)NRF_SPI0_BASE,
|
||||
SPI_1 = (int)NRF_SPI1_BASE,
|
||||
SPIS = (int)NRF_SPIS1_BASE
|
||||
} SPIName;
|
||||
|
||||
typedef enum {
|
||||
PWM_1 = 0,
|
||||
PWM_2
|
||||
} PWMName;
|
||||
|
||||
typedef enum {
|
||||
I2C_0 = (int)NRF_TWI0_BASE,
|
||||
I2C_1 = (int)NRF_TWI1_BASE
|
||||
} I2CName;
|
||||
|
||||
typedef enum {
|
||||
ADC0_0 = (int)NRF_ADC_BASE
|
||||
} ADCName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,177 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define PORT_SHIFT 3
|
||||
|
||||
typedef enum {
|
||||
p0 = 0,
|
||||
p1 = 1,
|
||||
p2 = 2,
|
||||
p3 = 3,
|
||||
p4 = 4,
|
||||
p5 = 5,
|
||||
p6 = 6,
|
||||
p7 = 7,
|
||||
p8 = 8,
|
||||
p9 = 9,
|
||||
p10 = 10,
|
||||
p11 = 11,
|
||||
p12 = 12,
|
||||
p13 = 13,
|
||||
p14 = 14,
|
||||
p15 = 15,
|
||||
p16 = 16,
|
||||
p17 = 17,
|
||||
p18 = 18,
|
||||
p19 = 19,
|
||||
p20 = 20,
|
||||
p21 = 21,
|
||||
p22 = 22,
|
||||
p23 = 23,
|
||||
p24 = 24,
|
||||
p25 = 25,
|
||||
p26 = 26,
|
||||
p27 = 27,
|
||||
p28 = 28,
|
||||
p29 = 29,
|
||||
p30 = 30,
|
||||
// p31=31,
|
||||
|
||||
P0_0 = p0,
|
||||
P0_1 = p1,
|
||||
P0_2 = p2,
|
||||
P0_3 = p3,
|
||||
P0_4 = p4,
|
||||
P0_5 = p5,
|
||||
P0_6 = p6,
|
||||
P0_7 = p7,
|
||||
|
||||
P0_8 = p8,
|
||||
P0_9 = p9,
|
||||
P0_10 = p10,
|
||||
P0_11 = p11,
|
||||
P0_12 = p12,
|
||||
P0_13 = p13,
|
||||
P0_14 = p14,
|
||||
P0_15 = p15,
|
||||
|
||||
P0_16 = p16,
|
||||
P0_17 = p17,
|
||||
P0_18 = p18,
|
||||
P0_19 = p19,
|
||||
P0_20 = p20,
|
||||
P0_21 = p21,
|
||||
P0_22 = p22,
|
||||
P0_23 = p23,
|
||||
|
||||
P0_24 = p24,
|
||||
P0_25 = p25,
|
||||
P0_26 = p26,
|
||||
P0_27 = p27,
|
||||
P0_28 = p28,
|
||||
P0_29 = p29,
|
||||
P0_30 = p30,
|
||||
|
||||
LED1 = p30,
|
||||
LED2 = p14,
|
||||
LED3 = p15,
|
||||
LED4 = p16,
|
||||
|
||||
RX_PIN_NUMBER = p7,
|
||||
TX_PIN_NUMBER = p8,
|
||||
CTS_PIN_NUMBER = p26,
|
||||
RTS_PIN_NUMBER = p27,
|
||||
|
||||
// mBed interface Pins
|
||||
USBTX = TX_PIN_NUMBER,
|
||||
USBRX = RX_PIN_NUMBER,
|
||||
|
||||
SPI_PSELMOSI0 = p25,
|
||||
SPI_PSELMISO0 = p28,
|
||||
SPI_PSELSS0 = p24,
|
||||
SPI_PSELSCK0 = p29,
|
||||
|
||||
SPI_PSELMOSI1 = p12,
|
||||
SPI_PSELMISO1 = p13,
|
||||
SPI_PSELSS1 = p14,
|
||||
SPI_PSELSCK1 = p15,
|
||||
|
||||
SPIS_PSELMOSI = p12,
|
||||
SPIS_PSELMISO = p13,
|
||||
SPIS_PSELSS = p14,
|
||||
SPIS_PSELSCK = p15,
|
||||
|
||||
I2C_SDA0 = p5,
|
||||
I2C_SCL0 = p6,
|
||||
|
||||
I2C_SDA1 = p13,
|
||||
I2C_SCL1 = p15,
|
||||
|
||||
D0 = p7,
|
||||
D1 = p8,
|
||||
D2 = p9,
|
||||
D3 = p10,
|
||||
D4 = p11,
|
||||
D5 = p12,
|
||||
D6 = p13,
|
||||
D7 = p17,
|
||||
|
||||
D8 = p18,
|
||||
D9 = p23,
|
||||
D10 = p24,
|
||||
D11 = p25,
|
||||
D12 = p28,
|
||||
D13 = p29,
|
||||
|
||||
D14 = p5,
|
||||
D15 = p6,
|
||||
|
||||
A0 = p1,
|
||||
A1 = p2,
|
||||
A2 = p3,
|
||||
A3 = p4,
|
||||
A4 = p5,
|
||||
A5 = p6,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullDown = 1,
|
||||
PullUp = 3,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,130 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2015 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define PORT_SHIFT 3
|
||||
|
||||
typedef enum {
|
||||
NC = (int)0xFFFFFFFF,
|
||||
p0 = 0,
|
||||
p1 = 1,
|
||||
p2 = 2,
|
||||
p3 = 3,
|
||||
p4 = 4,
|
||||
p5 = 5,
|
||||
p6 = 6,
|
||||
p7 = 7,
|
||||
p8 = 8,
|
||||
p9 = 9,
|
||||
p10 = 10,
|
||||
p11 = 11,
|
||||
p12 = 12,
|
||||
p13 = 13,
|
||||
p14 = 14,
|
||||
p15 = 15,
|
||||
p16 = 16,
|
||||
p17 = 17,
|
||||
p18 = 18,
|
||||
p19 = 19,
|
||||
p20 = 20,
|
||||
p21 = 21,
|
||||
p22 = 22,
|
||||
p23 = 23,
|
||||
p24 = 24,
|
||||
p25 = 25,
|
||||
p26 = 26,
|
||||
p27 = 27,
|
||||
p28 = 28,
|
||||
p29 = 29,
|
||||
p30 = 30,
|
||||
p31 = 31,
|
||||
|
||||
LED1 = p4,
|
||||
LED2 = p5,
|
||||
LED3 = p6,
|
||||
LED4 = p13,
|
||||
|
||||
BUTTON0 = p16,
|
||||
BUTTON1 = p17,
|
||||
|
||||
RX_PIN_NUMBER = p23,
|
||||
TX_PIN_NUMBER = p25,
|
||||
|
||||
// mBed interface Pins
|
||||
USBTX = TX_PIN_NUMBER,
|
||||
USBRX = RX_PIN_NUMBER,
|
||||
|
||||
SPI_PSELMOSI0 = p24,
|
||||
SPI_PSELMISO0 = p29,
|
||||
SPI_PSELSS0 = p30,
|
||||
SPI_PSELSCK0 = p21,
|
||||
|
||||
SPIS_PSELMOSI = p24,
|
||||
SPIS_PSELMISO = p29,
|
||||
SPIS_PSELSS = p30,
|
||||
SPIS_PSELSCK = p21,
|
||||
|
||||
I2C_SDA0 = p22,
|
||||
I2C_SCL0 = p20,
|
||||
|
||||
A0 = p26,
|
||||
A1 = p27,
|
||||
A2 = p4,
|
||||
A3 = p5,
|
||||
A4 = p6,
|
||||
|
||||
SWIO = p19,
|
||||
VERF0 = p0,
|
||||
|
||||
// SPI for controlling internal flash, don't use it.
|
||||
FLASH_SPIMOSI = 15,
|
||||
FLASH_SPIMISO = 9,
|
||||
FLASH_SPICS = 28,
|
||||
FLASH_SPICLK = 11,
|
||||
// Not connected
|
||||
CTS_PIN_NUMBER= NC,
|
||||
RTS_PIN_NUMBER= NC,
|
||||
SPI_PSELMOSI1 = NC,
|
||||
SPI_PSELMISO1 = NC,
|
||||
SPI_PSELSS1 = NC,
|
||||
SPI_PSELSCK1 = NC,
|
||||
A5 = NC
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullDown = 1,
|
||||
PullUp = 3,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
|
||||
// Check the 'features' section of the target description in 'targets.json' for more details.
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -1,128 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
/* No init flash in this version, 2015/10/27 */
|
||||
#if 0
|
||||
#define SPIM1_SCK_PIN 11u /**< SPI clock GPIO pin number. */
|
||||
#define SPIM1_MOSI_PIN 15u /**< SPI Master Out Slave In GPIO pin number. */
|
||||
#define SPIM1_MISO_PIN 9u /**< SPI Master In Slave Out GPIO pin number. */
|
||||
#define SPIM1_SS_PIN 28u /**< SPI Slave Select GPIO pin number. */
|
||||
|
||||
#define CMD_POWER_UP (0xAB)
|
||||
#define CMD_POWER_DOWN (0xB9)
|
||||
|
||||
void flash_init(void)
|
||||
{
|
||||
NRF_GPIO->PIN_CNF[SPIM1_MOSI_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_GPIO->PIN_CNF[SPIM1_MISO_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_GPIO->PIN_CNF[SPIM1_SCK_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
|
||||
|
||||
NRF_GPIO->PIN_CNF[SPIM1_SS_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
//cs = 1;
|
||||
NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos);
|
||||
|
||||
NRF_SPI1->ENABLE = 1;
|
||||
NRF_SPI1->PSELSCK = SPIM1_SCK_PIN;
|
||||
NRF_SPI1->PSELMOSI = SPIM1_MISO_PIN;
|
||||
NRF_SPI1->PSELMISO = SPIM1_MOSI_PIN;
|
||||
//spi.frequency(1000000);
|
||||
NRF_SPI1->FREQUENCY = 0x10000000; //1MHz
|
||||
|
||||
//spi.format(8,0);
|
||||
uint32_t config_mode = 0;
|
||||
config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos); //mode 0
|
||||
NRF_SPI1->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos));
|
||||
//cs = 0;
|
||||
NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN28_Clear << GPIO_OUTCLR_PIN28_Pos);
|
||||
//spi.write(CMD_POWER_UP);
|
||||
while (!NRF_SPI1->EVENTS_READY == 0) {
|
||||
}
|
||||
NRF_SPI1->TXD = (uint32_t)CMD_POWER_UP;
|
||||
while (!NRF_SPI1->EVENTS_READY == 1) {
|
||||
}
|
||||
NRF_SPI1->EVENTS_READY = 0;
|
||||
NRF_SPI1->RXD;
|
||||
//wait_ms(30);
|
||||
// Deselect the device
|
||||
//cs = 1;
|
||||
NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos);
|
||||
|
||||
}
|
||||
|
||||
void flash_powerDown(void)
|
||||
{
|
||||
NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN28_Clear << GPIO_OUTCLR_PIN28_Pos);
|
||||
//spi.write(CMD_POWER_DOWN);
|
||||
while (!NRF_SPI1->EVENTS_READY == 0) {
|
||||
}
|
||||
NRF_SPI1->TXD = (uint32_t)CMD_POWER_DOWN;
|
||||
while (!NRF_SPI1->EVENTS_READY == 1) {
|
||||
}
|
||||
NRF_SPI1->EVENTS_READY = 0;
|
||||
NRF_SPI1->RXD;
|
||||
NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos);
|
||||
|
||||
//wait for sleep
|
||||
//wait_us(3);
|
||||
}
|
||||
/* No init flash in this version, 2015/10/27 */
|
||||
#endif
|
||||
|
||||
void mbed_sdk_init()
|
||||
{
|
||||
// Default SWIO setting, pull SWIO(p19) to low for turning antenna switch to BLE radiated path
|
||||
NRF_GPIO->PIN_CNF[19] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
|
||||
NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN19_Clear << GPIO_OUTCLR_PIN19_Pos);
|
||||
|
||||
// Config External Crystal to 32MHz
|
||||
NRF_CLOCK->XTALFREQ = 0x00;
|
||||
NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
|
||||
NRF_CLOCK->TASKS_HFCLKSTART = 1;
|
||||
while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0)
|
||||
{// Do nothing.
|
||||
}
|
||||
|
||||
/* No init flash in this version, 2015/10/27 */
|
||||
// flash_init();
|
||||
//
|
||||
// //nrf_delay_ms(10);
|
||||
// flash_powerDown();
|
||||
/* No init flash in this version, 2015/10/27 */
|
||||
|
||||
}
|
||||
|
|
@ -1,71 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "rtc_api.h"
|
||||
|
||||
|
||||
#define LFCLK_FREQUENCY (32768UL)
|
||||
#define RTC0_COUNTER_PRESCALER ((LFCLK_FREQUENCY/8) - 1)
|
||||
#define COMPARE_COUNTERTIME (691200UL) //86400 x 8
|
||||
|
||||
|
||||
time_t initTime;
|
||||
|
||||
void rtc_init(void) {
|
||||
|
||||
NVIC_EnableIRQ(RTC0_IRQn); // Enable Interrupt for the RTC in the core.
|
||||
//NRF_RTC0->TASKS_STOP =1;
|
||||
NRF_RTC0->PRESCALER = RTC0_COUNTER_PRESCALER; // Set prescaler to a TICK of RTC_FREQUENCY.
|
||||
NRF_RTC0->CC[0] = COMPARE_COUNTERTIME; // Compare0 after approx COMPARE_COUNTERTIME seconds.
|
||||
|
||||
// Enable COMPARE0 event and COMPARE0 interrupt:
|
||||
NRF_RTC0->EVTENSET = RTC_EVTENSET_COMPARE0_Msk;
|
||||
NRF_RTC0->INTENSET = RTC_INTENSET_COMPARE0_Msk;
|
||||
NRF_RTC0->TASKS_START = 1;
|
||||
}
|
||||
|
||||
void rtc_free(void) {
|
||||
// [TODO]
|
||||
}
|
||||
|
||||
/*
|
||||
* Little check routine to see if the RTC has been enabled
|
||||
*
|
||||
* Clock Control Register
|
||||
* RTC_CCR[0] : 0 = Disabled, 1 = Enabled
|
||||
*
|
||||
*/
|
||||
int rtc_isenabled(void) {
|
||||
// [TODO] return(((NRF_RTC0->TASKS_START) & 0x01) != 0);
|
||||
}
|
||||
|
||||
time_t rtc_read(void) {
|
||||
|
||||
time_t t = initTime;
|
||||
t += (86400*NRF_RTC0->EVENTS_COMPARE[0]);
|
||||
t += (int)((NRF_RTC0->COUNTER)/8);
|
||||
return(t);
|
||||
}
|
||||
|
||||
void rtc_write(time_t t) {
|
||||
// Convert the time in to a tm
|
||||
|
||||
// Pause clock, and clear counter register (clears us count)
|
||||
NRF_RTC0->TASKS_STOP = 1;
|
||||
|
||||
initTime = t;
|
||||
// Restart clock
|
||||
NRF_RTC0->TASKS_START = 1;
|
||||
}
|
||||
|
|
@ -1,153 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define PORT_SHIFT 3
|
||||
|
||||
typedef enum {
|
||||
p0 = 0,
|
||||
p1 = 1,
|
||||
p2 = 2,
|
||||
p3 = 3,
|
||||
p4 = 4,
|
||||
p5 = 5,
|
||||
p6 = 6,
|
||||
p7 = 7,
|
||||
p8 = 8,
|
||||
p9 = 9,
|
||||
p10 = 10,
|
||||
p11 = 11,
|
||||
p12 = 12,
|
||||
p13 = 13,
|
||||
p14 = 14,
|
||||
p15 = 15,
|
||||
p16 = 16,
|
||||
p17 = 17,
|
||||
p18 = 18,
|
||||
p19 = 19,
|
||||
p20 = 20,
|
||||
p21 = 21,
|
||||
p22 = 22,
|
||||
p23 = 23,
|
||||
p24 = 24,
|
||||
p25 = 25,
|
||||
p26 = 26,
|
||||
p27 = 27,
|
||||
p28 = 28,
|
||||
p29 = 29,
|
||||
p30 = 30,
|
||||
// p31=31,
|
||||
|
||||
P0_0 = p0,
|
||||
P0_1 = p1,
|
||||
P0_2 = p2,
|
||||
P0_3 = p3,
|
||||
P0_4 = p4,
|
||||
P0_5 = p5,
|
||||
P0_6 = p6,
|
||||
P0_7 = p7,
|
||||
|
||||
P0_8 = p8,
|
||||
P0_9 = p9,
|
||||
P0_10 = p10,
|
||||
P0_11 = p11,
|
||||
P0_12 = p12,
|
||||
P0_13 = p13,
|
||||
P0_14 = p14,
|
||||
P0_15 = p15,
|
||||
|
||||
P0_16 = p16,
|
||||
P0_17 = p17,
|
||||
P0_18 = p18,
|
||||
P0_19 = p19,
|
||||
P0_20 = p20,
|
||||
P0_21 = p21,
|
||||
P0_22 = p22,
|
||||
P0_23 = p23,
|
||||
|
||||
P0_24 = p24,
|
||||
P0_25 = p25,
|
||||
P0_26 = p26,
|
||||
P0_27 = p27,
|
||||
P0_28 = p28,
|
||||
P0_29 = p29,
|
||||
P0_30 = p30,
|
||||
|
||||
LED1 = p18,
|
||||
LED2 = p19,
|
||||
LED3 = p18,
|
||||
LED4 = p19,
|
||||
|
||||
BUTTON1 = p16,
|
||||
BUTTON2 = p17,
|
||||
|
||||
RX_PIN_NUMBER = p11,
|
||||
TX_PIN_NUMBER = p9,
|
||||
CTS_PIN_NUMBER = p10,
|
||||
RTS_PIN_NUMBER = p8,
|
||||
|
||||
// mBed interface Pins
|
||||
USBTX = TX_PIN_NUMBER,
|
||||
USBRX = RX_PIN_NUMBER,
|
||||
|
||||
SPI_PSELMOSI0 = p20,
|
||||
SPI_PSELMISO0 = p22,
|
||||
SPI_PSELSS0 = p24,
|
||||
SPI_PSELSCK0 = p25,
|
||||
|
||||
SPI_PSELMOSI1 = p12,
|
||||
SPI_PSELMISO1 = p13,
|
||||
SPI_PSELSS1 = p14,
|
||||
SPI_PSELSCK1 = p15,
|
||||
|
||||
SPIS_PSELMOSI = p12,
|
||||
SPIS_PSELMISO = p13,
|
||||
SPIS_PSELSS = p14,
|
||||
SPIS_PSELSCK = p15,
|
||||
|
||||
I2C_SDA0 = p22,
|
||||
I2C_SCL0 = p20,
|
||||
|
||||
I2C_SDA1 = p13,
|
||||
I2C_SCL1 = p15,
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullDown = 1,
|
||||
PullUp = 3,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,153 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define PORT_SHIFT 3
|
||||
|
||||
typedef enum {
|
||||
p0 = 0,
|
||||
p1 = 1,
|
||||
p2 = 2,
|
||||
p3 = 3,
|
||||
p4 = 4,
|
||||
p5 = 5,
|
||||
p6 = 6,
|
||||
p7 = 7,
|
||||
p8 = 8,
|
||||
p9 = 9,
|
||||
p10 = 10,
|
||||
p11 = 11,
|
||||
p12 = 12,
|
||||
p13 = 13,
|
||||
p14 = 14,
|
||||
p15 = 15,
|
||||
p16 = 16,
|
||||
p17 = 17,
|
||||
p18 = 18,
|
||||
p19 = 19,
|
||||
p20 = 20,
|
||||
p21 = 21,
|
||||
p22 = 22,
|
||||
p23 = 23,
|
||||
p24 = 24,
|
||||
p25 = 25,
|
||||
p26 = 26,
|
||||
p27 = 27,
|
||||
p28 = 28,
|
||||
p29 = 29,
|
||||
p30 = 30,
|
||||
// p31=31,
|
||||
|
||||
P0_0 = p0,
|
||||
P0_1 = p1,
|
||||
P0_2 = p2,
|
||||
P0_3 = p3,
|
||||
P0_4 = p4,
|
||||
P0_5 = p5,
|
||||
P0_6 = p6,
|
||||
P0_7 = p7,
|
||||
|
||||
P0_8 = p8,
|
||||
P0_9 = p9,
|
||||
P0_10 = p10,
|
||||
P0_11 = p11,
|
||||
P0_12 = p12,
|
||||
P0_13 = p13,
|
||||
P0_14 = p14,
|
||||
P0_15 = p15,
|
||||
|
||||
P0_16 = p16,
|
||||
P0_17 = p17,
|
||||
P0_18 = p18,
|
||||
P0_19 = p19,
|
||||
P0_20 = p20,
|
||||
P0_21 = p21,
|
||||
P0_22 = p22,
|
||||
P0_23 = p23,
|
||||
|
||||
P0_24 = p24,
|
||||
P0_25 = p25,
|
||||
P0_26 = p26,
|
||||
P0_27 = p27,
|
||||
P0_28 = p28,
|
||||
P0_29 = p29,
|
||||
P0_30 = p30,
|
||||
|
||||
LED1 = p18,
|
||||
LED2 = p19,
|
||||
LED3 = p18,
|
||||
LED4 = p19,
|
||||
|
||||
BUTTON1 = p16,
|
||||
BUTTON2 = p17,
|
||||
|
||||
RX_PIN_NUMBER = p11,
|
||||
TX_PIN_NUMBER = p9,
|
||||
CTS_PIN_NUMBER = p10,
|
||||
RTS_PIN_NUMBER = p8,
|
||||
|
||||
// mBed interface Pins
|
||||
USBTX = TX_PIN_NUMBER,
|
||||
USBRX = RX_PIN_NUMBER,
|
||||
|
||||
SPI_PSELMOSI0 = p20,
|
||||
SPI_PSELMISO0 = p22,
|
||||
SPI_PSELSS0 = p24,
|
||||
SPI_PSELSCK0 = p25,
|
||||
|
||||
SPI_PSELMOSI1 = p12,
|
||||
SPI_PSELMISO1 = p13,
|
||||
SPI_PSELSS1 = p14,
|
||||
SPI_PSELSCK1 = p15,
|
||||
|
||||
SPIS_PSELMOSI = p12,
|
||||
SPIS_PSELMISO = p13,
|
||||
SPIS_PSELSS = p14,
|
||||
SPIS_PSELSCK = p15,
|
||||
|
||||
I2C_SDA0 = p22,
|
||||
I2C_SCL0 = p20,
|
||||
|
||||
I2C_SDA1 = p13,
|
||||
I2C_SCL1 = p15,
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullDown = 1,
|
||||
PullUp = 3,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
// The 'provides' section in 'target.json' is now used to create the device's hardware preprocessor switches.
|
||||
// Check the 'provides' section of the target description in 'targets.json' for more details.
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -1,106 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define PORT_SHIFT 3
|
||||
|
||||
typedef enum {
|
||||
p0 = 0,
|
||||
p1 = 1,
|
||||
p2 = 2,
|
||||
p3 = 3,
|
||||
p5 = 5,
|
||||
p8 = 8,
|
||||
p9 = 9,
|
||||
p11 = 11,
|
||||
p12 = 12,
|
||||
p15 = 15,
|
||||
p16 = 16,
|
||||
p18 = 18,
|
||||
p20 = 20,
|
||||
p21 = 21,
|
||||
p24 = 24,
|
||||
|
||||
P0_0 = p0,
|
||||
P0_1 = p1,
|
||||
P0_2 = p2,
|
||||
P0_3 = p3,
|
||||
P0_5 = p5,
|
||||
|
||||
P0_8 = p8,
|
||||
P0_9 = p9,
|
||||
P0_11 = p11,
|
||||
P0_12 = p12,
|
||||
P0_15 = p15,
|
||||
|
||||
P0_16 = p16,
|
||||
P0_18 = p18,
|
||||
P0_20 = p20,
|
||||
P0_21 = p21,
|
||||
|
||||
P0_24 = p24,
|
||||
|
||||
LED1 = p16,
|
||||
LED2 = p12,
|
||||
LED3 = p15,
|
||||
LEDR = LED1,
|
||||
LEDG = LED2,
|
||||
LEDB = LED3,
|
||||
|
||||
BUTTON1 = p8,
|
||||
BUTTON2 = p18,
|
||||
|
||||
RX_PIN_NUMBER = p21,
|
||||
TX_PIN_NUMBER = p24,
|
||||
CTS_PIN_NUMBER = p0,
|
||||
RTS_PIN_NUMBER = p20,
|
||||
|
||||
SPI_PSELMOSI0 = p2,
|
||||
SPI_PSELMISO0 = p5,
|
||||
SPI_PSELSS0 = p1,
|
||||
SPI_PSELSCK0 = p3,
|
||||
|
||||
I2C_SDA0 = p9,
|
||||
I2C_SCL0 = p11,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullDown = 1,
|
||||
PullUp = 3,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,57 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
#define DEVICE_PORTIN 1
|
||||
#define DEVICE_PORTOUT 1
|
||||
#define DEVICE_PORTINOUT 1
|
||||
|
||||
#define DEVICE_INTERRUPTIN 1
|
||||
|
||||
#define DEVICE_ANALOGIN 1
|
||||
#define DEVICE_ANALOGOUT 0
|
||||
|
||||
#define DEVICE_SERIAL 1
|
||||
|
||||
#define DEVICE_I2C 1
|
||||
#define DEVICE_I2CSLAVE 0
|
||||
|
||||
#define DEVICE_SPI 1
|
||||
#define DEVICE_SPISLAVE 1
|
||||
|
||||
#define DEVICE_CAN 0
|
||||
|
||||
#define DEVICE_RTC 0
|
||||
|
||||
#define DEVICE_ETHERNET 0
|
||||
|
||||
#define DEVICE_PWMOUT 1
|
||||
|
||||
#define DEVICE_SEMIHOST 0
|
||||
#define DEVICE_LOCALFILESYSTEM 0
|
||||
|
||||
#define DEVICE_SLEEP 1
|
||||
|
||||
#define DEVICE_DEBUG_AWARENESS 0
|
||||
|
||||
#define DEVICE_STDIO_MESSAGES 0
|
||||
|
||||
#define DEVICE_ERROR_PATTERN 1
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -1,150 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define PORT_SHIFT 3
|
||||
|
||||
typedef enum {
|
||||
p0 = 0,
|
||||
p1 = 1,
|
||||
p2 = 2,
|
||||
p3 = 3,
|
||||
p4 = 4,
|
||||
p5 = 5,
|
||||
p6 = 6,
|
||||
p7 = 7,
|
||||
p8 = 8,
|
||||
p9 = 9,
|
||||
p10 = 10,
|
||||
p11 = 11,
|
||||
p12 = 12,
|
||||
p13 = 13,
|
||||
p14 = 14,
|
||||
p15 = 15,
|
||||
p16 = 16,
|
||||
p17 = 17,
|
||||
p18 = 18,
|
||||
p19 = 19,
|
||||
p20 = 20,
|
||||
p21 = 21,
|
||||
p22 = 22,
|
||||
p23 = 23,
|
||||
p24 = 24,
|
||||
p25 = 25,
|
||||
p26 = 26,
|
||||
p27 = 27,
|
||||
p28 = 28,
|
||||
p29 = 29,
|
||||
p30 = 30,
|
||||
p31 = 31,
|
||||
p32 = 32,
|
||||
p33 = 33,
|
||||
p34 = 34,
|
||||
p35 = 35,
|
||||
// p31=31,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF,
|
||||
|
||||
|
||||
P0_0 = p0,
|
||||
P0_1 = p1,
|
||||
P0_2 = p2,
|
||||
P0_3 = p3,
|
||||
P0_4 = p4,
|
||||
P0_5 = p5,
|
||||
P0_6 = p6,
|
||||
P0_7 = p7,
|
||||
|
||||
P0_8 = p8,
|
||||
P0_9 = p9,
|
||||
P0_10 = p10,
|
||||
P0_11 = p11,
|
||||
P0_12 = p12,
|
||||
P0_13 = p13,
|
||||
P0_14 = p14,
|
||||
P0_15 = p15,
|
||||
|
||||
P0_16 = p16,
|
||||
P0_17 = p17,
|
||||
P0_18 = p18,
|
||||
P0_19 = p19,
|
||||
P0_20 = p20,
|
||||
P0_21 = p21,
|
||||
P0_22 = p22,
|
||||
P0_23 = p23,
|
||||
|
||||
P0_24 = p24,
|
||||
P0_25 = p25,
|
||||
P0_26 = p26,
|
||||
P0_27 = p27,
|
||||
P0_28 = p28,
|
||||
P0_29 = p29,
|
||||
P0_30 = p30,
|
||||
|
||||
LED = p30,
|
||||
LED1 = p30,
|
||||
LED2 = p0,
|
||||
LED3 = p8,
|
||||
LED4 = NC,
|
||||
|
||||
BUTTON1 = p29,
|
||||
BUTTON2 = p17,
|
||||
|
||||
|
||||
RX_PIN_NUMBER = p2,
|
||||
TX_PIN_NUMBER = p3,
|
||||
CTS_PIN_NUMBER = p11,
|
||||
RTS_PIN_NUMBER = p21,
|
||||
|
||||
// mBed interface Pins
|
||||
USBTX = TX_PIN_NUMBER,
|
||||
USBRX = RX_PIN_NUMBER,
|
||||
|
||||
SPIS_PSELMOSI = p12,
|
||||
SPIS_PSELMISO = p6,
|
||||
SPIS_PSELSCK = p9,
|
||||
|
||||
I2C_SDA0 = p17,
|
||||
I2C_SCL0 = p18,
|
||||
|
||||
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullDown = 1,
|
||||
PullUp = 3,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
|
||||
// Check the 'features' section of the target description in 'targets.json' for more details.
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
|
||||
// Check the 'features' section of the target description in 'targets.json' for more details.
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -1,145 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define PORT_SHIFT 3
|
||||
|
||||
typedef enum {
|
||||
p0 = 0,
|
||||
p1 = 1,
|
||||
p2 = 2,
|
||||
p3 = 3,
|
||||
p4 = 4,
|
||||
p5 = 5,
|
||||
p6 = 6,
|
||||
p7 = 7,
|
||||
p8 = 8,
|
||||
p9 = 9,
|
||||
p10 = 10,
|
||||
p11 = 11,
|
||||
p12 = 12,
|
||||
p13 = 13,
|
||||
p14 = 14,
|
||||
p15 = 15,
|
||||
p16 = 16,
|
||||
p17 = 17,
|
||||
p18 = 18,
|
||||
p19 = 19,
|
||||
p20 = 20,
|
||||
p21 = 21,
|
||||
p22 = 22,
|
||||
p23 = 23,
|
||||
p24 = 24,
|
||||
p25 = 25,
|
||||
p28 = 28,
|
||||
p29 = 29,
|
||||
p30 = 30,
|
||||
|
||||
P0_0 = p0,
|
||||
P0_1 = p1,
|
||||
P0_2 = p2,
|
||||
P0_3 = p3,
|
||||
P0_4 = p4,
|
||||
P0_5 = p5,
|
||||
P0_6 = p6,
|
||||
P0_7 = p7,
|
||||
|
||||
P0_8 = p8,
|
||||
P0_9 = p9,
|
||||
P0_10 = p10,
|
||||
P0_11 = p11,
|
||||
P0_12 = p12,
|
||||
P0_13 = p13,
|
||||
P0_14 = p14,
|
||||
P0_15 = p15,
|
||||
|
||||
P0_16 = p16,
|
||||
P0_17 = p17,
|
||||
P0_18 = p18,
|
||||
P0_19 = p19,
|
||||
P0_20 = p20,
|
||||
P0_21 = p21,
|
||||
P0_22 = p22,
|
||||
P0_23 = p23,
|
||||
|
||||
P0_24 = p24,
|
||||
P0_25 = p25,
|
||||
P0_28 = p28,
|
||||
P0_29 = p29,
|
||||
|
||||
LED1 = p21,
|
||||
LED2 = p22,
|
||||
LED3 = p23,
|
||||
LED4 = p23,
|
||||
LEDR = LED1,
|
||||
LEDG = LED2,
|
||||
LEDB = LED3,
|
||||
|
||||
RX_PIN_NUMBER = p11,
|
||||
TX_PIN_NUMBER = p9,
|
||||
CTS_PIN_NUMBER = p10,
|
||||
RTS_PIN_NUMBER = p8,
|
||||
|
||||
// mBed interface Pins
|
||||
USBTX = TX_PIN_NUMBER,
|
||||
USBRX = RX_PIN_NUMBER,
|
||||
|
||||
SPI_PSELMOSI0 = p15,
|
||||
SPI_PSELMISO0 = p16,
|
||||
SPI_PSELSS0 = p17,
|
||||
SPI_PSELSCK0 = p18,
|
||||
|
||||
SPI_PSELMOSI1 = p15,
|
||||
SPI_PSELMISO1 = p16,
|
||||
SPI_PSELSS1 = p17,
|
||||
SPI_PSELSCK1 = p18,
|
||||
|
||||
SPIS_PSELMOSI = p15,
|
||||
SPIS_PSELMISO = p16,
|
||||
SPIS_PSELSS = p17,
|
||||
SPIS_PSELSCK = p18,
|
||||
|
||||
I2C_SDA0 = p19,
|
||||
I2C_SCL0 = p20,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullDown = 1,
|
||||
PullUp = 3,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
|
||||
// Check the 'features' section of the target description in 'targets.json' for more details.
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -1,198 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define PORT_SHIFT 3
|
||||
|
||||
typedef enum {
|
||||
p0 = 0,
|
||||
p1 = 1,
|
||||
p2 = 2,
|
||||
p3 = 3,
|
||||
p4 = 4,
|
||||
p5 = 5,
|
||||
p6 = 6,
|
||||
p7 = 7,
|
||||
p8 = 8,
|
||||
p9 = 9,
|
||||
p10 = 10,
|
||||
p11 = 11,
|
||||
p12 = 12,
|
||||
p13 = 13,
|
||||
p14 = 14,
|
||||
p15 = 15,
|
||||
p16 = 16,
|
||||
p17 = 17,
|
||||
p18 = 18,
|
||||
p19 = 19,
|
||||
p20 = 20,
|
||||
p21 = 21,
|
||||
p22 = 22,
|
||||
p23 = 23,
|
||||
p24 = 24,
|
||||
p25 = 25,
|
||||
p26 = 26,
|
||||
p27 = 27,
|
||||
p28 = 28,
|
||||
p29 = 29,
|
||||
p30 = 30,
|
||||
|
||||
//NORMAL PINS...
|
||||
P0_0 = p0,
|
||||
P0_1 = p1,
|
||||
P0_2 = p2,
|
||||
P0_3 = p3,
|
||||
P0_4 = p4,
|
||||
P0_5 = p5,
|
||||
P0_6 = p6,
|
||||
P0_7 = p7,
|
||||
|
||||
P0_8 = p8,
|
||||
P0_9 = p9,
|
||||
P0_10 = p10,
|
||||
P0_11 = p11,
|
||||
P0_12 = p12,
|
||||
P0_13 = p13,
|
||||
P0_14 = p14,
|
||||
P0_15 = p15,
|
||||
|
||||
P0_16 = p16,
|
||||
P0_17 = p17,
|
||||
P0_18 = p18,
|
||||
P0_19 = p19,
|
||||
P0_20 = p20,
|
||||
P0_21 = p21,
|
||||
P0_22 = p22,
|
||||
P0_23 = p23,
|
||||
|
||||
P0_24 = p24,
|
||||
P0_25 = p25,
|
||||
P0_26 = p26,
|
||||
P0_27 = p27,
|
||||
P0_28 = p28,
|
||||
P0_29 = p29,
|
||||
P0_30 = p30,
|
||||
|
||||
//PADS
|
||||
PAD3 = p1,
|
||||
PAD2 = p2,
|
||||
PAD1 = p3,
|
||||
|
||||
|
||||
//LED MATRIX COLS
|
||||
COL1 = p4,
|
||||
COL2 = p5,
|
||||
COL3 = p6,
|
||||
COL4 = p7,
|
||||
COL5 = p8,
|
||||
COL6 = p9,
|
||||
COL7 = p10,
|
||||
COL8 = p11,
|
||||
COL9 = p12,
|
||||
|
||||
//LED MATRIX ROWS
|
||||
ROW1 = p13,
|
||||
ROW2 = p14,
|
||||
ROW3 = p15,
|
||||
|
||||
//NORMAL PIN (NO SPECIFIED FUNCTIONALITY)
|
||||
//PIN_16
|
||||
|
||||
// BUTTON A
|
||||
BUTTON_A = p17,
|
||||
|
||||
|
||||
//NORMAL PIN (NO SPECIFIED FUNCTIONALITY)
|
||||
//PIN_18
|
||||
|
||||
//TARGET RESET
|
||||
TGT_NRESET = p19,
|
||||
|
||||
//NORMAL PIN (NO SPECIFIED FUNCTIONALITY)
|
||||
//PIN_20
|
||||
|
||||
//MASTER OUT SLAVE IN
|
||||
MOSI = p21,
|
||||
|
||||
//MASTER IN SLAVE OUT
|
||||
MISO = p22,
|
||||
|
||||
//SERIAL CLOCK
|
||||
SCK = p23,
|
||||
|
||||
// RX AND TX PINS
|
||||
TGT_TX = p24,
|
||||
TGT_RX = p25,
|
||||
|
||||
//BUTTON B
|
||||
BUTTON_B = p26,
|
||||
|
||||
//ACCEL INTERRUPT PINS (MMA8653FC)
|
||||
ACCEL_INT2 = p27,
|
||||
ACCEL_INT1 = p28,
|
||||
|
||||
//MAGENETOMETER INTERRUPT PIN (MAG3110)
|
||||
MAG_INT1 = p29,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF,
|
||||
|
||||
RX_PIN_NUMBER = TGT_RX,
|
||||
TX_PIN_NUMBER = TGT_TX,
|
||||
CTS_PIN_NUMBER = 31, //unused ** REQUIRES A PROPER FIX **
|
||||
RTS_PIN_NUMBER = 31, //unused
|
||||
|
||||
// mBed interface Pins
|
||||
USBTX = TX_PIN_NUMBER,
|
||||
USBRX = RX_PIN_NUMBER,
|
||||
|
||||
LED1 = PAD1,
|
||||
LED2 = PAD2,
|
||||
LED3 = PAD3,
|
||||
LED4 = P0_16,
|
||||
|
||||
//SDA (SERIAL DATA LINE)
|
||||
I2C_SDA0 = p30,
|
||||
|
||||
//SCL (SERIAL CLOCK LINE)
|
||||
I2C_SCL0 = p0
|
||||
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullDown = 1,
|
||||
PullUp = 3,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
|
||||
// Check the 'features' section of the target description in 'targets.json' for more details.
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -1,174 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define PORT_SHIFT 3
|
||||
|
||||
typedef enum {
|
||||
p0 = 0,
|
||||
p1 = 1,
|
||||
p2 = 2,
|
||||
p3 = 3,
|
||||
p4 = 4,
|
||||
p5 = 5,
|
||||
p6 = 6,
|
||||
p7 = 7,
|
||||
p8 = 8,
|
||||
p9 = 9,
|
||||
p10 = 10,
|
||||
p11 = 11,
|
||||
p12 = 12,
|
||||
p13 = 13,
|
||||
p14 = 14,
|
||||
p15 = 15,
|
||||
p16 = 16,
|
||||
p17 = 17,
|
||||
p18 = 18,
|
||||
p19 = 19,
|
||||
p20 = 20,
|
||||
p21 = 21,
|
||||
p22 = 22,
|
||||
p23 = 23,
|
||||
p24 = 24,
|
||||
p25 = 25,
|
||||
p26 = 26,
|
||||
p27 = 27,
|
||||
p28 = 28,
|
||||
p29 = 29,
|
||||
p30 = 30,
|
||||
// p31=31,
|
||||
|
||||
P0_0 = p0,
|
||||
P0_1 = p1,
|
||||
P0_2 = p2,
|
||||
P0_3 = p3,
|
||||
P0_4 = p4,
|
||||
P0_5 = p5,
|
||||
P0_6 = p6,
|
||||
P0_7 = p7,
|
||||
|
||||
P0_8 = p8,
|
||||
P0_9 = p9,
|
||||
P0_10 = p10,
|
||||
P0_11 = p11,
|
||||
P0_12 = p12,
|
||||
P0_13 = p13,
|
||||
P0_14 = p14,
|
||||
P0_15 = p15,
|
||||
|
||||
P0_16 = p16,
|
||||
P0_17 = p17,
|
||||
P0_18 = p18,
|
||||
P0_19 = p19,
|
||||
P0_20 = p20,
|
||||
P0_21 = p21,
|
||||
P0_22 = p22,
|
||||
P0_23 = p23,
|
||||
|
||||
P0_24 = p24,
|
||||
P0_25 = p25,
|
||||
P0_26 = p26,
|
||||
P0_27 = p27,
|
||||
P0_28 = p28,
|
||||
P0_29 = p29,
|
||||
P0_30 = p30,
|
||||
|
||||
LED = p19,
|
||||
LED1 = p19,
|
||||
LED2 = p19,
|
||||
LED3 = p19,
|
||||
LED4 = p19,
|
||||
|
||||
RX_PIN_NUMBER = p11,
|
||||
TX_PIN_NUMBER = p9,
|
||||
CTS_PIN_NUMBER = p10,
|
||||
RTS_PIN_NUMBER = p8,
|
||||
|
||||
// mBed interface Pins
|
||||
USBTX = TX_PIN_NUMBER,
|
||||
USBRX = RX_PIN_NUMBER,
|
||||
|
||||
SPI_PSELMOSI0 = p9,
|
||||
SPI_PSELMISO0 = p11,
|
||||
SPI_PSELSS0 = p10,
|
||||
SPI_PSELSCK0 = p8,
|
||||
|
||||
SPI_PSELMOSI1 = p9,
|
||||
SPI_PSELMISO1 = p11,
|
||||
SPI_PSELSS1 = p10,
|
||||
SPI_PSELSCK1 = p8,
|
||||
|
||||
SPIS_PSELMOSI = p9,
|
||||
SPIS_PSELMISO = p11,
|
||||
SPIS_PSELSS = p10,
|
||||
SPIS_PSELSCK = p8,
|
||||
|
||||
I2C_SDA0 = p10,
|
||||
I2C_SCL0 = p8,
|
||||
|
||||
D0 = p11,
|
||||
D1 = p9,
|
||||
D2 = p10,
|
||||
D3 = p8,
|
||||
D4 = p28,
|
||||
D5 = p29,
|
||||
D6 = p15,
|
||||
D7 = p7,
|
||||
|
||||
D13 = p19,
|
||||
|
||||
A0 = p1,
|
||||
A1 = p2,
|
||||
A2 = p3,
|
||||
A3 = p4,
|
||||
A4 = p5,
|
||||
A5 = p6,
|
||||
|
||||
D19 = A0,
|
||||
D20 = A1,
|
||||
D21 = A2,
|
||||
D22 = A3,
|
||||
D23 = A4,
|
||||
D24 = A5,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullDown = 1,
|
||||
PullUp = 3,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
|
||||
// Check the 'features' section of the target description in 'targets.json' for more details.
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -1,193 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define PORT_SHIFT 3
|
||||
|
||||
typedef enum {
|
||||
p0 = 0,
|
||||
p1 = 1,
|
||||
p2 = 2,
|
||||
p3 = 3,
|
||||
p4 = 4,
|
||||
p5 = 5,
|
||||
p6 = 6,
|
||||
p7 = 7,
|
||||
p8 = 8,
|
||||
p9 = 9,
|
||||
p10 = 10,
|
||||
p11 = 11,
|
||||
p12 = 12,
|
||||
p13 = 13,
|
||||
p14 = 14,
|
||||
p15 = 15,
|
||||
p16 = 16,
|
||||
p17 = 17,
|
||||
p18 = 18,
|
||||
p19 = 19,
|
||||
p20 = 20,
|
||||
p21 = 21,
|
||||
p22 = 22,
|
||||
p23 = 23,
|
||||
p24 = 24,
|
||||
p25 = 25,
|
||||
p26 = 26,
|
||||
p27 = 27,
|
||||
p28 = 28,
|
||||
p29 = 29,
|
||||
p30 = 30,
|
||||
// p31=31,
|
||||
|
||||
P0_0 = p0,
|
||||
P0_1 = p1,
|
||||
P0_2 = p2,
|
||||
P0_3 = p3,
|
||||
P0_4 = p4,
|
||||
P0_5 = p5,
|
||||
P0_6 = p6,
|
||||
P0_7 = p7,
|
||||
|
||||
P0_8 = p8,
|
||||
P0_9 = p9,
|
||||
P0_10 = p10,
|
||||
P0_11 = p11,
|
||||
P0_12 = p12,
|
||||
P0_13 = p13,
|
||||
P0_14 = p14,
|
||||
P0_15 = p15,
|
||||
|
||||
P0_16 = p16,
|
||||
P0_17 = p17,
|
||||
P0_18 = p18,
|
||||
P0_19 = p19,
|
||||
P0_20 = p20,
|
||||
P0_21 = p21,
|
||||
P0_22 = p22,
|
||||
P0_23 = p23,
|
||||
|
||||
P0_24 = p24,
|
||||
P0_25 = p25,
|
||||
P0_26 = p26,
|
||||
P0_27 = p27,
|
||||
P0_28 = p28,
|
||||
P0_29 = p29,
|
||||
P0_30 = p30,
|
||||
|
||||
LED1 = p15,
|
||||
LED2 = p15,
|
||||
LED3 = p15,
|
||||
LED4 = p15,
|
||||
|
||||
BUTTON1 = p16,
|
||||
BUTTON2 = p17,
|
||||
|
||||
RX_PIN_NUMBER = p11,
|
||||
TX_PIN_NUMBER = p9,
|
||||
CTS_PIN_NUMBER = p10,
|
||||
RTS_PIN_NUMBER = p8,
|
||||
|
||||
// mBed interface Pins
|
||||
USBTX = TX_PIN_NUMBER,
|
||||
USBRX = RX_PIN_NUMBER,
|
||||
|
||||
SPI_PSELMOSI0 = p20,
|
||||
SPI_PSELMISO0 = p22,
|
||||
SPI_PSELSS0 = p14,
|
||||
SPI_PSELSCK0 = p25,
|
||||
|
||||
SPI_PSELMOSI1 = p20,
|
||||
SPI_PSELMISO1 = p22,
|
||||
SPI_PSELSS1 = p14,
|
||||
SPI_PSELSCK1 = p25,
|
||||
|
||||
SPIS_PSELMOSI = p20,
|
||||
SPIS_PSELMISO = p22,
|
||||
SPIS_PSELSS = p14,
|
||||
SPIS_PSELSCK = p25,
|
||||
|
||||
I2C_SDA0 = p29,
|
||||
I2C_SCL0 = p28,
|
||||
|
||||
/*
|
||||
I2C_SDA1 = p13,
|
||||
I2C_SCL1 = p15,
|
||||
*/
|
||||
|
||||
D0 = p11,
|
||||
D1 = p9,
|
||||
D2 = p10,
|
||||
D3 = p8,
|
||||
D4 = p21,
|
||||
D5 = p23,
|
||||
D6 = p16,
|
||||
D7 = p17,
|
||||
|
||||
D8 = p19,
|
||||
D9 = p18,
|
||||
D10 = p14,
|
||||
D11 = p12,
|
||||
D12 = p13,
|
||||
D13 = p15,
|
||||
|
||||
D14 = p29, // I2C - SDA
|
||||
D15 = p28, // I2C - SCL
|
||||
|
||||
D16 = p25, // SPI - SCK
|
||||
D17 = p22, // SPI - MISO
|
||||
D18 = p20, // SPI - MOSI
|
||||
|
||||
A0 = p1,
|
||||
A1 = p2,
|
||||
A2 = p3,
|
||||
A3 = p4,
|
||||
A4 = p5,
|
||||
A5 = p6,
|
||||
|
||||
D19 = A0,
|
||||
D20 = A1,
|
||||
D21 = A2,
|
||||
D22 = A3,
|
||||
D23 = A4,
|
||||
D24 = A5,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullDown = 1,
|
||||
PullUp = 3,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
|
||||
// Check the 'features' section of the target description in 'targets.json' for more details.
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -1,143 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define PORT_SHIFT 3
|
||||
|
||||
typedef enum {
|
||||
p0 = 0,
|
||||
p1 = 1,
|
||||
p2 = 2,
|
||||
p3 = 3,
|
||||
p4 = 4,
|
||||
p5 = 5,
|
||||
p6 = 6,
|
||||
p7 = 7,
|
||||
p8 = 8,
|
||||
p9 = 9,
|
||||
p10 = 10,
|
||||
p11 = 11,
|
||||
p12 = 12,
|
||||
p13 = 13,
|
||||
p14 = 14,
|
||||
p15 = 15,
|
||||
p16 = 16,
|
||||
p17 = 17,
|
||||
p18 = 18,
|
||||
p19 = 19,
|
||||
p20 = 20,
|
||||
p21 = 21,
|
||||
p22 = 22,
|
||||
p23 = 23,
|
||||
p24 = 24,
|
||||
p25 = 25,
|
||||
p26 = 26,
|
||||
p27 = 27,
|
||||
p28 = 28,
|
||||
p29 = 29,
|
||||
p30 = 30,
|
||||
// p31=31,
|
||||
|
||||
P0_0 = p0,
|
||||
P0_1 = p1,
|
||||
P0_2 = p2,
|
||||
P0_3 = p3,
|
||||
P0_4 = p4,
|
||||
P0_5 = p5,
|
||||
P0_6 = p6,
|
||||
P0_7 = p7,
|
||||
|
||||
P0_8 = p8,
|
||||
P0_9 = p9,
|
||||
P0_10 = p10,
|
||||
P0_11 = p11,
|
||||
P0_12 = p12,
|
||||
P0_13 = p13,
|
||||
P0_14 = p14,
|
||||
P0_15 = p15,
|
||||
|
||||
P0_16 = p16,
|
||||
P0_17 = p17,
|
||||
P0_18 = p18,
|
||||
P0_19 = p19,
|
||||
P0_20 = p20,
|
||||
P0_21 = p21,
|
||||
P0_22 = p22,
|
||||
P0_23 = p23,
|
||||
|
||||
P0_24 = p24,
|
||||
P0_25 = p25,
|
||||
P0_26 = p26,
|
||||
P0_27 = p27,
|
||||
P0_28 = p28,
|
||||
P0_29 = p29,
|
||||
P0_30 = p30,
|
||||
|
||||
LED1 = p21,
|
||||
LED2 = p22,
|
||||
LED3 = p23,
|
||||
LED4 = p24,
|
||||
|
||||
BUTTON1 = p17,
|
||||
BUTTON = BUTTON1,
|
||||
|
||||
RX_PIN_NUMBER = p11,
|
||||
TX_PIN_NUMBER = p9,
|
||||
CTS_PIN_NUMBER = p10,
|
||||
RTS_PIN_NUMBER = p8,
|
||||
|
||||
// mbed interface Pins
|
||||
USBTX = TX_PIN_NUMBER,
|
||||
USBRX = RX_PIN_NUMBER,
|
||||
|
||||
I2C_SDA0 = p18,
|
||||
I2C_SCL0 = p19,
|
||||
|
||||
MPU6050_SDA_PIN = p18,
|
||||
MPU6050_SCL_PIN = p19,
|
||||
MPU6050_INT_PIN = p20,
|
||||
|
||||
BATTERY_PIN = p1,
|
||||
VCC_CTRL_PIN = p30,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullDown = 1,
|
||||
PullUp = 3,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
|
||||
// Check the 'features' section of the target description in 'targets.json' for more details.
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -1,178 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2015 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define PORT_SHIFT 3
|
||||
|
||||
typedef enum {
|
||||
p0 = 0,
|
||||
p1 = 1,
|
||||
p2 = 2,
|
||||
p3 = 3,
|
||||
p4 = 4,
|
||||
p5 = 5,
|
||||
p6 = 6,
|
||||
p7 = 7,
|
||||
p8 = 8,
|
||||
p9 = 9,
|
||||
p10 = 10,
|
||||
p11 = 11,
|
||||
p12 = 12,
|
||||
p13 = 13,
|
||||
p14 = 14,
|
||||
p15 = 15,
|
||||
p16 = 16,
|
||||
p17 = 17,
|
||||
p18 = 18,
|
||||
p19 = 19,
|
||||
p20 = 20,
|
||||
p21 = 21,
|
||||
p22 = 22,
|
||||
p23 = 23,
|
||||
p24 = 24,
|
||||
p25 = 25,
|
||||
p26 = 26,
|
||||
p27 = 27,
|
||||
p28 = 28,
|
||||
p29 = 29,
|
||||
p30 = 30,
|
||||
|
||||
P0_0 = p0,
|
||||
P0_1 = p1,
|
||||
P0_2 = p2,
|
||||
P0_3 = p3,
|
||||
P0_4 = p4,
|
||||
P0_5 = p5,
|
||||
P0_6 = p6,
|
||||
P0_7 = p7,
|
||||
|
||||
P0_8 = p8,
|
||||
P0_9 = p9,
|
||||
P0_10 = p10,
|
||||
P0_11 = p11,
|
||||
P0_12 = p12,
|
||||
P0_13 = p13,
|
||||
P0_14 = p14,
|
||||
P0_15 = p15,
|
||||
|
||||
P0_16 = p16,
|
||||
P0_17 = p17,
|
||||
P0_18 = p18,
|
||||
P0_19 = p19,
|
||||
P0_20 = p20,
|
||||
P0_21 = p21,
|
||||
P0_22 = p22,
|
||||
P0_23 = p23,
|
||||
|
||||
P0_24 = p24,
|
||||
P0_25 = p25,
|
||||
P0_26 = p26,
|
||||
P0_27 = p27,
|
||||
P0_28 = p28,
|
||||
P0_29 = p29,
|
||||
P0_30 = p30,
|
||||
|
||||
LED1 = p21,
|
||||
LED2 = p22,
|
||||
LED3 = p23,
|
||||
LED4 = p24,
|
||||
|
||||
BUTTON1 = p17,
|
||||
BUTTON2 = p18,
|
||||
BUTTON3 = p19,
|
||||
BUTTON4 = p20,
|
||||
|
||||
RX_PIN_NUMBER = p11,
|
||||
TX_PIN_NUMBER = p9,
|
||||
CTS_PIN_NUMBER = p10,
|
||||
RTS_PIN_NUMBER = p8,
|
||||
|
||||
// mBed interface Pins
|
||||
USBTX = TX_PIN_NUMBER,
|
||||
USBRX = RX_PIN_NUMBER,
|
||||
|
||||
SPI_PSELMOSI0 = p25,
|
||||
SPI_PSELMISO0 = p28,
|
||||
SPI_PSELSS0 = p24,
|
||||
SPI_PSELSCK0 = p29,
|
||||
|
||||
SPI_PSELMOSI1 = p13,
|
||||
SPI_PSELMISO1 = p14,
|
||||
SPI_PSELSS1 = p12,
|
||||
SPI_PSELSCK1 = p15,
|
||||
|
||||
SPIS_PSELMOSI = p13,
|
||||
SPIS_PSELMISO = p14,
|
||||
SPIS_PSELSS = p12,
|
||||
SPIS_PSELSCK = p15,
|
||||
|
||||
I2C_SDA0 = p30,
|
||||
I2C_SCL0 = p7,
|
||||
|
||||
D0 = p12,
|
||||
D1 = p13,
|
||||
D2 = p14,
|
||||
D3 = p15,
|
||||
D4 = p16,
|
||||
D5 = p17,
|
||||
D6 = p18,
|
||||
D7 = p19,
|
||||
|
||||
D8 = p20,
|
||||
D9 = p23,
|
||||
D10 = p24,
|
||||
D11 = p25,
|
||||
D12 = p28,
|
||||
D13 = p29,
|
||||
|
||||
D14 = p30,
|
||||
D15 = p7,
|
||||
|
||||
A0 = p1,
|
||||
A1 = p2,
|
||||
A2 = p3,
|
||||
A3 = p4,
|
||||
A4 = p5,
|
||||
A5 = p6,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullDown = 1,
|
||||
PullUp = 3,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
|
||||
// Check the 'features' section of the target description in 'targets.json' for more details.
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -1,180 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
typedef enum {
|
||||
p0 = 0,
|
||||
p1 = 1,
|
||||
p2 = 2,
|
||||
p3 = 3,
|
||||
p4 = 4,
|
||||
p5 = 5,
|
||||
p6 = 6,
|
||||
p7 = 7,
|
||||
p8 = 8,
|
||||
p9 = 9,
|
||||
p10 = 10,
|
||||
p11 = 11,
|
||||
p12 = 12,
|
||||
p13 = 13,
|
||||
p14 = 14,
|
||||
p15 = 15,
|
||||
p16 = 16,
|
||||
p17 = 17,
|
||||
p18 = 18,
|
||||
p19 = 19,
|
||||
p20 = 20,
|
||||
p21 = 21,
|
||||
p22 = 22,
|
||||
p23 = 23,
|
||||
p24 = 24,
|
||||
p25 = 25,
|
||||
p26 = 26,
|
||||
p27 = 27,
|
||||
p28 = 28,
|
||||
p29 = 29,
|
||||
p30 = 30,
|
||||
|
||||
P0_0 = p0,
|
||||
P0_1 = p1,
|
||||
P0_2 = p2,
|
||||
P0_3 = p3,
|
||||
P0_4 = p4,
|
||||
P0_5 = p5,
|
||||
P0_6 = p6,
|
||||
P0_7 = p7,
|
||||
|
||||
P0_8 = p8,
|
||||
P0_9 = p9,
|
||||
P0_10 = p10,
|
||||
P0_11 = p11,
|
||||
P0_12 = p12,
|
||||
P0_13 = p13,
|
||||
P0_14 = p14,
|
||||
P0_15 = p15,
|
||||
|
||||
P0_16 = p16,
|
||||
P0_17 = p17,
|
||||
P0_18 = p18,
|
||||
P0_19 = p19,
|
||||
P0_20 = p20,
|
||||
P0_21 = p21,
|
||||
P0_22 = p22,
|
||||
P0_23 = p23,
|
||||
|
||||
P0_24 = p24,
|
||||
P0_25 = p25,
|
||||
P0_26 = p26,
|
||||
P0_27 = p27,
|
||||
P0_28 = p28,
|
||||
P0_29 = p29,
|
||||
P0_30 = p30,
|
||||
|
||||
LED1 = p18,
|
||||
LED2 = p19,
|
||||
LED3 = p18,
|
||||
LED4 = p19,
|
||||
|
||||
BUTTON1 = p16,
|
||||
BUTTON2 = p17,
|
||||
|
||||
RX_PIN_NUMBER = p11,
|
||||
TX_PIN_NUMBER = p9,
|
||||
CTS_PIN_NUMBER = 31, // unused
|
||||
RTS_PIN_NUMBER = 31, // unused
|
||||
|
||||
// mbed interface pins
|
||||
USBTX = TX_PIN_NUMBER,
|
||||
USBRX = RX_PIN_NUMBER,
|
||||
|
||||
SPI_PSELMOSI0 = p20,
|
||||
SPI_PSELMISO0 = p22,
|
||||
SPI_PSELSS0 = p24,
|
||||
SPI_PSELSCK0 = p25,
|
||||
|
||||
SPI_PSELMOSI1 = p12,
|
||||
SPI_PSELMISO1 = p13,
|
||||
SPI_PSELSS1 = p14,
|
||||
SPI_PSELSCK1 = p15,
|
||||
|
||||
SPIS_PSELMOSI = p12,
|
||||
SPIS_PSELMISO = p13,
|
||||
SPIS_PSELSS = p14,
|
||||
SPIS_PSELSCK = p15,
|
||||
|
||||
LED_CONNECT = P0_18,
|
||||
LED_MODE = P0_19,
|
||||
OUT_LOW= P0_20,
|
||||
SW1 = P0_16,
|
||||
SW2 = P0_17,
|
||||
|
||||
R_PWM = P0_28,
|
||||
R_IN1 = P0_30,
|
||||
R_IN2 = P0_0,
|
||||
L_PWM = P0_29,
|
||||
L_IN1 = P0_23,
|
||||
L_IN2 = P0_24,
|
||||
|
||||
MMC_SCK = P0_15,
|
||||
MMC_CS = P0_14,
|
||||
MMC_SDO = P0_13,
|
||||
MMC_SDI = P0_12,
|
||||
|
||||
R_ENC1 = P0_8,
|
||||
R_ENC2 = P0_10,
|
||||
L_ENC1 = P0_6,
|
||||
L_ENC2 = P0_7,
|
||||
|
||||
P1IN = P0_2,
|
||||
P2IN = P0_3,
|
||||
P3IN = P0_4,
|
||||
P4IN = P0_5,
|
||||
|
||||
I2C_SCL = P0_21,
|
||||
I2C_SDA = P0_22,
|
||||
|
||||
I2C_SCL0 = P0_21, //required definition for the i2c patch
|
||||
I2C_SDA0 = P0_22, //required definition for the i2c patch
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullDown = 1,
|
||||
PullUp = 3,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
|
||||
// Check the 'features' section of the target description in 'targets.json' for more details.
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -1,81 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "mbed_assert.h"
|
||||
#include "analogin_api.h"
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
|
||||
#define ANALOGIN_MEDIAN_FILTER 1
|
||||
#define ADC_10BIT_RANGE 0x3FF
|
||||
#define ADC_RANGE ADC_10BIT_RANGE
|
||||
|
||||
static const PinMap PinMap_ADC[] = {
|
||||
{p1, ADC0_0, 4},
|
||||
{p2, ADC0_0, 8},
|
||||
{p3, ADC0_0, 16},
|
||||
{p4, ADC0_0, 32},
|
||||
{p5, ADC0_0, 64},
|
||||
{p6, ADC0_0, 128},
|
||||
#ifndef TARGET_NRF51_DONGLE
|
||||
{p26, ADC0_0, 1},
|
||||
{p27, ADC0_0, 2},
|
||||
#endif
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
void analogin_init(analogin_t *obj, PinName pin)
|
||||
{
|
||||
int analogInputPin = 0;
|
||||
const PinMap *map = PinMap_ADC;
|
||||
|
||||
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); //(NRF_ADC_Type *)
|
||||
MBED_ASSERT(obj->adc != (ADCName)NC);
|
||||
|
||||
while (map->pin != NC) {
|
||||
if (map->pin == pin) {
|
||||
analogInputPin = map->function;
|
||||
break;
|
||||
}
|
||||
map++;
|
||||
}
|
||||
obj->adc_pin = (uint8_t)analogInputPin;
|
||||
|
||||
NRF_ADC->ENABLE = ADC_ENABLE_ENABLE_Enabled;
|
||||
NRF_ADC->CONFIG = (ADC_CONFIG_RES_10bit << ADC_CONFIG_RES_Pos) |
|
||||
(ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling << ADC_CONFIG_INPSEL_Pos) |
|
||||
(ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling << ADC_CONFIG_REFSEL_Pos) |
|
||||
(analogInputPin << ADC_CONFIG_PSEL_Pos) |
|
||||
(ADC_CONFIG_EXTREFSEL_None << ADC_CONFIG_EXTREFSEL_Pos);
|
||||
}
|
||||
|
||||
uint16_t analogin_read_u16(analogin_t *obj)
|
||||
{
|
||||
NRF_ADC->CONFIG &= ~ADC_CONFIG_PSEL_Msk;
|
||||
NRF_ADC->CONFIG |= obj->adc_pin << ADC_CONFIG_PSEL_Pos;
|
||||
NRF_ADC->EVENTS_END = 0;
|
||||
NRF_ADC->TASKS_START = 1;
|
||||
|
||||
while (!NRF_ADC->EVENTS_END) {
|
||||
}
|
||||
|
||||
return (uint16_t)NRF_ADC->RESULT; // 10 bit
|
||||
}
|
||||
|
||||
float analogin_read(analogin_t *obj)
|
||||
{
|
||||
uint16_t value = analogin_read_u16(obj);
|
||||
return (float)value * (1.0f / (float)ADC_RANGE);
|
||||
}
|
||||
|
|
@ -1,58 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "mbed_assert.h"
|
||||
#include "gpio_api.h"
|
||||
#include "pinmap.h"
|
||||
|
||||
void gpio_init(gpio_t *obj, PinName pin)
|
||||
{
|
||||
obj->pin = pin;
|
||||
if (pin == (PinName)NC) {
|
||||
return;
|
||||
}
|
||||
|
||||
obj->mask = (1ul << pin);
|
||||
|
||||
obj->reg_set = &NRF_GPIO->OUTSET;
|
||||
obj->reg_clr = &NRF_GPIO->OUTCLR;
|
||||
obj->reg_in = &NRF_GPIO->IN;
|
||||
obj->reg_dir = &NRF_GPIO->DIR;
|
||||
}
|
||||
|
||||
void gpio_mode(gpio_t *obj, PinMode mode)
|
||||
{
|
||||
pin_mode(obj->pin, mode);
|
||||
}
|
||||
|
||||
void gpio_dir(gpio_t *obj, PinDirection direction)
|
||||
{
|
||||
MBED_ASSERT(obj->pin != (PinName)NC);
|
||||
switch (direction) {
|
||||
case PIN_INPUT:
|
||||
NRF_GPIO->PIN_CNF[obj->pin] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
|
||||
break;
|
||||
case PIN_OUTPUT:
|
||||
NRF_GPIO->PIN_CNF[obj->pin] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -1,127 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <stddef.h>
|
||||
#include "cmsis.h"
|
||||
|
||||
#include "gpio_irq_api.h"
|
||||
#include "mbed_error.h"
|
||||
|
||||
#define CHANNEL_NUM 31
|
||||
|
||||
static uint32_t channel_ids[CHANNEL_NUM] = {0}; //each pin will be given an id, if id is 0 the pin can be ignored.
|
||||
static uint8_t channel_enabled[CHANNEL_NUM] = {0};
|
||||
static uint32_t portRISE = 0;
|
||||
static uint32_t portFALL = 0;
|
||||
static gpio_irq_handler irq_handler;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void GPIOTE_IRQHandler(void)
|
||||
{
|
||||
volatile uint32_t newVal = NRF_GPIO->IN;
|
||||
|
||||
if ((NRF_GPIOTE->EVENTS_PORT != 0) && ((NRF_GPIOTE->INTENSET & GPIOTE_INTENSET_PORT_Msk) != 0)) {
|
||||
NRF_GPIOTE->EVENTS_PORT = 0;
|
||||
|
||||
for (uint8_t i = 0; i<31; i++) {
|
||||
if (channel_ids[i]>0) {
|
||||
if (channel_enabled[i]) {
|
||||
if( ((newVal>>i)&1) && ( ( (NRF_GPIO->PIN_CNF[i] >>GPIO_PIN_CNF_SENSE_Pos) & GPIO_PIN_CNF_SENSE_Low) != GPIO_PIN_CNF_SENSE_Low) && ( (portRISE>>i)&1) ){
|
||||
irq_handler(channel_ids[i], IRQ_RISE);
|
||||
} else if ((((newVal >> i) & 1) == 0) &&
|
||||
(((NRF_GPIO->PIN_CNF[i] >> GPIO_PIN_CNF_SENSE_Pos) & GPIO_PIN_CNF_SENSE_Low) == GPIO_PIN_CNF_SENSE_Low) &&
|
||||
((portFALL >> i) & 1)) {
|
||||
irq_handler(channel_ids[i], IRQ_FALL);
|
||||
}
|
||||
}
|
||||
|
||||
if (NRF_GPIO->PIN_CNF[i] & GPIO_PIN_CNF_SENSE_Msk) {
|
||||
NRF_GPIO->PIN_CNF[i] &= ~(GPIO_PIN_CNF_SENSE_Msk);
|
||||
|
||||
if (newVal >> i & 1) {
|
||||
NRF_GPIO->PIN_CNF[i] |= (GPIO_PIN_CNF_SENSE_Low << GPIO_PIN_CNF_SENSE_Pos);
|
||||
} else {
|
||||
NRF_GPIO->PIN_CNF[i] |= (GPIO_PIN_CNF_SENSE_High << GPIO_PIN_CNF_SENSE_Pos);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
|
||||
{
|
||||
if (pin == NC) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
irq_handler = handler;
|
||||
obj->ch = pin;
|
||||
NRF_GPIOTE->EVENTS_PORT = 0;
|
||||
channel_ids[pin] = id;
|
||||
channel_enabled[pin] = 1;
|
||||
NRF_GPIOTE->INTENSET = GPIOTE_INTENSET_PORT_Set << GPIOTE_INTENSET_PORT_Pos;
|
||||
|
||||
NVIC_SetPriority(GPIOTE_IRQn, 3);
|
||||
NVIC_EnableIRQ (GPIOTE_IRQn);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void gpio_irq_free(gpio_irq_t *obj)
|
||||
{
|
||||
channel_ids[obj->ch] = 0;
|
||||
}
|
||||
|
||||
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
|
||||
{
|
||||
NRF_GPIO->PIN_CNF[obj->ch] &= ~(GPIO_PIN_CNF_SENSE_Msk);
|
||||
if (enable) {
|
||||
if (event == IRQ_RISE) {
|
||||
portRISE |= (1 << obj->ch);
|
||||
} else if (event == IRQ_FALL) {
|
||||
portFALL |= (1 << obj->ch);
|
||||
}
|
||||
} else {
|
||||
if (event == IRQ_RISE) {
|
||||
portRISE &= ~(1 << obj->ch);
|
||||
} else if (event == IRQ_FALL) {
|
||||
portFALL &= ~(1 << obj->ch);
|
||||
}
|
||||
}
|
||||
|
||||
if (((portRISE >> obj->ch) & 1) || ((portFALL >> obj->ch) & 1)) {
|
||||
if ((NRF_GPIO->IN >> obj->ch) & 1) {
|
||||
NRF_GPIO->PIN_CNF[obj->ch] |= (GPIO_PIN_CNF_SENSE_Low << GPIO_PIN_CNF_SENSE_Pos); // | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos);
|
||||
} else {
|
||||
NRF_GPIO->PIN_CNF[obj->ch] |= (GPIO_PIN_CNF_SENSE_High << GPIO_PIN_CNF_SENSE_Pos); //| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void gpio_irq_enable(gpio_irq_t *obj)
|
||||
{
|
||||
channel_enabled[obj->ch] = 1;
|
||||
}
|
||||
|
||||
void gpio_irq_disable(gpio_irq_t *obj)
|
||||
{
|
||||
channel_enabled[obj->ch] = 0;
|
||||
}
|
||||
|
|
@ -1,309 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "mbed_assert.h"
|
||||
#include "i2c_api.h"
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
#include "twi_master.h"
|
||||
#include "mbed_error.h"
|
||||
|
||||
// nRF51822's I2C_0 and SPI_0 (I2C_1, SPI_1 and SPIS1) share the same address.
|
||||
// They can't be used at the same time. So we use two global variable to track the usage.
|
||||
// See nRF51822 address information at nRF51822_PS v2.0.pdf - Table 15 Peripheral instance reference
|
||||
volatile i2c_spi_peripheral_t i2c0_spi0_peripheral = {0, 0, 0, 0};
|
||||
volatile i2c_spi_peripheral_t i2c1_spi1_peripheral = {0, 0, 0, 0};
|
||||
|
||||
void i2c_interface_enable(i2c_t *obj)
|
||||
{
|
||||
obj->i2c->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
|
||||
void twi_master_init(i2c_t *obj, PinName sda, PinName scl, int frequency)
|
||||
{
|
||||
NRF_GPIO->PIN_CNF[scl] = ((GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) |
|
||||
(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
|
||||
(GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |
|
||||
(GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) |
|
||||
(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos));
|
||||
|
||||
NRF_GPIO->PIN_CNF[sda] = ((GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) |
|
||||
(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
|
||||
(GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |
|
||||
(GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) |
|
||||
(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos));
|
||||
|
||||
obj->i2c->PSELSCL = scl;
|
||||
obj->i2c->PSELSDA = sda;
|
||||
// set default frequency at 100k
|
||||
i2c_frequency(obj, frequency);
|
||||
i2c_interface_enable(obj);
|
||||
}
|
||||
|
||||
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
|
||||
{
|
||||
NRF_TWI_Type *i2c = NULL;
|
||||
|
||||
if (i2c0_spi0_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_I2C &&
|
||||
i2c0_spi0_peripheral.sda_mosi == (uint8_t)sda &&
|
||||
i2c0_spi0_peripheral.scl_miso == (uint8_t)scl) {
|
||||
// The I2C with the same pins is already initialized
|
||||
i2c = (NRF_TWI_Type *)I2C_0;
|
||||
obj->peripheral = 0x1;
|
||||
} else if (i2c1_spi1_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_I2C &&
|
||||
i2c1_spi1_peripheral.sda_mosi == (uint8_t)sda &&
|
||||
i2c1_spi1_peripheral.scl_miso == (uint8_t)scl) {
|
||||
// The I2C with the same pins is already initialized
|
||||
i2c = (NRF_TWI_Type *)I2C_1;
|
||||
obj->peripheral = 0x2;
|
||||
} else if (i2c0_spi0_peripheral.usage == 0) {
|
||||
i2c0_spi0_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_I2C;
|
||||
i2c0_spi0_peripheral.sda_mosi = (uint8_t)sda;
|
||||
i2c0_spi0_peripheral.scl_miso = (uint8_t)scl;
|
||||
|
||||
i2c = (NRF_TWI_Type *)I2C_0;
|
||||
obj->peripheral = 0x1;
|
||||
} else if (i2c1_spi1_peripheral.usage == 0) {
|
||||
i2c1_spi1_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_I2C;
|
||||
i2c1_spi1_peripheral.sda_mosi = (uint8_t)sda;
|
||||
i2c1_spi1_peripheral.scl_miso = (uint8_t)scl;
|
||||
|
||||
i2c = (NRF_TWI_Type *)I2C_1;
|
||||
obj->peripheral = 0x2;
|
||||
} else {
|
||||
// No available peripheral
|
||||
error("No available I2C");
|
||||
}
|
||||
|
||||
twi_master_init_and_clear(i2c);
|
||||
|
||||
obj->i2c = i2c;
|
||||
obj->scl = scl;
|
||||
obj->sda = sda;
|
||||
obj->i2c->EVENTS_ERROR = 0;
|
||||
obj->i2c->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos;
|
||||
obj->i2c->POWER = 0;
|
||||
|
||||
for (int i = 0; i<100; i++) {
|
||||
}
|
||||
|
||||
obj->i2c->POWER = 1;
|
||||
twi_master_init(obj, sda, scl, 100000);
|
||||
}
|
||||
|
||||
void i2c_reset(i2c_t *obj)
|
||||
{
|
||||
obj->i2c->EVENTS_ERROR = 0;
|
||||
obj->i2c->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos;
|
||||
obj->i2c->POWER = 0;
|
||||
for (int i = 0; i<100; i++) {
|
||||
}
|
||||
|
||||
obj->i2c->POWER = 1;
|
||||
twi_master_init(obj, obj->sda, obj->scl, obj->freq);
|
||||
}
|
||||
|
||||
int i2c_start(i2c_t *obj)
|
||||
{
|
||||
int status = 0;
|
||||
i2c_reset(obj);
|
||||
obj->address_set = 0;
|
||||
return status;
|
||||
}
|
||||
|
||||
int i2c_stop(i2c_t *obj)
|
||||
{
|
||||
int timeOut = 100000;
|
||||
obj->i2c->EVENTS_STOPPED = 0;
|
||||
// write the stop bit
|
||||
obj->i2c->TASKS_STOP = 1;
|
||||
while (!obj->i2c->EVENTS_STOPPED) {
|
||||
timeOut--;
|
||||
if (timeOut<0) {
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
obj->address_set = 0;
|
||||
i2c_reset(obj);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int i2c_do_write(i2c_t *obj, int value)
|
||||
{
|
||||
int timeOut = 100000;
|
||||
obj->i2c->TXD = value;
|
||||
while (!obj->i2c->EVENTS_TXDSENT) {
|
||||
timeOut--;
|
||||
if (timeOut<0) {
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
obj->i2c->EVENTS_TXDSENT = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int i2c_do_read(i2c_t *obj, char *data, int last)
|
||||
{
|
||||
int timeOut = 100000;
|
||||
|
||||
if (last) {
|
||||
// To trigger stop task when a byte is received,
|
||||
// must be set before resume task.
|
||||
obj->i2c->SHORTS = 2;
|
||||
}
|
||||
|
||||
obj->i2c->TASKS_RESUME = 1;
|
||||
|
||||
while (!obj->i2c->EVENTS_RXDREADY) {
|
||||
timeOut--;
|
||||
if (timeOut<0) {
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
obj->i2c->EVENTS_RXDREADY = 0;
|
||||
*data = obj->i2c->RXD;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void i2c_frequency(i2c_t *obj, int hz)
|
||||
{
|
||||
if (hz<250000) {
|
||||
obj->freq = 100000;
|
||||
obj->i2c->FREQUENCY = (TWI_FREQUENCY_FREQUENCY_K100 << TWI_FREQUENCY_FREQUENCY_Pos);
|
||||
} else if (hz<400000) {
|
||||
obj->freq = 250000;
|
||||
obj->i2c->FREQUENCY = (TWI_FREQUENCY_FREQUENCY_K250 << TWI_FREQUENCY_FREQUENCY_Pos);
|
||||
} else {
|
||||
obj->freq = 400000;
|
||||
obj->i2c->FREQUENCY = (TWI_FREQUENCY_FREQUENCY_K400 << TWI_FREQUENCY_FREQUENCY_Pos);
|
||||
}
|
||||
}
|
||||
|
||||
int checkError(i2c_t *obj)
|
||||
{
|
||||
if (obj->i2c->EVENTS_ERROR == 1) {
|
||||
if (obj->i2c->ERRORSRC & TWI_ERRORSRC_ANACK_Msk) {
|
||||
obj->i2c->EVENTS_ERROR = 0;
|
||||
obj->i2c->TASKS_STOP = 1;
|
||||
return I2C_ERROR_BUS_BUSY;
|
||||
}
|
||||
|
||||
obj->i2c->EVENTS_ERROR = 0;
|
||||
obj->i2c->TASKS_STOP = 1;
|
||||
return I2C_ERROR_NO_SLAVE;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
|
||||
{
|
||||
int status, count, errorResult;
|
||||
obj->i2c->ADDRESS = (address >> 1);
|
||||
obj->i2c->SHORTS = 1; // to trigger suspend task when a byte is received
|
||||
obj->i2c->EVENTS_RXDREADY = 0;
|
||||
obj->i2c->TASKS_STARTRX = 1;
|
||||
|
||||
// Read in all except last byte
|
||||
for (count = 0; count < (length - 1); count++) {
|
||||
status = i2c_do_read(obj, &data[count], 0);
|
||||
if (status) {
|
||||
errorResult = checkError(obj);
|
||||
i2c_reset(obj);
|
||||
if (errorResult<0) {
|
||||
return errorResult;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
}
|
||||
|
||||
// read in last byte
|
||||
status = i2c_do_read(obj, &data[length - 1], 1);
|
||||
if (status) {
|
||||
i2c_reset(obj);
|
||||
return length - 1;
|
||||
}
|
||||
// If not repeated start, send stop.
|
||||
if (stop) {
|
||||
while (!obj->i2c->EVENTS_STOPPED) {
|
||||
}
|
||||
obj->i2c->EVENTS_STOPPED = 0;
|
||||
}
|
||||
return length;
|
||||
}
|
||||
|
||||
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
|
||||
{
|
||||
int status, errorResult;
|
||||
obj->i2c->ADDRESS = (address >> 1);
|
||||
obj->i2c->SHORTS = 0;
|
||||
obj->i2c->TASKS_STARTTX = 1;
|
||||
|
||||
for (int i = 0; i<length; i++) {
|
||||
status = i2c_do_write(obj, data[i]);
|
||||
if (status) {
|
||||
i2c_reset(obj);
|
||||
errorResult = checkError(obj);
|
||||
if (errorResult<0) {
|
||||
return errorResult;
|
||||
}
|
||||
return i;
|
||||
}
|
||||
}
|
||||
|
||||
// If not repeated start, send stop.
|
||||
if (stop) {
|
||||
if (i2c_stop(obj)) {
|
||||
return I2C_ERROR_NO_SLAVE;
|
||||
}
|
||||
}
|
||||
return length;
|
||||
}
|
||||
|
||||
int i2c_byte_read(i2c_t *obj, int last)
|
||||
{
|
||||
char data;
|
||||
int status;
|
||||
|
||||
status = i2c_do_read(obj, &data, last);
|
||||
if (status) {
|
||||
i2c_reset(obj);
|
||||
}
|
||||
return data;
|
||||
}
|
||||
|
||||
int i2c_byte_write(i2c_t *obj, int data)
|
||||
{
|
||||
int status = 0;
|
||||
if (!obj->address_set) {
|
||||
obj->address_set = 1;
|
||||
obj->i2c->ADDRESS = (data >> 1);
|
||||
|
||||
if (data & 1) {
|
||||
obj->i2c->EVENTS_RXDREADY = 0;
|
||||
obj->i2c->SHORTS = 1;
|
||||
obj->i2c->TASKS_STARTRX = 1;
|
||||
} else {
|
||||
obj->i2c->SHORTS = 0;
|
||||
obj->i2c->TASKS_STARTTX = 1;
|
||||
}
|
||||
} else {
|
||||
status = i2c_do_write(obj, data);
|
||||
if (status) {
|
||||
i2c_reset(obj);
|
||||
}
|
||||
}
|
||||
return (1 - status);
|
||||
}
|
||||
|
|
@ -1,86 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_OBJECTS_H
|
||||
#define MBED_OBJECTS_H
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "PortNames.h"
|
||||
#include "PeripheralNames.h"
|
||||
#include "PinNames.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define I2C_SPI_PERIPHERAL_FOR_I2C 1
|
||||
#define I2C_SPI_PERIPHERAL_FOR_SPI 2
|
||||
|
||||
typedef struct {
|
||||
uint8_t usage; // I2C: 1, SPI: 2
|
||||
uint8_t sda_mosi;
|
||||
uint8_t scl_miso;
|
||||
uint8_t sclk;
|
||||
} i2c_spi_peripheral_t;
|
||||
|
||||
struct serial_s {
|
||||
NRF_UART_Type *uart;
|
||||
int index;
|
||||
};
|
||||
|
||||
struct spi_s {
|
||||
NRF_SPI_Type *spi;
|
||||
NRF_SPIS_Type *spis;
|
||||
uint8_t peripheral;
|
||||
};
|
||||
|
||||
struct port_s {
|
||||
__IO uint32_t *reg_cnf;
|
||||
__IO uint32_t *reg_out;
|
||||
__I uint32_t *reg_in;
|
||||
PortName port;
|
||||
uint32_t mask;
|
||||
};
|
||||
|
||||
struct pwmout_s {
|
||||
PWMName pwm;
|
||||
PinName pin;
|
||||
};
|
||||
|
||||
struct i2c_s {
|
||||
NRF_TWI_Type *i2c;
|
||||
PinName sda;
|
||||
PinName scl;
|
||||
int freq;
|
||||
uint8_t address_set;
|
||||
uint8_t peripheral;
|
||||
};
|
||||
|
||||
struct analogin_s {
|
||||
ADCName adc;
|
||||
uint8_t adc_pin;
|
||||
};
|
||||
|
||||
struct gpio_irq_s {
|
||||
uint32_t ch;
|
||||
};
|
||||
|
||||
#include "gpio_object.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,84 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "port_api.h"
|
||||
#include "pinmap.h"
|
||||
#include "gpio_api.h"
|
||||
|
||||
PinName port_pin(PortName port, int pin_n)
|
||||
{
|
||||
return (PinName)(pin_n);
|
||||
}
|
||||
|
||||
void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
|
||||
{
|
||||
obj->port = port;
|
||||
obj->mask = mask;
|
||||
|
||||
obj->reg_out = &NRF_GPIO->OUT;
|
||||
obj->reg_in = &NRF_GPIO->IN;
|
||||
obj->reg_cnf = NRF_GPIO->PIN_CNF;
|
||||
|
||||
port_dir(obj, dir);
|
||||
}
|
||||
|
||||
void port_mode(port_t *obj, PinMode mode)
|
||||
{
|
||||
uint32_t i;
|
||||
// The mode is set per pin: reuse pinmap logic
|
||||
for (i = 0; i<31; i++) {
|
||||
if (obj->mask & (1 << i)) {
|
||||
pin_mode(port_pin(obj->port, i), mode);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void port_dir(port_t *obj, PinDirection dir)
|
||||
{
|
||||
int i;
|
||||
switch (dir) {
|
||||
case PIN_INPUT:
|
||||
for (i = 0; i<31; i++) {
|
||||
if (obj->mask & (1 << i)) {
|
||||
obj->reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
|
||||
}
|
||||
}
|
||||
break;
|
||||
case PIN_OUTPUT:
|
||||
for (i = 0; i<31; i++) {
|
||||
if (obj->mask & (1 << i)) {
|
||||
obj->reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void port_write(port_t *obj, int value)
|
||||
{
|
||||
*obj->reg_out = value;
|
||||
}
|
||||
|
||||
int port_read(port_t *obj)
|
||||
{
|
||||
return (*obj->reg_in);
|
||||
}
|
||||
|
|
@ -1,380 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "mbed_assert.h"
|
||||
#include "pwmout_api.h"
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
#include "mbed_error.h"
|
||||
|
||||
#define NO_PWMS 3
|
||||
#define TIMER_PRECISION 4 //4us ticks
|
||||
#define TIMER_PRESCALER 6 //4us ticks = 16Mhz/(2**6)
|
||||
static const PinMap PinMap_PWM[] = {
|
||||
{p0, PWM_1, 1},
|
||||
{p1, PWM_1, 1},
|
||||
{p2, PWM_1, 1},
|
||||
{p3, PWM_1, 1},
|
||||
{p4, PWM_1, 1},
|
||||
{p5, PWM_1, 1},
|
||||
{p6, PWM_1, 1},
|
||||
{p7, PWM_1, 1},
|
||||
{p8, PWM_1, 1},
|
||||
{p9, PWM_1, 1},
|
||||
{p10, PWM_1, 1},
|
||||
{p11, PWM_1, 1},
|
||||
{p12, PWM_1, 1},
|
||||
{p13, PWM_1, 1},
|
||||
{p14, PWM_1, 1},
|
||||
{p15, PWM_1, 1},
|
||||
{p16, PWM_1, 1},
|
||||
{p17, PWM_1, 1},
|
||||
{p18, PWM_1, 1},
|
||||
{p19, PWM_1, 1},
|
||||
{p20, PWM_1, 1},
|
||||
{p21, PWM_1, 1},
|
||||
{p22, PWM_1, 1},
|
||||
{p23, PWM_1, 1},
|
||||
{p24, PWM_1, 1},
|
||||
{p25, PWM_1, 1},
|
||||
{p28, PWM_1, 1},
|
||||
{p29, PWM_1, 1},
|
||||
{p30, PWM_1, 1},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
static NRF_TIMER_Type *Timers[1] = {
|
||||
NRF_TIMER2
|
||||
};
|
||||
|
||||
uint16_t PERIOD = 20000 / TIMER_PRECISION; //20ms
|
||||
uint8_t PWM_taken[NO_PWMS] = {0, 0, 0};
|
||||
uint16_t PULSE_WIDTH[NO_PWMS] = {1, 1, 1}; //set to 1 instead of 0
|
||||
uint16_t ACTUAL_PULSE[NO_PWMS] = {0, 0, 0};
|
||||
|
||||
|
||||
/** @brief Function for handling timer 2 peripheral interrupts.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void TIMER2_IRQHandler(void)
|
||||
{
|
||||
NRF_TIMER2->EVENTS_COMPARE[3] = 0;
|
||||
NRF_TIMER2->CC[3] = PERIOD;
|
||||
|
||||
if (PWM_taken[0]) {
|
||||
NRF_TIMER2->CC[0] = PULSE_WIDTH[0];
|
||||
}
|
||||
if (PWM_taken[1]) {
|
||||
NRF_TIMER2->CC[1] = PULSE_WIDTH[1];
|
||||
}
|
||||
if (PWM_taken[2]) {
|
||||
NRF_TIMER2->CC[2] = PULSE_WIDTH[2];
|
||||
}
|
||||
|
||||
NRF_TIMER2->TASKS_START = 1;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/** @brief Function for initializing the Timer peripherals.
|
||||
*/
|
||||
void timer_init(uint8_t pwmChoice)
|
||||
{
|
||||
NRF_TIMER_Type *timer = Timers[0];
|
||||
timer->TASKS_STOP = 0;
|
||||
|
||||
if (pwmChoice == 0) {
|
||||
timer->POWER = 0;
|
||||
timer->POWER = 1;
|
||||
timer->MODE = TIMER_MODE_MODE_Timer;
|
||||
timer->BITMODE = TIMER_BITMODE_BITMODE_16Bit << TIMER_BITMODE_BITMODE_Pos;
|
||||
timer->PRESCALER = TIMER_PRESCALER;
|
||||
timer->CC[3] = PERIOD;
|
||||
}
|
||||
|
||||
timer->CC[pwmChoice] = PULSE_WIDTH[pwmChoice];
|
||||
|
||||
//high priority application interrupt
|
||||
NVIC_SetPriority(TIMER2_IRQn, 1);
|
||||
NVIC_EnableIRQ(TIMER2_IRQn);
|
||||
|
||||
timer->TASKS_START = 0x01;
|
||||
}
|
||||
|
||||
static void timer_free()
|
||||
{
|
||||
NRF_TIMER_Type *timer = Timers[0];
|
||||
for(uint8_t i = 1; i < NO_PWMS; i++){
|
||||
if(PWM_taken[i]){
|
||||
break;
|
||||
}
|
||||
if((i == NO_PWMS - 1) && (!PWM_taken[i]))
|
||||
timer->TASKS_STOP = 0x01;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/** @brief Function for initializing the GPIO Tasks/Events peripheral.
|
||||
*/
|
||||
void gpiote_init(PinName pin, uint8_t channel_number)
|
||||
{
|
||||
// Connect GPIO input buffers and configure PWM_OUTPUT_PIN_NUMBER as an output.
|
||||
NRF_GPIO->PIN_CNF[pin] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_GPIO->OUTCLR = (1UL << pin);
|
||||
// Configure GPIOTE channel 0 to toggle the PWM pin state
|
||||
// @note Only one GPIOTE task can be connected to an output pin.
|
||||
/* Configure channel to Pin31, not connected to the pin, and configure as a tasks that will set it to proper level */
|
||||
NRF_GPIOTE->CONFIG[channel_number] = (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) |
|
||||
(31UL << GPIOTE_CONFIG_PSEL_Pos) |
|
||||
(GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos);
|
||||
/* Three NOPs are required to make sure configuration is written before setting tasks or getting events */
|
||||
__NOP();
|
||||
__NOP();
|
||||
__NOP();
|
||||
/* Launch the task to take the GPIOTE channel output to the desired level */
|
||||
NRF_GPIOTE->TASKS_OUT[channel_number] = 1;
|
||||
|
||||
/* Finally configure the channel as the caller expects. If OUTINIT works, the channel is configured properly.
|
||||
If it does not, the channel output inheritance sets the proper level. */
|
||||
NRF_GPIOTE->CONFIG[channel_number] = (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) |
|
||||
((uint32_t)pin << GPIOTE_CONFIG_PSEL_Pos) |
|
||||
((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos) |
|
||||
((uint32_t)GPIOTE_CONFIG_OUTINIT_Low << GPIOTE_CONFIG_OUTINIT_Pos); // ((uint32_t)GPIOTE_CONFIG_OUTINIT_High <<
|
||||
// GPIOTE_CONFIG_OUTINIT_Pos);//
|
||||
|
||||
/* Three NOPs are required to make sure configuration is written before setting tasks or getting events */
|
||||
__NOP();
|
||||
__NOP();
|
||||
__NOP();
|
||||
}
|
||||
|
||||
static void gpiote_free(PinName pin,uint8_t channel_number)
|
||||
{
|
||||
NRF_GPIOTE->TASKS_OUT[channel_number] = 0;
|
||||
NRF_GPIOTE->CONFIG[channel_number] = 0;
|
||||
NRF_GPIO->PIN_CNF[pin] = (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos);
|
||||
|
||||
}
|
||||
|
||||
/** @brief Function for initializing the Programmable Peripheral Interconnect peripheral.
|
||||
*/
|
||||
static void ppi_init(uint8_t pwm)
|
||||
{
|
||||
//using ppi channels 0-7 (only 0-7 are available)
|
||||
uint8_t channel_number = 2 * pwm;
|
||||
NRF_TIMER_Type *timer = Timers[0];
|
||||
|
||||
// Configure PPI channel 0 to toggle ADVERTISING_LED_PIN_NO on every TIMER1 COMPARE[0] match
|
||||
NRF_PPI->CH[channel_number].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pwm];
|
||||
NRF_PPI->CH[channel_number + 1].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pwm];
|
||||
NRF_PPI->CH[channel_number].EEP = (uint32_t)&timer->EVENTS_COMPARE[pwm];
|
||||
NRF_PPI->CH[channel_number + 1].EEP = (uint32_t)&timer->EVENTS_COMPARE[3];
|
||||
|
||||
// Enable PPI channels.
|
||||
NRF_PPI->CHEN |= (1 << channel_number) |
|
||||
(1 << (channel_number + 1));
|
||||
}
|
||||
|
||||
static void ppi_free(uint8_t pwm)
|
||||
{
|
||||
//using ppi channels 0-7 (only 0-7 are available)
|
||||
uint8_t channel_number = 2*pwm;
|
||||
|
||||
// Disable PPI channels.
|
||||
NRF_PPI->CHEN &= (~(1 << channel_number))
|
||||
& (~(1 << (channel_number+1)));
|
||||
}
|
||||
|
||||
void setModulation(pwmout_t *obj, uint8_t toggle, uint8_t high)
|
||||
{
|
||||
if (high) {
|
||||
NRF_GPIOTE->CONFIG[obj->pwm] |= ((uint32_t)GPIOTE_CONFIG_OUTINIT_High << GPIOTE_CONFIG_OUTINIT_Pos);
|
||||
if (toggle) {
|
||||
NRF_GPIOTE->CONFIG[obj->pwm] |= (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) |
|
||||
((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos);
|
||||
} else {
|
||||
NRF_GPIOTE->CONFIG[obj->pwm] &= ~((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos);
|
||||
NRF_GPIOTE->CONFIG[obj->pwm] |= ((uint32_t)GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos);
|
||||
}
|
||||
} else {
|
||||
NRF_GPIOTE->CONFIG[obj->pwm] &= ~((uint32_t)GPIOTE_CONFIG_OUTINIT_High << GPIOTE_CONFIG_OUTINIT_Pos);
|
||||
|
||||
if (toggle) {
|
||||
NRF_GPIOTE->CONFIG[obj->pwm] |= (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) |
|
||||
((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos);
|
||||
} else {
|
||||
NRF_GPIOTE->CONFIG[obj->pwm] &= ~((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos);
|
||||
NRF_GPIOTE->CONFIG[obj->pwm] |= ((uint32_t)GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void pwmout_init(pwmout_t *obj, PinName pin)
|
||||
{
|
||||
// determine the channel
|
||||
uint8_t pwmOutSuccess = 0;
|
||||
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
|
||||
|
||||
MBED_ASSERT(pwm != (PWMName)NC);
|
||||
|
||||
if (PWM_taken[(uint8_t)pwm]) {
|
||||
for (uint8_t i = 1; !pwmOutSuccess && (i<NO_PWMS); i++) {
|
||||
if (!PWM_taken[i]) {
|
||||
pwm = (PWMName)i;
|
||||
PWM_taken[i] = 1;
|
||||
pwmOutSuccess = 1;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
pwmOutSuccess = 1;
|
||||
PWM_taken[(uint8_t)pwm] = 1;
|
||||
}
|
||||
|
||||
if (!pwmOutSuccess) {
|
||||
error("PwmOut pin mapping failed. All available PWM channels are in use.");
|
||||
}
|
||||
|
||||
obj->pwm = pwm;
|
||||
obj->pin = pin;
|
||||
|
||||
gpiote_init(pin, (uint8_t)pwm);
|
||||
ppi_init((uint8_t)pwm);
|
||||
|
||||
if (pwm == 0) {
|
||||
NRF_POWER->TASKS_CONSTLAT = 1;
|
||||
}
|
||||
|
||||
timer_init((uint8_t)pwm);
|
||||
|
||||
//default to 20ms: standard for servos, and fine for e.g. brightness control
|
||||
pwmout_period_ms(obj, 20);
|
||||
pwmout_write (obj, 0);
|
||||
}
|
||||
|
||||
void pwmout_free(pwmout_t* obj) {
|
||||
MBED_ASSERT(obj->pwm != (PWMName)NC);
|
||||
pwmout_write(obj, 0);
|
||||
PWM_taken[obj->pwm] = 0;
|
||||
timer_free();
|
||||
ppi_free(obj->pwm);
|
||||
gpiote_free(obj->pin,obj->pwm);
|
||||
}
|
||||
|
||||
void pwmout_write(pwmout_t *obj, float value)
|
||||
{
|
||||
uint16_t oldPulseWidth;
|
||||
|
||||
NRF_TIMER2->EVENTS_COMPARE[3] = 0;
|
||||
NRF_TIMER2->TASKS_STOP = 1;
|
||||
|
||||
if (value < 0.0f) {
|
||||
value = 0.0;
|
||||
} else if (value > 1.0f) {
|
||||
value = 1.0;
|
||||
}
|
||||
|
||||
oldPulseWidth = ACTUAL_PULSE[obj->pwm];
|
||||
ACTUAL_PULSE[obj->pwm] = PULSE_WIDTH[obj->pwm] = value * PERIOD;
|
||||
|
||||
if (PULSE_WIDTH[obj->pwm] == 0) {
|
||||
PULSE_WIDTH[obj->pwm] = 1;
|
||||
setModulation(obj, 0, 0);
|
||||
} else if (PULSE_WIDTH[obj->pwm] == PERIOD) {
|
||||
PULSE_WIDTH[obj->pwm] = PERIOD - 1;
|
||||
setModulation(obj, 0, 1);
|
||||
} else if ((oldPulseWidth == 0) || (oldPulseWidth == PERIOD)) {
|
||||
setModulation(obj, 1, oldPulseWidth == PERIOD);
|
||||
}
|
||||
|
||||
NRF_TIMER2->INTENSET = TIMER_INTENSET_COMPARE3_Msk;
|
||||
NRF_TIMER2->SHORTS = TIMER_SHORTS_COMPARE3_CLEAR_Msk | TIMER_SHORTS_COMPARE3_STOP_Msk;
|
||||
NRF_TIMER2->TASKS_START = 1;
|
||||
}
|
||||
|
||||
float pwmout_read(pwmout_t *obj)
|
||||
{
|
||||
return ((float)PULSE_WIDTH[obj->pwm] / (float)PERIOD);
|
||||
}
|
||||
|
||||
void pwmout_period(pwmout_t *obj, float seconds)
|
||||
{
|
||||
pwmout_period_us(obj, seconds * 1000000.0f);
|
||||
}
|
||||
|
||||
void pwmout_period_ms(pwmout_t *obj, int ms)
|
||||
{
|
||||
pwmout_period_us(obj, ms * 1000);
|
||||
}
|
||||
|
||||
// Set the PWM period, keeping the duty cycle the same.
|
||||
void pwmout_period_us(pwmout_t *obj, int us)
|
||||
{
|
||||
uint32_t periodInTicks = us / TIMER_PRECISION;
|
||||
|
||||
NRF_TIMER2->EVENTS_COMPARE[3] = 0;
|
||||
NRF_TIMER2->TASKS_STOP = 1;
|
||||
|
||||
if (periodInTicks>((1 << 16) - 1)) {
|
||||
PERIOD = (1 << 16) - 1; //131ms
|
||||
} else if (periodInTicks<5) {
|
||||
PERIOD = 5;
|
||||
} else {
|
||||
PERIOD = periodInTicks;
|
||||
}
|
||||
NRF_TIMER2->INTENSET = TIMER_INTENSET_COMPARE3_Msk;
|
||||
NRF_TIMER2->SHORTS = TIMER_SHORTS_COMPARE3_CLEAR_Msk | TIMER_SHORTS_COMPARE3_STOP_Msk;
|
||||
NRF_TIMER2->TASKS_START = 1;
|
||||
}
|
||||
|
||||
void pwmout_pulsewidth(pwmout_t *obj, float seconds)
|
||||
{
|
||||
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
|
||||
}
|
||||
|
||||
void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
|
||||
{
|
||||
pwmout_pulsewidth_us(obj, ms * 1000);
|
||||
}
|
||||
|
||||
void pwmout_pulsewidth_us(pwmout_t *obj, int us)
|
||||
{
|
||||
uint32_t pulseInTicks = us / TIMER_PRECISION;
|
||||
uint16_t oldPulseWidth = ACTUAL_PULSE[obj->pwm];
|
||||
|
||||
NRF_TIMER2->EVENTS_COMPARE[3] = 0;
|
||||
NRF_TIMER2->TASKS_STOP = 1;
|
||||
|
||||
ACTUAL_PULSE[obj->pwm] = PULSE_WIDTH[obj->pwm] = pulseInTicks;
|
||||
|
||||
if (PULSE_WIDTH[obj->pwm] == 0) {
|
||||
PULSE_WIDTH[obj->pwm] = 1;
|
||||
setModulation(obj, 0, 0);
|
||||
} else if (PULSE_WIDTH[obj->pwm] == PERIOD) {
|
||||
PULSE_WIDTH[obj->pwm] = PERIOD - 1;
|
||||
setModulation(obj, 0, 1);
|
||||
} else if ((oldPulseWidth == 0) || (oldPulseWidth == PERIOD)) {
|
||||
setModulation(obj, 1, oldPulseWidth == PERIOD);
|
||||
}
|
||||
NRF_TIMER2->INTENSET = TIMER_INTENSET_COMPARE3_Msk;
|
||||
NRF_TIMER2->SHORTS = TIMER_SHORTS_COMPARE3_CLEAR_Msk | TIMER_SHORTS_COMPARE3_STOP_Msk;
|
||||
NRF_TIMER2->TASKS_START = 1;
|
||||
}
|
||||
|
|
@ -1,306 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
// math.h required for floating point operations for baud rate calculation
|
||||
//#include <math.h>
|
||||
#include <string.h>
|
||||
#include "mbed_assert.h"
|
||||
|
||||
#include "serial_api.h"
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
|
||||
/******************************************************************************
|
||||
* INITIALIZATION
|
||||
******************************************************************************/
|
||||
#define UART_NUM 1
|
||||
|
||||
static uint32_t serial_irq_ids[UART_NUM] = {0};
|
||||
static uart_irq_handler irq_handler;
|
||||
static const int acceptedSpeeds[18][2] = {
|
||||
{1200, UART_BAUDRATE_BAUDRATE_Baud1200},
|
||||
{2400, UART_BAUDRATE_BAUDRATE_Baud2400},
|
||||
{4800, UART_BAUDRATE_BAUDRATE_Baud4800},
|
||||
{9600, UART_BAUDRATE_BAUDRATE_Baud9600},
|
||||
{14400, UART_BAUDRATE_BAUDRATE_Baud14400},
|
||||
{19200, UART_BAUDRATE_BAUDRATE_Baud19200},
|
||||
{28800, UART_BAUDRATE_BAUDRATE_Baud28800},
|
||||
{31250, (0x00800000UL) /* 31250 baud */},
|
||||
{38400, UART_BAUDRATE_BAUDRATE_Baud38400},
|
||||
{56000, (0x00E51000UL) /* 56000 baud */},
|
||||
{57600, UART_BAUDRATE_BAUDRATE_Baud57600},
|
||||
{76800, UART_BAUDRATE_BAUDRATE_Baud76800},
|
||||
{115200, UART_BAUDRATE_BAUDRATE_Baud115200},
|
||||
{230400, UART_BAUDRATE_BAUDRATE_Baud230400},
|
||||
{250000, UART_BAUDRATE_BAUDRATE_Baud250000},
|
||||
{460800, UART_BAUDRATE_BAUDRATE_Baud460800},
|
||||
{921600, UART_BAUDRATE_BAUDRATE_Baud921600},
|
||||
{1000000, UART_BAUDRATE_BAUDRATE_Baud1M}
|
||||
};
|
||||
|
||||
int stdio_uart_inited = 0;
|
||||
serial_t stdio_uart;
|
||||
|
||||
|
||||
void serial_init(serial_t *obj, PinName tx, PinName rx) {
|
||||
UARTName uart = UART_0;
|
||||
obj->uart = (NRF_UART_Type *)uart;
|
||||
|
||||
//pin configurations --
|
||||
NRF_GPIO->OUT |= (1 << tx);
|
||||
NRF_GPIO->OUT |= (1 << RTS_PIN_NUMBER);
|
||||
NRF_GPIO->DIR |= (1 << tx); //TX_PIN_NUMBER);
|
||||
NRF_GPIO->DIR |= (1 << RTS_PIN_NUMBER);
|
||||
|
||||
NRF_GPIO->DIR &= ~(1 << rx); //RX_PIN_NUMBER);
|
||||
NRF_GPIO->DIR &= ~(1 << CTS_PIN_NUMBER);
|
||||
|
||||
|
||||
// set default baud rate and format
|
||||
serial_baud (obj, 9600);
|
||||
serial_format(obj, 8, ParityNone, 1);
|
||||
|
||||
obj->uart->ENABLE = (UART_ENABLE_ENABLE_Enabled << UART_ENABLE_ENABLE_Pos);
|
||||
obj->uart->TASKS_STARTTX = 1;
|
||||
obj->uart->TASKS_STARTRX = 1;
|
||||
obj->uart->EVENTS_RXDRDY = 0;
|
||||
// dummy write needed or TXDRDY trails write rather than leads write.
|
||||
// pins are disconnected so nothing is physically transmitted on the wire
|
||||
obj->uart->PSELTXD = 0xFFFFFFFF;
|
||||
obj->uart->EVENTS_TXDRDY = 0;
|
||||
obj->uart->TXD = 0;
|
||||
while (obj->uart->EVENTS_TXDRDY != 1);
|
||||
|
||||
obj->index = 0;
|
||||
|
||||
obj->uart->PSELRTS = RTS_PIN_NUMBER;
|
||||
obj->uart->PSELTXD = tx; //TX_PIN_NUMBER;
|
||||
obj->uart->PSELCTS = CTS_PIN_NUMBER;
|
||||
obj->uart->PSELRXD = rx; //RX_PIN_NUMBER;
|
||||
|
||||
// set rx/tx pins in PullUp mode
|
||||
if (tx != NC) {
|
||||
pin_mode(tx, PullUp);
|
||||
}
|
||||
if (rx != NC) {
|
||||
pin_mode(rx, PullUp);
|
||||
}
|
||||
|
||||
if (uart == STDIO_UART) {
|
||||
stdio_uart_inited = 1;
|
||||
memcpy(&stdio_uart, obj, sizeof(serial_t));
|
||||
}
|
||||
}
|
||||
|
||||
void serial_free(serial_t *obj)
|
||||
{
|
||||
serial_irq_ids[obj->index] = 0;
|
||||
}
|
||||
|
||||
// serial_baud
|
||||
// set the baud rate, taking in to account the current SystemFrequency
|
||||
void serial_baud(serial_t *obj, int baudrate)
|
||||
{
|
||||
if (baudrate<=1200) {
|
||||
obj->uart->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud1200;
|
||||
return;
|
||||
}
|
||||
|
||||
for (int i = 1; i<17; i++) {
|
||||
if (baudrate<acceptedSpeeds[i][0]) {
|
||||
obj->uart->BAUDRATE = acceptedSpeeds[i - 1][1];
|
||||
return;
|
||||
}
|
||||
}
|
||||
obj->uart->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud1M;
|
||||
}
|
||||
|
||||
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
|
||||
{
|
||||
// 0: 1 stop bits, 1: 2 stop bits
|
||||
// int parity_enable, parity_select;
|
||||
switch (parity) {
|
||||
case ParityNone:
|
||||
obj->uart->CONFIG = 0;
|
||||
break;
|
||||
default:
|
||||
obj->uart->CONFIG = (UART_CONFIG_PARITY_Included << UART_CONFIG_PARITY_Pos);
|
||||
return;
|
||||
}
|
||||
//no Flow Control
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
// * INTERRUPT HANDLING
|
||||
//******************************************************************************
|
||||
static inline void uart_irq(uint32_t iir, uint32_t index)
|
||||
{
|
||||
SerialIrq irq_type;
|
||||
switch (iir) {
|
||||
case 1:
|
||||
irq_type = TxIrq;
|
||||
break;
|
||||
case 2:
|
||||
irq_type = RxIrq;
|
||||
break;
|
||||
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
if (serial_irq_ids[index] != 0) {
|
||||
irq_handler(serial_irq_ids[index], irq_type);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void UART0_IRQHandler()
|
||||
{
|
||||
uint32_t irtype = 0;
|
||||
|
||||
if((NRF_UART0->INTENSET & 0x80) && NRF_UART0->EVENTS_TXDRDY) {
|
||||
irtype = 1;
|
||||
} else if((NRF_UART0->INTENSET & 0x04) && NRF_UART0->EVENTS_RXDRDY) {
|
||||
irtype = 2;
|
||||
}
|
||||
uart_irq(irtype, 0);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
|
||||
{
|
||||
irq_handler = handler;
|
||||
serial_irq_ids[obj->index] = id;
|
||||
}
|
||||
|
||||
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
|
||||
{
|
||||
IRQn_Type irq_n = (IRQn_Type)0;
|
||||
|
||||
switch ((int)obj->uart) {
|
||||
case UART_0:
|
||||
irq_n = UART0_IRQn;
|
||||
break;
|
||||
}
|
||||
|
||||
if (enable) {
|
||||
switch (irq) {
|
||||
case RxIrq:
|
||||
obj->uart->INTENSET = (UART_INTENSET_RXDRDY_Msk);
|
||||
break;
|
||||
case TxIrq:
|
||||
obj->uart->INTENSET = (UART_INTENSET_TXDRDY_Msk);
|
||||
break;
|
||||
}
|
||||
NVIC_SetPriority(irq_n, 3);
|
||||
NVIC_EnableIRQ(irq_n);
|
||||
} else { // disable
|
||||
// maseked writes to INTENSET dont disable and masked writes to
|
||||
// INTENCLR seemed to clear the entire register, not bits.
|
||||
// Added INTEN to memory map and seems to allow set and clearing of specific bits as desired
|
||||
int all_disabled = 0;
|
||||
switch (irq) {
|
||||
case RxIrq:
|
||||
obj->uart->INTENCLR = (UART_INTENCLR_RXDRDY_Msk);
|
||||
all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_TXDRDY_Msk)) == 0;
|
||||
break;
|
||||
case TxIrq:
|
||||
obj->uart->INTENCLR = (UART_INTENCLR_TXDRDY_Msk);
|
||||
all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_RXDRDY_Msk)) == 0;
|
||||
break;
|
||||
}
|
||||
|
||||
if (all_disabled) {
|
||||
NVIC_DisableIRQ(irq_n);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
//* READ/WRITE
|
||||
//******************************************************************************
|
||||
int serial_getc(serial_t *obj)
|
||||
{
|
||||
while (!serial_readable(obj)) {
|
||||
}
|
||||
|
||||
obj->uart->EVENTS_RXDRDY = 0;
|
||||
|
||||
return (uint8_t)obj->uart->RXD;
|
||||
}
|
||||
|
||||
void serial_putc(serial_t *obj, int c)
|
||||
{
|
||||
while (!serial_writable(obj)) {
|
||||
}
|
||||
|
||||
obj->uart->EVENTS_TXDRDY = 0;
|
||||
obj->uart->TXD = (uint8_t)c;
|
||||
}
|
||||
|
||||
int serial_readable(serial_t *obj)
|
||||
{
|
||||
return (obj->uart->EVENTS_RXDRDY == 1);
|
||||
}
|
||||
|
||||
int serial_writable(serial_t *obj)
|
||||
{
|
||||
return (obj->uart->EVENTS_TXDRDY == 1);
|
||||
}
|
||||
|
||||
void serial_break_set(serial_t *obj)
|
||||
{
|
||||
obj->uart->TASKS_SUSPEND = 1;
|
||||
}
|
||||
|
||||
void serial_break_clear(serial_t *obj)
|
||||
{
|
||||
obj->uart->TASKS_STARTTX = 1;
|
||||
obj->uart->TASKS_STARTRX = 1;
|
||||
}
|
||||
|
||||
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
|
||||
{
|
||||
|
||||
if (type == FlowControlRTSCTS || type == FlowControlRTS) {
|
||||
NRF_GPIO->DIR |= (1<<rxflow);
|
||||
pin_mode(rxflow, PullUp);
|
||||
obj->uart->PSELRTS = rxflow;
|
||||
|
||||
obj->uart->CONFIG |= 0x01; // Enable HWFC
|
||||
}
|
||||
|
||||
if (type == FlowControlRTSCTS || type == FlowControlCTS) {
|
||||
NRF_GPIO->DIR &= ~(1<<txflow);
|
||||
pin_mode(txflow, PullUp);
|
||||
obj->uart->PSELCTS = txflow;
|
||||
|
||||
obj->uart->CONFIG |= 0x01; // Enable HWFC;
|
||||
}
|
||||
|
||||
if (type == FlowControlNone) {
|
||||
obj->uart->PSELRTS = 0xFFFFFFFF; // Disable RTS
|
||||
obj->uart->PSELCTS = 0xFFFFFFFF; // Disable CTS
|
||||
|
||||
obj->uart->CONFIG &= ~0x01; // Enable HWFC;
|
||||
}
|
||||
}
|
||||
|
||||
void serial_clear(serial_t *obj) {
|
||||
}
|
||||
|
|
@ -1,286 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
//#include <math.h>
|
||||
#include "mbed_assert.h"
|
||||
#include "spi_api.h"
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
#include "mbed_error.h"
|
||||
|
||||
#define SPIS_MESSAGE_SIZE 1
|
||||
volatile uint8_t m_tx_buf[SPIS_MESSAGE_SIZE] = {0};
|
||||
volatile uint8_t m_rx_buf[SPIS_MESSAGE_SIZE] = {0};
|
||||
|
||||
// nRF51822's I2C_0 and SPI_0 (I2C_1, SPI_1 and SPIS1) share the same address.
|
||||
// They can't be used at the same time. So we use two global variable to track the usage.
|
||||
// See nRF51822 address information at nRF51822_PS v2.0.pdf - Table 15 Peripheral instance reference
|
||||
extern volatile i2c_spi_peripheral_t i2c0_spi0_peripheral; // from i2c_api.c
|
||||
extern volatile i2c_spi_peripheral_t i2c1_spi1_peripheral;
|
||||
|
||||
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
|
||||
{
|
||||
SPIName spi;
|
||||
|
||||
if (ssel == NC && i2c0_spi0_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_SPI &&
|
||||
i2c0_spi0_peripheral.sda_mosi == (uint8_t)mosi &&
|
||||
i2c0_spi0_peripheral.scl_miso == (uint8_t)miso &&
|
||||
i2c0_spi0_peripheral.sclk == (uint8_t)sclk) {
|
||||
// The SPI with the same pins is already initialized
|
||||
spi = SPI_0;
|
||||
obj->peripheral = 0x1;
|
||||
} else if (ssel == NC && i2c1_spi1_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_SPI &&
|
||||
i2c1_spi1_peripheral.sda_mosi == (uint8_t)mosi &&
|
||||
i2c1_spi1_peripheral.scl_miso == (uint8_t)miso &&
|
||||
i2c1_spi1_peripheral.sclk == (uint8_t)sclk) {
|
||||
// The SPI with the same pins is already initialized
|
||||
spi = SPI_1;
|
||||
obj->peripheral = 0x2;
|
||||
} else if (i2c1_spi1_peripheral.usage == 0) {
|
||||
i2c1_spi1_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_SPI;
|
||||
i2c1_spi1_peripheral.sda_mosi = (uint8_t)mosi;
|
||||
i2c1_spi1_peripheral.scl_miso = (uint8_t)miso;
|
||||
i2c1_spi1_peripheral.sclk = (uint8_t)sclk;
|
||||
|
||||
spi = SPI_1;
|
||||
obj->peripheral = 0x2;
|
||||
} else if (i2c0_spi0_peripheral.usage == 0) {
|
||||
i2c0_spi0_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_SPI;
|
||||
i2c0_spi0_peripheral.sda_mosi = (uint8_t)mosi;
|
||||
i2c0_spi0_peripheral.scl_miso = (uint8_t)miso;
|
||||
i2c0_spi0_peripheral.sclk = (uint8_t)sclk;
|
||||
|
||||
spi = SPI_0;
|
||||
obj->peripheral = 0x1;
|
||||
} else {
|
||||
// No available peripheral
|
||||
error("No available SPI");
|
||||
}
|
||||
|
||||
if (ssel==NC) {
|
||||
obj->spi = (NRF_SPI_Type *)spi;
|
||||
obj->spis = (NRF_SPIS_Type *)NC;
|
||||
} else {
|
||||
obj->spi = (NRF_SPI_Type *)NC;
|
||||
obj->spis = (NRF_SPIS_Type *)spi;
|
||||
}
|
||||
|
||||
// pin out the spi pins
|
||||
if (ssel != NC) { //slave
|
||||
obj->spis->POWER = 0;
|
||||
obj->spis->POWER = 1;
|
||||
|
||||
NRF_GPIO->PIN_CNF[mosi] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_GPIO->PIN_CNF[miso] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_GPIO->PIN_CNF[sclk] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_GPIO->PIN_CNF[ssel] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
|
||||
|
||||
obj->spis->PSELMOSI = mosi;
|
||||
obj->spis->PSELMISO = miso;
|
||||
obj->spis->PSELSCK = sclk;
|
||||
obj->spis->PSELCSN = ssel;
|
||||
|
||||
obj->spis->EVENTS_END = 0;
|
||||
obj->spis->EVENTS_ACQUIRED = 0;
|
||||
obj->spis->MAXRX = SPIS_MESSAGE_SIZE;
|
||||
obj->spis->MAXTX = SPIS_MESSAGE_SIZE;
|
||||
obj->spis->TXDPTR = (uint32_t)&m_tx_buf[0];
|
||||
obj->spis->RXDPTR = (uint32_t)&m_rx_buf[0];
|
||||
obj->spis->SHORTS = (SPIS_SHORTS_END_ACQUIRE_Enabled << SPIS_SHORTS_END_ACQUIRE_Pos);
|
||||
|
||||
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
|
||||
} else { //master
|
||||
obj->spi->POWER = 0;
|
||||
obj->spi->POWER = 1;
|
||||
|
||||
//NRF_GPIO->DIR |= (1<<mosi);
|
||||
NRF_GPIO->PIN_CNF[mosi] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
obj->spi->PSELMOSI = mosi;
|
||||
|
||||
NRF_GPIO->PIN_CNF[sclk] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
obj->spi->PSELSCK = sclk;
|
||||
|
||||
//NRF_GPIO->DIR &= ~(1<<miso);
|
||||
NRF_GPIO->PIN_CNF[miso] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
|
||||
|
||||
obj->spi->PSELMISO = miso;
|
||||
|
||||
obj->spi->EVENTS_READY = 0U;
|
||||
|
||||
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
|
||||
spi_frequency(obj, 1000000);
|
||||
}
|
||||
}
|
||||
|
||||
void spi_free(spi_t *obj)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void spi_disable(spi_t *obj, int slave)
|
||||
{
|
||||
if (slave) {
|
||||
obj->spis->ENABLE = (SPIS_ENABLE_ENABLE_Disabled << SPIS_ENABLE_ENABLE_Pos);
|
||||
} else {
|
||||
obj->spi->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void spi_enable(spi_t *obj, int slave)
|
||||
{
|
||||
if (slave) {
|
||||
obj->spis->ENABLE = (SPIS_ENABLE_ENABLE_Enabled << SPIS_ENABLE_ENABLE_Pos);
|
||||
} else {
|
||||
obj->spi->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
|
||||
}
|
||||
}
|
||||
|
||||
void spi_format(spi_t *obj, int bits, int mode, int slave)
|
||||
{
|
||||
uint32_t config_mode = 0;
|
||||
spi_disable(obj, slave);
|
||||
|
||||
if (bits != 8) {
|
||||
error("Only 8bits SPI supported");
|
||||
}
|
||||
|
||||
switch (mode) {
|
||||
case 0:
|
||||
config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
|
||||
break;
|
||||
case 1:
|
||||
config_mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
|
||||
break;
|
||||
case 2:
|
||||
config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
|
||||
break;
|
||||
case 3:
|
||||
config_mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
|
||||
break;
|
||||
default:
|
||||
error("SPI format error");
|
||||
break;
|
||||
}
|
||||
//default to msb first
|
||||
if (slave) {
|
||||
obj->spis->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos));
|
||||
} else {
|
||||
obj->spi->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos));
|
||||
}
|
||||
|
||||
spi_enable(obj, slave);
|
||||
}
|
||||
|
||||
void spi_frequency(spi_t *obj, int hz)
|
||||
{
|
||||
if ((int)obj->spi==NC) {
|
||||
return;
|
||||
}
|
||||
spi_disable(obj, 0);
|
||||
|
||||
if (hz<250000) { //125Kbps
|
||||
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_K125;
|
||||
} else if (hz<500000) { //250Kbps
|
||||
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_K250;
|
||||
} else if (hz<1000000) { //500Kbps
|
||||
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_K500;
|
||||
} else if (hz<2000000) { //1Mbps
|
||||
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M1;
|
||||
} else if (hz<4000000) { //2Mbps
|
||||
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M2;
|
||||
} else if (hz<8000000) { //4Mbps
|
||||
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M4;
|
||||
} else { //8Mbps
|
||||
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M8;
|
||||
}
|
||||
|
||||
spi_enable(obj, 0);
|
||||
}
|
||||
|
||||
static inline int spi_readable(spi_t *obj)
|
||||
{
|
||||
return (obj->spi->EVENTS_READY == 1);
|
||||
}
|
||||
|
||||
static inline int spi_writeable(spi_t *obj)
|
||||
{
|
||||
return (obj->spi->EVENTS_READY == 0);
|
||||
}
|
||||
|
||||
static inline int spi_read(spi_t *obj)
|
||||
{
|
||||
while (!spi_readable(obj)) {
|
||||
}
|
||||
|
||||
obj->spi->EVENTS_READY = 0;
|
||||
return (int)obj->spi->RXD;
|
||||
}
|
||||
|
||||
int spi_master_write(spi_t *obj, int value)
|
||||
{
|
||||
while (!spi_writeable(obj)) {
|
||||
}
|
||||
obj->spi->TXD = (uint32_t)value;
|
||||
return spi_read(obj);
|
||||
}
|
||||
|
||||
//static inline int spis_writeable(spi_t *obj) {
|
||||
// return (obj->spis->EVENTS_ACQUIRED==1);
|
||||
//}
|
||||
|
||||
int spi_slave_receive(spi_t *obj)
|
||||
{
|
||||
return obj->spis->EVENTS_END;
|
||||
}
|
||||
|
||||
int spi_slave_read(spi_t *obj)
|
||||
{
|
||||
return m_rx_buf[0];
|
||||
}
|
||||
|
||||
void spi_slave_write(spi_t *obj, int value)
|
||||
{
|
||||
m_tx_buf[0] = value & 0xFF;
|
||||
obj->spis->TASKS_RELEASE = 1;
|
||||
obj->spis->EVENTS_ACQUIRED = 0;
|
||||
obj->spis->EVENTS_END = 0;
|
||||
}
|
||||
|
|
@ -1,20 +0,0 @@
|
|||
/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
|
||||
*
|
||||
* The information contained herein is property of Nordic Semiconductor ASA.
|
||||
* Terms and conditions of usage are described in detail in NORDIC
|
||||
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* Licensees are granted free, non-transferable use of the information. NO
|
||||
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
|
||||
* the file.
|
||||
*
|
||||
*/
|
||||
#ifndef TWI_MASTER_CONFIG
|
||||
#define TWI_MASTER_CONFIG
|
||||
|
||||
#include "PinNames.h"
|
||||
|
||||
#define TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER (I2C_SCL0)
|
||||
#define TWI_MASTER_CONFIG_DATA_PIN_NUMBER (I2C_SDA0)
|
||||
|
||||
#endif
|
||||
|
|
@ -1,304 +0,0 @@
|
|||
/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
|
||||
*
|
||||
* The information contained herein is property of Nordic Semiconductor ASA.
|
||||
* Terms and conditions of usage are described in detail in NORDIC
|
||||
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* Licensees are granted free, non-transferable use of the information. NO
|
||||
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
|
||||
* the file.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "twi_master.h"
|
||||
#include "twi_config.h"
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "nrf.h"
|
||||
#include "nrf_delay.h"
|
||||
|
||||
/* Max cycles approximately to wait on RXDREADY and TXDREADY event,
|
||||
* This is optimized way instead of using timers, this is not power aware. */
|
||||
#define MAX_TIMEOUT_LOOPS (20000UL) /**< MAX while loops to wait for RXD/TXD event */
|
||||
|
||||
static bool twi_master_write(uint8_t * data, uint8_t data_length, bool issue_stop_condition, NRF_TWI_Type* twi)
|
||||
{
|
||||
uint32_t timeout = MAX_TIMEOUT_LOOPS; /* max loops to wait for EVENTS_TXDSENT event*/
|
||||
|
||||
if (data_length == 0)
|
||||
{
|
||||
/* Return false for requesting data of size 0 */
|
||||
return false;
|
||||
}
|
||||
|
||||
twi->TXD = *data++;
|
||||
twi->TASKS_STARTTX = 1;
|
||||
|
||||
/** @snippet [TWI HW master write] */
|
||||
while (true)
|
||||
{
|
||||
while (twi->EVENTS_TXDSENT == 0 && twi->EVENTS_ERROR == 0 && (--timeout))
|
||||
{
|
||||
// Do nothing.
|
||||
}
|
||||
|
||||
if (timeout == 0 || NRF_TWI1->EVENTS_ERROR != 0)
|
||||
{
|
||||
// Recover the peripheral as indicated by PAN 56: "TWI: TWI module lock-up." found at
|
||||
// Product Anomaly Notification document found at
|
||||
// https://www.nordicsemi.com/eng/Products/Bluetooth-R-low-energy/nRF51822/#Downloads
|
||||
twi->EVENTS_ERROR = 0;
|
||||
twi->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos;
|
||||
twi->POWER = 0;
|
||||
nrf_delay_us(5);
|
||||
twi->POWER = 1;
|
||||
twi->ENABLE = TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos;
|
||||
|
||||
(void)twi_master_init_and_clear(twi);
|
||||
|
||||
return false;
|
||||
}
|
||||
twi->EVENTS_TXDSENT = 0;
|
||||
if (--data_length == 0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
twi->TXD = *data++;
|
||||
}
|
||||
/** @snippet [TWI HW master write] */
|
||||
|
||||
if (issue_stop_condition)
|
||||
{
|
||||
twi->EVENTS_STOPPED = 0;
|
||||
twi->TASKS_STOP = 1;
|
||||
/* Wait until stop sequence is sent */
|
||||
while(twi->EVENTS_STOPPED == 0)
|
||||
{
|
||||
// Do nothing.
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
/** @brief Function for read by twi_master.
|
||||
*/
|
||||
static bool twi_master_read(uint8_t * data, uint8_t data_length, bool issue_stop_condition, NRF_TWI_Type* twi)
|
||||
{
|
||||
uint32_t timeout = MAX_TIMEOUT_LOOPS; /* max loops to wait for RXDREADY event*/
|
||||
|
||||
if (data_length == 0)
|
||||
{
|
||||
/* Return false for requesting data of size 0 */
|
||||
return false;
|
||||
}
|
||||
else if (data_length == 1)
|
||||
{
|
||||
NRF_PPI->CH[0].TEP = (uint32_t)&twi->TASKS_STOP;
|
||||
}
|
||||
else
|
||||
{
|
||||
NRF_PPI->CH[0].TEP = (uint32_t)&twi->TASKS_SUSPEND;
|
||||
}
|
||||
|
||||
NRF_PPI->CHENSET = PPI_CHENSET_CH0_Msk;
|
||||
twi->EVENTS_RXDREADY = 0;
|
||||
twi->TASKS_STARTRX = 1;
|
||||
|
||||
/** @snippet [TWI HW master read] */
|
||||
while (true)
|
||||
{
|
||||
while (twi->EVENTS_RXDREADY == 0 && NRF_TWI1->EVENTS_ERROR == 0 && (--timeout))
|
||||
{
|
||||
// Do nothing.
|
||||
}
|
||||
twi->EVENTS_RXDREADY = 0;
|
||||
|
||||
if (timeout == 0 || twi->EVENTS_ERROR != 0)
|
||||
{
|
||||
// Recover the peripheral as indicated by PAN 56: "TWI: TWI module lock-up." found at
|
||||
// Product Anomaly Notification document found at
|
||||
// https://www.nordicsemi.com/eng/Products/Bluetooth-R-low-energy/nRF51822/#Downloads
|
||||
twi->EVENTS_ERROR = 0;
|
||||
twi->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos;
|
||||
twi->POWER = 0;
|
||||
nrf_delay_us(5);
|
||||
twi->POWER = 1;
|
||||
twi->ENABLE = TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos;
|
||||
|
||||
(void)twi_master_init_and_clear(twi);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
*data++ = NRF_TWI1->RXD;
|
||||
|
||||
/* Configure PPI to stop TWI master before we get last BB event */
|
||||
if (--data_length == 1)
|
||||
{
|
||||
NRF_PPI->CH[0].TEP = (uint32_t)&NRF_TWI1->TASKS_STOP;
|
||||
}
|
||||
|
||||
if (data_length == 0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
// Recover the peripheral as indicated by PAN 56: "TWI: TWI module lock-up." found at
|
||||
// Product Anomaly Notification document found at
|
||||
// https://www.nordicsemi.com/eng/Products/Bluetooth-R-low-energy/nRF51822/#Downloads
|
||||
nrf_delay_us(20);
|
||||
twi->TASKS_RESUME = 1;
|
||||
}
|
||||
/** @snippet [TWI HW master read] */
|
||||
|
||||
/* Wait until stop sequence is sent */
|
||||
while(twi->EVENTS_STOPPED == 0)
|
||||
{
|
||||
// Do nothing.
|
||||
}
|
||||
twi->EVENTS_STOPPED = 0;
|
||||
|
||||
NRF_PPI->CHENCLR = PPI_CHENCLR_CH0_Msk;
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for detecting stuck slaves (SDA = 0 and SCL = 1) and tries to clear the bus.
|
||||
*
|
||||
* @return
|
||||
* @retval false Bus is stuck.
|
||||
* @retval true Bus is clear.
|
||||
*/
|
||||
static bool twi_master_clear_bus(NRF_TWI_Type* twi)
|
||||
{
|
||||
uint32_t twi_state;
|
||||
bool bus_clear;
|
||||
uint32_t clk_pin_config;
|
||||
uint32_t data_pin_config;
|
||||
|
||||
// Save and disable TWI hardware so software can take control over the pins.
|
||||
twi_state = twi->ENABLE;
|
||||
twi->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos;
|
||||
|
||||
clk_pin_config = \
|
||||
NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER];
|
||||
NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER] = \
|
||||
(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
|
||||
| (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \
|
||||
| (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
|
||||
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
|
||||
data_pin_config = \
|
||||
NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_DATA_PIN_NUMBER];
|
||||
NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_DATA_PIN_NUMBER] = \
|
||||
(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
|
||||
| (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \
|
||||
| (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
|
||||
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
|
||||
TWI_SDA_HIGH();
|
||||
TWI_SCL_HIGH();
|
||||
TWI_DELAY();
|
||||
|
||||
if ((TWI_SDA_READ() == 1) && (TWI_SCL_READ() == 1))
|
||||
{
|
||||
bus_clear = true;
|
||||
}
|
||||
else
|
||||
{
|
||||
uint_fast8_t i;
|
||||
bus_clear = false;
|
||||
|
||||
// Clock max 18 pulses worst case scenario(9 for master to send the rest of command and 9
|
||||
// for slave to respond) to SCL line and wait for SDA come high.
|
||||
for (i=18; i--;)
|
||||
{
|
||||
TWI_SCL_LOW();
|
||||
TWI_DELAY();
|
||||
TWI_SCL_HIGH();
|
||||
TWI_DELAY();
|
||||
|
||||
if (TWI_SDA_READ() == 1)
|
||||
{
|
||||
bus_clear = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER] = clk_pin_config;
|
||||
NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_DATA_PIN_NUMBER] = data_pin_config;
|
||||
|
||||
twi->ENABLE = twi_state;
|
||||
|
||||
return bus_clear;
|
||||
}
|
||||
|
||||
|
||||
/** @brief Function for initializing the twi_master.
|
||||
*/
|
||||
bool twi_master_init_and_clear(NRF_TWI_Type* twi)
|
||||
{
|
||||
/* To secure correct signal levels on the pins used by the TWI
|
||||
master when the system is in OFF mode, and when the TWI master is
|
||||
disabled, these pins must be configured in the GPIO peripheral.
|
||||
*/
|
||||
NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER] = \
|
||||
(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
|
||||
| (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \
|
||||
| (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
|
||||
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
|
||||
|
||||
NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_DATA_PIN_NUMBER] = \
|
||||
(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
|
||||
| (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \
|
||||
| (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \
|
||||
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
|
||||
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
|
||||
|
||||
twi->EVENTS_RXDREADY = 0;
|
||||
twi->EVENTS_TXDSENT = 0;
|
||||
twi->PSELSCL = TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER;
|
||||
twi->PSELSDA = TWI_MASTER_CONFIG_DATA_PIN_NUMBER;
|
||||
twi->FREQUENCY = TWI_FREQUENCY_FREQUENCY_K100 << TWI_FREQUENCY_FREQUENCY_Pos;
|
||||
NRF_PPI->CH[0].EEP = (uint32_t)&twi->EVENTS_BB;
|
||||
NRF_PPI->CH[0].TEP = (uint32_t)&twi->TASKS_SUSPEND;
|
||||
NRF_PPI->CHENCLR = PPI_CHENCLR_CH0_Msk;
|
||||
twi->ENABLE = TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos;
|
||||
|
||||
return twi_master_clear_bus(twi);
|
||||
}
|
||||
|
||||
|
||||
/** @brief Function for transfer by twi_master.
|
||||
*/
|
||||
bool twi_master_transfer(uint8_t address,
|
||||
uint8_t * data,
|
||||
uint8_t data_length,
|
||||
bool issue_stop_condition,
|
||||
NRF_TWI_Type* twi)
|
||||
{
|
||||
bool transfer_succeeded = false;
|
||||
if (data_length > 0 && twi_master_clear_bus(twi))
|
||||
{
|
||||
twi->ADDRESS = (address >> 1);
|
||||
|
||||
if ((address & TWI_READ_BIT))
|
||||
{
|
||||
transfer_succeeded = twi_master_read(data, data_length, issue_stop_condition, twi);
|
||||
}
|
||||
else
|
||||
{
|
||||
transfer_succeeded = twi_master_write(data, data_length, issue_stop_condition, twi);
|
||||
}
|
||||
}
|
||||
return transfer_succeeded;
|
||||
}
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
|
@ -1,112 +0,0 @@
|
|||
/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
|
||||
*
|
||||
* The information contained herein is property of Nordic Semiconductor ASA.
|
||||
* Terms and conditions of usage are described in detail in NORDIC
|
||||
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* Licensees are granted free, non-transferable use of the information. NO
|
||||
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
|
||||
* the file.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef TWI_MASTER_H
|
||||
#define TWI_MASTER_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*lint ++flb "Enter library region" */
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "nrf51.h"
|
||||
|
||||
/** @file
|
||||
* @brief Software controlled TWI Master driver.
|
||||
*
|
||||
*
|
||||
* @defgroup lib_driver_twi_master Software controlled TWI Master driver
|
||||
* @{
|
||||
* @ingroup nrf_drivers
|
||||
* @brief Software controlled TWI Master driver.
|
||||
*
|
||||
* Supported features:
|
||||
* - Repeated start
|
||||
* - No multi-master
|
||||
* - Only 7-bit addressing
|
||||
* - Supports clock stretching (with optional SMBus style slave timeout)
|
||||
* - Tries to handle slaves stuck in the middle of transfer
|
||||
*/
|
||||
|
||||
#define TWI_READ_BIT (0x01) //!< If this bit is set in the address field, transfer direction is from slave to master.
|
||||
|
||||
#define TWI_ISSUE_STOP ((bool)true) //!< Parameter for @ref twi_master_transfer
|
||||
#define TWI_DONT_ISSUE_STOP ((bool)false) //!< Parameter for @ref twi_master_transfer
|
||||
|
||||
/* These macros are needed to see if the slave is stuck and we as master send dummy clock cycles to end its wait */
|
||||
/*lint -e717 -save "Suppress do {} while (0) for these macros" */
|
||||
/*lint ++flb "Enter library region" */
|
||||
#define TWI_SCL_HIGH() do { NRF_GPIO->OUTSET = (1UL << TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER); } while(0) /*!< Pulls SCL line high */
|
||||
#define TWI_SCL_LOW() do { NRF_GPIO->OUTCLR = (1UL << TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER); } while(0) /*!< Pulls SCL line low */
|
||||
#define TWI_SDA_HIGH() do { NRF_GPIO->OUTSET = (1UL << TWI_MASTER_CONFIG_DATA_PIN_NUMBER); } while(0) /*!< Pulls SDA line high */
|
||||
#define TWI_SDA_LOW() do { NRF_GPIO->OUTCLR = (1UL << TWI_MASTER_CONFIG_DATA_PIN_NUMBER); } while(0) /*!< Pulls SDA line low */
|
||||
#define TWI_SDA_INPUT() do { NRF_GPIO->DIRCLR = (1UL << TWI_MASTER_CONFIG_DATA_PIN_NUMBER); } while(0) /*!< Configures SDA pin as input */
|
||||
#define TWI_SDA_OUTPUT() do { NRF_GPIO->DIRSET = (1UL << TWI_MASTER_CONFIG_DATA_PIN_NUMBER); } while(0) /*!< Configures SDA pin as output */
|
||||
#define TWI_SCL_OUTPUT() do { NRF_GPIO->DIRSET = (1UL << TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER); } while(0) /*!< Configures SCL pin as output */
|
||||
/*lint -restore */
|
||||
|
||||
#define TWI_SDA_READ() ((NRF_GPIO->IN >> TWI_MASTER_CONFIG_DATA_PIN_NUMBER) & 0x1UL) /*!< Reads current state of SDA */
|
||||
#define TWI_SCL_READ() ((NRF_GPIO->IN >> TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER) & 0x1UL) /*!< Reads current state of SCL */
|
||||
|
||||
#define TWI_DELAY() nrf_delay_us(4) /*!< Time to wait when pin states are changed. For fast-mode the delay can be zero and for standard-mode 4 us delay is sufficient. */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for initializing TWI bus IO pins and checks if the bus is operational.
|
||||
*
|
||||
* Both pins are configured as Standard-0, No-drive-1 (open drain).
|
||||
*
|
||||
* @param twi The TWI interface to use - either NRF_TWI0 or NRF_TWI1
|
||||
* @return
|
||||
* @retval true TWI bus is clear for transfers.
|
||||
* @retval false TWI bus is stuck.
|
||||
*/
|
||||
bool twi_master_init_and_clear(NRF_TWI_Type* twi);
|
||||
|
||||
/**
|
||||
* @brief Function for transferring data over TWI bus.
|
||||
*
|
||||
* If TWI master detects even one NACK from the slave or timeout occurs, STOP condition is issued
|
||||
* and the function returns false.
|
||||
* Bit 0 (@ref TWI_READ_BIT) in the address parameter controls transfer direction;
|
||||
* - If 1, master reads data_length number of bytes from the slave
|
||||
* - If 0, master writes data_length number of bytes to the slave.
|
||||
*
|
||||
* @note Make sure at least data_length number of bytes is allocated in data if TWI_READ_BIT is set.
|
||||
* @note @ref TWI_ISSUE_STOP
|
||||
*
|
||||
* @param address Data transfer direction (LSB) / Slave address (7 MSBs).
|
||||
* @param data Pointer to data.
|
||||
* @param data_length Number of bytes to transfer.
|
||||
* @param issue_stop_condition If @ref TWI_ISSUE_STOP, STOP condition is issued before exiting function. If @ref TWI_DONT_ISSUE_STOP, STOP condition is not issued before exiting function. If transfer failed for any reason, STOP condition will be issued in any case.
|
||||
* @param twi The TWI interface to use - either NRF_TWI0 or NRF_TWI1
|
||||
* @return
|
||||
* @retval true Data transfer succeeded without errors.
|
||||
* @retval false Data transfer failed.
|
||||
*/
|
||||
bool twi_master_transfer(uint8_t address, uint8_t *data, uint8_t data_length, bool issue_stop_condition, NRF_TWI_Type* twi);
|
||||
|
||||
/**
|
||||
*@}
|
||||
**/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
#endif //TWI_MASTER_H
|
||||
|
|
@ -1,602 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
#include "us_ticker_api.h"
|
||||
#include "cmsis.h"
|
||||
#include "PeripheralNames.h"
|
||||
#include "nrf_delay.h"
|
||||
#include "toolchain.h"
|
||||
|
||||
/*
|
||||
* Note: The micro-second timer API on the nRF51 platform is implemented using
|
||||
* the RTC counter run at 32kHz (sourced from an external oscillator). This is
|
||||
* a trade-off between precision and power. Running a normal 32-bit MCU counter
|
||||
* at high frequency causes the average power consumption to rise to a few
|
||||
* hundred micro-amps, which is prohibitive for typical low-power BLE
|
||||
* applications.
|
||||
* A 32kHz clock doesn't offer the precision needed for keeping u-second time,
|
||||
* but we're assuming that this will not be a problem for the average user.
|
||||
*/
|
||||
|
||||
#define MAX_RTC_COUNTER_VAL 0x00FFFFFF /**< Maximum value of the RTC counter. */
|
||||
#define RTC_CLOCK_FREQ (uint32_t)(32768)
|
||||
#define RTC1_IRQ_PRI 3 /**< Priority of the RTC1 interrupt (used
|
||||
* for checking for timeouts and executing
|
||||
* timeout handlers). This must be the same
|
||||
* as APP_IRQ_PRIORITY_LOW; taken from the
|
||||
* Nordic SDK. */
|
||||
#define MAX_RTC_TASKS_DELAY 47 /**< Maximum delay until an RTC task is executed. */
|
||||
|
||||
#define FUZZY_RTC_TICKS 2 /* RTC COMPARE occurs when a CC register is N and the RTC
|
||||
* COUNTER value transitions from N-1 to N. If we're trying to
|
||||
* setup a callback for a time which will arrive very shortly,
|
||||
* there are limits to how short the callback interval may be for us
|
||||
* to rely upon the RTC Compare trigger. If the COUNTER is N,
|
||||
* writing N+2 to a CC register is guaranteed to trigger a COMPARE
|
||||
* event at N+2. */
|
||||
|
||||
#define RTC_UNITS_TO_MICROSECONDS(RTC_UNITS) (((RTC_UNITS) * (uint64_t)1000000) / RTC_CLOCK_FREQ)
|
||||
#define MICROSECONDS_TO_RTC_UNITS(MICROS) ((((uint64_t)(MICROS) * RTC_CLOCK_FREQ) + 999999) / 1000000)
|
||||
|
||||
static bool us_ticker_inited = false;
|
||||
static volatile uint32_t overflowCount; /**< The number of times the 24-bit RTC counter has overflowed. */
|
||||
static volatile bool us_ticker_callbackPending = false;
|
||||
static uint32_t us_ticker_callbackTimestamp;
|
||||
static bool os_tick_started = false; /**< flag indicating if the os_tick has started */
|
||||
/**
|
||||
* The value previously set in the capture compare register of channel 1
|
||||
*/
|
||||
static uint32_t previous_tick_cc_value = 0;
|
||||
|
||||
/*
|
||||
RTX provide the following definitions which are used by the tick code:
|
||||
* os_trv: The number (minus 1) of clock cycle between two tick.
|
||||
* os_clockrate: Time duration between two ticks (in us).
|
||||
* OS_Tick_Handler: The function which handle a tick event.
|
||||
This function is special because it never returns.
|
||||
Those definitions are used by the code which handle the os tick.
|
||||
To allow compilation of us_ticker programs without RTOS, those symbols are
|
||||
exported from this module as weak ones.
|
||||
*/
|
||||
MBED_WEAK uint32_t const os_trv;
|
||||
MBED_WEAK uint32_t const os_clockrate;
|
||||
MBED_WEAK void OS_Tick_Handler() { }
|
||||
|
||||
static inline void rtc1_enableCompareInterrupt(void)
|
||||
{
|
||||
NRF_RTC1->EVTENCLR = RTC_EVTEN_COMPARE0_Msk;
|
||||
NRF_RTC1->INTENSET = RTC_INTENSET_COMPARE0_Msk;
|
||||
}
|
||||
|
||||
static inline void rtc1_disableCompareInterrupt(void)
|
||||
{
|
||||
NRF_RTC1->INTENCLR = RTC_INTENSET_COMPARE0_Msk;
|
||||
NRF_RTC1->EVTENCLR = RTC_EVTEN_COMPARE0_Msk;
|
||||
}
|
||||
|
||||
static inline void rtc1_enableOverflowInterrupt(void)
|
||||
{
|
||||
NRF_RTC1->EVTENCLR = RTC_EVTEN_OVRFLW_Msk;
|
||||
NRF_RTC1->INTENSET = RTC_INTENSET_OVRFLW_Msk;
|
||||
}
|
||||
|
||||
static inline void rtc1_disableOverflowInterrupt(void)
|
||||
{
|
||||
NRF_RTC1->INTENCLR = RTC_INTENSET_OVRFLW_Msk;
|
||||
NRF_RTC1->EVTENCLR = RTC_EVTEN_OVRFLW_Msk;
|
||||
}
|
||||
|
||||
static inline void invokeCallback(void)
|
||||
{
|
||||
us_ticker_callbackPending = false;
|
||||
rtc1_disableCompareInterrupt();
|
||||
us_ticker_irq_handler();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for starting the RTC1 timer. The RTC timer is expected to
|
||||
* keep running--some interrupts may be disabled temporarily.
|
||||
*/
|
||||
static void rtc1_start()
|
||||
{
|
||||
NRF_RTC1->PRESCALER = 0; /* for no pre-scaling. */
|
||||
|
||||
rtc1_enableOverflowInterrupt();
|
||||
|
||||
NVIC_SetPriority(RTC1_IRQn, RTC1_IRQ_PRI);
|
||||
NVIC_ClearPendingIRQ(RTC1_IRQn);
|
||||
NVIC_EnableIRQ(RTC1_IRQn);
|
||||
|
||||
NRF_RTC1->TASKS_START = 1;
|
||||
nrf_delay_us(MAX_RTC_TASKS_DELAY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for stopping the RTC1 timer. We don't expect to call this.
|
||||
*/
|
||||
void rtc1_stop(void)
|
||||
{
|
||||
// If the os tick has been started, RTC1 shouldn't be stopped
|
||||
// In that case, us ticker and overflow interrupt are disabled.
|
||||
if (os_tick_started) {
|
||||
rtc1_disableCompareInterrupt();
|
||||
rtc1_disableOverflowInterrupt();
|
||||
} else {
|
||||
NVIC_DisableIRQ(RTC1_IRQn);
|
||||
rtc1_disableCompareInterrupt();
|
||||
rtc1_disableOverflowInterrupt();
|
||||
|
||||
NRF_RTC1->TASKS_STOP = 1;
|
||||
nrf_delay_us(MAX_RTC_TASKS_DELAY);
|
||||
|
||||
NRF_RTC1->TASKS_CLEAR = 1;
|
||||
nrf_delay_us(MAX_RTC_TASKS_DELAY);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for returning the current value of the RTC1 counter.
|
||||
*
|
||||
* @return Current RTC1 counter as a 64-bit value with 56-bit precision (even
|
||||
* though the underlying counter is 24-bit)
|
||||
*/
|
||||
static inline uint64_t rtc1_getCounter64(void)
|
||||
{
|
||||
if (NRF_RTC1->EVENTS_OVRFLW) {
|
||||
overflowCount++;
|
||||
NRF_RTC1->EVENTS_OVRFLW = 0;
|
||||
NRF_RTC1->EVTENCLR = RTC_EVTEN_OVRFLW_Msk;
|
||||
}
|
||||
return ((uint64_t)overflowCount << 24) | NRF_RTC1->COUNTER;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for returning the current value of the RTC1 counter.
|
||||
*
|
||||
* @return Current RTC1 counter as a 32-bit value (even though the underlying counter is 24-bit)
|
||||
*/
|
||||
static inline uint32_t rtc1_getCounter(void)
|
||||
{
|
||||
return rtc1_getCounter64();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for handling the RTC1 interrupt for us ticker (capture compare channel 0 and overflow).
|
||||
*
|
||||
* @details Checks for timeouts, and executes timeout handlers for expired timers.
|
||||
*/
|
||||
void us_ticker_handler(void)
|
||||
{
|
||||
if (NRF_RTC1->EVENTS_OVRFLW) {
|
||||
overflowCount++;
|
||||
NRF_RTC1->EVENTS_OVRFLW = 0;
|
||||
NRF_RTC1->EVTENCLR = RTC_EVTEN_OVRFLW_Msk;
|
||||
}
|
||||
if (NRF_RTC1->EVENTS_COMPARE[0]) {
|
||||
NRF_RTC1->EVENTS_COMPARE[0] = 0;
|
||||
NRF_RTC1->EVTENCLR = RTC_EVTEN_COMPARE0_Msk;
|
||||
if (us_ticker_callbackPending && ((int)(us_ticker_callbackTimestamp - rtc1_getCounter()) <= 0))
|
||||
invokeCallback();
|
||||
}
|
||||
}
|
||||
|
||||
void us_ticker_init(void)
|
||||
{
|
||||
if (us_ticker_inited) {
|
||||
return;
|
||||
}
|
||||
|
||||
rtc1_start();
|
||||
us_ticker_inited = true;
|
||||
}
|
||||
|
||||
uint32_t us_ticker_read()
|
||||
{
|
||||
if (!us_ticker_inited) {
|
||||
us_ticker_init();
|
||||
}
|
||||
|
||||
/* Return a pseudo microsecond counter value. This is only as precise as the
|
||||
* 32khz low-freq clock source, but could be adequate.*/
|
||||
return RTC_UNITS_TO_MICROSECONDS(rtc1_getCounter64());
|
||||
}
|
||||
|
||||
/**
|
||||
* Setup the us_ticker callback interrupt to go at the given timestamp.
|
||||
*
|
||||
* @Note: Only one callback is pending at any time.
|
||||
*
|
||||
* @Note: If a callback is pending, and this function is called again, the new
|
||||
* callback-time overrides the existing callback setting. It is the caller's
|
||||
* responsibility to ensure that this function is called to setup a callback for
|
||||
* the earliest timeout.
|
||||
*
|
||||
* @Note: If this function is used to setup an interrupt which is immediately
|
||||
* pending--such as for 'now' or a time in the past,--then the callback is
|
||||
* invoked a few ticks later.
|
||||
*/
|
||||
void us_ticker_set_interrupt(timestamp_t timestamp)
|
||||
{
|
||||
if (!us_ticker_inited) {
|
||||
us_ticker_init();
|
||||
}
|
||||
|
||||
/*
|
||||
* The argument to this function is a 32-bit microsecond timestamp for when
|
||||
* a callback should be invoked. On the nRF51, we use an RTC timer running
|
||||
* at 32kHz to implement a low-power us-ticker. This results in a problem
|
||||
* based on the fact that 1000000 is not a multiple of 32768.
|
||||
*
|
||||
* Going from a micro-second based timestamp to a 32kHz based RTC-time is a
|
||||
* linear mapping; but this mapping doesn't preserve wraparounds--i.e. when
|
||||
* the 32-bit micro-second timestamp wraps around unfortunately the
|
||||
* underlying RTC counter doesn't. The result is that timestamp expiry
|
||||
* checks on micro-second timestamps don't yield the same result when
|
||||
* applied on the corresponding RTC timestamp values.
|
||||
*
|
||||
* One solution is to translate the incoming 32-bit timestamp into a virtual
|
||||
* 64-bit timestamp based on the knowledge of system-uptime, and then use
|
||||
* this wraparound-free 64-bit value to do a linear mapping to RTC time.
|
||||
* System uptime on an nRF is maintained using the 24-bit RTC counter. We
|
||||
* track the overflow count to extend the 24-bit hardware counter by an
|
||||
* additional 32 bits. RTC_UNITS_TO_MICROSECONDS() converts this into
|
||||
* microsecond units (in 64-bits).
|
||||
*/
|
||||
const uint64_t currentTime64 = RTC_UNITS_TO_MICROSECONDS(rtc1_getCounter64());
|
||||
uint64_t timestamp64 = (currentTime64 & ~(uint64_t)0xFFFFFFFFULL) + timestamp;
|
||||
if (((uint32_t)currentTime64 > 0x80000000) && (timestamp < 0x80000000)) {
|
||||
timestamp64 += (uint64_t)0x100000000ULL;
|
||||
}
|
||||
uint32_t newCallbackTime = MICROSECONDS_TO_RTC_UNITS(timestamp64);
|
||||
|
||||
/* Check for repeat setup of an existing callback. This is actually not
|
||||
* important; the following code should work even without this check. */
|
||||
if (us_ticker_callbackPending && (newCallbackTime == us_ticker_callbackTimestamp)) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* Check for callbacks which are immediately (or will *very* shortly become) pending.
|
||||
* Even if they are immediately pending, they are scheduled to trigger a few
|
||||
* ticks later. This keeps things simple by invoking the callback from an
|
||||
* independent interrupt context. */
|
||||
if ((int)(newCallbackTime - rtc1_getCounter()) <= (int)FUZZY_RTC_TICKS) {
|
||||
newCallbackTime = rtc1_getCounter() + FUZZY_RTC_TICKS;
|
||||
}
|
||||
|
||||
NRF_RTC1->CC[0] = newCallbackTime & MAX_RTC_COUNTER_VAL;
|
||||
us_ticker_callbackTimestamp = newCallbackTime;
|
||||
if (!us_ticker_callbackPending) {
|
||||
us_ticker_callbackPending = true;
|
||||
rtc1_enableCompareInterrupt();
|
||||
}
|
||||
}
|
||||
|
||||
void us_ticker_disable_interrupt(void)
|
||||
{
|
||||
if (us_ticker_callbackPending) {
|
||||
rtc1_disableCompareInterrupt();
|
||||
us_ticker_callbackPending = false;
|
||||
}
|
||||
}
|
||||
|
||||
void us_ticker_clear_interrupt(void)
|
||||
{
|
||||
NRF_RTC1->EVENTS_OVRFLW = 0;
|
||||
NRF_RTC1->EVENTS_COMPARE[0] = 0;
|
||||
}
|
||||
|
||||
|
||||
#if defined (__CC_ARM) /* ARMCC Compiler */
|
||||
|
||||
__asm void RTC1_IRQHandler(void)
|
||||
{
|
||||
IMPORT OS_Tick_Handler
|
||||
IMPORT us_ticker_handler
|
||||
|
||||
/**
|
||||
* Chanel 1 of RTC1 is used by RTX as a systick.
|
||||
* If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
|
||||
* Otherwise, just execute us_ticker_handler.
|
||||
* This function has to be written in assembly and tagged as naked because OS_Tick_Handler
|
||||
* will never return.
|
||||
* A c function would put lr on the stack before calling OS_Tick_Handler and this value
|
||||
* would never been dequeued.
|
||||
*
|
||||
* \code
|
||||
* void RTC1_IRQHandler(void) {
|
||||
if(NRF_RTC1->EVENTS_COMPARE[1]) {
|
||||
// never return...
|
||||
OS_Tick_Handler();
|
||||
} else {
|
||||
us_ticker_handler();
|
||||
}
|
||||
}
|
||||
* \endcode
|
||||
*/
|
||||
ldr r0,=0x40011144
|
||||
ldr r1, [r0, #0]
|
||||
cmp r1, #0
|
||||
beq US_TICKER_HANDLER
|
||||
bl OS_Tick_Handler
|
||||
US_TICKER_HANDLER
|
||||
push {r3, lr}
|
||||
bl us_ticker_handler
|
||||
pop {r3, pc}
|
||||
nop /* padding */
|
||||
}
|
||||
|
||||
#elif defined (__GNUC__) /* GNU Compiler */
|
||||
|
||||
__attribute__((naked)) void RTC1_IRQHandler(void)
|
||||
{
|
||||
/**
|
||||
* Chanel 1 of RTC1 is used by RTX as a systick.
|
||||
* If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
|
||||
* Otherwise, just execute us_ticker_handler.
|
||||
* This function has to be written in assembly and tagged as naked because OS_Tick_Handler
|
||||
* will never return.
|
||||
* A c function would put lr on the stack before calling OS_Tick_Handler and this value
|
||||
* would never been dequeued.
|
||||
*
|
||||
* \code
|
||||
* void RTC1_IRQHandler(void) {
|
||||
if(NRF_RTC1->EVENTS_COMPARE[1]) {
|
||||
// never return...
|
||||
OS_Tick_Handler();
|
||||
} else {
|
||||
us_ticker_handler();
|
||||
}
|
||||
}
|
||||
* \endcode
|
||||
*/
|
||||
__asm__ (
|
||||
"ldr r0,=0x40011144\n"
|
||||
"ldr r1, [r0, #0]\n"
|
||||
"cmp r1, #0\n"
|
||||
"beq US_TICKER_HANDLER\n"
|
||||
"bl OS_Tick_Handler\n"
|
||||
"US_TICKER_HANDLER:\n"
|
||||
"push {r3, lr}\n"
|
||||
"bl us_ticker_handler\n"
|
||||
"pop {r3, pc}\n"
|
||||
"nop"
|
||||
);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#error Compiler not supported.
|
||||
#error Provide a definition of RTC1_IRQHandler.
|
||||
|
||||
/*
|
||||
* Chanel 1 of RTC1 is used by RTX as a systick.
|
||||
* If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
|
||||
* Otherwise, just execute us_ticker_handler.
|
||||
* This function has to be written in assembly and tagged as naked because OS_Tick_Handler
|
||||
* will never return.
|
||||
* A c function would put lr on the stack before calling OS_Tick_Handler and this value
|
||||
* will never been dequeued. After a certain time a stack overflow will happen.
|
||||
*
|
||||
* \code
|
||||
* void RTC1_IRQHandler(void) {
|
||||
if(NRF_RTC1->EVENTS_COMPARE[1]) {
|
||||
// never return...
|
||||
OS_Tick_Handler();
|
||||
} else {
|
||||
us_ticker_handler();
|
||||
}
|
||||
}
|
||||
* \endcode
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Return the next number of clock cycle needed for the next tick.
|
||||
* @note This function has been carrefuly optimized for a systick occuring every 1000us.
|
||||
*/
|
||||
static uint32_t get_next_tick_cc_delta() {
|
||||
uint32_t delta = 0;
|
||||
|
||||
if (os_clockrate != 1000) {
|
||||
// In RTX, by default SYSTICK is is used.
|
||||
// A tick event is generated every os_trv + 1 clock cycles of the system timer.
|
||||
delta = os_trv + 1;
|
||||
} else {
|
||||
// If the clockrate is set to 1000us then 1000 tick should happen every second.
|
||||
// Unfortunatelly, when clockrate is set to 1000, os_trv is equal to 31.
|
||||
// If (os_trv + 1) is used as the delta value between two ticks, 1000 ticks will be
|
||||
// generated in 32000 clock cycle instead of 32768 clock cycles.
|
||||
// As a result, if a user schedule an OS timer to start in 100s, the timer will start
|
||||
// instead after 97.656s
|
||||
// The code below fix this issue, a clock rate of 1000s will generate 1000 ticks in 32768
|
||||
// clock cycles.
|
||||
// The strategy is simple, for 1000 ticks:
|
||||
// * 768 ticks will occur 33 clock cycles after the previous tick
|
||||
// * 232 ticks will occur 32 clock cycles after the previous tick
|
||||
// By default every delta is equal to 33.
|
||||
// Every five ticks (20%, 200 delta in one second), the delta is equal to 32
|
||||
// The remaining (32) deltas equal to 32 are distributed using primes numbers.
|
||||
static uint32_t counter = 0;
|
||||
if ((counter % 5) == 0 || (counter % 31) == 0 || (counter % 139) == 0 || (counter == 503)) {
|
||||
delta = 32;
|
||||
} else {
|
||||
delta = 33;
|
||||
}
|
||||
++counter;
|
||||
if (counter == 1000) {
|
||||
counter = 0;
|
||||
}
|
||||
}
|
||||
return delta;
|
||||
}
|
||||
|
||||
static inline void clear_tick_interrupt() {
|
||||
NRF_RTC1->EVENTS_COMPARE[1] = 0;
|
||||
NRF_RTC1->EVTENCLR = (1 << 17);
|
||||
}
|
||||
|
||||
/**
|
||||
* Indicate if a value is included in a range which can be wrapped.
|
||||
* @param begin start of the range
|
||||
* @param end end of the range
|
||||
* @param val value to check
|
||||
* @return true if the value is included in the range and false otherwise.
|
||||
*/
|
||||
static inline bool is_in_wrapped_range(uint32_t begin, uint32_t end, uint32_t val) {
|
||||
// regular case, begin < end
|
||||
// return true if begin <= val < end
|
||||
if (begin < end) {
|
||||
if (begin <= val && val < end) {
|
||||
return true;
|
||||
} else {
|
||||
return false;
|
||||
}
|
||||
} else {
|
||||
// In this case end < begin because it has wrap around the limits
|
||||
// return false if end < val < begin
|
||||
if (end < val && val < begin) {
|
||||
return false;
|
||||
} else {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Register the next tick.
|
||||
*/
|
||||
static void register_next_tick() {
|
||||
previous_tick_cc_value = NRF_RTC1->CC[1];
|
||||
uint32_t delta = get_next_tick_cc_delta();
|
||||
uint32_t new_compare_value = (previous_tick_cc_value + delta) & MAX_RTC_COUNTER_VAL;
|
||||
|
||||
// Disable irq directly for few cycles,
|
||||
// Validation of the new CC value against the COUNTER,
|
||||
// Setting the new CC value and enabling CC IRQ should be an atomic operation
|
||||
// Otherwise, there is a possibility to set an invalid CC value because
|
||||
// the RTC1 keeps running.
|
||||
// This code is very short 20-38 cycles in the worst case, it shouldn't
|
||||
// disturb softdevice.
|
||||
__disable_irq();
|
||||
uint32_t current_counter = NRF_RTC1->COUNTER;
|
||||
|
||||
// If an overflow occur, set the next tick in COUNTER + delta clock cycles
|
||||
if (is_in_wrapped_range(previous_tick_cc_value, new_compare_value, current_counter) == false) {
|
||||
new_compare_value = current_counter + delta;
|
||||
}
|
||||
NRF_RTC1->CC[1] = new_compare_value;
|
||||
|
||||
// set the interrupt of CC channel 1 and reenable IRQs
|
||||
NRF_RTC1->INTENSET = RTC_INTENSET_COMPARE1_Msk;
|
||||
__enable_irq();
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize alternative hardware timer as RTX kernel timer
|
||||
* This function is directly called by RTX.
|
||||
* @note this function shouldn't be called directly.
|
||||
* @return IRQ number of the alternative hardware timer
|
||||
*/
|
||||
int os_tick_init (void)
|
||||
{
|
||||
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos);
|
||||
NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
|
||||
NRF_CLOCK->TASKS_LFCLKSTART = 1;
|
||||
|
||||
while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {
|
||||
// wait for the low frequency clock start
|
||||
}
|
||||
|
||||
NRF_RTC1->PRESCALER = 0; /* for no pre-scaling. */
|
||||
|
||||
NVIC_SetPriority(RTC1_IRQn, RTC1_IRQ_PRI);
|
||||
NVIC_ClearPendingIRQ(RTC1_IRQn);
|
||||
NVIC_EnableIRQ(RTC1_IRQn);
|
||||
|
||||
NRF_RTC1->TASKS_START = 1;
|
||||
nrf_delay_us(MAX_RTC_TASKS_DELAY);
|
||||
|
||||
NRF_RTC1->CC[1] = 0;
|
||||
clear_tick_interrupt();
|
||||
register_next_tick();
|
||||
|
||||
os_tick_started = true;
|
||||
|
||||
return RTC1_IRQn;
|
||||
}
|
||||
|
||||
/**
|
||||
* Acknowledge the tick interrupt.
|
||||
* This function is called by the function OS_Tick_Handler of RTX.
|
||||
* @note this function shouldn't be called directly.
|
||||
*/
|
||||
void os_tick_irqack(void)
|
||||
{
|
||||
clear_tick_interrupt();
|
||||
register_next_tick();
|
||||
}
|
||||
|
||||
/**
|
||||
* Returns the overflow flag of the alternative hardware timer.
|
||||
* @note This function is exposed by RTX kernel.
|
||||
* @return 1 if the timer has overflowed and 0 otherwise.
|
||||
*/
|
||||
uint32_t os_tick_ovf(void) {
|
||||
uint32_t current_counter = NRF_RTC1->COUNTER;
|
||||
uint32_t next_tick_cc_value = NRF_RTC1->CC[1];
|
||||
|
||||
return is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter) ? 0 : 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Return the value of the alternative hardware timer.
|
||||
* @note The documentation is not very clear about what is expected as a result,
|
||||
* is it an ascending counter, a descending one ?
|
||||
* None of this is specified.
|
||||
* The default systick is a descending counter and this function return values in
|
||||
* descending order, even if the internal counter used is an ascending one.
|
||||
* @return the value of the alternative hardware timer.
|
||||
*/
|
||||
uint32_t os_tick_val(void) {
|
||||
uint32_t current_counter = NRF_RTC1->COUNTER;
|
||||
uint32_t next_tick_cc_value = NRF_RTC1->CC[1];
|
||||
|
||||
// do not use os_tick_ovf because its counter value can be different
|
||||
if(is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter)) {
|
||||
if (next_tick_cc_value > previous_tick_cc_value) {
|
||||
return next_tick_cc_value - current_counter;
|
||||
} else if(current_counter <= next_tick_cc_value) {
|
||||
return next_tick_cc_value - current_counter;
|
||||
} else {
|
||||
return next_tick_cc_value + (MAX_RTC_COUNTER_VAL - current_counter);
|
||||
}
|
||||
} else {
|
||||
// use (os_trv + 1) has the base step, can be totally inacurate ...
|
||||
uint32_t clock_cycles_by_tick = os_trv + 1;
|
||||
|
||||
// if current counter has wrap arround, add the limit to it.
|
||||
if (current_counter < next_tick_cc_value) {
|
||||
current_counter = current_counter + MAX_RTC_COUNTER_VAL;
|
||||
}
|
||||
|
||||
return clock_cycles_by_tick - ((current_counter - next_tick_cc_value) % clock_cycles_by_tick);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* Copyright (c) 2013 Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
|
||||
* integrated circuit in a product or a software update for such product, must reproduce
|
||||
* the above copyright notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary or object form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef MBED_PERIPHERALNAMES_H
|
||||
#define MBED_PERIPHERALNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define STDIO_UART_TX TX_PIN_NUMBER
|
||||
#define STDIO_UART_RX RX_PIN_NUMBER
|
||||
#define STDIO_UART UART_0
|
||||
|
||||
typedef enum {
|
||||
UART_0 = (int)NRF_UART0_BASE
|
||||
} UARTName;
|
||||
|
||||
|
||||
typedef enum {
|
||||
SPI_0 = (int)NRF_SPI0_BASE,
|
||||
SPI_1 = (int)NRF_SPI1_BASE,
|
||||
SPIS = (int)NRF_SPIS1_BASE
|
||||
} SPIName;
|
||||
|
||||
typedef enum {
|
||||
PWM_1 = 0,
|
||||
PWM_2
|
||||
} PWMName;
|
||||
|
||||
typedef enum {
|
||||
I2C_0 = (int)NRF_TWI0_BASE,
|
||||
I2C_1 = (int)NRF_TWI1_BASE
|
||||
} I2CName;
|
||||
|
||||
typedef enum {
|
||||
ADC0_0 = (int)NRF_ADC_BASE
|
||||
} ADCName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright (c) 2013 Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
|
||||
* integrated circuit in a product or a software update for such product, must reproduce
|
||||
* the above copyright notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary or object form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef MBED_PORTNAMES_H
|
||||
#define MBED_PORTNAMES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
Port0 = 0 //GPIO pins 0-31
|
||||
} PortName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -1,18 +1,41 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2013 Nordic Semiconductor
|
||||
/*
|
||||
* Copyright (c) 2013 Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
|
||||
* integrated circuit in a product or a software update for such product, must reproduce
|
||||
* the above copyright notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
* 4. This software, with or without modification, must only be used with a
|
||||
* Nordic Semiconductor ASA integrated circuit.
|
||||
*
|
||||
* 5. Any software provided in binary or object form under this license must not be reverse
|
||||
* engineered, decompiled, modified and/or disassembled.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "mbed_assert.h"
|
||||
#include "analogin_api.h"
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
#include "nrf_drv_adc.h"
|
||||
|
||||
#ifdef DEVICE_ANALOGIN
|
||||
|
||||
|
||||
#define ADC_10BIT_RANGE 0x3FF
|
||||
#define ADC_RANGE ADC_10BIT_RANGE
|
||||
|
||||
static const PinMap PinMap_ADC[] = {
|
||||
{p1, ADC0_0, 4},
|
||||
{p2, ADC0_0, 8},
|
||||
{p3, ADC0_0, 16},
|
||||
{p4, ADC0_0, 32},
|
||||
{p5, ADC0_0, 64},
|
||||
{p6, ADC0_0, 128},
|
||||
#ifndef TARGET_NRF51_DONGLE
|
||||
{p26, ADC0_0, 1},
|
||||
{p27, ADC0_0, 2},
|
||||
#endif
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
|
||||
void analogin_init(analogin_t *obj, PinName pin)
|
||||
{
|
||||
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
|
||||
MBED_ASSERT(obj->adc != (ADCName)NC);
|
||||
|
||||
uint32_t pinFunc = pinmap_function(pin, PinMap_ADC);
|
||||
MBED_ASSERT(pinFunc != (uint32_t)NC);
|
||||
|
||||
obj->adc_pin = pinFunc;
|
||||
|
||||
ret_code_t ret_code;
|
||||
// p_config, event_handler
|
||||
ret_code = nrf_drv_adc_init(NULL , NULL); // select blocking mode
|
||||
MBED_ASSERT((ret_code == NRF_SUCCESS) || (ret_code == NRF_ERROR_INVALID_STATE)); //NRF_ERROR_INVALID_STATE expected for multiple channels used.
|
||||
}
|
||||
|
||||
uint16_t analogin_read_u16(analogin_t *obj)
|
||||
{
|
||||
nrf_adc_value_t adc_value;
|
||||
|
||||
nrf_drv_adc_channel_t adc_channel;
|
||||
|
||||
// initialization by assigment because IAR dosen't support variable initializer in declaration statement.
|
||||
adc_channel.config.config.resolution = NRF_ADC_CONFIG_RES_10BIT;
|
||||
adc_channel.config.config.input = NRF_ADC_CONFIG_SCALING_INPUT_FULL_SCALE;
|
||||
adc_channel.config.config.reference = NRF_ADC_CONFIG_REF_VBG;
|
||||
adc_channel.config.config.ain = (obj->adc_pin);
|
||||
adc_channel.p_next = NULL;
|
||||
|
||||
|
||||
ret_code_t ret_code;
|
||||
|
||||
ret_code = nrf_drv_adc_sample_convert( &adc_channel, &adc_value);
|
||||
MBED_ASSERT(ret_code == NRF_SUCCESS);
|
||||
|
||||
return adc_value;
|
||||
}
|
||||
|
||||
float analogin_read(analogin_t *obj)
|
||||
{
|
||||
uint16_t value = analogin_read_u16(obj);
|
||||
|
||||
return (float)value * (1.0f / (float)ADC_RANGE);
|
||||
}
|
||||
|
||||
#endif // DEVICE_ANALOGIN
|
||||
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Reference in New Issue