diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
index 33ad3de755..473bd8a7e5 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
@@ -24,6 +24,14 @@
 
 #include "cycfg_clocks.h"
 
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_UART_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_UART_CLK_DIV_HW,
+		.channel_num = CYBSP_UART_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj = 
 	{
@@ -52,6 +60,13 @@
 
 void init_cycfg_clocks(void)
 {
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 719U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_UART_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
 	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 1U, 77U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
index 2ba0f1937b..9b8200af2e 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
@@ -35,6 +35,9 @@
 extern "C" {
 #endif
 
+#define CYBSP_UART_CLK_DIV_ENABLED 1U
+#define CYBSP_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
+#define CYBSP_UART_CLK_DIV_NUM 0U
 #define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
 #define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
 #define CYBSP_BT_UART_CLK_DIV_NUM 1U
@@ -45,6 +48,9 @@ extern "C" {
 #define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
 
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_UART_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
 #endif //defined (CY_USING_HAL)
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
index c26f522b06..1300f6a404 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
@@ -24,6 +24,20 @@
 
 #include "cycfg_peripherals.h"
 
+#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
+                 CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
+                 CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
+                 CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \
+                 CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U))
+
 cy_stc_csd_context_t cy_csd_0_context = 
 {
 	.lockKey = CY_CSD_NONE_KEY,
@@ -136,6 +150,31 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
 		.channel_num = 0U,
 	};
 #endif //defined (CY_USING_HAL)
+const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config = 
+{
+	.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
+	.epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
+	.epBuffer = NULL,
+	.epBufferSize = 0U,
+	.dmaConfig[0] = NULL,
+	.dmaConfig[1] = NULL,
+	.dmaConfig[2] = NULL,
+	.dmaConfig[3] = NULL,
+	.dmaConfig[4] = NULL,
+	.dmaConfig[5] = NULL,
+	.dmaConfig[6] = NULL,
+	.dmaConfig[7] = NULL,
+	.enableLpm = false,
+	.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
+};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USBUART_obj = 
+	{
+		.type = CYHAL_RSC_USB,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_peripherals(void)
@@ -163,4 +202,9 @@ void init_cycfg_peripherals(void)
 #if defined (CY_USING_HAL)
 		cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
 #endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USBUART_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
index deff2270e5..08b0a43fed 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
@@ -37,6 +37,7 @@
 #include "cycfg_qspi_memslot.h"
 #include "cy_mcwdt.h"
 #include "cy_rtc.h"
+#include "cy_usbfs_dev_drv.h"
 
 #if defined(__cplusplus)
 extern "C" {
@@ -113,6 +114,14 @@ extern "C" {
 #define CYBSP_RTC_100_YEAR_OFFSET (8U)
 #define CYBSP_RTC_10_YEAR_OFFSET (4U)
 #define CYBSP_RTC_YEAR_OFFSET (0U)
+#define CYBSP_USBUART_ENABLED 1U
+#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U
+#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
+#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
+#define CYBSP_USBUART_HW USBFS0
+#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
+#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn
+#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn
 
 extern cy_stc_csd_context_t cy_csd_0_context;
 extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
@@ -135,6 +144,10 @@ extern const cy_stc_rtc_config_t CYBSP_RTC_config;
 #if defined (CY_USING_HAL)
 	extern const cyhal_resource_inst_t CYBSP_RTC_obj;
 #endif //defined (CY_USING_HAL)
+extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USBUART_obj;
+#endif //defined (CY_USING_HAL)
 
 void init_cycfg_peripherals(void);
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
index 14f111d2a7..2d6e9e041a 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
@@ -216,6 +216,54 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config =
 		.channel_num = CYBSP_QSPI_SPI_CLOCK_PIN,
 	};
 #endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config = 
+{
+	.outVal = 1,
+	.driveMode = CY_GPIO_DM_ANALOG,
+	.hsiom = CYBSP_USB_DP_HSIOM,
+	.intEdge = CY_GPIO_INTR_DISABLE,
+	.intMask = 0UL,
+	.vtrip = CY_GPIO_VTRIP_CMOS,
+	.slewRate = CY_GPIO_SLEW_FAST,
+	.driveSel = CY_GPIO_DRIVE_1_2,
+	.vregEn = 0UL,
+	.ibufMode = 0UL,
+	.vtripSel = 0UL,
+	.vrefSel = 0UL,
+	.vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USB_DP_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_USB_DP_PORT_NUM,
+		.channel_num = CYBSP_USB_DP_PIN,
+	};
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config = 
+{
+	.outVal = 1,
+	.driveMode = CY_GPIO_DM_ANALOG,
+	.hsiom = CYBSP_USB_DM_HSIOM,
+	.intEdge = CY_GPIO_INTR_DISABLE,
+	.intMask = 0UL,
+	.vtrip = CY_GPIO_VTRIP_CMOS,
+	.slewRate = CY_GPIO_SLEW_FAST,
+	.driveSel = CY_GPIO_DRIVE_1_2,
+	.vregEn = 0UL,
+	.ibufMode = 0UL,
+	.vtripSel = 0UL,
+	.vrefSel = 0UL,
+	.vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USB_DM_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_USB_DM_PORT_NUM,
+		.channel_num = CYBSP_USB_DM_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = 
 {
 	.outVal = 1,
@@ -408,6 +456,30 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
 		.channel_num = CYBSP_BT_HOST_WAKE_PIN,
 	};
 #endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config = 
+{
+	.outVal = 1,
+	.driveMode = CY_GPIO_DM_ANALOG,
+	.hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM,
+	.intEdge = CY_GPIO_INTR_RISING,
+	.intMask = 1UL,
+	.vtrip = CY_GPIO_VTRIP_CMOS,
+	.slewRate = CY_GPIO_SLEW_FAST,
+	.driveSel = CY_GPIO_DRIVE_1_2,
+	.vregEn = 0UL,
+	.ibufMode = 0UL,
+	.vtripSel = 0UL,
+	.vrefSel = 0UL,
+	.vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WIFI_HOST_WAKE_PORT_NUM,
+		.channel_num = CYBSP_WIFI_HOST_WAKE_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config = 
 {
 	.outVal = 1,
@@ -812,6 +884,16 @@ void init_cycfg_pins(void)
 		cyhal_hwmgr_reserve(&CYBSP_QSPI_SPI_CLOCK_obj);
 #endif //defined (CY_USING_HAL)
 
+	Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj);
+#endif //defined (CY_USING_HAL)
+
 #if defined (CY_USING_HAL)
 		cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj);
 #endif //defined (CY_USING_HAL)
@@ -851,6 +933,11 @@ void init_cycfg_pins(void)
 		cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
 #endif //defined (CY_USING_HAL)
 
+	Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WIFI_HOST_WAKE_obj);
+#endif //defined (CY_USING_HAL)
+
 	Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
 #if defined (CY_USING_HAL)
 		cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
index 4975b85b7e..608ed5c6ff 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
@@ -228,6 +228,54 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_QSPI_SPI_CLOCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
 #endif //defined (CY_USING_HAL)
+#define CYBSP_USB_DP_ENABLED 1U
+#define CYBSP_USB_DP_PORT GPIO_PRT14
+#define CYBSP_USB_DP_PORT_NUM 14U
+#define CYBSP_USB_DP_PIN 0U
+#define CYBSP_USB_DP_NUM 0U
+#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_USB_DP_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_14_pin_0_HSIOM
+	#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM
+#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DP_HAL_PORT_PIN P14_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_USB_DM_ENABLED 1U
+#define CYBSP_USB_DM_PORT GPIO_PRT14
+#define CYBSP_USB_DM_PORT_NUM 14U
+#define CYBSP_USB_DM_PIN 1U
+#define CYBSP_USB_DM_NUM 1U
+#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_USB_DM_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_14_pin_1_HSIOM
+	#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM
+#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DM_HAL_PORT_PIN P14_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
 #define CYBSP_CSD_RX_ENABLED 1U
 #define CYBSP_CSD_RX_PORT GPIO_PRT1
 #define CYBSP_CSD_RX_PORT_NUM 1U
@@ -420,6 +468,30 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
 #endif //defined (CY_USING_HAL)
+#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U
+#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT4
+#define CYBSP_WIFI_HOST_WAKE_PORT_NUM 4U
+#define CYBSP_WIFI_HOST_WAKE_PIN 1U
+#define CYBSP_WIFI_HOST_WAKE_NUM 1U
+#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_4_pin_1_HSIOM
+	#define ioss_0_port_4_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_4_pin_1_HSIOM
+#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WIFI_HOST_WAKE_HAL_PORT_PIN P4_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WIFI_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_RISE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WIFI_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WIFI_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
 #define CYBSP_EZI2C_SCL_ENABLED 1U
 #define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
 #define CYBSP_EZI2C_SCL_PORT_NUM 6U
@@ -813,6 +885,14 @@ extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config;
 #if defined (CY_USING_HAL)
 	extern const cyhal_resource_inst_t CYBSP_QSPI_SPI_CLOCK_obj;
 #endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USB_DP_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USB_DM_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config;
 #if defined (CY_USING_HAL)
 	extern const cyhal_resource_inst_t CYBSP_CSD_RX_obj;
@@ -845,6 +925,10 @@ extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
 #if defined (CY_USING_HAL)
 	extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj;
 #endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
 #if defined (CY_USING_HAL)
 	extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
index c4e5bcf916..14d433859d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
@@ -24,7 +24,7 @@
 
 #include "cycfg_qspi_memslot.h"
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0xECU,
@@ -42,7 +42,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x06U,
@@ -60,7 +60,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x04U,
@@ -78,7 +78,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0xDCU,
@@ -96,7 +96,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x60U,
@@ -114,7 +114,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x34U,
@@ -132,7 +132,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x35U,
@@ -150,7 +150,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x05U,
@@ -168,7 +168,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x01U,
@@ -186,34 +186,34 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
+const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 =
 {
     /* Specifies the number of address bytes used by the memory slave device. */
     .numOfAddrBytes = 0x04U,
     /* The size of the memory. */
     .memSize = 0x04000000U,
     /* Specifies the Read command. */
-    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
+    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd,
     /* Specifies the Write Enable command. */
-    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
+    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd,
     /* Specifies the Write Disable command. */
-    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
+    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd,
     /* Specifies the Erase command. */
-    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
+    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd,
     /* Specifies the sector size of each erase. */
     .eraseSize = 0x00040000U,
     /* Specifies the Chip Erase command. */
-    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
+    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd,
     /* Specifies the Program command. */
-    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
+    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd,
     /* Specifies the page size for programming. */
     .programSize = 0x00000200U,
     /* Specifies the command to read the QE-containing status register. */
-    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
+    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd,
     /* Specifies the command to read the WIP-containing status register. */
-    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
+    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd,
     /* Specifies the command to write into the QE-containing status register. */
-    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
+    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
     /* The mask for the status register. */
     .stsRegBusyMask = 0x01U,
     /* The mask for the status register. */
@@ -226,7 +226,7 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
     .programTime = 1300U
 };
 
-const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
+const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 =
 {
     /* Determines the slot number where the memory device is placed. */
     .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
@@ -244,11 +244,11 @@ const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
     Valid when the memory mapped mode is enabled. */
     .dualQuadSlots = 0,
     /* The configuration of the device. */
-    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
+    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0
 };
 
 const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
-   &S25FL512SX4byteaddr_SlaveSlot_0
+   &S25FL512S_4byteaddr_SlaveSlot_0
 };
 
 const cy_stc_smif_block_config_t smifBlockConfig =
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
index 32f9b49b2e..0ee62b1d55 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
@@ -28,19 +28,19 @@
 
 #define CY_SMIF_DEVICE_NUM 1
 
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
 
-extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
+extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0;
 
-extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
+extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0;
 extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
 
 extern const cy_stc_smif_block_config_t smifBlockConfig;
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
index a8562c420e..2a31711071 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
@@ -73,7 +73,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
 	.refDiv = 20U,
 	.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
 	.enableOutputDiv = true,
-	.lockTolerance = 10U,
+	.lockTolerance = 4U,
 	.igain = 9U,
 	.pgain = 5U,
 	.settlingCount = 8U,
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
index a79663451d..8453a4470f 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
@@ -1,34 +1,6 @@
-[Device="CY8C624ABZI-D44"]
+[Device=CY8C624ABZI-D44]
  
 [Blocks]
-# User IO
-# CYBSP_USER_LED1
-ioss[0].port[11].pin[1]
-# CYBSP_USER_LED2
-ioss[0].port[1].pin[5]
-# CYBSP_USER_LED3
-ioss[0].port[1].pin[1]
-# CYBSP_USER_LED4
-ioss[0].port[0].pin[5]
-# CYBSP_USER_LED5
-ioss[0].port[7].pin[3]
-# CYBSP_USER_BTN1
-ioss[0].port[0].pin[4]
-# CYBSP_USER_BTN2
-ioss[0].port[1].pin[4] 
-
-# Debug
-# CYBSP_DEBUG_UART
-scb[5]
-# CYBSP_DEBUG_UART_RX
-ioss[0].port[5].pin[0]
-# CYBSP_DEBUG_UART_TX
-ioss[0].port[5].pin[1]
-# CYBSP_DEBUG_UART_RTS
-ioss[0].port[5].pin[2]
-# CYBSP_DEBUG_UART_CTS 
-ioss[0].port[5].pin[3]
-
 # WIFI
 # CYBSP_WIFI_SDIO
 sdhc[0]
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus
index 602d095a87..b2964f1eaf 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Design version="11" device_library_hint_path="../../psoc6pdl/devicesupport.xml" xmlns="http://cypress.com/xsd/cydesignfile_v2">
+<Design version="11" xmlns="http://cypress.com/xsd/cydesignfile_v2">
     <ToolInfo version="1.0.0"/>
     <Devices>
         <Device mpn="CY8C624ABZI-D44">
@@ -124,6 +124,26 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
+                <Block location="ioss[0].port[14].pin[0]" alias="CYBSP_USB_DP" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[14].pin[1]" alias="CYBSP_USB_DM" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
                 <Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_RX" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                     <Param id="initialState" value="1"/>
@@ -204,6 +224,16 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
+                <Block location="ioss[0].port[4].pin[1]" alias="CYBSP_WIFI_HOST_WAKE" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_RISING"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
                 <Block location="ioss[0].port[6].pin[0]" alias="CYBSP_EZI2C_SCL" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
                     <Param id="initialState" value="1"/>
@@ -354,6 +384,11 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
+                <Block location="peri[0].div_16[0]" alias="CYBSP_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
+                    <Param id="intDivider" value="720"/>
+                    <Param id="fracDivider" value="0"/>
+                    <Param id="startOnReset" value="true"/>
+                </Block>
                 <Block location="peri[0].div_16[1]" alias="CYBSP_BT_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
                     <Param id="intDivider" value="78"/>
                     <Param id="fracDivider" value="0"/>
@@ -467,7 +502,7 @@
                     <Param id="hibernate" value="true"/>
                 </Block>
                 <Block location="srss[0].clock[0].imo[0]" alias="" template="mxs40imo" version="1.0">
-                    <Param id="trim" value="1"/>
+                    <Param id="trim" value="0.25"/>
                 </Block>
                 <Block location="srss[0].clock[0].lfclk[0]" alias="" template="mxs40lfclk" version="1.1">
                     <Param id="sourceClock" value="ilo"/>
@@ -525,7 +560,6 @@
                     <Param id="inFlash" value="true"/>
                 </Block>
                 <Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
-                    <Param id="pwrEstimator" value="0"/>
                     <Param id="pwrMode" value="LDO_1_1"/>
                     <Param id="actPwrMode" value="LP"/>
                     <Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
@@ -565,6 +599,27 @@
                     <Param id="dstStopHour" value="0"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
+                <Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.1">
+                    <Param id="epMask" value="0"/>
+                    <Param id="mngMode" value="CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU"/>
+                    <Param id="bufSize" value="512"/>
+                    <Param id="epAccess" value="CY_USBFS_DEV_DRV_USE_8_BITS_DR"/>
+                    <Param id="enableLpm" value="false"/>
+                    <Param id="lpmIntr" value="0x0U"/>
+                    <Param id="ArbIntr" value="0x0U"/>
+                    <Param id="ep0CntrIntr" value="0x2U"/>
+                    <Param id="busResetIntr" value="0x2U"/>
+                    <Param id="sofIntr" value="0x1U"/>
+                    <Param id="ep0Intr" value="0x1U"/>
+                    <Param id="ep1Intr" value="0x1U"/>
+                    <Param id="ep2Intr" value="0x1U"/>
+                    <Param id="ep3Intr" value="0x1U"/>
+                    <Param id="ep4Intr" value="0x1U"/>
+                    <Param id="ep5Intr" value="0x1U"/>
+                    <Param id="ep6Intr" value="0x1U"/>
+                    <Param id="ep7Intr" value="0x1U"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
             </BlockConfig>
             <Netlist>
                 <Net>
@@ -639,6 +694,18 @@
                     <Port name="ioss[0].port[11].pin[7].digital_inout[0]"/>
                     <Port name="smif[0].spi_clk[0]"/>
                 </Net>
+                <Net>
+                    <Port name="ioss[0].port[14].pin[0].aux[0]"/>
+                    <Port name="usb[0].usb_dp_pad[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[14].pin[1].aux[0]"/>
+                    <Port name="usb[0].usb_dm_pad[0]"/>
+                </Net>
+                <Net>
+                    <Port name="peri[0].div_16[0].clk[0]"/>
+                    <Port name="usb[0].clock_dev_brs[0]"/>
+                </Net>
                 <Net>
                     <Port name="peri[0].div_16[1].clk[0]"/>
                     <Port name="scb[2].clock[0]"/>
@@ -655,6 +722,10 @@
                     <Port name="smif[0].clk_if[0]"/>
                     <Port name="srss[0].clock[0].hfclk[2].root_clk[0]"/>
                 </Net>
+                <Net>
+                    <Port name="srss[0].clock[0].hfclk[3].root_clk[0]"/>
+                    <Port name="usb[0].clk_usb_dev[0]"/>
+                </Net>
                 <Mux name="sense" location="csd[0].csd[0]">
                     <Arm>
                         <Port name="ioss[0].port[7].pin[7].analog[0]"/>
@@ -700,9 +771,6 @@
             <Netlist/>
         </Device>
     </Devices>
-    <Libraries>
-        <Library name="bt_sdk" version="1.1"/>
-        <Library name="psoc6sw" version="1.2"/>
-    </Libraries>
+    <Libraries/>
     <ConfiguratorData/>
 </Design>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
index a80bc9b255..28210ff466 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
@@ -1,24 +1,4 @@
-[Device="CY8C6347BZI-BLD53"]
+[Device=CY8C6347BZI-BLD53]
  
 [Blocks]
-# User IO
-# CYBSP_USER_LED1
-ioss[0].port[1].pin[5]
-# CYBSP_USER_LED2
-ioss[0].port[13].pin[7]
-# CYBSP_USER_LED3
-ioss[0].port[0].pin[3]
-# CYBSP_USER_LED4
-ioss[0].port[1].pin[1]
-# CYBSP_USER_LED5
-ioss[0].port[11].pin[1]
-# CYBSP_USER_BTN1
-ioss[0].port[0].pin[4]
-
-# Debug
-# CYBSP_DEBUG_UART
-scb[5]
-# CYBSP_DEBUG_UART_RX
-ioss[0].port[5].pin[0]
-# CYBSP_DEBUG_UART_TX
-ioss[0].port[5].pin[1]
+# Nothing needs to be reserved for this device
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus
index 29698a4c27..5b9ac8b1ab 100755
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus
@@ -560,8 +560,6 @@
             </Netlist>
         </Device>
     </Devices>
-    <Libraries>
-        <Library name="psoc6sw" version="1.2"/>
-    </Libraries>
+    <Libraries/>
     <ConfiguratorData/>
 </Design>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
index cda6d4025b..cb430a4164 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
@@ -28,7 +28,6 @@ void init_cycfg_all(void)
 {
 	init_cycfg_system();
 	init_cycfg_clocks();
-	init_cycfg_dmas();
 	init_cycfg_routing();
 	init_cycfg_peripherals();
 	init_cycfg_pins();
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
index 3585cf91ba..9abc7f0f4a 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
@@ -32,7 +32,6 @@ extern "C" {
 #include "cycfg_notices.h"
 #include "cycfg_system.h"
 #include "cycfg_clocks.h"
-#include "cycfg_dmas.h"
 #include "cycfg_routing.h"
 #include "cycfg_peripherals.h"
 #include "cycfg_pins.h"
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
index 151484a1da..2a4822d1d4 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
@@ -32,14 +32,6 @@
 		.channel_num = CYBSP_USB_CLK_DIV_NUM,
 	};
 #endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj = 
-	{
-		.type = CYHAL_RSC_CLOCK,
-		.block_num = CYBSP_SDIO_DIV_HW,
-		.channel_num = CYBSP_SDIO_DIV_NUM,
-	};
-#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj = 
 	{
@@ -57,11 +49,11 @@
 	};
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t peri_0_div_8_4_obj = 
+	const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj = 
 	{
 		.type = CYHAL_RSC_CLOCK,
-		.block_num = peri_0_div_8_4_HW,
-		.channel_num = peri_0_div_8_4_NUM,
+		.block_num = CYBSP_BT_UART_CLK_DIV_HW,
+		.channel_num = CYBSP_BT_UART_CLK_DIV_NUM,
 	};
 #endif //defined (CY_USING_HAL)
 
@@ -75,13 +67,6 @@ void init_cycfg_clocks(void)
 		cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj);
 #endif //defined (CY_USING_HAL)
 
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
-#if defined (CY_USING_HAL)
-		cyhal_hwmgr_reserve(&CYBSP_SDIO_DIV_obj);
-#endif //defined (CY_USING_HAL)
-
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
 	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
@@ -100,6 +85,6 @@ void init_cycfg_clocks(void)
 	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 108U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
 #if defined (CY_USING_HAL)
-		cyhal_hwmgr_reserve(&peri_0_div_8_4_obj);
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj);
 #endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
index 516b0c3730..ab4a3aeaa8 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
@@ -38,25 +38,19 @@ extern "C" {
 #define CYBSP_USB_CLK_DIV_ENABLED 1U
 #define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
 #define CYBSP_USB_CLK_DIV_NUM 0U
-#define CYBSP_SDIO_DIV_ENABLED 1U
-#define CYBSP_SDIO_DIV_HW CY_SYSCLK_DIV_8_BIT
-#define CYBSP_SDIO_DIV_NUM 0U
 #define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
 #define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
 #define CYBSP_CSD_CLK_DIV_ENABLED 1U
 #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_CSD_CLK_DIV_NUM 3U
-#define peri_0_div_8_4_ENABLED 1U
-#define peri_0_div_8_4_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_4_NUM 4U
+#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
+#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_BT_UART_CLK_DIV_NUM 4U
 
 #if defined (CY_USING_HAL)
 	extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj;
 #endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj;
-#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
 #endif //defined (CY_USING_HAL)
@@ -64,7 +58,7 @@ extern "C" {
 	extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t peri_0_div_8_4_obj;
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
 #endif //defined (CY_USING_HAL)
 
 void init_cycfg_clocks(void);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c
deleted file mode 100644
index 8d86919551..0000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_dmas.c
-*
-* Description:
-* DMA configuration
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_dmas.h"
-
-const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config = 
-{
-	.retrigger = CY_DMA_RETRIG_IM,
-	.interruptType = CY_DMA_1ELEMENT,
-	.triggerOutType = CY_DMA_1ELEMENT,
-	.channelState = CY_DMA_CHANNEL_DISABLED,
-	.triggerInType = CY_DMA_1ELEMENT,
-	.dataSize = CY_DMA_BYTE,
-	.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
-	.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
-	.descriptorType = CY_DMA_1D_TRANSFER,
-	.srcAddress = NULL,
-	.dstAddress = NULL,
-	.srcXincrement = 0,
-	.dstXincrement = 1,
-	.xCount = 6,
-	.srcYincrement = 0,
-	.dstYincrement = 0,
-	.yCount = 1,
-	.nextDescriptor = NULL,
-};
-cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0 = 
-{
-	.ctl = 0UL,
-	.src = 0UL,
-	.dst = 0UL,
-	.xCtl = 0UL,
-	.yCtl = 0UL,
-	.nextPtr = 0UL,
-};
-const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig = 
-{
-	.descriptor = &cpuss_0_dw0_0_chan_0_Descriptor_0,
-	.preemptable = true,
-	.priority = 1,
-	.enable = false,
-	.bufferable = false,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj = 
-	{
-		.type = CYHAL_RSC_DMA,
-		.block_num = 0U,
-		.channel_num = cpuss_0_dw0_0_chan_0_CHANNEL,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config = 
-{
-	.retrigger = CY_DMA_RETRIG_16CYC,
-	.interruptType = CY_DMA_1ELEMENT,
-	.triggerOutType = CY_DMA_1ELEMENT,
-	.channelState = CY_DMA_CHANNEL_DISABLED,
-	.triggerInType = CY_DMA_1ELEMENT,
-	.dataSize = CY_DMA_BYTE,
-	.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
-	.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
-	.descriptorType = CY_DMA_1D_TRANSFER,
-	.srcAddress = NULL,
-	.dstAddress = NULL,
-	.srcXincrement = 1,
-	.dstXincrement = 0,
-	.xCount = 5,
-	.srcYincrement = 0,
-	.dstYincrement = 0,
-	.yCount = 1,
-	.nextDescriptor = NULL,
-};
-cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0 = 
-{
-	.ctl = 0UL,
-	.src = 0UL,
-	.dst = 0UL,
-	.xCtl = 0UL,
-	.yCtl = 0UL,
-	.nextPtr = 0UL,
-};
-const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig = 
-{
-	.descriptor = &cpuss_0_dw0_0_chan_1_Descriptor_0,
-	.preemptable = true,
-	.priority = 1,
-	.enable = false,
-	.bufferable = false,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj = 
-	{
-		.type = CYHAL_RSC_DMA,
-		.block_num = 0U,
-		.channel_num = cpuss_0_dw0_0_chan_1_CHANNEL,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config = 
-{
-	.retrigger = CY_DMA_RETRIG_4CYC,
-	.interruptType = CY_DMA_DESCR,
-	.triggerOutType = CY_DMA_1ELEMENT,
-	.channelState = CY_DMA_CHANNEL_DISABLED,
-	.triggerInType = CY_DMA_X_LOOP,
-	.dataSize = CY_DMA_HALFWORD,
-	.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
-	.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
-	.descriptorType = CY_DMA_2D_TRANSFER,
-	.srcAddress = NULL,
-	.dstAddress = NULL,
-	.srcXincrement = 2,
-	.dstXincrement = 0,
-	.xCount = 10,
-	.srcYincrement = 10,
-	.dstYincrement = 0,
-	.yCount = 2,
-	.nextDescriptor = NULL,
-};
-cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0 = 
-{
-	.ctl = 0UL,
-	.src = 0UL,
-	.dst = 0UL,
-	.xCtl = 0UL,
-	.yCtl = 0UL,
-	.nextPtr = 0UL,
-};
-const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig = 
-{
-	.descriptor = &cpuss_0_dw1_0_chan_1_Descriptor_0,
-	.preemptable = false,
-	.priority = 0,
-	.enable = false,
-	.bufferable = false,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj = 
-	{
-		.type = CYHAL_RSC_DMA,
-		.block_num = 1U,
-		.channel_num = cpuss_0_dw1_0_chan_1_CHANNEL,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config = 
-{
-	.retrigger = CY_DMA_RETRIG_IM,
-	.interruptType = CY_DMA_DESCR,
-	.triggerOutType = CY_DMA_1ELEMENT,
-	.channelState = CY_DMA_CHANNEL_DISABLED,
-	.triggerInType = CY_DMA_X_LOOP,
-	.dataSize = CY_DMA_HALFWORD,
-	.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
-	.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
-	.descriptorType = CY_DMA_2D_TRANSFER,
-	.srcAddress = NULL,
-	.dstAddress = NULL,
-	.srcXincrement = 0,
-	.dstXincrement = 2,
-	.xCount = 10,
-	.srcYincrement = 0,
-	.dstYincrement = 10,
-	.yCount = 2,
-	.nextDescriptor = NULL,
-};
-cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0 = 
-{
-	.ctl = 0UL,
-	.src = 0UL,
-	.dst = 0UL,
-	.xCtl = 0UL,
-	.yCtl = 0UL,
-	.nextPtr = 0UL,
-};
-const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig = 
-{
-	.descriptor = &cpuss_0_dw1_0_chan_3_Descriptor_0,
-	.preemptable = false,
-	.priority = 0,
-	.enable = false,
-	.bufferable = false,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj = 
-	{
-		.type = CYHAL_RSC_DMA,
-		.block_num = 1U,
-		.channel_num = cpuss_0_dw1_0_chan_3_CHANNEL,
-	};
-#endif //defined (CY_USING_HAL)
-
-
-void init_cycfg_dmas(void)
-{
-#if defined (CY_USING_HAL)
-		cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_0_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-		cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_1_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-		cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_1_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-		cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_3_obj);
-#endif //defined (CY_USING_HAL)
-}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h
deleted file mode 100644
index d6c0d6587d..0000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_dmas.h
-*
-* Description:
-* DMA configuration
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_DMAS_H)
-#define CYCFG_DMAS_H
-
-#include "cycfg_notices.h"
-#include "cy_dma.h"
-#if defined (CY_USING_HAL)
-	#include "cyhal_hwmgr.h"
-#endif //defined (CY_USING_HAL)
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define cpuss_0_dw0_0_chan_0_ENABLED 1U
-#define cpuss_0_dw0_0_chan_0_HW DW0
-#define cpuss_0_dw0_0_chan_0_CHANNEL 0U
-#define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn
-#define cpuss_0_dw0_0_chan_1_ENABLED 1U
-#define cpuss_0_dw0_0_chan_1_HW DW0
-#define cpuss_0_dw0_0_chan_1_CHANNEL 1U
-#define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn
-#define cpuss_0_dw1_0_chan_1_ENABLED 1U
-#define cpuss_0_dw1_0_chan_1_HW DW1
-#define cpuss_0_dw1_0_chan_1_CHANNEL 1U
-#define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn
-#define cpuss_0_dw1_0_chan_3_ENABLED 1U
-#define cpuss_0_dw1_0_chan_3_HW DW1
-#define cpuss_0_dw1_0_chan_3_CHANNEL 3U
-#define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn
-
-extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config;
-extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0;
-extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config;
-extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0;
-extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config;
-extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0;
-extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config;
-extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0;
-extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj;
-#endif //defined (CY_USING_HAL)
-
-void init_cycfg_dmas(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_DMAS_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
index 106b3ad7a0..3d5385559e 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
@@ -118,7 +118,6 @@ extern "C" {
 #define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U
 #define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
 #define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
-#define CYBSP_USBUART_USB_CORE 4U
 #define CYBSP_USBUART_HW USBFS0
 #define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
 #define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
index ca1cca6896..7daee6bb07 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
@@ -216,11 +216,11 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
 		.channel_num = CYBSP_QSPI_SCK_PIN,
 	};
 #endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config = 
+const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config = 
 {
 	.outVal = 1,
 	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = ioss_0_port_14_pin_0_HSIOM,
+	.hsiom = CYBSP_USB_DP_HSIOM,
 	.intEdge = CY_GPIO_INTR_DISABLE,
 	.intMask = 0UL,
 	.vtrip = CY_GPIO_VTRIP_CMOS,
@@ -233,18 +233,18 @@ const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config =
 	.vohSel = 0UL,
 };
 #if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t ioss_0_port_14_pin_0_obj = 
+	const cyhal_resource_inst_t CYBSP_USB_DP_obj = 
 	{
 		.type = CYHAL_RSC_GPIO,
-		.block_num = ioss_0_port_14_pin_0_PORT_NUM,
-		.channel_num = ioss_0_port_14_pin_0_PIN,
+		.block_num = CYBSP_USB_DP_PORT_NUM,
+		.channel_num = CYBSP_USB_DP_PIN,
 	};
 #endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config = 
+const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config = 
 {
 	.outVal = 1,
 	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = ioss_0_port_14_pin_1_HSIOM,
+	.hsiom = CYBSP_USB_DM_HSIOM,
 	.intEdge = CY_GPIO_INTR_DISABLE,
 	.intMask = 0UL,
 	.vtrip = CY_GPIO_VTRIP_CMOS,
@@ -257,11 +257,11 @@ const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config =
 	.vohSel = 0UL,
 };
 #if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t ioss_0_port_14_pin_1_obj = 
+	const cyhal_resource_inst_t CYBSP_USB_DM_obj = 
 	{
 		.type = CYHAL_RSC_GPIO,
-		.block_num = ioss_0_port_14_pin_1_PORT_NUM,
-		.channel_num = ioss_0_port_14_pin_1_PIN,
+		.block_num = CYBSP_USB_DM_PORT_NUM,
+		.channel_num = CYBSP_USB_DM_PIN,
 	};
 #endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = 
@@ -884,14 +884,14 @@ void init_cycfg_pins(void)
 		cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj);
 #endif //defined (CY_USING_HAL)
 
-	Cy_GPIO_Pin_Init(ioss_0_port_14_pin_0_PORT, ioss_0_port_14_pin_0_PIN, &ioss_0_port_14_pin_0_config);
+	Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config);
 #if defined (CY_USING_HAL)
-		cyhal_hwmgr_reserve(&ioss_0_port_14_pin_0_obj);
+		cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj);
 #endif //defined (CY_USING_HAL)
 
-	Cy_GPIO_Pin_Init(ioss_0_port_14_pin_1_PORT, ioss_0_port_14_pin_1_PIN, &ioss_0_port_14_pin_1_config);
+	Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config);
 #if defined (CY_USING_HAL)
-		cyhal_hwmgr_reserve(&ioss_0_port_14_pin_1_obj);
+		cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj);
 #endif //defined (CY_USING_HAL)
 
 #if defined (CY_USING_HAL)
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
index 9bf6916e7b..95f624c7a5 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
@@ -228,51 +228,53 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
 #endif //defined (CY_USING_HAL)
-#define ioss_0_port_14_pin_0_ENABLED 1U
-#define ioss_0_port_14_pin_0_PORT GPIO_PRT14
-#define ioss_0_port_14_pin_0_PORT_NUM 14U
-#define ioss_0_port_14_pin_0_PIN 0U
-#define ioss_0_port_14_pin_0_NUM 0U
-#define ioss_0_port_14_pin_0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define ioss_0_port_14_pin_0_INIT_DRIVESTATE 1
+#define CYBSP_USB_DP_ENABLED 1U
+#define CYBSP_USB_DP_PORT GPIO_PRT14
+#define CYBSP_USB_DP_PORT_NUM 14U
+#define CYBSP_USB_DP_PIN 0U
+#define CYBSP_USB_DP_NUM 0U
+#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_USB_DP_INIT_DRIVESTATE 1
 #ifndef ioss_0_port_14_pin_0_HSIOM
 	#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
 #endif
-#define ioss_0_port_14_pin_0_IRQ ioss_interrupts_gpio_14_IRQn
+#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM
+#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn
 #if defined (CY_USING_HAL)
-	#define ioss_0_port_14_pin_0_HAL_PORT_PIN P14_0
+	#define CYBSP_USB_DP_HAL_PORT_PIN P14_0
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-	#define ioss_0_port_14_pin_0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+	#define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-	#define ioss_0_port_14_pin_0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+	#define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT 
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-	#define ioss_0_port_14_pin_0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+	#define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
 #endif //defined (CY_USING_HAL)
-#define ioss_0_port_14_pin_1_ENABLED 1U
-#define ioss_0_port_14_pin_1_PORT GPIO_PRT14
-#define ioss_0_port_14_pin_1_PORT_NUM 14U
-#define ioss_0_port_14_pin_1_PIN 1U
-#define ioss_0_port_14_pin_1_NUM 1U
-#define ioss_0_port_14_pin_1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define ioss_0_port_14_pin_1_INIT_DRIVESTATE 1
+#define CYBSP_USB_DM_ENABLED 1U
+#define CYBSP_USB_DM_PORT GPIO_PRT14
+#define CYBSP_USB_DM_PORT_NUM 14U
+#define CYBSP_USB_DM_PIN 1U
+#define CYBSP_USB_DM_NUM 1U
+#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_USB_DM_INIT_DRIVESTATE 1
 #ifndef ioss_0_port_14_pin_1_HSIOM
 	#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
 #endif
-#define ioss_0_port_14_pin_1_IRQ ioss_interrupts_gpio_14_IRQn
+#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM
+#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn
 #if defined (CY_USING_HAL)
-	#define ioss_0_port_14_pin_1_HAL_PORT_PIN P14_1
+	#define CYBSP_USB_DM_HAL_PORT_PIN P14_1
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-	#define ioss_0_port_14_pin_1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+	#define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-	#define ioss_0_port_14_pin_1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+	#define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT 
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-	#define ioss_0_port_14_pin_1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+	#define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
 #endif //defined (CY_USING_HAL)
 #define CYBSP_CSD_TX_ENABLED 1U
 #define CYBSP_CSD_TX_PORT GPIO_PRT1
@@ -883,13 +885,13 @@ extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
 #if defined (CY_USING_HAL)
 	extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj;
 #endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config;
 #if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t ioss_0_port_14_pin_0_obj;
+	extern const cyhal_resource_inst_t CYBSP_USB_DP_obj;
 #endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config;
 #if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t ioss_0_port_14_pin_1_obj;
+	extern const cyhal_resource_inst_t CYBSP_USB_DM_obj;
 #endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
 #if defined (CY_USING_HAL)
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
index c4e5bcf916..14d433859d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
@@ -24,7 +24,7 @@
 
 #include "cycfg_qspi_memslot.h"
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0xECU,
@@ -42,7 +42,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x06U,
@@ -60,7 +60,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x04U,
@@ -78,7 +78,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0xDCU,
@@ -96,7 +96,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x60U,
@@ -114,7 +114,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x34U,
@@ -132,7 +132,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x35U,
@@ -150,7 +150,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x05U,
@@ -168,7 +168,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x01U,
@@ -186,34 +186,34 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
+const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 =
 {
     /* Specifies the number of address bytes used by the memory slave device. */
     .numOfAddrBytes = 0x04U,
     /* The size of the memory. */
     .memSize = 0x04000000U,
     /* Specifies the Read command. */
-    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
+    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd,
     /* Specifies the Write Enable command. */
-    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
+    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd,
     /* Specifies the Write Disable command. */
-    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
+    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd,
     /* Specifies the Erase command. */
-    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
+    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd,
     /* Specifies the sector size of each erase. */
     .eraseSize = 0x00040000U,
     /* Specifies the Chip Erase command. */
-    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
+    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd,
     /* Specifies the Program command. */
-    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
+    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd,
     /* Specifies the page size for programming. */
     .programSize = 0x00000200U,
     /* Specifies the command to read the QE-containing status register. */
-    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
+    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd,
     /* Specifies the command to read the WIP-containing status register. */
-    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
+    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd,
     /* Specifies the command to write into the QE-containing status register. */
-    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
+    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
     /* The mask for the status register. */
     .stsRegBusyMask = 0x01U,
     /* The mask for the status register. */
@@ -226,7 +226,7 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
     .programTime = 1300U
 };
 
-const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
+const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 =
 {
     /* Determines the slot number where the memory device is placed. */
     .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
@@ -244,11 +244,11 @@ const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
     Valid when the memory mapped mode is enabled. */
     .dualQuadSlots = 0,
     /* The configuration of the device. */
-    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
+    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0
 };
 
 const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
-   &S25FL512SX4byteaddr_SlaveSlot_0
+   &S25FL512S_4byteaddr_SlaveSlot_0
 };
 
 const cy_stc_smif_block_config_t smifBlockConfig =
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
index 32f9b49b2e..0ee62b1d55 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
@@ -28,19 +28,19 @@
 
 #define CY_SMIF_DEVICE_NUM 1
 
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
 
-extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
+extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0;
 
-extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
+extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0;
 extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
 
 extern const cy_stc_smif_block_config_t smifBlockConfig;
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
index c58ceb548d..79a5f7bedc 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
@@ -1,31 +1,14 @@
-[Device="CY8C6247BZI-D54"]
+[Device=CY8C6247BZI-D54]
  
 [Blocks]
-# User IO
-# CYBSP_USER_LED1
-ioss[0].port[1].pin[5]
-# CYBSP_USER_LED2
-ioss[0].port[13].pin[7]
-# CYBSP_USER_LED3
-ioss[0].port[0].pin[3]
-# CYBSP_USER_LED4
-ioss[0].port[1].pin[1]
-# CYBSP_USER_LED5
-ioss[0].port[11].pin[1]
-# CYBSP_USER_BTN1
-ioss[0].port[0].pin[4]
-
-# Debug
-# CYBSP_DEBUG_UART
-scb[5]
-# CYBSP_DEBUG_UART_RX
-ioss[0].port[5].pin[0]
-# CYBSP_DEBUG_UART_TX
-ioss[0].port[5].pin[1]
-
 # WIFI
 # CYBSP_WIFI_SDIO
 udb[0]
+peri[0].div_8[0]
+cpuss[0].dw0[0].chan[0]
+cpuss[0].dw0[0].chan[1]
+cpuss[0].dw1[0].chan[1]
+cpuss[0].dw1[0].chan[3]
 # CYBSP_WIFI_SDIO_D0
 ioss[0].port[2].pin[0]
 # CYBSP_WIFI_SDIO_D1
@@ -39,4 +22,21 @@ ioss[0].port[2].pin[4]
 # CYBSP_WIFI_SDIO_CLK
 ioss[0].port[2].pin[5]
 # CYBSP_WIFI_WL_REG_ON
-ioss[0].port[2].pin[6]
\ No newline at end of file
+ioss[0].port[2].pin[6]
+
+[RoutingResources]
+# CYBSP_WIFI_SDIO
+cpuss[0].dw0_tr_in[0] 
+cpuss[0].dw0_tr_in[1] 
+cpuss[0].dw1_tr_in[1] 
+cpuss[0].dw1_tr_in[3] 
+
+udb[0].tr_udb[0] 
+udb[0].tr_udb[1] 
+udb[0].tr_udb[3] 
+udb[0].tr_udb[7] 
+
+tr_group[0].input[43] 
+tr_group[0].input[44] 
+tr_group[0].input[47] 
+tr_group[0].input[48] 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus
index 089526cce0..ac79c2d9f7 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus
@@ -8,114 +8,6 @@
                     <Param id="dbgMode" value="SWD"/>
                     <Param id="traceEnable" value="false"/>
                 </Block>
-                <Block location="cpuss[0].dw0[0].chan[0]" alias="" template="mxs40dma" version="1.0">
-                    <Param id="CRC_DATA_REVERSE" value="false"/>
-                    <Param id="CRC_DATA_XOR" value="0"/>
-                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
-                    <Param id="CRC_REMINDER_XOR" value="0"/>
-                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
-                    <Param id="CHANNEL_PRIORITY" value="1"/>
-                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
-                    <Param id="PREEMPTABLE" value="true"/>
-                    <Param id="BUFFERABLE" value="false"/>
-                    <Param id="DESCR_SELECTION" value="0"/>
-                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="INTR_OUT_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="ENABLE_CHAINING_0" value="false"/>
-                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
-                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_IM"/>
-                    <Param id="DATA_TRANSFER_WIDTH_0" value="ByteToByte"/>
-                    <Param id="X_NUM_OF_ELEMENTS_0" value="6"/>
-                    <Param id="X_SRC_INCREMENT_0" value="0"/>
-                    <Param id="X_DST_INCREMENT_0" value="1"/>
-                    <Param id="CRC_0" value="false"/>
-                    <Param id="Y_NUM_OF_ELEMENTS_0" value="1"/>
-                    <Param id="Y_SRC_INCREMENT_0" value="0"/>
-                    <Param id="Y_DST_INCREMENT_0" value="0"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="cpuss[0].dw0[0].chan[1]" alias="" template="mxs40dma" version="1.0">
-                    <Param id="CRC_DATA_REVERSE" value="false"/>
-                    <Param id="CRC_DATA_XOR" value="0"/>
-                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
-                    <Param id="CRC_REMINDER_XOR" value="0"/>
-                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
-                    <Param id="CHANNEL_PRIORITY" value="1"/>
-                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
-                    <Param id="PREEMPTABLE" value="true"/>
-                    <Param id="BUFFERABLE" value="false"/>
-                    <Param id="DESCR_SELECTION" value="0"/>
-                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="INTR_OUT_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="ENABLE_CHAINING_0" value="false"/>
-                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
-                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_16CYC"/>
-                    <Param id="DATA_TRANSFER_WIDTH_0" value="ByteToByte"/>
-                    <Param id="X_NUM_OF_ELEMENTS_0" value="5"/>
-                    <Param id="X_SRC_INCREMENT_0" value="1"/>
-                    <Param id="X_DST_INCREMENT_0" value="0"/>
-                    <Param id="CRC_0" value="false"/>
-                    <Param id="Y_NUM_OF_ELEMENTS_0" value="1"/>
-                    <Param id="Y_SRC_INCREMENT_0" value="0"/>
-                    <Param id="Y_DST_INCREMENT_0" value="0"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="cpuss[0].dw1[0].chan[1]" alias="" template="mxs40dma" version="1.0">
-                    <Param id="CRC_DATA_REVERSE" value="false"/>
-                    <Param id="CRC_DATA_XOR" value="0"/>
-                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
-                    <Param id="CRC_REMINDER_XOR" value="0"/>
-                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
-                    <Param id="CHANNEL_PRIORITY" value="0"/>
-                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
-                    <Param id="PREEMPTABLE" value="false"/>
-                    <Param id="BUFFERABLE" value="false"/>
-                    <Param id="DESCR_SELECTION" value="0"/>
-                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="INTR_OUT_0" value="CY_DMA_DESCR"/>
-                    <Param id="ENABLE_CHAINING_0" value="false"/>
-                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
-                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_X_LOOP"/>
-                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_4CYC"/>
-                    <Param id="DATA_TRANSFER_WIDTH_0" value="HalfwordToHalfword"/>
-                    <Param id="X_NUM_OF_ELEMENTS_0" value="10"/>
-                    <Param id="X_SRC_INCREMENT_0" value="2"/>
-                    <Param id="X_DST_INCREMENT_0" value="0"/>
-                    <Param id="CRC_0" value="false"/>
-                    <Param id="Y_NUM_OF_ELEMENTS_0" value="2"/>
-                    <Param id="Y_SRC_INCREMENT_0" value="10"/>
-                    <Param id="Y_DST_INCREMENT_0" value="0"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="cpuss[0].dw1[0].chan[3]" alias="" template="mxs40dma" version="1.0">
-                    <Param id="CRC_DATA_REVERSE" value="false"/>
-                    <Param id="CRC_DATA_XOR" value="0"/>
-                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
-                    <Param id="CRC_REMINDER_XOR" value="0"/>
-                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
-                    <Param id="CHANNEL_PRIORITY" value="0"/>
-                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
-                    <Param id="PREEMPTABLE" value="false"/>
-                    <Param id="BUFFERABLE" value="false"/>
-                    <Param id="DESCR_SELECTION" value="0"/>
-                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="INTR_OUT_0" value="CY_DMA_DESCR"/>
-                    <Param id="ENABLE_CHAINING_0" value="false"/>
-                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
-                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_X_LOOP"/>
-                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_IM"/>
-                    <Param id="DATA_TRANSFER_WIDTH_0" value="HalfwordToHalfword"/>
-                    <Param id="X_NUM_OF_ELEMENTS_0" value="10"/>
-                    <Param id="X_SRC_INCREMENT_0" value="0"/>
-                    <Param id="X_DST_INCREMENT_0" value="2"/>
-                    <Param id="CRC_0" value="false"/>
-                    <Param id="Y_NUM_OF_ELEMENTS_0" value="2"/>
-                    <Param id="Y_SRC_INCREMENT_0" value="0"/>
-                    <Param id="Y_DST_INCREMENT_0" value="10"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="csd[0].csd[0]" alias="CYBSP_CSD" template="mxs40csd" version="2.0">
                     <Param id="CapSenseEnable" value="true"/>
                     <Param id="CapSenseCore" value="4"/>
@@ -232,7 +124,7 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[14].pin[0]" alias="" template="mxs40pin" version="1.1">
+                <Block location="ioss[0].port[14].pin[0]" alias="CYBSP_USB_DP" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@@ -242,7 +134,7 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[14].pin[1]" alias="" template="mxs40pin" version="1.1">
+                <Block location="ioss[0].port[14].pin[1]" alias="CYBSP_USB_DM" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@@ -497,11 +389,6 @@
                     <Param id="fracDivider" value="0"/>
                     <Param id="startOnReset" value="true"/>
                 </Block>
-                <Block location="peri[0].div_8[0]" alias="CYBSP_SDIO_DIV" template="mxs40peripheralclock" version="1.0">
-                    <Param id="intDivider" value="1"/>
-                    <Param id="fracDivider" value="0"/>
-                    <Param id="startOnReset" value="true"/>
-                </Block>
                 <Block location="peri[0].div_8[1]" alias="CYBSP_CSD_COMM_CLK_DIV" template="mxs40peripheralclock" version="1.0">
                     <Param id="intDivider" value="8"/>
                     <Param id="fracDivider" value="0"/>
@@ -512,7 +399,7 @@
                     <Param id="fracDivider" value="0"/>
                     <Param id="startOnReset" value="true"/>
                 </Block>
-                <Block location="peri[0].div_8[4]" alias="" template="mxs40peripheralclock" version="1.0">
+                <Block location="peri[0].div_8[4]" alias="CYBSP_BT_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
                     <Param id="intDivider" value="109"/>
                     <Param id="fracDivider" value="0"/>
                     <Param id="startOnReset" value="true"/>
@@ -673,7 +560,6 @@
                     <Param id="inFlash" value="true"/>
                 </Block>
                 <Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
-                    <Param id="pwrEstimator" value="0"/>
                     <Param id="pwrMode" value="LDO_1_1"/>
                     <Param id="actPwrMode" value="LP"/>
                     <Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
@@ -713,12 +599,10 @@
                     <Param id="dstStopHour" value="0"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.0">
-                    <Param id="configurator" value="0"/>
-                    <Param id="UsbCore" value="4"/>
+                <Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.1">
                     <Param id="epMask" value="0"/>
-                    <Param id="bufSize" value="512"/>
                     <Param id="mngMode" value="CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU"/>
+                    <Param id="bufSize" value="512"/>
                     <Param id="epAccess" value="CY_USBFS_DEV_DRV_USE_8_BITS_DR"/>
                     <Param id="enableLpm" value="false"/>
                     <Param id="lpmIntr" value="0x0U"/>
@@ -887,8 +771,6 @@
             <Netlist/>
         </Device>
     </Devices>
-    <Libraries>
-        <Library name="psoc6sw" version="1.2"/>
-    </Libraries>
+    <Libraries/>
     <ConfiguratorData/>
 </Design>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
index 3639c4da05..06429f5183 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
@@ -24,6 +24,14 @@
 
 #include "cycfg_clocks.h"
 
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_USB_CLK_DIV_HW,
+		.channel_num = CYBSP_USB_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = 
 	{
@@ -52,6 +60,13 @@
 
 void init_cycfg_clocks(void)
 {
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 499U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
 	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
index 30aec8b8b4..eb49bf1b7c 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
@@ -35,6 +35,9 @@
 extern "C" {
 #endif
 
+#define CYBSP_USB_CLK_DIV_ENABLED 1U
+#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
+#define CYBSP_USB_CLK_DIV_NUM 0U
 #define CYBSP_CSD_CLK_DIV_ENABLED 1U
 #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_CSD_CLK_DIV_NUM 0U
@@ -45,6 +48,9 @@ extern "C" {
 #define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_BT_UART_CLK_DIV_NUM 3U
 
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
 #endif //defined (CY_USING_HAL)
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
index 022f8d7208..edb443da8a 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
@@ -24,6 +24,20 @@
 
 #include "cycfg_peripherals.h"
 
+#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
+                 CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
+                 CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
+                 CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \
+                 CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U))
+
 cy_stc_csd_context_t cy_csd_0_context = 
 {
 	.lockKey = CY_CSD_NONE_KEY,
@@ -136,6 +150,31 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
 		.channel_num = 0U,
 	};
 #endif //defined (CY_USING_HAL)
+const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config = 
+{
+	.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
+	.epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
+	.epBuffer = NULL,
+	.epBufferSize = 0U,
+	.dmaConfig[0] = NULL,
+	.dmaConfig[1] = NULL,
+	.dmaConfig[2] = NULL,
+	.dmaConfig[3] = NULL,
+	.dmaConfig[4] = NULL,
+	.dmaConfig[5] = NULL,
+	.dmaConfig[6] = NULL,
+	.dmaConfig[7] = NULL,
+	.enableLpm = false,
+	.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
+};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USBUART_obj = 
+	{
+		.type = CYHAL_RSC_USB,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_peripherals(void)
@@ -163,4 +202,9 @@ void init_cycfg_peripherals(void)
 #if defined (CY_USING_HAL)
 		cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
 #endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USBUART_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
index 2749cb0f4b..0df379d569 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
@@ -37,6 +37,7 @@
 #include "cycfg_qspi_memslot.h"
 #include "cy_mcwdt.h"
 #include "cy_rtc.h"
+#include "cy_usbfs_dev_drv.h"
 
 #if defined(__cplusplus)
 extern "C" {
@@ -113,6 +114,14 @@ extern "C" {
 #define CYBSP_RTC_100_YEAR_OFFSET (8U)
 #define CYBSP_RTC_10_YEAR_OFFSET (4U)
 #define CYBSP_RTC_YEAR_OFFSET (0U)
+#define CYBSP_USBUART_ENABLED 1U
+#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U
+#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
+#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
+#define CYBSP_USBUART_HW USBFS0
+#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
+#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn
+#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn
 
 extern cy_stc_csd_context_t cy_csd_0_context;
 extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
@@ -135,6 +144,10 @@ extern const cy_stc_rtc_config_t CYBSP_RTC_config;
 #if defined (CY_USING_HAL)
 	extern const cyhal_resource_inst_t CYBSP_RTC_obj;
 #endif //defined (CY_USING_HAL)
+extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USBUART_obj;
+#endif //defined (CY_USING_HAL)
 
 void init_cycfg_peripherals(void);
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
index 54a6937a3e..d7a628353b 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
@@ -240,6 +240,54 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
 		.channel_num = CYBSP_QSPI_SCK_PIN,
 	};
 #endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config = 
+{
+	.outVal = 1,
+	.driveMode = CY_GPIO_DM_ANALOG,
+	.hsiom = CYBSP_USB_DP_HSIOM,
+	.intEdge = CY_GPIO_INTR_DISABLE,
+	.intMask = 0UL,
+	.vtrip = CY_GPIO_VTRIP_CMOS,
+	.slewRate = CY_GPIO_SLEW_FAST,
+	.driveSel = CY_GPIO_DRIVE_1_2,
+	.vregEn = 0UL,
+	.ibufMode = 0UL,
+	.vtripSel = 0UL,
+	.vrefSel = 0UL,
+	.vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USB_DP_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_USB_DP_PORT_NUM,
+		.channel_num = CYBSP_USB_DP_PIN,
+	};
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config = 
+{
+	.outVal = 1,
+	.driveMode = CY_GPIO_DM_ANALOG,
+	.hsiom = CYBSP_USB_DM_HSIOM,
+	.intEdge = CY_GPIO_INTR_DISABLE,
+	.intMask = 0UL,
+	.vtrip = CY_GPIO_VTRIP_CMOS,
+	.slewRate = CY_GPIO_SLEW_FAST,
+	.driveSel = CY_GPIO_DRIVE_1_2,
+	.vregEn = 0UL,
+	.ibufMode = 0UL,
+	.vtripSel = 0UL,
+	.vrefSel = 0UL,
+	.vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USB_DM_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_USB_DM_PORT_NUM,
+		.channel_num = CYBSP_USB_DM_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = 
 {
 	.outVal = 1,
@@ -841,6 +889,16 @@ void init_cycfg_pins(void)
 		cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj);
 #endif //defined (CY_USING_HAL)
 
+	Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj);
+#endif //defined (CY_USING_HAL)
+
 #if defined (CY_USING_HAL)
 		cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
 #endif //defined (CY_USING_HAL)
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
index b04921c52f..76eaef0b40 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
@@ -252,6 +252,54 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
 #endif //defined (CY_USING_HAL)
+#define CYBSP_USB_DP_ENABLED 1U
+#define CYBSP_USB_DP_PORT GPIO_PRT14
+#define CYBSP_USB_DP_PORT_NUM 14U
+#define CYBSP_USB_DP_PIN 0U
+#define CYBSP_USB_DP_NUM 0U
+#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_USB_DP_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_14_pin_0_HSIOM
+	#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM
+#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DP_HAL_PORT_PIN P14_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_USB_DM_ENABLED 1U
+#define CYBSP_USB_DM_PORT GPIO_PRT14
+#define CYBSP_USB_DM_PORT_NUM 14U
+#define CYBSP_USB_DM_PIN 1U
+#define CYBSP_USB_DM_NUM 1U
+#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_USB_DM_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_14_pin_1_HSIOM
+	#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM
+#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DM_HAL_PORT_PIN P14_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
 #define CYBSP_CSD_TX_ENABLED 1U
 #define CYBSP_CSD_TX_PORT GPIO_PRT1
 #define CYBSP_CSD_TX_PORT_NUM 1U
@@ -841,6 +889,14 @@ extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
 #if defined (CY_USING_HAL)
 	extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj;
 #endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USB_DP_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USB_DM_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
 #if defined (CY_USING_HAL)
 	extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj;
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
index c4e5bcf916..14d433859d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
@@ -24,7 +24,7 @@
 
 #include "cycfg_qspi_memslot.h"
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0xECU,
@@ -42,7 +42,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x06U,
@@ -60,7 +60,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x04U,
@@ -78,7 +78,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0xDCU,
@@ -96,7 +96,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x60U,
@@ -114,7 +114,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x34U,
@@ -132,7 +132,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x35U,
@@ -150,7 +150,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x05U,
@@ -168,7 +168,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x01U,
@@ -186,34 +186,34 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
+const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 =
 {
     /* Specifies the number of address bytes used by the memory slave device. */
     .numOfAddrBytes = 0x04U,
     /* The size of the memory. */
     .memSize = 0x04000000U,
     /* Specifies the Read command. */
-    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
+    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd,
     /* Specifies the Write Enable command. */
-    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
+    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd,
     /* Specifies the Write Disable command. */
-    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
+    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd,
     /* Specifies the Erase command. */
-    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
+    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd,
     /* Specifies the sector size of each erase. */
     .eraseSize = 0x00040000U,
     /* Specifies the Chip Erase command. */
-    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
+    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd,
     /* Specifies the Program command. */
-    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
+    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd,
     /* Specifies the page size for programming. */
     .programSize = 0x00000200U,
     /* Specifies the command to read the QE-containing status register. */
-    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
+    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd,
     /* Specifies the command to read the WIP-containing status register. */
-    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
+    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd,
     /* Specifies the command to write into the QE-containing status register. */
-    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
+    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
     /* The mask for the status register. */
     .stsRegBusyMask = 0x01U,
     /* The mask for the status register. */
@@ -226,7 +226,7 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
     .programTime = 1300U
 };
 
-const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
+const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 =
 {
     /* Determines the slot number where the memory device is placed. */
     .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
@@ -244,11 +244,11 @@ const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
     Valid when the memory mapped mode is enabled. */
     .dualQuadSlots = 0,
     /* The configuration of the device. */
-    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
+    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0
 };
 
 const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
-   &S25FL512SX4byteaddr_SlaveSlot_0
+   &S25FL512S_4byteaddr_SlaveSlot_0
 };
 
 const cy_stc_smif_block_config_t smifBlockConfig =
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
index 32f9b49b2e..0ee62b1d55 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
@@ -28,19 +28,19 @@
 
 #define CY_SMIF_DEVICE_NUM 1
 
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
 
-extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
+extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0;
 
-extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
+extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0;
 extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
 
 extern const cy_stc_smif_block_config_t smifBlockConfig;
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
index 89e36dce12..d2306adee2 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
@@ -76,7 +76,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
 	.refDiv = 20U,
 	.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
 	.enableOutputDiv = true,
-	.lockTolerance = 10U,
+	.lockTolerance = 4U,
 	.igain = 9U,
 	.pgain = 5U,
 	.settlingCount = 8U,
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
index 779bac9b78..8453a4470f 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
@@ -1,20 +1,6 @@
-[Device="CY8C624ABZI-D44"]
+[Device=CY8C624ABZI-D44]
  
 [Blocks]
-# User IO
-# CYBSP_USER_LED1
-ioss[0].port[13].pin[7]
-# CYBSP_USER_BTN1
-ioss[0].port[0].pin[4]
-
-# Debug
-# CYBSP_DEBUG_UART
-scb[5]
-# CYBSP_DEBUG_UART_RX
-ioss[0].port[5].pin[0]
-# CYBSP_DEBUG_UART_TX
-ioss[0].port[5].pin[1]
-
 # WIFI
 # CYBSP_WIFI_SDIO
 sdhc[0]
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense
index 239c647ba5..43d6108110 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense
@@ -74,5 +74,336 @@
         <Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
         <Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
     </CsxProperties>
-    <Widgets/>
+    <Widgets>
+        <Widget id="Button0" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="Button1" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="LinearSlider0" type="LINEAR_SLIDER">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Sns0" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns1" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns2" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns3" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns4" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+    </Widgets>
 </Configuration>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus
index 586b4c9934..7212a7127a 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Design version="11" device_library_hint_path="../../psoc6pdl/devicesupport.xml" xmlns="http://cypress.com/xsd/cydesignfile_v2">
+<Design version="11" xmlns="http://cypress.com/xsd/cydesignfile_v2">
     <ToolInfo version="1.0.0"/>
     <Devices>
         <Device mpn="CY8C624ABZI-D44">
@@ -134,6 +134,26 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
+                <Block location="ioss[0].port[14].pin[0]" alias="CYBSP_USB_DP" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[14].pin[1]" alias="CYBSP_USB_DM" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
                 <Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_TX" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                     <Param id="initialState" value="1"/>
@@ -364,6 +384,11 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
+                <Block location="peri[0].div_16[0]" alias="CYBSP_USB_CLK_DIV" template="mxs40peripheralclock" version="1.0">
+                    <Param id="intDivider" value="500"/>
+                    <Param id="fracDivider" value="0"/>
+                    <Param id="startOnReset" value="true"/>
+                </Block>
                 <Block location="peri[0].div_8[0]" alias="CYBSP_CSD_CLK_DIV" template="mxs40peripheralclock" version="1.0">
                     <Param id="intDivider" value="256"/>
                     <Param id="fracDivider" value="0"/>
@@ -474,7 +499,7 @@
                     <Param id="hibernate" value="true"/>
                 </Block>
                 <Block location="srss[0].clock[0].imo[0]" alias="" template="mxs40imo" version="1.0">
-                    <Param id="trim" value="1"/>
+                    <Param id="trim" value="0.25"/>
                 </Block>
                 <Block location="srss[0].clock[0].lfclk[0]" alias="" template="mxs40lfclk" version="1.1">
                     <Param id="sourceClock" value="wco"/>
@@ -531,7 +556,6 @@
                     <Param id="inFlash" value="true"/>
                 </Block>
                 <Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
-                    <Param id="pwrEstimator" value="0"/>
                     <Param id="pwrMode" value="LDO_1_1"/>
                     <Param id="actPwrMode" value="LP"/>
                     <Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
@@ -571,6 +595,27 @@
                     <Param id="dstStopHour" value="0"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
+                <Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.1">
+                    <Param id="epMask" value="0"/>
+                    <Param id="mngMode" value="CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU"/>
+                    <Param id="bufSize" value="512"/>
+                    <Param id="epAccess" value="CY_USBFS_DEV_DRV_USE_8_BITS_DR"/>
+                    <Param id="enableLpm" value="false"/>
+                    <Param id="lpmIntr" value="0x0U"/>
+                    <Param id="ArbIntr" value="0x0U"/>
+                    <Param id="ep0CntrIntr" value="0x2U"/>
+                    <Param id="busResetIntr" value="0x2U"/>
+                    <Param id="sofIntr" value="0x1U"/>
+                    <Param id="ep0Intr" value="0x1U"/>
+                    <Param id="ep1Intr" value="0x1U"/>
+                    <Param id="ep2Intr" value="0x1U"/>
+                    <Param id="ep3Intr" value="0x1U"/>
+                    <Param id="ep4Intr" value="0x1U"/>
+                    <Param id="ep5Intr" value="0x1U"/>
+                    <Param id="ep6Intr" value="0x1U"/>
+                    <Param id="ep7Intr" value="0x1U"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
             </BlockConfig>
             <Netlist>
                 <Net>
@@ -645,6 +690,18 @@
                     <Port name="ioss[0].port[11].pin[7].digital_inout[0]"/>
                     <Port name="smif[0].spi_clk[0]"/>
                 </Net>
+                <Net>
+                    <Port name="ioss[0].port[14].pin[0].aux[0]"/>
+                    <Port name="usb[0].usb_dp_pad[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[14].pin[1].aux[0]"/>
+                    <Port name="usb[0].usb_dm_pad[0]"/>
+                </Net>
+                <Net>
+                    <Port name="peri[0].div_16[0].clk[0]"/>
+                    <Port name="usb[0].clock_dev_brs[0]"/>
+                </Net>
                 <Net>
                     <Port name="peri[0].div_8[1].clk[0]"/>
                     <Port name="scb[3].clock[0]"/>
@@ -661,6 +718,10 @@
                     <Port name="smif[0].clk_if[0]"/>
                     <Port name="srss[0].clock[0].hfclk[2].root_clk[0]"/>
                 </Net>
+                <Net>
+                    <Port name="srss[0].clock[0].hfclk[3].root_clk[0]"/>
+                    <Port name="usb[0].clk_usb_dev[0]"/>
+                </Net>
                 <Mux name="sense" location="csd[0].csd[0]">
                     <Arm>
                         <Port name="ioss[0].port[7].pin[7].analog[0]"/>
@@ -706,8 +767,6 @@
             <Netlist/>
         </Device>
     </Devices>
-    <Libraries>
-        <Library name="psoc6sw" version="1.2"/>
-    </Libraries>
+    <Libraries/>
     <ConfiguratorData/>
 </Design>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
index 54dbf991f9..36da6ec41b 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
@@ -24,18 +24,37 @@
 
 #include "cycfg_clocks.h"
 
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_USB_CLK_DIV_HW,
+		.channel_num = CYBSP_USB_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_I2C_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_I2C_CLK_DIV_HW,
+		.channel_num = CYBSP_I2C_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+
 
 void init_cycfg_clocks(void)
 {
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
 	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 499U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
-
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 35U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
 	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_I2C_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
index aef4c18422..aee335b703 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
@@ -27,21 +27,28 @@
 
 #include "cycfg_notices.h"
 #include "cy_sysclk.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 
 #if defined(__cplusplus)
 extern "C" {
 #endif
 
-#define peri_0_div_16_0_ENABLED 1U
-#define peri_0_div_16_0_HW CY_SYSCLK_DIV_16_BIT
-#define peri_0_div_16_0_NUM 0U
-#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
-#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
-#define CYBSP_DEBUG_UART_CLK_DIV_NUM 0U
+#define CYBSP_USB_CLK_DIV_ENABLED 1U
+#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
+#define CYBSP_USB_CLK_DIV_NUM 0U
 #define CYBSP_I2C_CLK_DIV_ENABLED 1U
 #define CYBSP_I2C_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_I2C_CLK_DIV_NUM 1U
 
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_I2C_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+
 void init_cycfg_clocks(void);
 
 #if defined(__cplusplus)
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
index 3fce96da0b..3b6a06b6ef 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
@@ -24,6 +24,20 @@
 
 #include "cycfg_peripherals.h"
 
+#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
+                 CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
+                 CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
+                 CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \
+                 CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \
+                 CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U))
+
 const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config = 
 {
 	.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
@@ -32,34 +46,14 @@ const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config =
 	.subAddressSize = CY_SCB_EZI2C_SUB_ADDR8_BITS,
 	.enableWakeFromSleep = false,
 };
-const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config = 
-{
-	.uartMode = CY_SCB_UART_STANDARD,
-	.enableMutliProcessorMode = false,
-	.smartCardRetryOnNack = false,
-	.irdaInvertRx = false,
-	.irdaEnableLowPowerReceiver = false,
-	.oversample = 12,
-	.enableMsbFirst = false,
-	.dataWidth = 8UL,
-	.parity = CY_SCB_UART_PARITY_NONE,
-	.stopBits = CY_SCB_UART_STOP_BITS_1,
-	.enableInputFilter = false,
-	.breakWidth = 11UL,
-	.dropOnFrameError = false,
-	.dropOnParityError = false,
-	.receiverAddress = 0x0UL,
-	.receiverAddressMask = 0x0UL,
-	.acceptAddrInFifo = false,
-	.enableCts = false,
-	.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
-	.rtsRxFifoLevel = 0UL,
-	.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
-	.rxFifoTriggerLevel = 63UL,
-	.rxFifoIntEnableMask = 0UL,
-	.txFifoTriggerLevel = 63UL,
-	.txFifoIntEnableMask = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_I2C_obj = 
+	{
+		.type = CYHAL_RSC_SCB,
+		.block_num = 3U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_smif_config_t CYBSP_QSPI_config = 
 {
 	.mode = (uint32_t)CY_SMIF_NORMAL,
@@ -67,11 +61,54 @@ const cy_stc_smif_config_t CYBSP_QSPI_config =
 	.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
 	.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_obj = 
+	{
+		.type = CYHAL_RSC_SMIF,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config = 
+{
+	.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
+	.epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
+	.epBuffer = NULL,
+	.epBufferSize = 0U,
+	.dmaConfig[0] = NULL,
+	.dmaConfig[1] = NULL,
+	.dmaConfig[2] = NULL,
+	.dmaConfig[3] = NULL,
+	.dmaConfig[4] = NULL,
+	.dmaConfig[5] = NULL,
+	.dmaConfig[6] = NULL,
+	.dmaConfig[7] = NULL,
+	.enableLpm = false,
+	.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
+};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USBUART_obj = 
+	{
+		.type = CYHAL_RSC_USB,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_peripherals(void)
 {
 	Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_I2C_obj);
+#endif //defined (CY_USING_HAL)
 
-	Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USBUART_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
index 871b62dc66..7680b5fe23 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
@@ -28,9 +28,12 @@
 #include "cycfg_notices.h"
 #include "cy_scb_ezi2c.h"
 #include "cy_sysclk.h"
-#include "cy_scb_uart.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 #include "cy_smif.h"
 #include "cycfg_qspi_memslot.h"
+#include "cy_usbfs_dev_drv.h"
 
 #if defined(__cplusplus)
 extern "C" {
@@ -39,9 +42,6 @@ extern "C" {
 #define CYBSP_I2C_ENABLED 1U
 #define CYBSP_I2C_HW SCB3
 #define CYBSP_I2C_IRQ scb_3_interrupt_IRQn
-#define CYBSP_DEBUG_UART_ENABLED 1U
-#define CYBSP_DEBUG_UART_HW SCB5
-#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
 #define CYBSP_QSPI_ENABLED 1U
 #define CYBSP_QSPI_HW SMIF0
 #define CYBSP_QSPI_IRQ smif_interrupt_IRQn
@@ -60,10 +60,27 @@ extern "C" {
 #define CYBSP_QSPI_SS2 (0UL)
 #define CYBSP_QSPI_SS3 (0UL)
 #define CYBSP_QSPI_DESELECT_DELAY 7
+#define CYBSP_USBUART_ENABLED 1U
+#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U
+#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
+#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
+#define CYBSP_USBUART_HW USBFS0
+#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
+#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn
+#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn
 
 extern const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config;
-extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_I2C_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_smif_config_t CYBSP_QSPI_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USBUART_obj;
+#endif //defined (CY_USING_HAL)
 
 void init_cycfg_peripherals(void);
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
index 18d8b8518e..9a0642174b 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
@@ -40,6 +40,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WCO_IN_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WCO_IN_PORT_NUM,
+		.channel_num = CYBSP_WCO_IN_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = 
 {
 	.outVal = 1,
@@ -56,22 +64,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_SW2_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_PULLUP,
-	.hsiom = CYBSP_SW2_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WCO_OUT_PORT_NUM,
+		.channel_num = CYBSP_WCO_OUT_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config = 
 {
 	.outVal = 1,
@@ -88,6 +88,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_SS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_SS_PORT_NUM,
+		.channel_num = CYBSP_QSPI_SS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config = 
 {
 	.outVal = 1,
@@ -104,6 +112,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D3_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D3_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D3_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config = 
 {
 	.outVal = 1,
@@ -120,6 +136,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D2_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D2_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D2_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config = 
 {
 	.outVal = 1,
@@ -136,6 +160,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D1_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config = 
 {
 	.outVal = 1,
@@ -152,6 +184,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D0_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = 
 {
 	.outVal = 1,
@@ -168,6 +208,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_SCK_PORT_NUM,
+		.channel_num = CYBSP_QSPI_SCK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config = 
 {
 	.outVal = 1,
@@ -184,6 +232,14 @@ const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_ECO_IN_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_ECO_IN_PORT_NUM,
+		.channel_num = CYBSP_ECO_IN_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config = 
 {
 	.outVal = 1,
@@ -200,22 +256,14 @@ const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED3_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED3_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_ECO_OUT_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_ECO_OUT_PORT_NUM,
+		.channel_num = CYBSP_ECO_OUT_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config = 
 {
 	.outVal = 1,
@@ -232,6 +280,14 @@ const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USB_DP_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_USB_DP_PORT_NUM,
+		.channel_num = CYBSP_USB_DP_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config = 
 {
 	.outVal = 1,
@@ -248,54 +304,14 @@ const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED4_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED4_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t ioss_0_port_5_pin_0_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_HIGHZ,
-	.hsiom = ioss_0_port_5_pin_0_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t ioss_0_port_5_pin_1_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = ioss_0_port_5_pin_1_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USB_DM_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_USB_DM_PORT_NUM,
+		.channel_num = CYBSP_USB_DM_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_config = 
 {
 	.outVal = 1,
@@ -312,6 +328,14 @@ const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_I2C_SCL_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_I2C_SCL_PORT_NUM,
+		.channel_num = CYBSP_I2C_SCL_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_config = 
 {
 	.outVal = 1,
@@ -328,6 +352,14 @@ const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_I2C_SDA_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_I2C_SDA_PORT_NUM,
+		.channel_num = CYBSP_I2C_SDA_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWO_config = 
 {
 	.outVal = 1,
@@ -337,13 +369,21 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
 	.intMask = 0UL,
 	.vtrip = CY_GPIO_VTRIP_CMOS,
 	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_FULL,
+	.driveSel = CY_GPIO_DRIVE_1_2,
 	.vregEn = 0UL,
 	.ibufMode = 0UL,
 	.vtripSel = 0UL,
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWO_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWO_PORT_NUM,
+		.channel_num = CYBSP_SWO_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = 
 {
 	.outVal = 1,
@@ -353,13 +393,21 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
 	.intMask = 0UL,
 	.vtrip = CY_GPIO_VTRIP_CMOS,
 	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_FULL,
+	.driveSel = CY_GPIO_DRIVE_1_2,
 	.vregEn = 0UL,
 	.ibufMode = 0UL,
 	.vtripSel = 0UL,
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWDIO_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWDIO_PORT_NUM,
+		.channel_num = CYBSP_SWDIO_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config = 
 {
 	.outVal = 1,
@@ -369,58 +417,107 @@ const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config =
 	.intMask = 0UL,
 	.vtrip = CY_GPIO_VTRIP_CMOS,
 	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_FULL,
+	.driveSel = CY_GPIO_DRIVE_1_2,
 	.vregEn = 0UL,
 	.ibufMode = 0UL,
 	.vtripSel = 0UL,
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWCLK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWCLK_PORT_NUM,
+		.channel_num = CYBSP_SWCLK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_pins(void)
 {
 	Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_SW2_PORT, CYBSP_SW2_PIN, &CYBSP_SW2_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_ECO_IN_PORT, CYBSP_ECO_IN_PIN, &CYBSP_ECO_IN_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_ECO_IN_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_ECO_OUT_PORT, CYBSP_ECO_OUT_PIN, &CYBSP_ECO_OUT_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED3_PORT, CYBSP_LED3_PIN, &CYBSP_LED3_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_ECO_OUT_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED4_PORT, CYBSP_LED4_PIN, &CYBSP_LED4_config);
-
-	Cy_GPIO_Pin_Init(ioss_0_port_5_pin_0_PORT, ioss_0_port_5_pin_0_PIN, &ioss_0_port_5_pin_0_config);
-
-	Cy_GPIO_Pin_Init(ioss_0_port_5_pin_1_PORT, ioss_0_port_5_pin_1_PIN, &ioss_0_port_5_pin_1_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_I2C_SCL_PORT, CYBSP_I2C_SCL_PIN, &CYBSP_I2C_SCL_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_I2C_SCL_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_I2C_SDA_PORT, CYBSP_I2C_SDA_PIN, &CYBSP_I2C_SDA_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_I2C_SDA_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWCLK_PORT, CYBSP_SWCLK_PIN, &CYBSP_SWCLK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWCLK_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
index d6937cc557..3dff95f9a7 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
@@ -27,6 +27,9 @@
 
 #include "cycfg_notices.h"
 #include "cy_gpio.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 #include "cycfg_routing.h"
 
 #if defined(__cplusplus)
@@ -45,6 +48,18 @@ extern "C" {
 #endif
 #define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
 #define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
 #define CYBSP_WCO_OUT_ENABLED 1U
 #define CYBSP_WCO_OUT_PORT GPIO_PRT0
 #define CYBSP_WCO_OUT_PORT_NUM 0U
@@ -57,18 +72,18 @@ extern "C" {
 #endif
 #define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
 #define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_SW2_ENABLED 1U
-#define CYBSP_SW2_PORT GPIO_PRT0
-#define CYBSP_SW2_PORT_NUM 0U
-#define CYBSP_SW2_PIN 4U
-#define CYBSP_SW2_NUM 4U
-#define CYBSP_SW2_DRIVEMODE CY_GPIO_DM_PULLUP
-#define CYBSP_SW2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_4_HSIOM
-	#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SW2_HSIOM ioss_0_port_0_pin_4_HSIOM
-#define CYBSP_SW2_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
 #define CYBSP_QSPI_SS_ENABLED 1U
 #define CYBSP_QSPI_SS_PORT GPIO_PRT11
 #define CYBSP_QSPI_SS_PORT_NUM 11U
@@ -81,6 +96,18 @@ extern "C" {
 #endif
 #define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
 #define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
 #define CYBSP_QSPI_D3_ENABLED 1U
 #define CYBSP_QSPI_D3_PORT GPIO_PRT11
 #define CYBSP_QSPI_D3_PORT_NUM 11U
@@ -93,6 +120,18 @@ extern "C" {
 #endif
 #define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
 #define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_PORT_PIN P11_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
 #define CYBSP_QSPI_D2_ENABLED 1U
 #define CYBSP_QSPI_D2_PORT GPIO_PRT11
 #define CYBSP_QSPI_D2_PORT_NUM 11U
@@ -105,6 +144,18 @@ extern "C" {
 #endif
 #define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
 #define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_PORT_PIN P11_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
 #define CYBSP_QSPI_D1_ENABLED 1U
 #define CYBSP_QSPI_D1_PORT GPIO_PRT11
 #define CYBSP_QSPI_D1_PORT_NUM 11U
@@ -117,6 +168,18 @@ extern "C" {
 #endif
 #define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
 #define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_PORT_PIN P11_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
 #define CYBSP_QSPI_D0_ENABLED 1U
 #define CYBSP_QSPI_D0_PORT GPIO_PRT11
 #define CYBSP_QSPI_D0_PORT_NUM 11U
@@ -129,6 +192,18 @@ extern "C" {
 #endif
 #define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
 #define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_PORT_PIN P11_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
 #define CYBSP_QSPI_SCK_ENABLED 1U
 #define CYBSP_QSPI_SCK_PORT GPIO_PRT11
 #define CYBSP_QSPI_SCK_PORT_NUM 11U
@@ -141,6 +216,18 @@ extern "C" {
 #endif
 #define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
 #define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
 #define CYBSP_ECO_IN_ENABLED 1U
 #define CYBSP_ECO_IN_PORT GPIO_PRT12
 #define CYBSP_ECO_IN_PORT_NUM 12U
@@ -153,6 +240,18 @@ extern "C" {
 #endif
 #define CYBSP_ECO_IN_HSIOM ioss_0_port_12_pin_6_HSIOM
 #define CYBSP_ECO_IN_IRQ ioss_interrupts_gpio_12_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_ECO_IN_HAL_PORT_PIN P12_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_ECO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_ECO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_ECO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
 #define CYBSP_ECO_OUT_ENABLED 1U
 #define CYBSP_ECO_OUT_PORT GPIO_PRT12
 #define CYBSP_ECO_OUT_PORT_NUM 12U
@@ -165,18 +264,18 @@ extern "C" {
 #endif
 #define CYBSP_ECO_OUT_HSIOM ioss_0_port_12_pin_7_HSIOM
 #define CYBSP_ECO_OUT_IRQ ioss_interrupts_gpio_12_IRQn
-#define CYBSP_LED3_ENABLED 1U
-#define CYBSP_LED3_PORT GPIO_PRT13
-#define CYBSP_LED3_PORT_NUM 13U
-#define CYBSP_LED3_PIN 7U
-#define CYBSP_LED3_NUM 7U
-#define CYBSP_LED3_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_13_pin_7_HSIOM
-	#define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED3_HSIOM ioss_0_port_13_pin_7_HSIOM
-#define CYBSP_LED3_IRQ ioss_interrupts_gpio_13_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_ECO_OUT_HAL_PORT_PIN P12_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_ECO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_ECO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_ECO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
 #define CYBSP_USB_DP_ENABLED 1U
 #define CYBSP_USB_DP_PORT GPIO_PRT14
 #define CYBSP_USB_DP_PORT_NUM 14U
@@ -189,6 +288,18 @@ extern "C" {
 #endif
 #define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM
 #define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DP_HAL_PORT_PIN P14_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
 #define CYBSP_USB_DM_ENABLED 1U
 #define CYBSP_USB_DM_PORT GPIO_PRT14
 #define CYBSP_USB_DM_PORT_NUM 14U
@@ -201,40 +312,18 @@ extern "C" {
 #endif
 #define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM
 #define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn
-#define CYBSP_LED4_ENABLED 1U
-#define CYBSP_LED4_PORT GPIO_PRT1
-#define CYBSP_LED4_PORT_NUM 1U
-#define CYBSP_LED4_PIN 5U
-#define CYBSP_LED4_NUM 5U
-#define CYBSP_LED4_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED4_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_5_HSIOM
-	#define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED4_HSIOM ioss_0_port_1_pin_5_HSIOM
-#define CYBSP_LED4_IRQ ioss_interrupts_gpio_1_IRQn
-#define ioss_0_port_5_pin_0_ENABLED 1U
-#define ioss_0_port_5_pin_0_PORT GPIO_PRT5
-#define ioss_0_port_5_pin_0_PORT_NUM 5U
-#define ioss_0_port_5_pin_0_PIN 0U
-#define ioss_0_port_5_pin_0_NUM 0U
-#define ioss_0_port_5_pin_0_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define ioss_0_port_5_pin_0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_0_HSIOM
-	#define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define ioss_0_port_5_pin_0_IRQ ioss_interrupts_gpio_5_IRQn
-#define ioss_0_port_5_pin_1_ENABLED 1U
-#define ioss_0_port_5_pin_1_PORT GPIO_PRT5
-#define ioss_0_port_5_pin_1_PORT_NUM 5U
-#define ioss_0_port_5_pin_1_PIN 1U
-#define ioss_0_port_5_pin_1_NUM 1U
-#define ioss_0_port_5_pin_1_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define ioss_0_port_5_pin_1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_1_HSIOM
-	#define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define ioss_0_port_5_pin_1_IRQ ioss_interrupts_gpio_5_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DM_HAL_PORT_PIN P14_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
 #define CYBSP_I2C_SCL_ENABLED 1U
 #define CYBSP_I2C_SCL_PORT GPIO_PRT6
 #define CYBSP_I2C_SCL_PORT_NUM 6U
@@ -247,6 +336,18 @@ extern "C" {
 #endif
 #define CYBSP_I2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
 #define CYBSP_I2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_I2C_SCL_HAL_PORT_PIN P6_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_I2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_I2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_I2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
+#endif //defined (CY_USING_HAL)
 #define CYBSP_I2C_SDA_ENABLED 1U
 #define CYBSP_I2C_SDA_PORT GPIO_PRT6
 #define CYBSP_I2C_SDA_PORT_NUM 6U
@@ -259,8 +360,21 @@ extern "C" {
 #endif
 #define CYBSP_I2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
 #define CYBSP_I2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_I2C_SDA_HAL_PORT_PIN P6_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_I2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_I2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_I2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
+#endif //defined (CY_USING_HAL)
 #define CYBSP_SWO_ENABLED 1U
 #define CYBSP_SWO_PORT GPIO_PRT6
+#define CYBSP_SWO_PORT_NUM 6U
 #define CYBSP_SWO_PIN 4U
 #define CYBSP_SWO_NUM 4U
 #define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
@@ -270,8 +384,21 @@ extern "C" {
 #endif
 #define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
 #define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_PORT_PIN P6_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
 #define CYBSP_SWDIO_ENABLED 1U
 #define CYBSP_SWDIO_PORT GPIO_PRT6
+#define CYBSP_SWDIO_PORT_NUM 6U
 #define CYBSP_SWDIO_PIN 6U
 #define CYBSP_SWDIO_NUM 6U
 #define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
@@ -281,8 +408,21 @@ extern "C" {
 #endif
 #define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
 #define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
+#endif //defined (CY_USING_HAL)
 #define CYBSP_SWCLK_ENABLED 1U
 #define CYBSP_SWCLK_PORT GPIO_PRT6
+#define CYBSP_SWCLK_PORT_NUM 6U
 #define CYBSP_SWCLK_PIN 7U
 #define CYBSP_SWCLK_NUM 7U
 #define CYBSP_SWCLK_DRIVEMODE CY_GPIO_DM_PULLDOWN
@@ -292,29 +432,87 @@ extern "C" {
 #endif
 #define CYBSP_SWCLK_HSIOM ioss_0_port_6_pin_7_HSIOM
 #define CYBSP_SWCLK_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWCLK_HAL_PORT_PIN P6_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWCLK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWCLK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWCLK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
+#endif //defined (CY_USING_HAL)
 
 extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SW2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D3_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D2_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D1_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D0_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_ECO_IN_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_ECO_OUT_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USB_DP_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED4_config;
-extern const cy_stc_gpio_pin_config_t ioss_0_port_5_pin_0_config;
-extern const cy_stc_gpio_pin_config_t ioss_0_port_5_pin_1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USB_DM_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_I2C_SCL_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_I2C_SDA_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWO_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWCLK_obj;
+#endif //defined (CY_USING_HAL)
 
 void init_cycfg_pins(void);
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
index eff29bf693..4a64223055 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
@@ -40,8 +40,6 @@ void init_cycfg_routing(void);
 #define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
 #define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
 #define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
-#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
-#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
 #define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
 #define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
 #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
index b6c01928d4..663193f6ab 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
@@ -71,13 +71,53 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
 	.refDiv = 20U,
 	.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
 	.enableOutputDiv = true,
-	.lockTolerance = 10U,
+	.lockTolerance = 4U,
 	.igain = 9U,
 	.pgain = 5U,
 	.settlingCount = 8U,
 	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
 	.cco_Freq = 355U,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 1U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 2U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 3U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 4U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = 
 {
 	.feedbackDiv = 30,
@@ -501,4 +541,24 @@ void init_cycfg_system(void)
 	
 	/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
 	SystemCoreClockUpdate();
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
index 4bdd873358..f3da5da073 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
@@ -27,6 +27,9 @@
 
 #include "cycfg_notices.h"
 #include "cy_sysclk.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 #include "cy_gpio.h"
 #include "cy_syspm.h"
 
@@ -75,6 +78,22 @@ extern "C" {
 #define CY_CFG_PWR_VDDIO0_MV 3300
 #define CY_CFG_PWR_VDDIO1_MV 3300
 
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
+#endif //defined (CY_USING_HAL)
+
 void init_cycfg_system(void);
 
 #if defined(__cplusplus)
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
index 982f685fc4..866126ae96 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
@@ -1,18 +1,4 @@
-[Device="CYB06447BZI-D54"]
+[Device=CYB06447BZI-D54]
  
 [Blocks]
-# User IO
-# CYBSP_USER_LED1
-ioss[0].port[13].pin[7]
-# CYBSP_USER_LED2
-ioss[0].port[1].pin[5]
-# CYBSP_USER_BTN1
-ioss[0].port[0].pin[4]
-
-# Debug
-# CYBSP_DEBUG_UART
-scb[5]
-# CYBSP_DEBUG_UART_RX
-ioss[0].port[5].pin[0]
-# CYBSP_DEBUG_UART_TX
-ioss[0].port[5].pin[1]
+# Nothing needs to be reserved for this board
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi
new file mode 100644
index 0000000000..a4c24aff9c
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi
@@ -0,0 +1,63 @@
+<?xml version="1.0"?>
+<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
+<Configuration app="QSPI" major="2" minor="0">
+    <DevicePath>PSoC 6.xml</DevicePath>
+    <SlotConfigs>
+        <SlotConfig>
+            <SlaveSlot>0</SlaveSlot>
+            <PartNumber>S25FL128S</PartNumber>
+            <MemoryMapped>true</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18000000</StartAddress>
+            <Size>0x1000000</Size>
+            <EndAddress>0x18FFFFFF</EndAddress>
+            <WriteEnable>true</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
+            <MemoryConfigsPath>S25FL128S</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>1</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18010000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1801FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>2</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18020000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1802FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>3</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18030000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1803FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+    </SlotConfigs>
+</Configuration>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus
index ad8992850d..460fe57995 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus
@@ -28,16 +28,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[0].pin[4]" alias="CYBSP_SW2" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
                     <Param id="initialState" value="1"/>
@@ -118,16 +108,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[13].pin[7]" alias="CYBSP_LED3" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[14].pin[0]" alias="CYBSP_USB_DP" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                     <Param id="initialState" value="1"/>
@@ -148,36 +128,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[1].pin[5]" alias="CYBSP_LED4" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[5].pin[0]" alias="" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[5].pin[1]" alias="" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[6].pin[0]" alias="CYBSP_I2C_SCL" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
                     <Param id="initialState" value="1"/>
@@ -228,16 +178,11 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="peri[0].div_16[0]" alias="" template="mxs40peripheralclock" version="1.0">
+                <Block location="peri[0].div_16[0]" alias="CYBSP_USB_CLK_DIV" template="mxs40peripheralclock" version="1.0">
                     <Param id="intDivider" value="500"/>
                     <Param id="fracDivider" value="0"/>
                     <Param id="startOnReset" value="true"/>
                 </Block>
-                <Block location="peri[0].div_8[0]" alias="CYBSP_DEBUG_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
-                    <Param id="intDivider" value="36"/>
-                    <Param id="fracDivider" value="0"/>
-                    <Param id="startOnReset" value="true"/>
-                </Block>
                 <Block location="peri[0].div_8[1]" alias="CYBSP_I2C_CLK_DIV" template="mxs40peripheralclock" version="1.0">
                     <Param id="intDivider" value="4"/>
                     <Param id="fracDivider" value="0"/>
@@ -252,51 +197,6 @@
                     <Param id="EnableWakeup" value="false"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="scb[5]" alias="CYBSP_DEBUG_UART" template="mxs40uart" version="1.0">
-                    <Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
-                    <Param id="IrdaLowPower" value="false"/>
-                    <Param id="BaudRate" value="115200"/>
-                    <Param id="Oversample" value="12"/>
-                    <Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
-                    <Param id="DataWidth" value="8"/>
-                    <Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
-                    <Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
-                    <Param id="EnableInputFilter" value="false"/>
-                    <Param id="EnableTxEn" value="false"/>
-                    <Param id="FlowControl" value="false"/>
-                    <Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
-                    <Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
-                    <Param id="RtsTriggerLevel" value="63"/>
-                    <Param id="RxTriggerLevel" value="63"/>
-                    <Param id="TxTriggerLevel" value="63"/>
-                    <Param id="MultiProc" value="false"/>
-                    <Param id="MpRxAddress" value="0"/>
-                    <Param id="MpRxAddressMask" value="255"/>
-                    <Param id="MpRxAcceptAddress" value="false"/>
-                    <Param id="DropOnFrameErr" value="false"/>
-                    <Param id="DropOnParityErr" value="false"/>
-                    <Param id="BreakSignalBits" value="11"/>
-                    <Param id="SmCardRetryOnNack" value="false"/>
-                    <Param id="IrdaPolarity" value="NON_INVERTING"/>
-                    <Param id="inFlash" value="true"/>
-                    <Param id="ApiMode" value="HIGH_LEVEL"/>
-                    <Param id="IntrRxNotEmpty" value="false"/>
-                    <Param id="IntrRxFull" value="false"/>
-                    <Param id="IntrRxOverflow" value="false"/>
-                    <Param id="IntrRxUnderflow" value="false"/>
-                    <Param id="IntrRxFrameErr" value="false"/>
-                    <Param id="IntrRxParityErr" value="false"/>
-                    <Param id="IntrRxBreakDetected" value="false"/>
-                    <Param id="IntrRxTrigger" value="false"/>
-                    <Param id="IntrTxUartDone" value="false"/>
-                    <Param id="IntrTxUartLostArb" value="false"/>
-                    <Param id="IntrTxUartNack" value="false"/>
-                    <Param id="IntrTxEmpty" value="false"/>
-                    <Param id="IntrTxNotFull" value="false"/>
-                    <Param id="IntrTxOverflow" value="false"/>
-                    <Param id="IntrTxUnderflow" value="false"/>
-                    <Param id="IntrTxTrigger" value="false"/>
-                </Block>
                 <Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
                     <Param id="configurator" value="0"/>
                     <Param id="isrAlignment" value="false"/>
@@ -334,7 +234,7 @@
                     <Param id="hibernate" value="true"/>
                 </Block>
                 <Block location="srss[0].clock[0].imo[0]" alias="" template="mxs40imo" version="1.0">
-                    <Param id="trim" value="1"/>
+                    <Param id="trim" value="0.25"/>
                 </Block>
                 <Block location="srss[0].clock[0].lfclk[0]" alias="" template="mxs40lfclk" version="1.1">
                     <Param id="sourceClock" value="wco"/>
@@ -375,7 +275,6 @@
                     <Param id="accuracyPpm" value="150"/>
                 </Block>
                 <Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
-                    <Param id="pwrEstimator" value="0"/>
                     <Param id="pwrMode" value="LDO_1_1"/>
                     <Param id="actPwrMode" value="LP"/>
                     <Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
@@ -390,6 +289,27 @@
                     <Param id="vddio0Mv" value="3300"/>
                     <Param id="vddio1Mv" value="3300"/>
                 </Block>
+                <Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.1">
+                    <Param id="epMask" value="0"/>
+                    <Param id="mngMode" value="CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU"/>
+                    <Param id="bufSize" value="512"/>
+                    <Param id="epAccess" value="CY_USBFS_DEV_DRV_USE_8_BITS_DR"/>
+                    <Param id="enableLpm" value="false"/>
+                    <Param id="lpmIntr" value="0x0U"/>
+                    <Param id="ArbIntr" value="0x0U"/>
+                    <Param id="ep0CntrIntr" value="0x2U"/>
+                    <Param id="busResetIntr" value="0x2U"/>
+                    <Param id="sofIntr" value="0x1U"/>
+                    <Param id="ep0Intr" value="0x1U"/>
+                    <Param id="ep1Intr" value="0x1U"/>
+                    <Param id="ep2Intr" value="0x1U"/>
+                    <Param id="ep3Intr" value="0x1U"/>
+                    <Param id="ep4Intr" value="0x1U"/>
+                    <Param id="ep5Intr" value="0x1U"/>
+                    <Param id="ep6Intr" value="0x1U"/>
+                    <Param id="ep7Intr" value="0x1U"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
             </BlockConfig>
             <Netlist>
                 <Net>
@@ -412,14 +332,6 @@
                     <Port name="ioss[0].port[0].pin[1].analog[0]"/>
                     <Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
                 </Net>
-                <Net>
-                    <Port name="ioss[0].port[5].pin[0].digital_inout[0]"/>
-                    <Port name="scb[5].uart_rx[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[5].pin[1].digital_inout[0]"/>
-                    <Port name="scb[5].uart_tx[0]"/>
-                </Net>
                 <Net>
                     <Port name="ioss[0].port[6].pin[0].digital_inout[0]"/>
                     <Port name="scb[3].i2c_scl[0]"/>
@@ -453,8 +365,16 @@
                     <Port name="smif[0].spi_clk[0]"/>
                 </Net>
                 <Net>
-                    <Port name="peri[0].div_8[0].clk[0]"/>
-                    <Port name="scb[5].clock[0]"/>
+                    <Port name="ioss[0].port[14].pin[0].aux[0]"/>
+                    <Port name="usb[0].usb_dp_pad[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[14].pin[1].aux[0]"/>
+                    <Port name="usb[0].usb_dm_pad[0]"/>
+                </Net>
+                <Net>
+                    <Port name="peri[0].div_16[0].clk[0]"/>
+                    <Port name="usb[0].clock_dev_brs[0]"/>
                 </Net>
                 <Net>
                     <Port name="peri[0].div_8[1].clk[0]"/>
@@ -468,11 +388,13 @@
                     <Port name="smif[0].clk_if[0]"/>
                     <Port name="srss[0].clock[0].hfclk[2].root_clk[0]"/>
                 </Net>
+                <Net>
+                    <Port name="srss[0].clock[0].hfclk[3].root_clk[0]"/>
+                    <Port name="usb[0].clk_usb_dev[0]"/>
+                </Net>
             </Netlist>
         </Device>
     </Devices>
-    <Libraries>
-        <Library name="psoc6sw" version="1.2"/>
-    </Libraries>
+    <Libraries/>
     <ConfiguratorData/>
 </Design>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
index cda6d4025b..cb430a4164 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
@@ -28,7 +28,6 @@ void init_cycfg_all(void)
 {
 	init_cycfg_system();
 	init_cycfg_clocks();
-	init_cycfg_dmas();
 	init_cycfg_routing();
 	init_cycfg_peripherals();
 	init_cycfg_pins();
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
index 3585cf91ba..9abc7f0f4a 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
@@ -32,7 +32,6 @@ extern "C" {
 #include "cycfg_notices.h"
 #include "cycfg_system.h"
 #include "cycfg_clocks.h"
-#include "cycfg_dmas.h"
 #include "cycfg_routing.h"
 #include "cycfg_peripherals.h"
 #include "cycfg_pins.h"
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
index 54d1df91cb..6a19f39283 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
@@ -25,19 +25,11 @@
 #include "cycfg_clocks.h"
 
 #if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_USB_UART_CLK_DIV_obj = 
+	const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj = 
 	{
 		.type = CYHAL_RSC_CLOCK,
-		.block_num = CYBSP_USB_UART_CLK_DIV_HW,
-		.channel_num = CYBSP_USB_UART_CLK_DIV_NUM,
-	};
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_SDIO_CLK_DIV_obj = 
-	{
-		.type = CYHAL_RSC_CLOCK,
-		.block_num = CYBSP_SDIO_CLK_DIV_HW,
-		.channel_num = CYBSP_SDIO_CLK_DIV_NUM,
+		.block_num = CYBSP_USB_CLK_DIV_HW,
+		.channel_num = CYBSP_USB_CLK_DIV_NUM,
 	};
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
@@ -49,11 +41,11 @@
 	};
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t peri_0_div_8_3_obj = 
+	const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj = 
 	{
 		.type = CYHAL_RSC_CLOCK,
-		.block_num = peri_0_div_8_3_HW,
-		.channel_num = peri_0_div_8_3_NUM,
+		.block_num = CYBSP_BT_UART_CLK_DIV_HW,
+		.channel_num = CYBSP_BT_UART_CLK_DIV_NUM,
 	};
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
@@ -88,14 +80,7 @@ void init_cycfg_clocks(void)
 	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
 #if defined (CY_USING_HAL)
-		cyhal_hwmgr_reserve(&CYBSP_USB_UART_CLK_DIV_obj);
-#endif //defined (CY_USING_HAL)
-
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
-#if defined (CY_USING_HAL)
-		cyhal_hwmgr_reserve(&CYBSP_SDIO_CLK_DIV_obj);
+		cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj);
 #endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
@@ -109,7 +94,7 @@ void init_cycfg_clocks(void)
 	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 108U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
 #if defined (CY_USING_HAL)
-		cyhal_hwmgr_reserve(&peri_0_div_8_3_obj);
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj);
 #endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
index c1e5915eb0..3c26bd3bb7 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
@@ -35,18 +35,15 @@
 extern "C" {
 #endif
 
-#define CYBSP_USB_UART_CLK_DIV_ENABLED 1U
-#define CYBSP_USB_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
-#define CYBSP_USB_UART_CLK_DIV_NUM 0U
-#define CYBSP_SDIO_CLK_DIV_ENABLED 1U
-#define CYBSP_SDIO_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
-#define CYBSP_SDIO_CLK_DIV_NUM 0U
+#define CYBSP_USB_CLK_DIV_ENABLED 1U
+#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
+#define CYBSP_USB_CLK_DIV_NUM 0U
 #define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
 #define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
-#define peri_0_div_8_3_ENABLED 1U
-#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_3_NUM 3U
+#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
+#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_BT_UART_CLK_DIV_NUM 3U
 #define CYBSP_CSD_CLK_DIV_ENABLED 1U
 #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_CSD_CLK_DIV_NUM 4U
@@ -58,16 +55,13 @@ extern "C" {
 #define CYBSP_WL_UART_CLK_DIV_NUM 6U
 
 #if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_USB_UART_CLK_DIV_obj;
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_SDIO_CLK_DIV_obj;
+	extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj;
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t peri_0_div_8_3_obj;
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c
deleted file mode 100644
index 8d86919551..0000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_dmas.c
-*
-* Description:
-* DMA configuration
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_dmas.h"
-
-const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config = 
-{
-	.retrigger = CY_DMA_RETRIG_IM,
-	.interruptType = CY_DMA_1ELEMENT,
-	.triggerOutType = CY_DMA_1ELEMENT,
-	.channelState = CY_DMA_CHANNEL_DISABLED,
-	.triggerInType = CY_DMA_1ELEMENT,
-	.dataSize = CY_DMA_BYTE,
-	.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
-	.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
-	.descriptorType = CY_DMA_1D_TRANSFER,
-	.srcAddress = NULL,
-	.dstAddress = NULL,
-	.srcXincrement = 0,
-	.dstXincrement = 1,
-	.xCount = 6,
-	.srcYincrement = 0,
-	.dstYincrement = 0,
-	.yCount = 1,
-	.nextDescriptor = NULL,
-};
-cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0 = 
-{
-	.ctl = 0UL,
-	.src = 0UL,
-	.dst = 0UL,
-	.xCtl = 0UL,
-	.yCtl = 0UL,
-	.nextPtr = 0UL,
-};
-const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig = 
-{
-	.descriptor = &cpuss_0_dw0_0_chan_0_Descriptor_0,
-	.preemptable = true,
-	.priority = 1,
-	.enable = false,
-	.bufferable = false,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj = 
-	{
-		.type = CYHAL_RSC_DMA,
-		.block_num = 0U,
-		.channel_num = cpuss_0_dw0_0_chan_0_CHANNEL,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config = 
-{
-	.retrigger = CY_DMA_RETRIG_16CYC,
-	.interruptType = CY_DMA_1ELEMENT,
-	.triggerOutType = CY_DMA_1ELEMENT,
-	.channelState = CY_DMA_CHANNEL_DISABLED,
-	.triggerInType = CY_DMA_1ELEMENT,
-	.dataSize = CY_DMA_BYTE,
-	.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
-	.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
-	.descriptorType = CY_DMA_1D_TRANSFER,
-	.srcAddress = NULL,
-	.dstAddress = NULL,
-	.srcXincrement = 1,
-	.dstXincrement = 0,
-	.xCount = 5,
-	.srcYincrement = 0,
-	.dstYincrement = 0,
-	.yCount = 1,
-	.nextDescriptor = NULL,
-};
-cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0 = 
-{
-	.ctl = 0UL,
-	.src = 0UL,
-	.dst = 0UL,
-	.xCtl = 0UL,
-	.yCtl = 0UL,
-	.nextPtr = 0UL,
-};
-const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig = 
-{
-	.descriptor = &cpuss_0_dw0_0_chan_1_Descriptor_0,
-	.preemptable = true,
-	.priority = 1,
-	.enable = false,
-	.bufferable = false,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj = 
-	{
-		.type = CYHAL_RSC_DMA,
-		.block_num = 0U,
-		.channel_num = cpuss_0_dw0_0_chan_1_CHANNEL,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config = 
-{
-	.retrigger = CY_DMA_RETRIG_4CYC,
-	.interruptType = CY_DMA_DESCR,
-	.triggerOutType = CY_DMA_1ELEMENT,
-	.channelState = CY_DMA_CHANNEL_DISABLED,
-	.triggerInType = CY_DMA_X_LOOP,
-	.dataSize = CY_DMA_HALFWORD,
-	.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
-	.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
-	.descriptorType = CY_DMA_2D_TRANSFER,
-	.srcAddress = NULL,
-	.dstAddress = NULL,
-	.srcXincrement = 2,
-	.dstXincrement = 0,
-	.xCount = 10,
-	.srcYincrement = 10,
-	.dstYincrement = 0,
-	.yCount = 2,
-	.nextDescriptor = NULL,
-};
-cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0 = 
-{
-	.ctl = 0UL,
-	.src = 0UL,
-	.dst = 0UL,
-	.xCtl = 0UL,
-	.yCtl = 0UL,
-	.nextPtr = 0UL,
-};
-const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig = 
-{
-	.descriptor = &cpuss_0_dw1_0_chan_1_Descriptor_0,
-	.preemptable = false,
-	.priority = 0,
-	.enable = false,
-	.bufferable = false,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj = 
-	{
-		.type = CYHAL_RSC_DMA,
-		.block_num = 1U,
-		.channel_num = cpuss_0_dw1_0_chan_1_CHANNEL,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config = 
-{
-	.retrigger = CY_DMA_RETRIG_IM,
-	.interruptType = CY_DMA_DESCR,
-	.triggerOutType = CY_DMA_1ELEMENT,
-	.channelState = CY_DMA_CHANNEL_DISABLED,
-	.triggerInType = CY_DMA_X_LOOP,
-	.dataSize = CY_DMA_HALFWORD,
-	.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
-	.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
-	.descriptorType = CY_DMA_2D_TRANSFER,
-	.srcAddress = NULL,
-	.dstAddress = NULL,
-	.srcXincrement = 0,
-	.dstXincrement = 2,
-	.xCount = 10,
-	.srcYincrement = 0,
-	.dstYincrement = 10,
-	.yCount = 2,
-	.nextDescriptor = NULL,
-};
-cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0 = 
-{
-	.ctl = 0UL,
-	.src = 0UL,
-	.dst = 0UL,
-	.xCtl = 0UL,
-	.yCtl = 0UL,
-	.nextPtr = 0UL,
-};
-const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig = 
-{
-	.descriptor = &cpuss_0_dw1_0_chan_3_Descriptor_0,
-	.preemptable = false,
-	.priority = 0,
-	.enable = false,
-	.bufferable = false,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj = 
-	{
-		.type = CYHAL_RSC_DMA,
-		.block_num = 1U,
-		.channel_num = cpuss_0_dw1_0_chan_3_CHANNEL,
-	};
-#endif //defined (CY_USING_HAL)
-
-
-void init_cycfg_dmas(void)
-{
-#if defined (CY_USING_HAL)
-		cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_0_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-		cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_1_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-		cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_1_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-		cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_3_obj);
-#endif //defined (CY_USING_HAL)
-}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h
deleted file mode 100644
index d6c0d6587d..0000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_dmas.h
-*
-* Description:
-* DMA configuration
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_DMAS_H)
-#define CYCFG_DMAS_H
-
-#include "cycfg_notices.h"
-#include "cy_dma.h"
-#if defined (CY_USING_HAL)
-	#include "cyhal_hwmgr.h"
-#endif //defined (CY_USING_HAL)
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define cpuss_0_dw0_0_chan_0_ENABLED 1U
-#define cpuss_0_dw0_0_chan_0_HW DW0
-#define cpuss_0_dw0_0_chan_0_CHANNEL 0U
-#define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn
-#define cpuss_0_dw0_0_chan_1_ENABLED 1U
-#define cpuss_0_dw0_0_chan_1_HW DW0
-#define cpuss_0_dw0_0_chan_1_CHANNEL 1U
-#define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn
-#define cpuss_0_dw1_0_chan_1_ENABLED 1U
-#define cpuss_0_dw1_0_chan_1_HW DW1
-#define cpuss_0_dw1_0_chan_1_CHANNEL 1U
-#define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn
-#define cpuss_0_dw1_0_chan_3_ENABLED 1U
-#define cpuss_0_dw1_0_chan_3_HW DW1
-#define cpuss_0_dw1_0_chan_3_CHANNEL 3U
-#define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn
-
-extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config;
-extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0;
-extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config;
-extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0;
-extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config;
-extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0;
-extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config;
-extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0;
-extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj;
-#endif //defined (CY_USING_HAL)
-
-void init_cycfg_dmas(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_DMAS_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
index d02d6fc904..201696099e 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
@@ -123,9 +123,8 @@ extern "C" {
 #define CYBSP_RTC_YEAR_OFFSET (0U)
 #define CYBSP_USBUART_ENABLED 1U
 #define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 7U
-#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 140U
+#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
 #define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
-#define CYBSP_USBUART_USB_CORE 4U
 #define CYBSP_USBUART_HW USBFS0
 #define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
 #define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
index c4e5bcf916..14d433859d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
@@ -24,7 +24,7 @@
 
 #include "cycfg_qspi_memslot.h"
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0xECU,
@@ -42,7 +42,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x06U,
@@ -60,7 +60,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x04U,
@@ -78,7 +78,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0xDCU,
@@ -96,7 +96,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x60U,
@@ -114,7 +114,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x34U,
@@ -132,7 +132,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x35U,
@@ -150,7 +150,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x05U,
@@ -168,7 +168,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x01U,
@@ -186,34 +186,34 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
+const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 =
 {
     /* Specifies the number of address bytes used by the memory slave device. */
     .numOfAddrBytes = 0x04U,
     /* The size of the memory. */
     .memSize = 0x04000000U,
     /* Specifies the Read command. */
-    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
+    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd,
     /* Specifies the Write Enable command. */
-    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
+    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd,
     /* Specifies the Write Disable command. */
-    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
+    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd,
     /* Specifies the Erase command. */
-    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
+    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd,
     /* Specifies the sector size of each erase. */
     .eraseSize = 0x00040000U,
     /* Specifies the Chip Erase command. */
-    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
+    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd,
     /* Specifies the Program command. */
-    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
+    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd,
     /* Specifies the page size for programming. */
     .programSize = 0x00000200U,
     /* Specifies the command to read the QE-containing status register. */
-    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
+    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd,
     /* Specifies the command to read the WIP-containing status register. */
-    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
+    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd,
     /* Specifies the command to write into the QE-containing status register. */
-    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
+    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
     /* The mask for the status register. */
     .stsRegBusyMask = 0x01U,
     /* The mask for the status register. */
@@ -226,7 +226,7 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
     .programTime = 1300U
 };
 
-const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
+const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 =
 {
     /* Determines the slot number where the memory device is placed. */
     .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
@@ -244,11 +244,11 @@ const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
     Valid when the memory mapped mode is enabled. */
     .dualQuadSlots = 0,
     /* The configuration of the device. */
-    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
+    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0
 };
 
 const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
-   &S25FL512SX4byteaddr_SlaveSlot_0
+   &S25FL512S_4byteaddr_SlaveSlot_0
 };
 
 const cy_stc_smif_block_config_t smifBlockConfig =
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
index 32f9b49b2e..0ee62b1d55 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
@@ -28,19 +28,19 @@
 
 #define CY_SMIF_DEVICE_NUM 1
 
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
 
-extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
+extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0;
 
-extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
+extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0;
 extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
 
 extern const cy_stc_smif_block_config_t smifBlockConfig;
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
index a055be07d2..a8490a965d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
@@ -1,27 +1,14 @@
-[Device="CY8C6247BZI-D54"]
+[Device=CY8C6247BZI-D54]
  
 [Blocks]
-# User IO
-# CYBSP_USER_LED1
-ioss[0].port[0].pin[3]
-# CYBSP_USER_LED2
-ioss[0].port[1].pin[1]
-# CYBSP_USER_LED3
-ioss[0].port[10].pin[6]
-# CYBSP_USER_BTN1
-ioss[0].port[0].pin[4]
-
-# Debug
-# CYBSP_DEBUG_UART
-scb[6]
-# CYBSP_DEBUG_UART_RX
-ioss[0].port[13].pin[0]
-# CYBSP_DEBUG_UART_TX
-ioss[0].port[13].pin[1]
-
 # WIFI
 # CYBSP_WIFI_SDIO
 udb[0]
+peri[0].div_8[0]
+cpuss[0].dw0[0].chan[0]
+cpuss[0].dw0[0].chan[1]
+cpuss[0].dw1[0].chan[1]
+cpuss[0].dw1[0].chan[3]
 # CYBSP_WIFI_SDIO_D0
 ioss[0].port[2].pin[0]
 # CYBSP_WIFI_SDIO_D1
@@ -35,4 +22,21 @@ ioss[0].port[2].pin[4]
 # CYBSP_WIFI_SDIO_CLK
 ioss[0].port[2].pin[5]
 # CYBSP_WIFI_WL_REG_ON
-ioss[0].port[2].pin[6]
\ No newline at end of file
+ioss[0].port[2].pin[6]
+
+[RoutingResources]
+# CYBSP_WIFI_SDIO
+cpuss[0].dw0_tr_in[0] 
+cpuss[0].dw0_tr_in[1] 
+cpuss[0].dw1_tr_in[1] 
+cpuss[0].dw1_tr_in[3] 
+
+udb[0].tr_udb[0] 
+udb[0].tr_udb[1] 
+udb[0].tr_udb[3] 
+udb[0].tr_udb[7] 
+
+tr_group[0].input[43] 
+tr_group[0].input[44] 
+tr_group[0].input[47] 
+tr_group[0].input[48] 
\ No newline at end of file
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus
index 6bc9933317..6ded06e121 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus
@@ -8,114 +8,6 @@
                     <Param id="dbgMode" value="SWD"/>
                     <Param id="traceEnable" value="true"/>
                 </Block>
-                <Block location="cpuss[0].dw0[0].chan[0]" alias="" template="mxs40dma" version="1.0">
-                    <Param id="CRC_DATA_REVERSE" value="false"/>
-                    <Param id="CRC_DATA_XOR" value="0"/>
-                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
-                    <Param id="CRC_REMINDER_XOR" value="0"/>
-                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
-                    <Param id="CHANNEL_PRIORITY" value="1"/>
-                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
-                    <Param id="PREEMPTABLE" value="true"/>
-                    <Param id="BUFFERABLE" value="false"/>
-                    <Param id="DESCR_SELECTION" value="0"/>
-                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="INTR_OUT_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="ENABLE_CHAINING_0" value="false"/>
-                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
-                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_IM"/>
-                    <Param id="DATA_TRANSFER_WIDTH_0" value="ByteToByte"/>
-                    <Param id="X_NUM_OF_ELEMENTS_0" value="6"/>
-                    <Param id="X_SRC_INCREMENT_0" value="0"/>
-                    <Param id="X_DST_INCREMENT_0" value="1"/>
-                    <Param id="CRC_0" value="false"/>
-                    <Param id="Y_NUM_OF_ELEMENTS_0" value="1"/>
-                    <Param id="Y_SRC_INCREMENT_0" value="0"/>
-                    <Param id="Y_DST_INCREMENT_0" value="0"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="cpuss[0].dw0[0].chan[1]" alias="" template="mxs40dma" version="1.0">
-                    <Param id="CRC_DATA_REVERSE" value="false"/>
-                    <Param id="CRC_DATA_XOR" value="0"/>
-                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
-                    <Param id="CRC_REMINDER_XOR" value="0"/>
-                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
-                    <Param id="CHANNEL_PRIORITY" value="1"/>
-                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
-                    <Param id="PREEMPTABLE" value="true"/>
-                    <Param id="BUFFERABLE" value="false"/>
-                    <Param id="DESCR_SELECTION" value="0"/>
-                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="INTR_OUT_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="ENABLE_CHAINING_0" value="false"/>
-                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
-                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_16CYC"/>
-                    <Param id="DATA_TRANSFER_WIDTH_0" value="ByteToByte"/>
-                    <Param id="X_NUM_OF_ELEMENTS_0" value="5"/>
-                    <Param id="X_SRC_INCREMENT_0" value="1"/>
-                    <Param id="X_DST_INCREMENT_0" value="0"/>
-                    <Param id="CRC_0" value="false"/>
-                    <Param id="Y_NUM_OF_ELEMENTS_0" value="1"/>
-                    <Param id="Y_SRC_INCREMENT_0" value="0"/>
-                    <Param id="Y_DST_INCREMENT_0" value="0"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="cpuss[0].dw1[0].chan[1]" alias="" template="mxs40dma" version="1.0">
-                    <Param id="CRC_DATA_REVERSE" value="false"/>
-                    <Param id="CRC_DATA_XOR" value="0"/>
-                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
-                    <Param id="CRC_REMINDER_XOR" value="0"/>
-                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
-                    <Param id="CHANNEL_PRIORITY" value="0"/>
-                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
-                    <Param id="PREEMPTABLE" value="false"/>
-                    <Param id="BUFFERABLE" value="false"/>
-                    <Param id="DESCR_SELECTION" value="0"/>
-                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="INTR_OUT_0" value="CY_DMA_DESCR"/>
-                    <Param id="ENABLE_CHAINING_0" value="false"/>
-                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
-                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_X_LOOP"/>
-                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_4CYC"/>
-                    <Param id="DATA_TRANSFER_WIDTH_0" value="HalfwordToHalfword"/>
-                    <Param id="X_NUM_OF_ELEMENTS_0" value="10"/>
-                    <Param id="X_SRC_INCREMENT_0" value="2"/>
-                    <Param id="X_DST_INCREMENT_0" value="0"/>
-                    <Param id="CRC_0" value="false"/>
-                    <Param id="Y_NUM_OF_ELEMENTS_0" value="2"/>
-                    <Param id="Y_SRC_INCREMENT_0" value="10"/>
-                    <Param id="Y_DST_INCREMENT_0" value="0"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="cpuss[0].dw1[0].chan[3]" alias="" template="mxs40dma" version="1.0">
-                    <Param id="CRC_DATA_REVERSE" value="false"/>
-                    <Param id="CRC_DATA_XOR" value="0"/>
-                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
-                    <Param id="CRC_REMINDER_XOR" value="0"/>
-                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
-                    <Param id="CHANNEL_PRIORITY" value="0"/>
-                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
-                    <Param id="PREEMPTABLE" value="false"/>
-                    <Param id="BUFFERABLE" value="false"/>
-                    <Param id="DESCR_SELECTION" value="0"/>
-                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="INTR_OUT_0" value="CY_DMA_DESCR"/>
-                    <Param id="ENABLE_CHAINING_0" value="false"/>
-                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
-                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_X_LOOP"/>
-                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_IM"/>
-                    <Param id="DATA_TRANSFER_WIDTH_0" value="HalfwordToHalfword"/>
-                    <Param id="X_NUM_OF_ELEMENTS_0" value="10"/>
-                    <Param id="X_SRC_INCREMENT_0" value="0"/>
-                    <Param id="X_DST_INCREMENT_0" value="2"/>
-                    <Param id="CRC_0" value="false"/>
-                    <Param id="Y_NUM_OF_ELEMENTS_0" value="2"/>
-                    <Param id="Y_SRC_INCREMENT_0" value="0"/>
-                    <Param id="Y_DST_INCREMENT_0" value="10"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="csd[0].csd[0]" alias="CYBSP_CapSense" template="mxs40csd" version="2.0">
                     <Param id="CapSenseEnable" value="true"/>
                     <Param id="CapSenseCore" value="4"/>
@@ -762,22 +654,17 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="peri[0].div_16[0]" alias="CYBSP_USB_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
+                <Block location="peri[0].div_16[0]" alias="CYBSP_USB_CLK_DIV" template="mxs40peripheralclock" version="1.0">
                     <Param id="intDivider" value="1000"/>
                     <Param id="fracDivider" value="0"/>
                     <Param id="startOnReset" value="true"/>
                 </Block>
-                <Block location="peri[0].div_8[0]" alias="CYBSP_SDIO_CLK_DIV" template="mxs40peripheralclock" version="1.0">
-                    <Param id="intDivider" value="1"/>
-                    <Param id="fracDivider" value="0"/>
-                    <Param id="startOnReset" value="true"/>
-                </Block>
                 <Block location="peri[0].div_8[1]" alias="CYBSP_CSD_COMM_CLK_DIV" template="mxs40peripheralclock" version="1.0">
                     <Param id="intDivider" value="8"/>
                     <Param id="fracDivider" value="0"/>
                     <Param id="startOnReset" value="true"/>
                 </Block>
-                <Block location="peri[0].div_8[3]" alias="" template="mxs40peripheralclock" version="1.0">
+                <Block location="peri[0].div_8[3]" alias="CYBSP_BT_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
                     <Param id="intDivider" value="109"/>
                     <Param id="fracDivider" value="0"/>
                     <Param id="startOnReset" value="true"/>
@@ -1041,7 +928,6 @@
                     <Param id="inFlash" value="true"/>
                 </Block>
                 <Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
-                    <Param id="pwrEstimator" value="0"/>
                     <Param id="pwrMode" value="LDO_1_1"/>
                     <Param id="actPwrMode" value="LP"/>
                     <Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
@@ -1081,12 +967,10 @@
                     <Param id="dstStopHour" value="0"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.0">
-                    <Param id="configurator" value=""/>
-                    <Param id="UsbCore" value="4"/>
+                <Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.1">
                     <Param id="epMask" value="7"/>
-                    <Param id="bufSize" value="140"/>
                     <Param id="mngMode" value="CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU"/>
+                    <Param id="bufSize" value="140"/>
                     <Param id="epAccess" value="CY_USBFS_DEV_DRV_USE_8_BITS_DR"/>
                     <Param id="enableLpm" value="false"/>
                     <Param id="lpmIntr" value="0x0U"/>
@@ -1246,6 +1130,14 @@
                     <Port name="peri[0].div_8[3].clk[0]"/>
                     <Port name="scb[2].clock[0]"/>
                 </Net>
+                <Net>
+                    <Port name="peri[0].div_8[5].clk[0]"/>
+                    <Port name="scb[1].clock[0]"/>
+                </Net>
+                <Net>
+                    <Port name="peri[0].div_8[6].clk[0]"/>
+                    <Port name="scb[5].clock[0]"/>
+                </Net>
                 <Net>
                     <Port name="smif[0].clk_hf[0]"/>
                     <Port name="srss[0].clock[0].hfclk[0].root_clk[0]"/>
@@ -1303,8 +1195,6 @@
             <Netlist/>
         </Device>
     </Devices>
-    <Libraries>
-        <Library name="psoc6sw" version="1.2"/>
-    </Libraries>
+    <Libraries/>
     <ConfiguratorData/>
 </Design>