mirror of https://github.com/ARMmbed/mbed-os.git
Merge remote-tracking branch 'upstream/master'
Martin Olejar
commit
f0586081ee
|
|
@ -78,6 +78,7 @@ STMicroelectronics:
|
||||||
Nordic:
|
Nordic:
|
||||||
* [nRF51822-mKIT](https://developer.mbed.org/platforms/Nordic-nRF51822/) (Cortex-M0)
|
* [nRF51822-mKIT](https://developer.mbed.org/platforms/Nordic-nRF51822/) (Cortex-M0)
|
||||||
* [Arch BLE](https://developer.mbed.org/platforms/Seeed-Arch-BLE/) (Cortex-M0)
|
* [Arch BLE](https://developer.mbed.org/platforms/Seeed-Arch-BLE/) (Cortex-M0)
|
||||||
|
|
||||||
Supported Toolchains and IDEs
|
Supported Toolchains and IDEs
|
||||||
-----------------------------
|
-----------------------------
|
||||||
* GCC ARM: [GNU Tools for ARM Embedded Processors](https://launchpad.net/gcc-arm-embedded/4.7/4.7-2012-q4-major)
|
* GCC ARM: [GNU Tools for ARM Embedded Processors](https://launchpad.net/gcc-arm-embedded/4.7/4.7-2012-q4-major)
|
||||||
|
|
@ -85,8 +86,8 @@ Supported Toolchains and IDEs
|
||||||
* IAR: [IAR Embedded Workbench](http://www.iar.com/en/Products/IAR-Embedded-Workbench/ARM/)
|
* IAR: [IAR Embedded Workbench](http://www.iar.com/en/Products/IAR-Embedded-Workbench/ARM/)
|
||||||
* GCC code_red: [Red Suite](http://www.code-red-tech.com/)
|
* GCC code_red: [Red Suite](http://www.code-red-tech.com/)
|
||||||
* GCC CodeSourcery: [Sourcery CodeBench](http://www.mentor.com/embedded-software/codesourcery)
|
* GCC CodeSourcery: [Sourcery CodeBench](http://www.mentor.com/embedded-software/codesourcery)
|
||||||
* Em::Blocks: [EmBlocks](http://www.emblocks.org/web/)
|
* GCC ARM: [Em::Blocks](http://www.emblocks.org/web/)
|
||||||
* CooCox: [CoIDE](http://www.coocox.org/)
|
* GCC ARM: [CooCox CoIDE](http://www.coocox.org/)
|
||||||
|
|
||||||
API Documentation
|
API Documentation
|
||||||
-----------------
|
-----------------
|
||||||
|
|
|
||||||
|
|
@ -23,8 +23,10 @@ Timer::Timer() : _running(), _start(), _time() {
|
||||||
}
|
}
|
||||||
|
|
||||||
void Timer::start() {
|
void Timer::start() {
|
||||||
_start = us_ticker_read();
|
if (!_running) {
|
||||||
_running = 1;
|
_start = us_ticker_read();
|
||||||
|
_running = 1;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void Timer::stop() {
|
void Timer::stop() {
|
||||||
|
|
|
||||||
|
|
@ -37,7 +37,7 @@ void us_ticker_irq_handler(void) {
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((int)(head->timestamp - us_ticker_read()) <= 0) {
|
if ((int64_t)(head->timestamp - us_ticker_read()) <= 0) {
|
||||||
// This event was in the past:
|
// This event was in the past:
|
||||||
// point to the following one and execute its handler
|
// point to the following one and execute its handler
|
||||||
ticker_event_t *p = head;
|
ticker_event_t *p = head;
|
||||||
|
|
@ -70,7 +70,7 @@ void us_ticker_insert_event(ticker_event_t *obj, timestamp_t timestamp, uint32_t
|
||||||
ticker_event_t *prev = NULL, *p = head;
|
ticker_event_t *prev = NULL, *p = head;
|
||||||
while (p != NULL) {
|
while (p != NULL) {
|
||||||
/* check if we come before p */
|
/* check if we come before p */
|
||||||
if ((int)(timestamp - p->timestamp) <= 0) {
|
if ((int64_t)(timestamp - p->timestamp) < 0) {
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
/* go to the next element */
|
/* go to the next element */
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,32 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
*/
|
*/
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,32 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,32 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
*/
|
*/
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,32 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,32 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic for KL05Z
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
*/
|
*/
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFF000) // Vectors positioned at start of RAM
|
#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFF000) // Vectors positioned at start of RAM
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,32 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
*/
|
*/
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,32 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
*/
|
*/
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,32 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic for LCP407x_8x
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
/* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
|
/* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
|
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
|
||||||
|
|
@ -1,9 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
/* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
|
/* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,45 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x800;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x800;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
define symbol __CRP_start__ = 0x000002FC;
|
||||||
|
define symbol __CRP_end__ = 0x000002FF;
|
||||||
|
|
||||||
|
define symbol __region_USB_PKG_RAM_start__ = 0x20004000;
|
||||||
|
define symbol __region_USB_PKG_RAM_end__ = 0x200047FF;
|
||||||
|
|
||||||
|
define symbol __RAM1_start__ = 0x20000000;
|
||||||
|
define symbol __RAM1_end__ = 0x200007FF;
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
|
||||||
|
define region USB_PKG_RAM_region = mem:[from __region_USB_PKG_RAM_start__ to __region_USB_PKG_RAM_end__];
|
||||||
|
define region RAM1_region = mem:[from __RAM1_start__ to __RAM1_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
|
place in CRP_region { section .crp };
|
||||||
|
place in USB_PKG_RAM_region
|
||||||
|
{ readwrite data section USB_PACKET_MEMORY };
|
||||||
|
place in RAM1_region { section .sram };
|
||||||
|
|
@ -0,0 +1,168 @@
|
||||||
|
/**************************************************
|
||||||
|
*
|
||||||
|
* Part one of the system initialization code, contains low-level
|
||||||
|
* initialization, plain thumb variant.
|
||||||
|
*
|
||||||
|
* Copyright 2012 IAR Systems. All rights reserved.
|
||||||
|
*
|
||||||
|
* $Revision: 1106 $
|
||||||
|
*
|
||||||
|
**************************************************/
|
||||||
|
|
||||||
|
;
|
||||||
|
; The modules in this file are included in the libraries, and may be replaced
|
||||||
|
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||||
|
; a user defined start symbol.
|
||||||
|
; To override the cstartup defined in the library, simply add your modified
|
||||||
|
; version to the workbench project.
|
||||||
|
;
|
||||||
|
; The vector table is normally located at address 0.
|
||||||
|
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||||
|
; The name "__vector_table" has special meaning for C-SPY:
|
||||||
|
; it is where the SP start value is found, and the NVIC vector
|
||||||
|
; table register (VTOR) is initialized to this address if != 0.
|
||||||
|
;
|
||||||
|
; Cortex-M version
|
||||||
|
;
|
||||||
|
|
||||||
|
MODULE ?cstartup
|
||||||
|
|
||||||
|
;; Forward declaration of sections.
|
||||||
|
SECTION CSTACK:DATA:NOROOT(3)
|
||||||
|
|
||||||
|
SECTION .intvec:CODE:NOROOT(2)
|
||||||
|
|
||||||
|
EXTERN __iar_program_start
|
||||||
|
PUBLIC __vector_table
|
||||||
|
PUBLIC __vector_table_0x1c
|
||||||
|
|
||||||
|
DATA
|
||||||
|
__vector_table
|
||||||
|
DCD sfe(CSTACK) ; Top of Stack
|
||||||
|
DCD __iar_program_start ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
__vector_table_0x1c
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
DCD FLEX_INT0_IRQHandler ; GPIO pin interrupt 0
|
||||||
|
DCD FLEX_INT1_IRQHandler ; GPIO pin interrupt 1
|
||||||
|
DCD FLEX_INT2_IRQHandler ; GPIO pin interrupt 2
|
||||||
|
DCD FLEX_INT3_IRQHandler ; GPIO pin interrupt 3
|
||||||
|
DCD FLEX_INT4_IRQHandler ; GPIO pin interrupt 4
|
||||||
|
DCD FLEX_INT5_IRQHandler ; GPIO pin interrupt 5
|
||||||
|
DCD FLEX_INT6_IRQHandler ; GPIO pin interrupt 6
|
||||||
|
DCD FLEX_INT7_IRQHandler ; GPIO pin interrupt 7
|
||||||
|
DCD GINT0_IRQHandler ; GPIO GROUP0 interrupt
|
||||||
|
DCD GINT1_IRQHandler ; GPIO GROUP1 interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SSP1_IRQHandler ; SSP1 interrupt
|
||||||
|
DCD I2C_IRQHandler ; I2C interrupt
|
||||||
|
DCD CT16B0_IRQHandler ; CT16B0 Match 0-3, Capture 0
|
||||||
|
DCD CT16B1_IRQHandler ; CT16B1 Match 0-3, Capture 0
|
||||||
|
DCD CT32B0_IRQHandler ; CT32B0 Match 0-3, Capture 0
|
||||||
|
DCD CT32B1_IRQHandler ; CT32B1 Match 0-3, Capture 0
|
||||||
|
DCD SSP0_IRQHandler ; SSP0 interrupt
|
||||||
|
DCD USART_IRQHandler ; USART interrupt
|
||||||
|
DCD USB_IRQHandler ; USB_IRQ interrupt
|
||||||
|
DCD USB_FIQHandler ; USB_FIQ interrupt
|
||||||
|
DCD ADC_IRQHandler ; ADC interrupt
|
||||||
|
DCD WWDT_IRQHandler ; WWDT interrupt
|
||||||
|
DCD BOD_IRQHandler ; BOD interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD USBWakeup_IRQHandler ; USB_WAKEUP interrupt
|
||||||
|
|
||||||
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
;;
|
||||||
|
;; Default interrupt handlers.
|
||||||
|
;;
|
||||||
|
|
||||||
|
PUBWEAK NMI_Handler
|
||||||
|
PUBWEAK HardFault_Handler
|
||||||
|
PUBWEAK MemManage_Handler
|
||||||
|
PUBWEAK BusFault_Handler
|
||||||
|
PUBWEAK UsageFault_Handler
|
||||||
|
PUBWEAK SVC_Handler
|
||||||
|
PUBWEAK DebugMon_Handler
|
||||||
|
PUBWEAK PendSV_Handler
|
||||||
|
PUBWEAK SysTick_Handler
|
||||||
|
PUBWEAK FLEX_INT0_IRQHandler
|
||||||
|
PUBWEAK FLEX_INT1_IRQHandler
|
||||||
|
PUBWEAK FLEX_INT2_IRQHandler
|
||||||
|
PUBWEAK FLEX_INT3_IRQHandler
|
||||||
|
PUBWEAK FLEX_INT4_IRQHandler
|
||||||
|
PUBWEAK FLEX_INT5_IRQHandler
|
||||||
|
PUBWEAK FLEX_INT6_IRQHandler
|
||||||
|
PUBWEAK FLEX_INT7_IRQHandler
|
||||||
|
PUBWEAK GINT0_IRQHandler
|
||||||
|
PUBWEAK GINT1_IRQHandler
|
||||||
|
PUBWEAK SSP1_IRQHandler
|
||||||
|
PUBWEAK I2C_IRQHandler
|
||||||
|
PUBWEAK CT16B0_IRQHandler
|
||||||
|
PUBWEAK CT16B1_IRQHandler
|
||||||
|
PUBWEAK CT32B0_IRQHandler
|
||||||
|
PUBWEAK CT32B1_IRQHandler
|
||||||
|
PUBWEAK SSP0_IRQHandler
|
||||||
|
PUBWEAK USART_IRQHandler
|
||||||
|
PUBWEAK USB_IRQHandler
|
||||||
|
PUBWEAK USB_FIQHandler
|
||||||
|
PUBWEAK ADC_IRQHandler
|
||||||
|
PUBWEAK WWDT_IRQHandler
|
||||||
|
PUBWEAK BOD_IRQHandler
|
||||||
|
PUBWEAK USBWakeup_IRQHandler
|
||||||
|
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
NMI_Handler
|
||||||
|
HardFault_Handler
|
||||||
|
MemManage_Handler
|
||||||
|
BusFault_Handler
|
||||||
|
UsageFault_Handler
|
||||||
|
SVC_Handler
|
||||||
|
DebugMon_Handler
|
||||||
|
PendSV_Handler
|
||||||
|
SysTick_Handler
|
||||||
|
FLEX_INT0_IRQHandler
|
||||||
|
FLEX_INT1_IRQHandler
|
||||||
|
FLEX_INT2_IRQHandler
|
||||||
|
FLEX_INT3_IRQHandler
|
||||||
|
FLEX_INT4_IRQHandler
|
||||||
|
FLEX_INT5_IRQHandler
|
||||||
|
FLEX_INT6_IRQHandler
|
||||||
|
FLEX_INT7_IRQHandler
|
||||||
|
GINT0_IRQHandler
|
||||||
|
GINT1_IRQHandler
|
||||||
|
SSP1_IRQHandler
|
||||||
|
I2C_IRQHandler
|
||||||
|
CT16B0_IRQHandler
|
||||||
|
CT16B1_IRQHandler
|
||||||
|
CT32B0_IRQHandler
|
||||||
|
CT32B1_IRQHandler
|
||||||
|
SSP0_IRQHandler
|
||||||
|
USART_IRQHandler
|
||||||
|
USB_IRQHandler
|
||||||
|
USB_FIQHandler
|
||||||
|
ADC_IRQHandler
|
||||||
|
WWDT_IRQHandler
|
||||||
|
BOD_IRQHandler
|
||||||
|
USBWakeup_IRQHandler
|
||||||
|
Default_Handler
|
||||||
|
B Default_Handler
|
||||||
|
|
||||||
|
END
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic for LCP1768
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
|
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x02000000) // Vectors positioned at start of RAM
|
#define NVIC_RAM_VECTOR_ADDRESS (0x02000000) // Vectors positioned at start of RAM
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
|
||||||
|
|
@ -9,7 +9,7 @@ define symbol __region_ROM_end__ = 0x0007FFFF;
|
||||||
define symbol __NVIC_start__ = 0x10000000;
|
define symbol __NVIC_start__ = 0x10000000;
|
||||||
define symbol __NVIC_end__ = 0x100000C7;
|
define symbol __NVIC_end__ = 0x100000C7;
|
||||||
define symbol __region_RAM_start__ = 0x100000C8;
|
define symbol __region_RAM_start__ = 0x100000C8;
|
||||||
define symbol __region_RAM_end__ = 0x1000FFDF;
|
define symbol __region_RAM_end__ = 0x10007FDF;
|
||||||
define symbol _AHB_RAM_start__ = 0x2007C000;
|
define symbol _AHB_RAM_start__ = 0x2007C000;
|
||||||
define symbol _AHB_RAM_end__ = 0x20083FFF;
|
define symbol _AHB_RAM_end__ = 0x20083FFF;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic for LCP1768
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
|
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
|
||||||
|
|
@ -1,9 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic for LPC2368
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic for LCP407x_8x
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
|
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic for LCP43xx
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
|
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
|
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,14 @@
|
||||||
|
|
||||||
|
LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
|
||||||
|
ER_IROM1 0x00000000 0x8000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
|
||||||
|
; 8KB - 0xC0 = 0x1F40
|
||||||
|
RW_IRAM1 0x10000000+0xC0 0x2000-0xC0 {
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,218 @@
|
||||||
|
;/*****************************************************************************
|
||||||
|
; * @file: startup_LPC8xx.s
|
||||||
|
; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
|
||||||
|
; * for the NXP LPC8xx Device Series
|
||||||
|
; * @version: V1.0
|
||||||
|
; * @date: 16. Aug. 2012
|
||||||
|
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||||
|
; *
|
||||||
|
; * Copyright (C) 2012 ARM Limited. All rights reserved.
|
||||||
|
; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
|
||||||
|
; * processor based microcontrollers. This file can be freely distributed
|
||||||
|
; * within development tools that are supporting such ARM based processors.
|
||||||
|
; *
|
||||||
|
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||||
|
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||||
|
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||||
|
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||||
|
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||||
|
; *
|
||||||
|
; *****************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
EXPORT __initial_sp
|
||||||
|
|
||||||
|
__initial_sp EQU 0x10002000
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000000
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD SPI0_IRQHandler ; SPI0 controller
|
||||||
|
DCD SPI1_IRQHandler ; SPI1 controller
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD UART0_IRQHandler ; UART0
|
||||||
|
DCD UART1_IRQHandler ; UART1
|
||||||
|
DCD UART2_IRQHandler ; UART2
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD I2C1_IRQHandler ; I2C1 controller
|
||||||
|
DCD I2C0_IRQHandler ; I2C0 controller
|
||||||
|
DCD SCT_IRQHandler ; Smart Counter Timer
|
||||||
|
DCD MRT_IRQHandler ; Multi-Rate Timer
|
||||||
|
DCD CMP_IRQHandler ; Comparator
|
||||||
|
DCD WDT_IRQHandler ; PIO1 (0:11)
|
||||||
|
DCD BOD_IRQHandler ; Brown Out Detect
|
||||||
|
DCD Flash_IRQHandler ; Flash interrupt
|
||||||
|
DCD WKT_IRQHandler ; Wakeup timer
|
||||||
|
DCD ADC_SEQA_IRQHandler ; ADC sequence A completion
|
||||||
|
DCD ADC_SEQB_IRQHandler ; ADC sequence B completion
|
||||||
|
DCD ADC_THCMP_IRQHandler ; ADC threshold compare
|
||||||
|
DCD ADC_OVR_IRQHandler ; ADC overrun
|
||||||
|
DCD DMA__RQHandler ; DMA interrupt
|
||||||
|
DCD I2C2_IRQHandler ; I2C2 controller
|
||||||
|
DCD I2C3_IRQHandler ; I2C3 controller
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PININT0_IRQHandler ; PIO INT0
|
||||||
|
DCD PININT1_IRQHandler ; PIO INT1
|
||||||
|
DCD PININT2_IRQHandler ; PIO INT2
|
||||||
|
DCD PININT3_IRQHandler ; PIO INT3
|
||||||
|
DCD PININT4_IRQHandler ; PIO INT4
|
||||||
|
DCD PININT5_IRQHandler ; PIO INT5
|
||||||
|
DCD PININT6_IRQHandler ; PIO INT6
|
||||||
|
DCD PININT7_IRQHandler ; PIO INT7
|
||||||
|
|
||||||
|
|
||||||
|
IF :LNOT::DEF:NO_CRP
|
||||||
|
AREA |.ARM.__at_0x02FC|, CODE, READONLY
|
||||||
|
CRP_Key DCD 0xFFFFFFFF
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset Handler
|
||||||
|
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
EXPORT SPI0_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT UART0_IRQHandler [WEAK]
|
||||||
|
EXPORT UART1_IRQHandler [WEAK]
|
||||||
|
EXPORT UART2_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C0_IRQHandler [WEAK]
|
||||||
|
EXPORT SCT_IRQHandler [WEAK]
|
||||||
|
EXPORT MRT_IRQHandler [WEAK]
|
||||||
|
EXPORT CMP_IRQHandler [WEAK]
|
||||||
|
EXPORT WDT_IRQHandler [WEAK]
|
||||||
|
EXPORT BOD_IRQHandler [WEAK]
|
||||||
|
EXPORT Flash_IRQHandler [WEAK]
|
||||||
|
EXPORT WKT_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC_SEQA_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC_SEQB_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC_THCMP_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC_OVR_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA__RQHandler [WEAK]
|
||||||
|
EXPORT I2C2_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C3_IRQHandler [WEAK]
|
||||||
|
EXPORT PININT0_IRQHandler [WEAK]
|
||||||
|
EXPORT PININT1_IRQHandler [WEAK]
|
||||||
|
EXPORT PININT2_IRQHandler [WEAK]
|
||||||
|
EXPORT PININT3_IRQHandler [WEAK]
|
||||||
|
EXPORT PININT4_IRQHandler [WEAK]
|
||||||
|
EXPORT PININT5_IRQHandler [WEAK]
|
||||||
|
EXPORT PININT6_IRQHandler [WEAK]
|
||||||
|
EXPORT PININT7_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
NMI_Handler
|
||||||
|
SPI0_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
UART0_IRQHandler
|
||||||
|
UART1_IRQHandler
|
||||||
|
UART2_IRQHandler
|
||||||
|
I2C1_IRQHandler
|
||||||
|
I2C0_IRQHandler
|
||||||
|
SCT_IRQHandler
|
||||||
|
MRT_IRQHandler
|
||||||
|
CMP_IRQHandler
|
||||||
|
WDT_IRQHandler
|
||||||
|
BOD_IRQHandler
|
||||||
|
Flash_IRQHandler
|
||||||
|
WKT_IRQHandler
|
||||||
|
ADC_SEQA_IRQHandler
|
||||||
|
ADC_SEQB_IRQHandler
|
||||||
|
ADC_THCMP_IRQHandler
|
||||||
|
ADC_OVR_IRQHandler
|
||||||
|
DMA__RQHandler
|
||||||
|
I2C2_IRQHandler
|
||||||
|
I2C3_IRQHandler
|
||||||
|
PININT0_IRQHandler
|
||||||
|
PININT1_IRQHandler
|
||||||
|
PININT2_IRQHandler
|
||||||
|
PININT3_IRQHandler
|
||||||
|
PININT4_IRQHandler
|
||||||
|
PININT5_IRQHandler
|
||||||
|
PININT6_IRQHandler
|
||||||
|
PININT7_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
END
|
||||||
|
|
@ -0,0 +1,389 @@
|
||||||
|
/******************************************************************************
|
||||||
|
* @file: system_LPC8xx.c
|
||||||
|
* @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
|
||||||
|
* for the NXP LPC8xx Device Series
|
||||||
|
* @version: V1.0
|
||||||
|
* @date: 16. Aug. 2012
|
||||||
|
*----------------------------------------------------------------------------
|
||||||
|
*
|
||||||
|
* Copyright (C) 2012 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* ARM Limited (ARM) is supplying this software for use with Cortex-M0+
|
||||||
|
* processor based microcontrollers. This file can be freely distributed
|
||||||
|
* within development tools that are supporting such ARM based processors.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||||
|
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||||
|
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
#include <stdint.h>
|
||||||
|
#include "LPC82x.h"
|
||||||
|
|
||||||
|
/*
|
||||||
|
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*--------------------- Clock Configuration ----------------------------------*/
|
||||||
|
//
|
||||||
|
// <e> Clock Configuration
|
||||||
|
#define CLOCK_SETUP 1
|
||||||
|
// <h> System Oscillator Control Register (SYSOSCCTRL)
|
||||||
|
// <o.0> BYPASS: System Oscillator Bypass Enable
|
||||||
|
// <i> If enabled then PLL input (sys_osc_clk) is fed
|
||||||
|
// <i> directly from XTALIN and XTALOUT pins.
|
||||||
|
// <o.1> FREQRANGE: System Oscillator Frequency Range
|
||||||
|
// <i> Determines frequency range for Low-power oscillator.
|
||||||
|
// <0=> 1 - 20 MHz
|
||||||
|
// <1=> 15 - 25 MHz
|
||||||
|
// </h>
|
||||||
|
#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||||
|
//
|
||||||
|
// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
|
||||||
|
// <o.0..4> DIVSEL: Select Divider for Fclkana
|
||||||
|
// <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
|
||||||
|
// <0-31>
|
||||||
|
// <o.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
|
||||||
|
// <0=> Undefined
|
||||||
|
// <1=> 0.6 MHz
|
||||||
|
// <2=> 1.05 MHz
|
||||||
|
// <3=> 1.4 MHz
|
||||||
|
// <4=> 1.75 MHz
|
||||||
|
// <5=> 2.1 MHz
|
||||||
|
// <6=> 2.4 MHz
|
||||||
|
// <7=> 2.7 MHz
|
||||||
|
// <8=> 3.0 MHz
|
||||||
|
// <9=> 3.25 MHz
|
||||||
|
// <10=> 3.5 MHz
|
||||||
|
// <11=> 3.75 MHz
|
||||||
|
// <12=> 4.0 MHz
|
||||||
|
// <13=> 4.2 MHz
|
||||||
|
// <14=> 4.4 MHz
|
||||||
|
// <15=> 4.6 MHz
|
||||||
|
#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||||
|
// </h>
|
||||||
|
// <h> System PLL Control Register (SYSPLLCTRL)
|
||||||
|
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
|
||||||
|
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
|
||||||
|
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
|
||||||
|
// <o.0..4> MSEL: Feedback Divider Selection
|
||||||
|
// <i> M = MSEL + 1
|
||||||
|
// <0-31>
|
||||||
|
// <o.5..6> PSEL: Post Divider Selection
|
||||||
|
// <0=> P = 1
|
||||||
|
// <1=> P = 2
|
||||||
|
// <2=> P = 4
|
||||||
|
// <3=> P = 8
|
||||||
|
// </h>
|
||||||
|
#define SYSPLLCTRL_Val 0x00000024 // Reset: 0x000
|
||||||
|
//
|
||||||
|
// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
|
||||||
|
// <o.0..1> SEL: System PLL Clock Source
|
||||||
|
// <0=> IRC
|
||||||
|
// <1=> Crystal Oscillator
|
||||||
|
// <2=> Reserved
|
||||||
|
// <3=> CLKIN. External clock input.
|
||||||
|
// </h>
|
||||||
|
#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000
|
||||||
|
//
|
||||||
|
// <h> Main Clock Source Select Register (MAINCLKSEL)
|
||||||
|
// <o.0..1> SEL: Clock Source for Main Clock
|
||||||
|
// <0=> IRC Oscillator
|
||||||
|
// <1=> PLL input
|
||||||
|
// <2=> Watchdog Oscillator
|
||||||
|
// <3=> PLL output
|
||||||
|
// </h>
|
||||||
|
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
|
||||||
|
// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
|
||||||
|
// <o.0..7> DIV: System AHB Clock Divider
|
||||||
|
// <i> Divides main clock to provide system clock to core, memories, and peripherals.
|
||||||
|
// <i> 0 = is disabled
|
||||||
|
// <0-255>
|
||||||
|
// </h>
|
||||||
|
#define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
//#define CLOCK_SETUP 0 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal:
|
||||||
|
|
||||||
|
/*
|
||||||
|
#if (CLOCK_SETUP == 0)
|
||||||
|
#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||||
|
#define WDTOSCCTRL_Val 0x00000024 // Reset: 0x000
|
||||||
|
#define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000
|
||||||
|
#define SYSPLLCLKSEL_Val 0x00000003 // Reset: 0x000
|
||||||
|
#define MAINCLKSEL_Val 0x00000000 // Reset: 0x000
|
||||||
|
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
|
||||||
|
#elif (CLOCK_SETUP == 2)
|
||||||
|
// #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||||
|
#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||||
|
#define SYSPLLCTRL_Val 0x00000040 // Reset: 0x000
|
||||||
|
#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
|
||||||
|
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
|
||||||
|
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
|
||||||
|
#endif
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
//-------- <<< end of configuration section >>> ------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------
|
||||||
|
Check the register settings
|
||||||
|
*----------------------------------------------------------------------------*/
|
||||||
|
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
|
||||||
|
#define CHECK_RSVD(val, mask) (val & mask)
|
||||||
|
|
||||||
|
/* Clock Configuration -------------------------------------------------------*/
|
||||||
|
#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
|
||||||
|
#error "SYSOSCCTRL: Invalid values of reserved bits!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
|
||||||
|
#error "WDTOSCCTRL: Invalid values of reserved bits!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
|
||||||
|
#error "SYSPLLCLKSEL: Value out of range!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
|
||||||
|
#error "SYSPLLCTRL: Invalid values of reserved bits!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
|
||||||
|
#error "MAINCLKSEL: Invalid values of reserved bits!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
|
||||||
|
#error "SYSAHBCLKDIV: Value out of range!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------
|
||||||
|
DEFINES
|
||||||
|
*----------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------
|
||||||
|
Define clocks
|
||||||
|
*----------------------------------------------------------------------------*/
|
||||||
|
#define __XTAL (12000000UL) /* Oscillator frequency */
|
||||||
|
#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
|
||||||
|
#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
|
||||||
|
#define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */
|
||||||
|
|
||||||
|
|
||||||
|
#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
|
||||||
|
#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
|
||||||
|
|
||||||
|
#if (CLOCK_SETUP) /* Clock Setup */
|
||||||
|
#if (__FREQSEL == 0)
|
||||||
|
#define __WDT_OSC_CLK ( 0) /* undefined */
|
||||||
|
#elif (__FREQSEL == 1)
|
||||||
|
#define __WDT_OSC_CLK ( 500000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 2)
|
||||||
|
#define __WDT_OSC_CLK ( 800000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 3)
|
||||||
|
#define __WDT_OSC_CLK (1100000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 4)
|
||||||
|
#define __WDT_OSC_CLK (1400000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 5)
|
||||||
|
#define __WDT_OSC_CLK (1600000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 6)
|
||||||
|
#define __WDT_OSC_CLK (1800000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 7)
|
||||||
|
#define __WDT_OSC_CLK (2000000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 8)
|
||||||
|
#define __WDT_OSC_CLK (2200000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 9)
|
||||||
|
#define __WDT_OSC_CLK (2400000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 10)
|
||||||
|
#define __WDT_OSC_CLK (2600000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 11)
|
||||||
|
#define __WDT_OSC_CLK (2700000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 12)
|
||||||
|
#define __WDT_OSC_CLK (2900000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 13)
|
||||||
|
#define __WDT_OSC_CLK (3100000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 14)
|
||||||
|
#define __WDT_OSC_CLK (3200000 / __DIVSEL)
|
||||||
|
#else
|
||||||
|
#define __WDT_OSC_CLK (3400000 / __DIVSEL)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* sys_pllclkin calculation */
|
||||||
|
#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
|
||||||
|
#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
|
||||||
|
#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||||
|
#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
|
||||||
|
#elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
|
||||||
|
#define __SYS_PLLCLKIN (__CLKIN_CLK)
|
||||||
|
#else
|
||||||
|
#define __SYS_PLLCLKIN (0)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
|
||||||
|
|
||||||
|
/* main clock calculation */
|
||||||
|
#if ((MAINCLKSEL_Val & 0x03) == 0)
|
||||||
|
#define __MAIN_CLOCK (__IRC_OSC_CLK)
|
||||||
|
#elif ((MAINCLKSEL_Val & 0x03) == 1)
|
||||||
|
#define __MAIN_CLOCK (__SYS_PLLCLKIN)
|
||||||
|
#elif ((MAINCLKSEL_Val & 0x03) == 2)
|
||||||
|
#if (__FREQSEL == 0)
|
||||||
|
#error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
|
||||||
|
#else
|
||||||
|
#define __MAIN_CLOCK (__WDT_OSC_CLK)
|
||||||
|
#endif
|
||||||
|
#elif ((MAINCLKSEL_Val & 0x03) == 3)
|
||||||
|
#define __MAIN_CLOCK (__SYS_PLLCLKOUT)
|
||||||
|
#else
|
||||||
|
#define __MAIN_CLOCK (0)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
|
||||||
|
|
||||||
|
#else
|
||||||
|
#define __SYSTEM_CLOCK (__IRC_OSC_CLK)
|
||||||
|
#endif // CLOCK_SETUP
|
||||||
|
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------
|
||||||
|
Clock Variable definitions
|
||||||
|
*----------------------------------------------------------------------------*/
|
||||||
|
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
|
||||||
|
uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------
|
||||||
|
Clock functions
|
||||||
|
*----------------------------------------------------------------------------*/
|
||||||
|
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||||
|
{
|
||||||
|
uint32_t wdt_osc = 0;
|
||||||
|
|
||||||
|
/* Determine clock frequency according to clock register values */
|
||||||
|
switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
|
||||||
|
case 0: wdt_osc = 0; break;
|
||||||
|
case 1: wdt_osc = 500000; break;
|
||||||
|
case 2: wdt_osc = 800000; break;
|
||||||
|
case 3: wdt_osc = 1100000; break;
|
||||||
|
case 4: wdt_osc = 1400000; break;
|
||||||
|
case 5: wdt_osc = 1600000; break;
|
||||||
|
case 6: wdt_osc = 1800000; break;
|
||||||
|
case 7: wdt_osc = 2000000; break;
|
||||||
|
case 8: wdt_osc = 2200000; break;
|
||||||
|
case 9: wdt_osc = 2400000; break;
|
||||||
|
case 10: wdt_osc = 2600000; break;
|
||||||
|
case 11: wdt_osc = 2700000; break;
|
||||||
|
case 12: wdt_osc = 2900000; break;
|
||||||
|
case 13: wdt_osc = 3100000; break;
|
||||||
|
case 14: wdt_osc = 3200000; break;
|
||||||
|
case 15: wdt_osc = 3400000; break;
|
||||||
|
}
|
||||||
|
wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
|
||||||
|
|
||||||
|
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
|
||||||
|
case 0: /* Internal RC oscillator */
|
||||||
|
SystemCoreClock = __IRC_OSC_CLK;
|
||||||
|
break;
|
||||||
|
case 1: /* Input Clock to System PLL */
|
||||||
|
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||||
|
case 0: /* Internal RC oscillator */
|
||||||
|
SystemCoreClock = __IRC_OSC_CLK;
|
||||||
|
break;
|
||||||
|
case 1: /* System oscillator */
|
||||||
|
SystemCoreClock = __SYS_OSC_CLK;
|
||||||
|
break;
|
||||||
|
case 2: /* Reserved */
|
||||||
|
SystemCoreClock = 0;
|
||||||
|
break;
|
||||||
|
case 3: /* CLKIN pin */
|
||||||
|
SystemCoreClock = __CLKIN_CLK;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case 2: /* WDT Oscillator */
|
||||||
|
SystemCoreClock = wdt_osc;
|
||||||
|
break;
|
||||||
|
case 3: /* System PLL Clock Out */
|
||||||
|
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||||
|
case 0: /* Internal RC oscillator */
|
||||||
|
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||||
|
break;
|
||||||
|
case 1: /* System oscillator */
|
||||||
|
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||||
|
break;
|
||||||
|
case 2: /* Reserved */
|
||||||
|
SystemCoreClock = 0;
|
||||||
|
break;
|
||||||
|
case 3: /* CLKIN pin */
|
||||||
|
SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Initialize the system
|
||||||
|
*
|
||||||
|
* @param none
|
||||||
|
* @return none
|
||||||
|
*
|
||||||
|
* @brief Setup the microcontroller system.
|
||||||
|
* Initialize the System.
|
||||||
|
*/
|
||||||
|
void SystemInit (void) {
|
||||||
|
volatile uint32_t i;
|
||||||
|
|
||||||
|
/* System clock to the IOCON & the SWM need to be enabled or
|
||||||
|
most of the I/O related peripherals won't work. */
|
||||||
|
LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
|
||||||
|
|
||||||
|
#if (CLOCK_SETUP) /* Clock Setup */
|
||||||
|
|
||||||
|
#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||||
|
LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
|
||||||
|
LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
|
||||||
|
LPC_SWM->PINENABLE0 &= ~(0x3 << 6); /* XTALIN and XTALOUT */
|
||||||
|
LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */
|
||||||
|
for (i = 0; i < 200; i++) __NOP();
|
||||||
|
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ((SYSPLLCLKSEL_Val & 0x03) == 3)
|
||||||
|
LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
|
||||||
|
LPC_SWM->PINENABLE0 &= ~(0x1 << 9); /* CLKIN */
|
||||||
|
for (i = 0; i < 200; i++) __NOP();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up System PLL */
|
||||||
|
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
|
||||||
|
LPC_SYSCON->SYSPLLCLKUEN = 0;
|
||||||
|
LPC_SYSCON->SYSPLLCLKUEN = 1; /* Update Clock Source */
|
||||||
|
while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
|
||||||
|
|
||||||
|
#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
|
||||||
|
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
|
||||||
|
LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */
|
||||||
|
while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (((MAINCLKSEL_Val & 0x03) == 2) )
|
||||||
|
LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
|
||||||
|
LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */
|
||||||
|
for (i = 0; i < 200; i++) __NOP();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
|
||||||
|
LPC_SYSCON->MAINCLKUEN = 0;
|
||||||
|
LPC_SYSCON->MAINCLKUEN = 1; /* Update MCLK Clock Source */
|
||||||
|
while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
|
||||||
|
|
||||||
|
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
|
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,33 @@
|
||||||
/* mbed Microcontroller Library - cmsis_nvic
|
/* mbed Microcontroller Library
|
||||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
*/
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
|
||||||
|
|
@ -1,11 +1,11 @@
|
||||||
/* Linker script for STM32F407 */
|
/* Linker script for STM32F429ZI */
|
||||||
|
|
||||||
/* Linker script to configure memory regions. */
|
/* Linker script to configure memory regions. */
|
||||||
MEMORY
|
MEMORY
|
||||||
{
|
{
|
||||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048k
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048k
|
||||||
CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
|
CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
RAM (rwx) : ORIGIN = 0x20000188, LENGTH = 192k - 0x188
|
RAM (rwx) : ORIGIN = 0x200001AC, LENGTH = 192k - 0x1AC
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Linker script to place sections and symbol values. Should be used together
|
/* Linker script to place sections and symbol values. Should be used together
|
||||||
|
|
|
||||||
|
|
@ -1,6 +1,9 @@
|
||||||
/**
|
/**
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @file startup_stm32f407xx.s
|
* @file startup_stm32f429xx.s
|
||||||
|
* based on startup_stm32f407xx.s with additional interrupt vectors
|
||||||
|
*
|
||||||
|
* file startup_stm32f407xx.s
|
||||||
* @author MCD Application Team
|
* @author MCD Application Team
|
||||||
* @version V2.0.0
|
* @version V2.0.0
|
||||||
* @date 18-February-2014
|
* @date 18-February-2014
|
||||||
|
|
@ -273,10 +276,19 @@ g_pfnVectors:
|
||||||
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||||
.word OTG_HS_IRQHandler /* USB OTG HS */
|
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||||
.word DCMI_IRQHandler /* DCMI */
|
.word DCMI_IRQHandler /* DCMI */
|
||||||
.word 0 /* CRYP crypto */
|
.word CRYP_IRQHandler /* CRYP crypto */
|
||||||
.word HASH_RNG_IRQHandler /* Hash and Rng */
|
.word HASH_RNG_IRQHandler /* Hash and Rng */
|
||||||
.word FPU_IRQHandler /* FPU */
|
.word FPU_IRQHandler /* FPU */
|
||||||
|
.word UART7_IRQHandler /* UART7 */
|
||||||
|
.word UART8_IRQHandler /* UART8 */
|
||||||
|
.word SPI4_IRQHandler /* SPI4 */
|
||||||
|
.word SPI5_IRQHandler /* SPI5 */
|
||||||
|
.word SPI6_IRQHandler /* SPI6 */
|
||||||
|
.word SAI1_IRQHandler /* SAI1 */
|
||||||
|
.word LCD_IRQHandler /* LTDC */
|
||||||
|
.word LCDErr_IRQHandler /* LTDC Error */
|
||||||
|
.word DMA2D_IRQHandler /* DMA2D */
|
||||||
|
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
*
|
*
|
||||||
|
|
@ -546,13 +558,44 @@ g_pfnVectors:
|
||||||
.weak OTG_HS_IRQHandler
|
.weak OTG_HS_IRQHandler
|
||||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DCMI_IRQHandler
|
.weak DCMI_IRQHandler
|
||||||
.thumb_set DCMI_IRQHandler,Default_Handler
|
.thumb_set DCMI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak HASH_RNG_IRQHandler
|
|
||||||
.thumb_set HASH_RNG_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak FPU_IRQHandler
|
.weak CRYP_IRQHandler
|
||||||
.thumb_set FPU_IRQHandler,Default_Handler
|
.thumb_set CRYP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HASH_RNG_IRQHandler
|
||||||
|
.thumb_set HASH_RNG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FPU_IRQHandler
|
||||||
|
.thumb_set FPU_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART7_IRQHandler
|
||||||
|
.thumb_set UART7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART8_IRQHandler
|
||||||
|
.thumb_set UART8_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI4_IRQHandler
|
||||||
|
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI5_IRQHandler
|
||||||
|
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI6_IRQHandler
|
||||||
|
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI1_IRQHandler
|
||||||
|
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LCD_IRQHandler
|
||||||
|
.thumb_set LCD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LCDErr_IRQHandler
|
||||||
|
.thumb_set LCDErr_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2D_IRQHandler
|
||||||
|
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,151 @@
|
||||||
|
/* Linker script for STM32F407 */
|
||||||
|
|
||||||
|
/* Linker script to configure memory regions. */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x10000
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000188, LENGTH = 0x3000 - 0x0188
|
||||||
|
/* CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x1000 */
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Linker script to place sections and symbol values. Should be used together
|
||||||
|
* with other linker script that defines memory regions FLASH and RAM.
|
||||||
|
* It references following symbols, which must be defined in code:
|
||||||
|
* Reset_Handler : Entry of reset handler
|
||||||
|
*
|
||||||
|
* It defines following symbols, which code can use without definition:
|
||||||
|
* __exidx_start
|
||||||
|
* __exidx_end
|
||||||
|
* __etext
|
||||||
|
* __data_start__
|
||||||
|
* __preinit_array_start
|
||||||
|
* __preinit_array_end
|
||||||
|
* __init_array_start
|
||||||
|
* __init_array_end
|
||||||
|
* __fini_array_start
|
||||||
|
* __fini_array_end
|
||||||
|
* __data_end__
|
||||||
|
* __bss_start__
|
||||||
|
* __bss_end__
|
||||||
|
* __end__
|
||||||
|
* end
|
||||||
|
* __HeapLimit
|
||||||
|
* __StackLimit
|
||||||
|
* __StackTop
|
||||||
|
* __stack
|
||||||
|
*/
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
KEEP(*(.isr_vector))
|
||||||
|
*(.text*)
|
||||||
|
|
||||||
|
KEEP(*(.init))
|
||||||
|
KEEP(*(.fini))
|
||||||
|
|
||||||
|
/* .ctors */
|
||||||
|
*crtbegin.o(.ctors)
|
||||||
|
*crtbegin?.o(.ctors)
|
||||||
|
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||||
|
*(SORT(.ctors.*))
|
||||||
|
*(.ctors)
|
||||||
|
|
||||||
|
/* .dtors */
|
||||||
|
*crtbegin.o(.dtors)
|
||||||
|
*crtbegin?.o(.dtors)
|
||||||
|
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||||
|
*(SORT(.dtors.*))
|
||||||
|
*(.dtors)
|
||||||
|
|
||||||
|
*(.rodata*)
|
||||||
|
|
||||||
|
KEEP(*(.eh_frame*))
|
||||||
|
} > FLASH
|
||||||
|
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} > FLASH
|
||||||
|
|
||||||
|
__exidx_start = .;
|
||||||
|
.ARM.exidx :
|
||||||
|
{
|
||||||
|
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||||
|
} > FLASH
|
||||||
|
__exidx_end = .;
|
||||||
|
|
||||||
|
__etext = .;
|
||||||
|
|
||||||
|
.data : AT (__etext)
|
||||||
|
{
|
||||||
|
__data_start__ = .;
|
||||||
|
*(vtable)
|
||||||
|
*(.data*)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* preinit data */
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP(*(.preinit_array))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* init data */
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP(*(SORT(.init_array.*)))
|
||||||
|
KEEP(*(.init_array))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* finit data */
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP(*(SORT(.fini_array.*)))
|
||||||
|
KEEP(*(.fini_array))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
|
||||||
|
KEEP(*(.jcr*))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* All data end */
|
||||||
|
__data_end__ = .;
|
||||||
|
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__bss_start__ = .;
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__bss_end__ = .;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
.heap (COPY):
|
||||||
|
{
|
||||||
|
__end__ = .;
|
||||||
|
end = __end__;
|
||||||
|
*(.heap*)
|
||||||
|
__HeapLimit = .;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||||
|
* used for linker to calculate size of stack sections, and assign
|
||||||
|
* values to stack symbols later */
|
||||||
|
.stack_dummy (COPY):
|
||||||
|
{
|
||||||
|
*(.stack*)
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Set stack top to end of RAM, and stack limit move down by
|
||||||
|
* size of stack_dummy section */
|
||||||
|
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||||
|
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||||
|
PROVIDE(__stack = __StackTop);
|
||||||
|
|
||||||
|
/* Check if data + heap + stack exceeds RAM limit */
|
||||||
|
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,288 @@
|
||||||
|
/* File: startup_STM32F40x.S
|
||||||
|
* Purpose: startup file for Cortex-M4 devices. Should use with
|
||||||
|
* GCC for ARM Embedded Processors
|
||||||
|
* Version: V1.4
|
||||||
|
* Date: 09 July 2012
|
||||||
|
*
|
||||||
|
* Copyright (c) 2011, 2012, ARM Limited
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
* Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
* Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
|
||||||
|
* Neither the name of the ARM Limited nor the
|
||||||
|
names of its contributors may be used to endorse or promote products
|
||||||
|
derived from this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||||
|
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||||
|
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||||
|
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
.syntax unified
|
||||||
|
.arch armv7-m
|
||||||
|
|
||||||
|
.section .stack
|
||||||
|
.align 3
|
||||||
|
#ifdef __STACK_SIZE
|
||||||
|
.equ Stack_Size, __STACK_SIZE
|
||||||
|
#else
|
||||||
|
.equ Stack_Size, 0xc00
|
||||||
|
#endif
|
||||||
|
.globl __StackTop
|
||||||
|
.globl __StackLimit
|
||||||
|
__StackLimit:
|
||||||
|
.space Stack_Size
|
||||||
|
.size __StackLimit, . - __StackLimit
|
||||||
|
__StackTop:
|
||||||
|
.size __StackTop, . - __StackTop
|
||||||
|
|
||||||
|
.section .heap
|
||||||
|
.align 3
|
||||||
|
#ifdef __HEAP_SIZE
|
||||||
|
.equ Heap_Size, __HEAP_SIZE
|
||||||
|
#else
|
||||||
|
.equ Heap_Size, 0x400
|
||||||
|
#endif
|
||||||
|
.globl __HeapBase
|
||||||
|
.globl __HeapLimit
|
||||||
|
__HeapBase:
|
||||||
|
.if Heap_Size
|
||||||
|
.space Heap_Size
|
||||||
|
.endif
|
||||||
|
.size __HeapBase, . - __HeapBase
|
||||||
|
__HeapLimit:
|
||||||
|
.size __HeapLimit, . - __HeapLimit
|
||||||
|
|
||||||
|
.section .isr_vector
|
||||||
|
.align 2
|
||||||
|
.globl __isr_vector
|
||||||
|
__isr_vector:
|
||||||
|
.long __StackTop /* Top of Stack */
|
||||||
|
.long Reset_Handler /* Reset Handler */
|
||||||
|
.long NMI_Handler /* NMI Handler */
|
||||||
|
.long HardFault_Handler /* Hard Fault Handler */
|
||||||
|
.long MemManage_Handler /* MPU Fault Handler */
|
||||||
|
.long BusFault_Handler /* Bus Fault Handler */
|
||||||
|
.long UsageFault_Handler /* Usage Fault Handler */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long SVC_Handler /* SVCall Handler */
|
||||||
|
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long PendSV_Handler /* PendSV Handler */
|
||||||
|
.long SysTick_Handler /* SysTick Handler */
|
||||||
|
|
||||||
|
/* External interrupts */
|
||||||
|
.long WWDG_IRQHandler /* Window WatchDog */
|
||||||
|
.long PVD_IRQHandler /* PVD through EXTI Line detection */
|
||||||
|
.long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||||
|
.long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||||
|
.long FLASH_IRQHandler /* FLASH */
|
||||||
|
.long RCC_IRQHandler /* RCC */
|
||||||
|
.long EXTI0_IRQHandler /* EXTI Line0 */
|
||||||
|
.long EXTI1_IRQHandler /* EXTI Line1 */
|
||||||
|
.long EXTI2_TSC_IRQHandler /* EXTI Line2 */
|
||||||
|
.long EXTI3_IRQHandler /* EXTI Line3 */
|
||||||
|
.long EXTI4_IRQHandler /* EXTI Line4 */
|
||||||
|
.long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||||
|
.long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||||
|
.long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||||
|
.long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||||
|
.long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||||
|
.long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||||
|
.long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||||
|
.long ADC1_2_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||||
|
.long CAN_TX_IRQHandler /* Reserved */
|
||||||
|
.long CAN_RX0_IRQHandler /* Reserved */
|
||||||
|
.long CAN_RX1_IRQHandler /* Reserved */
|
||||||
|
.long CAN_SCE_IRQHandler /* Reserved */
|
||||||
|
.long EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||||
|
.long TIM1_BRK_TIM15_IRQHandler /* TIM1 Break and TIM9 */
|
||||||
|
.long TIM1_UP_TIM16_IRQHandler /* TIM1 Update and TIM10 */
|
||||||
|
.long TIM1_TRG_COM_TIM17_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
|
||||||
|
.long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||||
|
.long TIM2_IRQHandler /* TIM2 */
|
||||||
|
.long TIM3_IRQHandler /* TIM3 */
|
||||||
|
.long 0 /* TIM4 */
|
||||||
|
.long I2C1_EV_IRQHandler /* I2C1 Event */
|
||||||
|
.long I2C1_ER_IRQHandler /* I2C1 Error */
|
||||||
|
.long 0 /* I2C2 Event */
|
||||||
|
.long 0 /* I2C2 Error */
|
||||||
|
.long SPI1_IRQHandler /* SPI1 */
|
||||||
|
.long 0 /* SPI2 */
|
||||||
|
.long USART1_IRQHandler /* USART1 */
|
||||||
|
.long USART2_IRQHandler /* USART2 */
|
||||||
|
.long USART3_IRQHandler /* Reserved */
|
||||||
|
.long EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||||
|
.long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||||
|
.long 0 /* USB OTG FS Wakeup through EXTI line */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* DMA1 Stream7 */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* SDIO */
|
||||||
|
.long 0 /* TIM5 */
|
||||||
|
.long 0 /* SPI3 */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long TIM6_DAC1_IRQHandler /* Reserved */
|
||||||
|
.long TIM7_DAC2_IRQHandler /* Reserved */
|
||||||
|
.long 0 /* DMA2 Stream 0 */
|
||||||
|
.long 0 /* DMA2 Stream 1 */
|
||||||
|
.long 0 /* DMA2 Stream 2 */
|
||||||
|
.long 0 /* DMA2 Stream 3 */
|
||||||
|
.long 0 /* DMA2 Stream 4 */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long COMP2_IRQHandler /* Reserved */
|
||||||
|
.long COMP4_6_IRQHandler /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long HRTIM1_Master_IRQHandler /* USB OTG FS */
|
||||||
|
.long HRTIM1_TIMA_IRQHandler /* DMA2 Stream 5 */
|
||||||
|
.long HRTIM1_TIMB_IRQHandler /* DMA2 Stream 6 */
|
||||||
|
.long HRTIM1_TIMC_IRQHandler /* DMA2 Stream 7 */
|
||||||
|
.long HRTIM1_TIMD_IRQHandler /* USART6 */
|
||||||
|
.long HRTIM1_TIME_IRQHandler /* I2C3 event */
|
||||||
|
.long HRTIM1_FLT_IRQHandler /* I2C3 error */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long FPU_IRQHandler /* FPU */
|
||||||
|
|
||||||
|
.size __isr_vector, . - __isr_vector
|
||||||
|
|
||||||
|
.text
|
||||||
|
.thumb
|
||||||
|
.thumb_func
|
||||||
|
.align 2
|
||||||
|
.globl Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
/* Loop to copy data from read only memory to RAM. The ranges
|
||||||
|
* of copy from/to are specified by following symbols evaluated in
|
||||||
|
* linker script.
|
||||||
|
* __etext: End of code section, i.e., begin of data sections to copy from.
|
||||||
|
* __data_start__/__data_end__: RAM address range that data should be
|
||||||
|
* copied to. Both must be aligned to 4 bytes boundary. */
|
||||||
|
|
||||||
|
ldr r1, =__etext
|
||||||
|
ldr r2, =__data_start__
|
||||||
|
ldr r3, =__data_end__
|
||||||
|
|
||||||
|
.LC0:
|
||||||
|
cmp r2, r3
|
||||||
|
ittt lt
|
||||||
|
ldrlt r0, [r1], #4
|
||||||
|
strlt r0, [r2], #4
|
||||||
|
blt .LC0
|
||||||
|
|
||||||
|
ldr r0, =SystemInit
|
||||||
|
blx r0
|
||||||
|
ldr r0, =_start
|
||||||
|
bx r0
|
||||||
|
.pool
|
||||||
|
.size Reset_Handler, . - Reset_Handler
|
||||||
|
|
||||||
|
.text
|
||||||
|
/* Macro to define default handlers. Default handler
|
||||||
|
* will be weak symbol and just dead loops. They can be
|
||||||
|
* overwritten by other handlers */
|
||||||
|
.macro def_default_handler handler_name
|
||||||
|
.align 1
|
||||||
|
.thumb_func
|
||||||
|
.weak \handler_name
|
||||||
|
.type \handler_name, %function
|
||||||
|
\handler_name :
|
||||||
|
b .
|
||||||
|
.size \handler_name, . - \handler_name
|
||||||
|
.endm
|
||||||
|
|
||||||
|
def_default_handler NMI_Handler
|
||||||
|
def_default_handler HardFault_Handler
|
||||||
|
def_default_handler MemManage_Handler
|
||||||
|
def_default_handler BusFault_Handler
|
||||||
|
def_default_handler UsageFault_Handler
|
||||||
|
def_default_handler SVC_Handler
|
||||||
|
def_default_handler DebugMon_Handler
|
||||||
|
def_default_handler PendSV_Handler
|
||||||
|
def_default_handler SysTick_Handler
|
||||||
|
def_default_handler Default_Handler
|
||||||
|
|
||||||
|
.macro def_irq_default_handler handler_name
|
||||||
|
.weak \handler_name
|
||||||
|
.set \handler_name, Default_Handler
|
||||||
|
.endm
|
||||||
|
|
||||||
|
def_irq_default_handler WWDG_IRQHandler
|
||||||
|
def_irq_default_handler PVD_IRQHandler
|
||||||
|
def_irq_default_handler TAMP_STAMP_IRQHandler
|
||||||
|
def_irq_default_handler RTC_WKUP_IRQHandler
|
||||||
|
def_irq_default_handler FLASH_IRQHandler
|
||||||
|
def_irq_default_handler RCC_IRQHandler
|
||||||
|
def_irq_default_handler EXTI0_IRQHandler
|
||||||
|
def_irq_default_handler EXTI1_IRQHandler
|
||||||
|
def_irq_default_handler EXTI2_TSC_IRQHandler
|
||||||
|
def_irq_default_handler EXTI3_IRQHandler
|
||||||
|
def_irq_default_handler EXTI4_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream0_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream1_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream2_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream3_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream4_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream5_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream6_IRQHandler
|
||||||
|
def_irq_default_handler ADC1_2_IRQHandler
|
||||||
|
def_irq_default_handler CAN_TX_IRQHandler
|
||||||
|
def_irq_default_handler CAN_RX0_IRQHandler
|
||||||
|
def_irq_default_handler CAN_RX1_IRQHandler
|
||||||
|
def_irq_default_handler CAN_SCE_IRQHandler
|
||||||
|
def_irq_default_handler EXTI9_5_IRQHandler
|
||||||
|
def_irq_default_handler TIM1_BRK_TIM15_IRQHandler
|
||||||
|
def_irq_default_handler TIM1_UP_TIM16_IRQHandler
|
||||||
|
def_irq_default_handler TIM1_TRG_COM_TIM17_IRQHandler
|
||||||
|
def_irq_default_handler TIM1_CC_IRQHandler
|
||||||
|
def_irq_default_handler TIM2_IRQHandler
|
||||||
|
def_irq_default_handler TIM3_IRQHandler
|
||||||
|
def_irq_default_handler I2C1_EV_IRQHandler
|
||||||
|
def_irq_default_handler I2C1_ER_IRQHandler
|
||||||
|
def_irq_default_handler SPI1_IRQHandler
|
||||||
|
def_irq_default_handler USART1_IRQHandler
|
||||||
|
def_irq_default_handler USART2_IRQHandler
|
||||||
|
def_irq_default_handler USART3_IRQHandler
|
||||||
|
def_irq_default_handler EXTI15_10_IRQHandler
|
||||||
|
def_irq_default_handler RTC_Alarm_IRQHandler
|
||||||
|
def_irq_default_handler TIM6_DAC1_IRQHandler
|
||||||
|
def_irq_default_handler TIM7_DAC2_IRQHandler
|
||||||
|
def_irq_default_handler COMP2_IRQHandler
|
||||||
|
def_irq_default_handler COMP4_6_IRQHandler
|
||||||
|
def_irq_default_handler HRTIM1_Master_IRQHandler
|
||||||
|
def_irq_default_handler HRTIM1_TIMA_IRQHandler
|
||||||
|
def_irq_default_handler HRTIM1_TIMB_IRQHandler
|
||||||
|
def_irq_default_handler HRTIM1_TIMC_IRQHandler
|
||||||
|
def_irq_default_handler HRTIM1_TIMD_IRQHandler
|
||||||
|
def_irq_default_handler HRTIM1_TIME_IRQHandler
|
||||||
|
def_irq_default_handler HRTIM1_FLT_IRQHandler
|
||||||
|
def_irq_default_handler FPU_IRQHandler
|
||||||
|
def_irq_default_handler DEF_IRQHandler
|
||||||
|
|
||||||
|
.end
|
||||||
|
|
@ -0,0 +1,523 @@
|
||||||
|
;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32f411xe.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Version : V2.1.0
|
||||||
|
;* Date : 19-June-2014
|
||||||
|
;* Description : STM32F411xExx devices vector table for EWARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == _iar_program_start,
|
||||||
|
;* - Set the vector table entries with the exceptions ISR
|
||||||
|
;* address.
|
||||||
|
;* - Configure the system clock
|
||||||
|
;* - Branches to main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;********************************************************************************
|
||||||
|
;*
|
||||||
|
;* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;* are permitted provided that the following conditions are met:
|
||||||
|
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer.
|
||||||
|
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer in the documentation
|
||||||
|
;* and/or other materials provided with the distribution.
|
||||||
|
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
;* may be used to endorse or promote products derived from this software
|
||||||
|
;* without specific prior written permission.
|
||||||
|
;*
|
||||||
|
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;*
|
||||||
|
;*******************************************************************************
|
||||||
|
;
|
||||||
|
;
|
||||||
|
; The modules in this file are included in the libraries, and may be replaced
|
||||||
|
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||||
|
; a user defined start symbol.
|
||||||
|
; To override the cstartup defined in the library, simply add your modified
|
||||||
|
; version to the workbench project.
|
||||||
|
;
|
||||||
|
; The vector table is normally located at address 0.
|
||||||
|
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||||
|
; The name "__vector_table" has special meaning for C-SPY:
|
||||||
|
; it is where the SP start value is found, and the NVIC vector
|
||||||
|
; table register (VTOR) is initialized to this address if != 0.
|
||||||
|
;
|
||||||
|
; Cortex-M version
|
||||||
|
;
|
||||||
|
|
||||||
|
MODULE ?cstartup
|
||||||
|
|
||||||
|
;; Forward declaration of sections.
|
||||||
|
SECTION CSTACK:DATA:NOROOT(3)
|
||||||
|
|
||||||
|
SECTION .intvec:CODE:NOROOT(2)
|
||||||
|
|
||||||
|
EXTERN __iar_program_start
|
||||||
|
EXTERN SystemInit
|
||||||
|
PUBLIC __vector_table
|
||||||
|
|
||||||
|
DATA
|
||||||
|
__vector_table
|
||||||
|
DCD sfe(CSTACK)
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window WatchDog
|
||||||
|
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||||
|
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||||
|
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||||
|
DCD FLASH_IRQHandler ; FLASH
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||||
|
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||||
|
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||||
|
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||||
|
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||||
|
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||||
|
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||||
|
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||||
|
DCD ADC_IRQHandler ; ADC1
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||||
|
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
|
||||||
|
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
|
||||||
|
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||||
|
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SDIO_IRQHandler ; SDIO
|
||||||
|
DCD TIM5_IRQHandler ; TIM5
|
||||||
|
DCD SPI3_IRQHandler ; SPI3
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||||
|
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||||
|
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||||
|
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||||
|
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||||
|
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||||
|
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||||
|
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||||
|
DCD USART6_IRQHandler ; USART6
|
||||||
|
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||||
|
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD FPU_IRQHandler ; FPU
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SPI4_IRQHandler ; SPI4
|
||||||
|
DCD SPI5_IRQHandler ; SPI5
|
||||||
|
|
||||||
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
;;
|
||||||
|
;; Default interrupt handlers.
|
||||||
|
;;
|
||||||
|
THUMB
|
||||||
|
PUBWEAK Reset_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||||
|
Reset_Handler
|
||||||
|
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__iar_program_start
|
||||||
|
BX R0
|
||||||
|
|
||||||
|
PUBWEAK NMI_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
NMI_Handler
|
||||||
|
B NMI_Handler
|
||||||
|
|
||||||
|
PUBWEAK HardFault_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
HardFault_Handler
|
||||||
|
B HardFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK MemManage_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
MemManage_Handler
|
||||||
|
B MemManage_Handler
|
||||||
|
|
||||||
|
PUBWEAK BusFault_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
BusFault_Handler
|
||||||
|
B BusFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK UsageFault_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
UsageFault_Handler
|
||||||
|
B UsageFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK SVC_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
SVC_Handler
|
||||||
|
B SVC_Handler
|
||||||
|
|
||||||
|
PUBWEAK DebugMon_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DebugMon_Handler
|
||||||
|
B DebugMon_Handler
|
||||||
|
|
||||||
|
PUBWEAK PendSV_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PendSV_Handler
|
||||||
|
B PendSV_Handler
|
||||||
|
|
||||||
|
PUBWEAK SysTick_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
SysTick_Handler
|
||||||
|
B SysTick_Handler
|
||||||
|
|
||||||
|
PUBWEAK WWDG_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
WWDG_IRQHandler
|
||||||
|
B WWDG_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PVD_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PVD_IRQHandler
|
||||||
|
B PVD_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TAMP_STAMP_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TAMP_STAMP_IRQHandler
|
||||||
|
B TAMP_STAMP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
B RTC_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FLASH_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
FLASH_IRQHandler
|
||||||
|
B FLASH_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RCC_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
RCC_IRQHandler
|
||||||
|
B RCC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
B EXTI0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
B EXTI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
B EXTI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
B EXTI3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI4_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
B EXTI4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA1_Stream0_IRQHandler
|
||||||
|
B DMA1_Stream0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA1_Stream1_IRQHandler
|
||||||
|
B DMA1_Stream1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA1_Stream2_IRQHandler
|
||||||
|
B DMA1_Stream2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA1_Stream3_IRQHandler
|
||||||
|
B DMA1_Stream3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream4_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA1_Stream4_IRQHandler
|
||||||
|
B DMA1_Stream4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream5_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA1_Stream5_IRQHandler
|
||||||
|
B DMA1_Stream5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream6_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA1_Stream6_IRQHandler
|
||||||
|
B DMA1_Stream6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ADC_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
ADC_IRQHandler
|
||||||
|
B ADC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI9_5_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
B EXTI9_5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM1_BRK_TIM9_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TIM1_BRK_TIM9_IRQHandler
|
||||||
|
B TIM1_BRK_TIM9_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM1_UP_TIM10_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TIM1_UP_TIM10_IRQHandler
|
||||||
|
B TIM1_UP_TIM10_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TIM1_TRG_COM_TIM11_IRQHandler
|
||||||
|
B TIM1_TRG_COM_TIM11_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM1_CC_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
B TIM1_CC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TIM2_IRQHandler
|
||||||
|
B TIM2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TIM3_IRQHandler
|
||||||
|
B TIM3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM4_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TIM4_IRQHandler
|
||||||
|
B TIM4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C1_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
B I2C1_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C1_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
B I2C1_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C2_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
B I2C2_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C2_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
B I2C2_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
SPI1_IRQHandler
|
||||||
|
B SPI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
SPI2_IRQHandler
|
||||||
|
B SPI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
USART1_IRQHandler
|
||||||
|
B USART1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
USART2_IRQHandler
|
||||||
|
B USART2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI15_10_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
B EXTI15_10_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_Alarm_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
B RTC_Alarm_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK OTG_FS_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
OTG_FS_WKUP_IRQHandler
|
||||||
|
B OTG_FS_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream7_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA1_Stream7_IRQHandler
|
||||||
|
B DMA1_Stream7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SDIO_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
SDIO_IRQHandler
|
||||||
|
B SDIO_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM5_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TIM5_IRQHandler
|
||||||
|
B TIM5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
SPI3_IRQHandler
|
||||||
|
B SPI3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA2_Stream0_IRQHandler
|
||||||
|
B DMA2_Stream0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA2_Stream1_IRQHandler
|
||||||
|
B DMA2_Stream1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA2_Stream2_IRQHandler
|
||||||
|
B DMA2_Stream2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA2_Stream3_IRQHandler
|
||||||
|
B DMA2_Stream3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream4_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA2_Stream4_IRQHandler
|
||||||
|
B DMA2_Stream4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK OTG_FS_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
OTG_FS_IRQHandler
|
||||||
|
B OTG_FS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream5_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA2_Stream5_IRQHandler
|
||||||
|
B DMA2_Stream5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream6_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA2_Stream6_IRQHandler
|
||||||
|
B DMA2_Stream6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream7_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA2_Stream7_IRQHandler
|
||||||
|
B DMA2_Stream7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART6_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
USART6_IRQHandler
|
||||||
|
B USART6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C3_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
I2C3_EV_IRQHandler
|
||||||
|
B I2C3_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C3_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
I2C3_ER_IRQHandler
|
||||||
|
B I2C3_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FPU_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
FPU_IRQHandler
|
||||||
|
B FPU_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI4_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
SPI4_IRQHandler
|
||||||
|
B SPI4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI5_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
SPI5_IRQHandler
|
||||||
|
B SPI5_IRQHandler
|
||||||
|
|
||||||
|
END
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
|
|
@ -206,7 +206,7 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
|
||||||
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
|
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
|
||||||
{
|
{
|
||||||
/* Check ADC handle */
|
/* Check ADC handle */
|
||||||
if(hadc == NULL)
|
if(hadc == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -259,7 +259,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
|
||||||
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
|
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
|
||||||
{
|
{
|
||||||
/* Check ADC handle */
|
/* Check ADC handle */
|
||||||
if(hadc == NULL)
|
if(hadc == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -112,7 +112,7 @@
|
||||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
|
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
|
||||||
{
|
{
|
||||||
/* Check the CRC handle allocation */
|
/* Check the CRC handle allocation */
|
||||||
if(hcrc == NULL)
|
if(hcrc == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -145,7 +145,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
|
||||||
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
|
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
|
||||||
{
|
{
|
||||||
/* Check the CRC handle allocation */
|
/* Check the CRC handle allocation */
|
||||||
if(hcrc == NULL)
|
if(hcrc == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -71,7 +71,7 @@ typedef enum
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
#ifndef NULL
|
#ifndef NULL
|
||||||
#define NULL (void *) 0
|
#define HAL_NULL (void *) 0
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define HAL_MAX_DELAY 0xFFFFFFFF
|
#define HAL_MAX_DELAY 0xFFFFFFFF
|
||||||
|
|
|
||||||
|
|
@ -172,7 +172,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
||||||
uint32_t tmp = 0;
|
uint32_t tmp = 0;
|
||||||
|
|
||||||
/* Check the DMA peripheral state */
|
/* Check the DMA peripheral state */
|
||||||
if(hdma == NULL)
|
if(hdma == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -262,7 +262,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
||||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
|
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
|
||||||
{
|
{
|
||||||
/* Check the DMA peripheral state */
|
/* Check the DMA peripheral state */
|
||||||
if(hdma == NULL)
|
if(hdma == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -648,7 +648,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||||
/* Process Unlocked */
|
/* Process Unlocked */
|
||||||
__HAL_UNLOCK(hdma);
|
__HAL_UNLOCK(hdma);
|
||||||
|
|
||||||
if(hdma->XferErrorCallback != NULL)
|
if(hdma->XferErrorCallback != HAL_NULL)
|
||||||
{
|
{
|
||||||
/* Transfer error callback */
|
/* Transfer error callback */
|
||||||
hdma->XferErrorCallback(hdma);
|
hdma->XferErrorCallback(hdma);
|
||||||
|
|
@ -675,7 +675,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||||
/* Process Unlocked */
|
/* Process Unlocked */
|
||||||
__HAL_UNLOCK(hdma);
|
__HAL_UNLOCK(hdma);
|
||||||
|
|
||||||
if(hdma->XferErrorCallback != NULL)
|
if(hdma->XferErrorCallback != HAL_NULL)
|
||||||
{
|
{
|
||||||
/* Transfer error callback */
|
/* Transfer error callback */
|
||||||
hdma->XferErrorCallback(hdma);
|
hdma->XferErrorCallback(hdma);
|
||||||
|
|
@ -702,7 +702,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||||
/* Process Unlocked */
|
/* Process Unlocked */
|
||||||
__HAL_UNLOCK(hdma);
|
__HAL_UNLOCK(hdma);
|
||||||
|
|
||||||
if(hdma->XferErrorCallback != NULL)
|
if(hdma->XferErrorCallback != HAL_NULL)
|
||||||
{
|
{
|
||||||
/* Transfer error callback */
|
/* Transfer error callback */
|
||||||
hdma->XferErrorCallback(hdma);
|
hdma->XferErrorCallback(hdma);
|
||||||
|
|
@ -748,7 +748,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||||
hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
|
hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
|
||||||
}
|
}
|
||||||
|
|
||||||
if(hdma->XferHalfCpltCallback != NULL)
|
if(hdma->XferHalfCpltCallback != HAL_NULL)
|
||||||
{
|
{
|
||||||
/* Half transfer callback */
|
/* Half transfer callback */
|
||||||
hdma->XferHalfCpltCallback(hdma);
|
hdma->XferHalfCpltCallback(hdma);
|
||||||
|
|
@ -768,7 +768,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||||
/* Current memory buffer used is Memory 1 */
|
/* Current memory buffer used is Memory 1 */
|
||||||
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
|
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
|
||||||
{
|
{
|
||||||
if(hdma->XferM1CpltCallback != NULL)
|
if(hdma->XferM1CpltCallback != HAL_NULL)
|
||||||
{
|
{
|
||||||
/* Transfer complete Callback for memory1 */
|
/* Transfer complete Callback for memory1 */
|
||||||
hdma->XferM1CpltCallback(hdma);
|
hdma->XferM1CpltCallback(hdma);
|
||||||
|
|
@ -777,7 +777,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||||
/* Current memory buffer used is Memory 0 */
|
/* Current memory buffer used is Memory 0 */
|
||||||
else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
|
else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
|
||||||
{
|
{
|
||||||
if(hdma->XferCpltCallback != NULL)
|
if(hdma->XferCpltCallback != HAL_NULL)
|
||||||
{
|
{
|
||||||
/* Transfer complete Callback for memory0 */
|
/* Transfer complete Callback for memory0 */
|
||||||
hdma->XferCpltCallback(hdma);
|
hdma->XferCpltCallback(hdma);
|
||||||
|
|
@ -804,7 +804,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||||
/* Process Unlocked */
|
/* Process Unlocked */
|
||||||
__HAL_UNLOCK(hdma);
|
__HAL_UNLOCK(hdma);
|
||||||
|
|
||||||
if(hdma->XferCpltCallback != NULL)
|
if(hdma->XferCpltCallback != HAL_NULL)
|
||||||
{
|
{
|
||||||
/* Transfer complete callback */
|
/* Transfer complete callback */
|
||||||
hdma->XferCpltCallback(hdma);
|
hdma->XferCpltCallback(hdma);
|
||||||
|
|
|
||||||
|
|
@ -708,7 +708,7 @@ static void FLASH_SetErrorCode(void)
|
||||||
|
|
||||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
|
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
|
||||||
{
|
{
|
||||||
pFlash.ErrorCode |= FLASH_ERROR_PGA;
|
pFlash.ErrorCode |= (FLASH_ErrorTypeDef)FLASH_ERROR_PGA;
|
||||||
}
|
}
|
||||||
|
|
||||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
|
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
|
||||||
|
|
|
||||||
|
|
@ -119,7 +119,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
|
||||||
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
|
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
|
||||||
{
|
{
|
||||||
/* Check the HCD handle allocation */
|
/* Check the HCD handle allocation */
|
||||||
if(hhcd == NULL)
|
if(hhcd == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -233,7 +233,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
|
||||||
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
|
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
|
||||||
{
|
{
|
||||||
/* Check the HCD handle allocation */
|
/* Check the HCD handle allocation */
|
||||||
if(hhcd == NULL)
|
if(hhcd == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -280,7 +280,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
||||||
uint32_t pclk1 = 0;
|
uint32_t pclk1 = 0;
|
||||||
|
|
||||||
/* Check the I2C handle allocation */
|
/* Check the I2C handle allocation */
|
||||||
if(hi2c == NULL)
|
if(hi2c == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -355,7 +355,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
||||||
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
|
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
|
||||||
{
|
{
|
||||||
/* Check the I2C handle allocation */
|
/* Check the I2C handle allocation */
|
||||||
if(hi2c == NULL)
|
if(hi2c == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -484,7 +484,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
|
||||||
{
|
{
|
||||||
if(hi2c->State == HAL_I2C_STATE_READY)
|
if(hi2c->State == HAL_I2C_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -582,7 +582,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
|
||||||
{
|
{
|
||||||
if(hi2c->State == HAL_I2C_STATE_READY)
|
if(hi2c->State == HAL_I2C_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -773,7 +773,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
|
||||||
{
|
{
|
||||||
if(hi2c->State == HAL_I2C_STATE_READY)
|
if(hi2c->State == HAL_I2C_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -878,7 +878,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
|
||||||
{
|
{
|
||||||
if(hi2c->State == HAL_I2C_STATE_READY)
|
if(hi2c->State == HAL_I2C_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -970,7 +970,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
|
||||||
{
|
{
|
||||||
if(hi2c->State == HAL_I2C_STATE_READY)
|
if(hi2c->State == HAL_I2C_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1041,7 +1041,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
|
||||||
{
|
{
|
||||||
if(hi2c->State == HAL_I2C_STATE_READY)
|
if(hi2c->State == HAL_I2C_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1139,7 +1139,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
|
||||||
{
|
{
|
||||||
if(hi2c->State == HAL_I2C_STATE_READY)
|
if(hi2c->State == HAL_I2C_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1192,7 +1192,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
|
||||||
{
|
{
|
||||||
if(hi2c->State == HAL_I2C_STATE_READY)
|
if(hi2c->State == HAL_I2C_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1246,7 +1246,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
|
||||||
{
|
{
|
||||||
if(hi2c->State == HAL_I2C_STATE_READY)
|
if(hi2c->State == HAL_I2C_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1322,7 +1322,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
|
||||||
{
|
{
|
||||||
if(hi2c->State == HAL_I2C_STATE_READY)
|
if(hi2c->State == HAL_I2C_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1408,7 +1408,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
|
||||||
{
|
{
|
||||||
if(hi2c->State == HAL_I2C_STATE_READY)
|
if(hi2c->State == HAL_I2C_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1493,7 +1493,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
|
||||||
{
|
{
|
||||||
if(hi2c->State == HAL_I2C_STATE_READY)
|
if(hi2c->State == HAL_I2C_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1566,7 +1566,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
|
||||||
|
|
||||||
if(hi2c->State == HAL_I2C_STATE_READY)
|
if(hi2c->State == HAL_I2C_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1666,7 +1666,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
|
||||||
|
|
||||||
if(hi2c->State == HAL_I2C_STATE_READY)
|
if(hi2c->State == HAL_I2C_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1858,7 +1858,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
|
||||||
|
|
||||||
if(hi2c->State == HAL_I2C_STATE_READY)
|
if(hi2c->State == HAL_I2C_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1931,7 +1931,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
|
||||||
|
|
||||||
if(hi2c->State == HAL_I2C_STATE_READY)
|
if(hi2c->State == HAL_I2C_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -2034,7 +2034,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
|
||||||
|
|
||||||
if(hi2c->State == HAL_I2C_STATE_READY)
|
if(hi2c->State == HAL_I2C_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -2112,7 +2112,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
|
||||||
|
|
||||||
if(hi2c->State == HAL_I2C_STATE_READY)
|
if(hi2c->State == HAL_I2C_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -205,7 +205,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
|
||||||
uint32_t tmp = 0, i2sclk = 0;
|
uint32_t tmp = 0, i2sclk = 0;
|
||||||
|
|
||||||
/* Check the I2S handle allocation */
|
/* Check the I2S handle allocation */
|
||||||
if(hi2s == NULL)
|
if(hi2s == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -383,7 +383,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
|
||||||
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
|
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
|
||||||
{
|
{
|
||||||
/* Check the I2S handle allocation */
|
/* Check the I2S handle allocation */
|
||||||
if(hi2s == NULL)
|
if(hi2s == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -492,7 +492,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
|
||||||
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
|
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
|
||||||
{
|
{
|
||||||
uint32_t tmp1 = 0, tmp2 = 0;
|
uint32_t tmp1 = 0, tmp2 = 0;
|
||||||
if((pData == NULL ) || (Size == 0))
|
if((pData == HAL_NULL ) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -574,7 +574,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
|
||||||
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
|
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
|
||||||
{
|
{
|
||||||
uint32_t tmp1 = 0, tmp2 = 0;
|
uint32_t tmp1 = 0, tmp2 = 0;
|
||||||
if((pData == NULL ) || (Size == 0))
|
if((pData == HAL_NULL ) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -659,7 +659,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
|
||||||
uint32_t tmp1 = 0, tmp2 = 0;
|
uint32_t tmp1 = 0, tmp2 = 0;
|
||||||
if(hi2s->State == HAL_I2S_STATE_READY)
|
if(hi2s->State == HAL_I2S_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -727,7 +727,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
|
||||||
uint32_t tmp1 = 0, tmp2 = 0;
|
uint32_t tmp1 = 0, tmp2 = 0;
|
||||||
if(hi2s->State == HAL_I2S_STATE_READY)
|
if(hi2s->State == HAL_I2S_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -793,7 +793,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
|
||||||
uint32_t *tmp;
|
uint32_t *tmp;
|
||||||
uint32_t tmp1 = 0, tmp2 = 0;
|
uint32_t tmp1 = 0, tmp2 = 0;
|
||||||
|
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -878,7 +878,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
|
||||||
uint32_t *tmp;
|
uint32_t *tmp;
|
||||||
uint32_t tmp1 = 0, tmp2 = 0;
|
uint32_t tmp1 = 0, tmp2 = 0;
|
||||||
|
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1071,12 +1071,12 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Abort the I2S DMA Stream tx */
|
/* Abort the I2S DMA Stream tx */
|
||||||
if(hi2s->hdmatx != NULL)
|
if(hi2s->hdmatx != HAL_NULL)
|
||||||
{
|
{
|
||||||
HAL_DMA_Abort(hi2s->hdmatx);
|
HAL_DMA_Abort(hi2s->hdmatx);
|
||||||
}
|
}
|
||||||
/* Abort the I2S DMA Stream rx */
|
/* Abort the I2S DMA Stream rx */
|
||||||
if(hi2s->hdmarx != NULL)
|
if(hi2s->hdmarx != HAL_NULL)
|
||||||
{
|
{
|
||||||
HAL_DMA_Abort(hi2s->hdmarx);
|
HAL_DMA_Abort(hi2s->hdmarx);
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -186,7 +186,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p
|
||||||
uint32_t tickstart = 0;
|
uint32_t tickstart = 0;
|
||||||
uint32_t tmp1 = 0, tmp2 = 0;
|
uint32_t tmp1 = 0, tmp2 = 0;
|
||||||
|
|
||||||
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
|
if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -360,7 +360,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t
|
||||||
|
|
||||||
if(hi2s->State == HAL_I2S_STATE_READY)
|
if(hi2s->State == HAL_I2S_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
|
if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -485,7 +485,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_
|
||||||
uint32_t *tmp;
|
uint32_t *tmp;
|
||||||
uint32_t tmp1 = 0, tmp2 = 0;
|
uint32_t tmp1 = 0, tmp2 = 0;
|
||||||
|
|
||||||
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
|
if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -202,7 +202,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
|
||||||
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
|
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
|
||||||
{
|
{
|
||||||
/* Check the IRDA handle allocation */
|
/* Check the IRDA handle allocation */
|
||||||
if(hirda == NULL)
|
if(hirda == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -260,7 +260,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
|
||||||
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
|
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
|
||||||
{
|
{
|
||||||
/* Check the IRDA handle allocation */
|
/* Check the IRDA handle allocation */
|
||||||
if(hirda == NULL)
|
if(hirda == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -380,7 +380,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
|
||||||
tmp1 = hirda->State;
|
tmp1 = hirda->State;
|
||||||
if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX))
|
if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX))
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -472,7 +472,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
|
||||||
tmp1 = hirda->State;
|
tmp1 = hirda->State;
|
||||||
if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX))
|
if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX))
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -564,7 +564,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData
|
||||||
tmp1 = hirda->State;
|
tmp1 = hirda->State;
|
||||||
if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX))
|
if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX))
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -619,7 +619,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
|
||||||
tmp1 = hirda->State;
|
tmp1 = hirda->State;
|
||||||
if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX))
|
if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX))
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -676,7 +676,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
|
||||||
tmp1 = hirda->State;
|
tmp1 = hirda->State;
|
||||||
if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX))
|
if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX))
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -743,7 +743,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
|
||||||
tmp1 = hirda->State;
|
tmp1 = hirda->State;
|
||||||
if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX))
|
if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX))
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -882,12 +882,12 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
|
||||||
hirda->Instance->CR3 &= ~USART_CR3_DMAR;
|
hirda->Instance->CR3 &= ~USART_CR3_DMAR;
|
||||||
|
|
||||||
/* Abort the UART DMA tx Stream */
|
/* Abort the UART DMA tx Stream */
|
||||||
if(hirda->hdmatx != NULL)
|
if(hirda->hdmatx != HAL_NULL)
|
||||||
{
|
{
|
||||||
HAL_DMA_Abort(hirda->hdmatx);
|
HAL_DMA_Abort(hirda->hdmatx);
|
||||||
}
|
}
|
||||||
/* Abort the UART DMA rx Stream */
|
/* Abort the UART DMA rx Stream */
|
||||||
if(hirda->hdmarx != NULL)
|
if(hirda->hdmarx != HAL_NULL)
|
||||||
{
|
{
|
||||||
HAL_DMA_Abort(hirda->hdmarx);
|
HAL_DMA_Abort(hirda->hdmarx);
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -164,7 +164,7 @@
|
||||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
||||||
{
|
{
|
||||||
/* Check the IWDG handle allocation */
|
/* Check the IWDG handle allocation */
|
||||||
if(hiwdg == NULL)
|
if(hiwdg == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -124,7 +124,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
|
||||||
uint32_t i = 0;
|
uint32_t i = 0;
|
||||||
|
|
||||||
/* Check the PCD handle allocation */
|
/* Check the PCD handle allocation */
|
||||||
if(hpcd == NULL)
|
if(hpcd == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -191,7 +191,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
|
||||||
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
|
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
|
||||||
{
|
{
|
||||||
/* Check the PCD handle allocation */
|
/* Check the PCD handle allocation */
|
||||||
if(hpcd == NULL)
|
if(hpcd == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -203,7 +203,7 @@
|
||||||
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
|
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
|
||||||
{
|
{
|
||||||
/* Check the RTC peripheral state */
|
/* Check the RTC peripheral state */
|
||||||
if(hrtc == NULL)
|
if(hrtc == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -2574,7 +2574,7 @@ static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardS
|
||||||
SDIO_CmdInitTypeDef sdio_cmdinitstructure;
|
SDIO_CmdInitTypeDef sdio_cmdinitstructure;
|
||||||
HAL_SD_ErrorTypedef errorstate = SD_OK;
|
HAL_SD_ErrorTypedef errorstate = SD_OK;
|
||||||
|
|
||||||
if(pCardStatus == NULL)
|
if(pCardStatus == HAL_NULL)
|
||||||
{
|
{
|
||||||
errorstate = SD_INVALID_PARAMETER;
|
errorstate = SD_INVALID_PARAMETER;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -222,7 +222,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
|
||||||
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
|
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
|
||||||
{
|
{
|
||||||
/* Check the SMARTCARD handle allocation */
|
/* Check the SMARTCARD handle allocation */
|
||||||
if(hsc == NULL)
|
if(hsc == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -285,7 +285,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
|
||||||
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
|
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
|
||||||
{
|
{
|
||||||
/* Check the SMARTCARD handle allocation */
|
/* Check the SMARTCARD handle allocation */
|
||||||
if(hsc == NULL)
|
if(hsc == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -404,7 +404,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
|
||||||
tmp1 = hsc->State;
|
tmp1 = hsc->State;
|
||||||
if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
|
if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -497,7 +497,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
|
||||||
tmp1 = hsc->State;
|
tmp1 = hsc->State;
|
||||||
if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
|
if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -594,7 +594,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_
|
||||||
tmp1 = hsc->State;
|
tmp1 = hsc->State;
|
||||||
if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
|
if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -652,7 +652,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t
|
||||||
tmp1 = hsc->State;
|
tmp1 = hsc->State;
|
||||||
if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
|
if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -711,7 +711,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8
|
||||||
tmp1 = hsc->State;
|
tmp1 = hsc->State;
|
||||||
if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
|
if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -776,7 +776,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_
|
||||||
tmp1 = hsc->State;
|
tmp1 = hsc->State;
|
||||||
if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
|
if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -169,7 +169,7 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin
|
||||||
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
|
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
|
||||||
{
|
{
|
||||||
/* Check the SPI handle allocation */
|
/* Check the SPI handle allocation */
|
||||||
if(hspi == NULL)
|
if(hspi == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -230,7 +230,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
|
||||||
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
|
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
|
||||||
{
|
{
|
||||||
/* Check the SPI handle allocation */
|
/* Check the SPI handle allocation */
|
||||||
if(hspi == NULL)
|
if(hspi == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -345,7 +345,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
|
||||||
|
|
||||||
if(hspi->State == HAL_SPI_STATE_READY)
|
if(hspi->State == HAL_SPI_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL ) || (Size == 0))
|
if((pData == HAL_NULL ) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -489,7 +489,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
|
||||||
|
|
||||||
if(hspi->State == HAL_SPI_STATE_READY)
|
if(hspi->State == HAL_SPI_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL ) || (Size == 0))
|
if((pData == HAL_NULL ) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -665,7 +665,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
|
||||||
tmpstate = hspi->State;
|
tmpstate = hspi->State;
|
||||||
if((tmpstate == HAL_SPI_STATE_READY) || (tmpstate == HAL_SPI_STATE_BUSY_RX))
|
if((tmpstate == HAL_SPI_STATE_READY) || (tmpstate == HAL_SPI_STATE_BUSY_RX))
|
||||||
{
|
{
|
||||||
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
|
if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -912,7 +912,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
|
||||||
{
|
{
|
||||||
if(hspi->State == HAL_SPI_STATE_READY)
|
if(hspi->State == HAL_SPI_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -987,7 +987,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
|
||||||
{
|
{
|
||||||
if(hspi->State == HAL_SPI_STATE_READY)
|
if(hspi->State == HAL_SPI_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1071,7 +1071,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
|
||||||
if((tmpstate == HAL_SPI_STATE_READY) || \
|
if((tmpstate == HAL_SPI_STATE_READY) || \
|
||||||
((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmpstate == HAL_SPI_STATE_BUSY_RX)))
|
((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmpstate == HAL_SPI_STATE_BUSY_RX)))
|
||||||
{
|
{
|
||||||
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
|
if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1140,7 +1140,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
|
||||||
{
|
{
|
||||||
if(hspi->State == HAL_SPI_STATE_READY)
|
if(hspi->State == HAL_SPI_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1223,7 +1223,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
|
||||||
{
|
{
|
||||||
if(hspi->State == HAL_SPI_STATE_READY)
|
if(hspi->State == HAL_SPI_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pData == NULL) || (Size == 0))
|
if((pData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1315,7 +1315,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
|
||||||
if((tmpstate == HAL_SPI_STATE_READY) || ((hspi->Init.Mode == SPI_MODE_MASTER) && \
|
if((tmpstate == HAL_SPI_STATE_READY) || ((hspi->Init.Mode == SPI_MODE_MASTER) && \
|
||||||
(hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmpstate == HAL_SPI_STATE_BUSY_RX)))
|
(hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmpstate == HAL_SPI_STATE_BUSY_RX)))
|
||||||
{
|
{
|
||||||
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
|
if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1378,9 +1378,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
|
||||||
/* Enable Rx DMA Request */
|
/* Enable Rx DMA Request */
|
||||||
hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
|
hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
|
||||||
|
|
||||||
/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
|
/* Set the SPI Tx DMA transfer complete callback as HAL_NULL because the communication closing
|
||||||
is performed in DMA reception complete callback */
|
is performed in DMA reception complete callback */
|
||||||
hspi->hdmatx->XferCpltCallback = NULL;
|
hspi->hdmatx->XferCpltCallback = HAL_NULL;
|
||||||
|
|
||||||
/* Set the DMA error callback */
|
/* Set the DMA error callback */
|
||||||
hspi->hdmatx->XferErrorCallback = SPI_DMAError;
|
hspi->hdmatx->XferErrorCallback = SPI_DMAError;
|
||||||
|
|
@ -1466,12 +1466,12 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Abort the SPI DMA tx Stream */
|
/* Abort the SPI DMA tx Stream */
|
||||||
if(hspi->hdmatx != NULL)
|
if(hspi->hdmatx != HAL_NULL)
|
||||||
{
|
{
|
||||||
HAL_DMA_Abort(hspi->hdmatx);
|
HAL_DMA_Abort(hspi->hdmatx);
|
||||||
}
|
}
|
||||||
/* Abort the SPI DMA rx Stream */
|
/* Abort the SPI DMA rx Stream */
|
||||||
if(hspi->hdmarx != NULL)
|
if(hspi->hdmarx != HAL_NULL)
|
||||||
{
|
{
|
||||||
HAL_DMA_Abort(hspi->hdmarx);
|
HAL_DMA_Abort(hspi->hdmarx);
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -200,7 +200,7 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
|
||||||
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
|
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
|
||||||
{
|
{
|
||||||
/* Check the TIM handle allocation */
|
/* Check the TIM handle allocation */
|
||||||
if(htim == NULL)
|
if(htim == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -477,7 +477,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
|
||||||
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
|
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
|
||||||
{
|
{
|
||||||
/* Check the TIM handle allocation */
|
/* Check the TIM handle allocation */
|
||||||
if(htim == NULL)
|
if(htim == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -984,7 +984,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
|
||||||
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
|
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
|
||||||
{
|
{
|
||||||
/* Check the TIM handle allocation */
|
/* Check the TIM handle allocation */
|
||||||
if(htim == NULL)
|
if(htim == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1494,7 +1494,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
|
||||||
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
|
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
|
||||||
{
|
{
|
||||||
/* Check the TIM handle allocation */
|
/* Check the TIM handle allocation */
|
||||||
if(htim == NULL)
|
if(htim == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1970,7 +1970,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
|
||||||
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
|
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
|
||||||
{
|
{
|
||||||
/* Check the TIM handle allocation */
|
/* Check the TIM handle allocation */
|
||||||
if(htim == NULL)
|
if(htim == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -2245,7 +2245,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
|
||||||
uint32_t tmpccer = 0;
|
uint32_t tmpccer = 0;
|
||||||
|
|
||||||
/* Check the TIM handle allocation */
|
/* Check the TIM handle allocation */
|
||||||
if(htim == NULL)
|
if(htim == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -155,7 +155,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
|
||||||
TIM_OC_InitTypeDef OC_Config;
|
TIM_OC_InitTypeDef OC_Config;
|
||||||
|
|
||||||
/* Check the TIM handle allocation */
|
/* Check the TIM handle allocation */
|
||||||
if(htim == NULL)
|
if(htim == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -231,7 +231,7 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,
|
||||||
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
||||||
{
|
{
|
||||||
/* Check the UART handle allocation */
|
/* Check the UART handle allocation */
|
||||||
if(huart == NULL)
|
if(huart == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -287,7 +287,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
||||||
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
|
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
|
||||||
{
|
{
|
||||||
/* Check the UART handle allocation */
|
/* Check the UART handle allocation */
|
||||||
if(huart == NULL)
|
if(huart == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -339,7 +339,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
|
||||||
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
|
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
|
||||||
{
|
{
|
||||||
/* Check the UART handle allocation */
|
/* Check the UART handle allocation */
|
||||||
if(huart == NULL)
|
if(huart == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -398,7 +398,7 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
|
||||||
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethode)
|
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethode)
|
||||||
{
|
{
|
||||||
/* Check the UART handle allocation */
|
/* Check the UART handle allocation */
|
||||||
if(huart == NULL)
|
if(huart == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -455,7 +455,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
|
||||||
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
|
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
|
||||||
{
|
{
|
||||||
/* Check the UART handle allocation */
|
/* Check the UART handle allocation */
|
||||||
if(huart == NULL)
|
if(huart == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -576,7 +576,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
|
||||||
tmp1 = huart->State;
|
tmp1 = huart->State;
|
||||||
if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_RX))
|
if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_RX))
|
||||||
{
|
{
|
||||||
if((pData == NULL ) || (Size == 0))
|
if((pData == HAL_NULL ) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -670,7 +670,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
|
||||||
tmp1 = huart->State;
|
tmp1 = huart->State;
|
||||||
if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_TX))
|
if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_TX))
|
||||||
{
|
{
|
||||||
if((pData == NULL ) || (Size == 0))
|
if((pData == HAL_NULL ) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -768,7 +768,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
|
||||||
tmp = huart->State;
|
tmp = huart->State;
|
||||||
if((tmp == HAL_UART_STATE_READY) || (tmp == HAL_UART_STATE_BUSY_RX))
|
if((tmp == HAL_UART_STATE_READY) || (tmp == HAL_UART_STATE_BUSY_RX))
|
||||||
{
|
{
|
||||||
if((pData == NULL ) || (Size == 0))
|
if((pData == HAL_NULL ) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -826,7 +826,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
|
||||||
tmp = huart->State;
|
tmp = huart->State;
|
||||||
if((tmp == HAL_UART_STATE_READY) || (tmp == HAL_UART_STATE_BUSY_TX))
|
if((tmp == HAL_UART_STATE_READY) || (tmp == HAL_UART_STATE_BUSY_TX))
|
||||||
{
|
{
|
||||||
if((pData == NULL ) || (Size == 0))
|
if((pData == HAL_NULL ) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -885,7 +885,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
|
||||||
tmp1 = huart->State;
|
tmp1 = huart->State;
|
||||||
if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_RX))
|
if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_RX))
|
||||||
{
|
{
|
||||||
if((pData == NULL ) || (Size == 0))
|
if((pData == HAL_NULL ) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -953,7 +953,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
|
||||||
tmp1 = huart->State;
|
tmp1 = huart->State;
|
||||||
if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_TX))
|
if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_TX))
|
||||||
{
|
{
|
||||||
if((pData == NULL ) || (Size == 0))
|
if((pData == HAL_NULL ) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1094,12 +1094,12 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
|
||||||
huart->Instance->CR3 &= ~USART_CR3_DMAR;
|
huart->Instance->CR3 &= ~USART_CR3_DMAR;
|
||||||
|
|
||||||
/* Abort the UART DMA tx Stream */
|
/* Abort the UART DMA tx Stream */
|
||||||
if(huart->hdmatx != NULL)
|
if(huart->hdmatx != HAL_NULL)
|
||||||
{
|
{
|
||||||
HAL_DMA_Abort(huart->hdmatx);
|
HAL_DMA_Abort(huart->hdmatx);
|
||||||
}
|
}
|
||||||
/* Abort the UART DMA rx Stream */
|
/* Abort the UART DMA rx Stream */
|
||||||
if(huart->hdmarx != NULL)
|
if(huart->hdmarx != HAL_NULL)
|
||||||
{
|
{
|
||||||
HAL_DMA_Abort(huart->hdmarx);
|
HAL_DMA_Abort(huart->hdmarx);
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -213,7 +213,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar
|
||||||
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
|
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
|
||||||
{
|
{
|
||||||
/* Check the USART handle allocation */
|
/* Check the USART handle allocation */
|
||||||
if(husart == NULL)
|
if(husart == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -257,7 +257,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
|
||||||
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
|
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
|
||||||
{
|
{
|
||||||
/* Check the USART handle allocation */
|
/* Check the USART handle allocation */
|
||||||
if(husart == NULL)
|
if(husart == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -380,7 +380,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
|
||||||
|
|
||||||
if(husart->State == HAL_USART_STATE_READY)
|
if(husart->State == HAL_USART_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pTxData == NULL) || (Size == 0))
|
if((pTxData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -457,7 +457,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
|
||||||
|
|
||||||
if(husart->State == HAL_USART_STATE_READY)
|
if(husart->State == HAL_USART_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pRxData == NULL) || (Size == 0))
|
if((pRxData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -559,7 +559,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
|
||||||
|
|
||||||
if(husart->State == HAL_USART_STATE_READY)
|
if(husart->State == HAL_USART_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
|
if((pTxData == HAL_NULL) || (pRxData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -667,7 +667,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
|
||||||
{
|
{
|
||||||
if(husart->State == HAL_USART_STATE_READY)
|
if(husart->State == HAL_USART_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pTxData == NULL) || (Size == 0))
|
if((pTxData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -716,7 +716,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
|
||||||
{
|
{
|
||||||
if(husart->State == HAL_USART_STATE_READY)
|
if(husart->State == HAL_USART_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pRxData == NULL) || (Size == 0))
|
if((pRxData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -766,7 +766,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
|
||||||
{
|
{
|
||||||
if(husart->State == HAL_USART_STATE_READY)
|
if(husart->State == HAL_USART_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
|
if((pTxData == HAL_NULL) || (pRxData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -820,7 +820,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
|
||||||
|
|
||||||
if(husart->State == HAL_USART_STATE_READY)
|
if(husart->State == HAL_USART_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pTxData == NULL) || (Size == 0))
|
if((pTxData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -878,7 +878,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
|
||||||
|
|
||||||
if(husart->State == HAL_USART_STATE_READY)
|
if(husart->State == HAL_USART_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pRxData == NULL) || (Size == 0))
|
if((pRxData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -951,7 +951,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
|
||||||
|
|
||||||
if(husart->State == HAL_USART_STATE_READY)
|
if(husart->State == HAL_USART_STATE_READY)
|
||||||
{
|
{
|
||||||
if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
|
if((pTxData == HAL_NULL) || (pRxData == HAL_NULL) || (Size == 0))
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -1069,12 +1069,12 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Abort the USART DMA Tx Stream */
|
/* Abort the USART DMA Tx Stream */
|
||||||
if(husart->hdmatx != NULL)
|
if(husart->hdmatx != HAL_NULL)
|
||||||
{
|
{
|
||||||
HAL_DMA_Abort(husart->hdmatx);
|
HAL_DMA_Abort(husart->hdmatx);
|
||||||
}
|
}
|
||||||
/* Abort the USART DMA Rx Stream */
|
/* Abort the USART DMA Rx Stream */
|
||||||
if(husart->hdmarx != NULL)
|
if(husart->hdmarx != HAL_NULL)
|
||||||
{
|
{
|
||||||
HAL_DMA_Abort(husart->hdmarx);
|
HAL_DMA_Abort(husart->hdmarx);
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -151,7 +151,7 @@
|
||||||
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
|
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
|
||||||
{
|
{
|
||||||
/* Check the WWDG handle allocation */
|
/* Check the WWDG handle allocation */
|
||||||
if(hwwdg == NULL)
|
if(hwwdg == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
@ -192,7 +192,7 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
|
||||||
HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg)
|
HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg)
|
||||||
{
|
{
|
||||||
/* Check the WWDG handle allocation */
|
/* Check the WWDG handle allocation */
|
||||||
if(hwwdg == NULL)
|
if(hwwdg == HAL_NULL)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -1,4 +1,4 @@
|
||||||
; STM32L1xx Ultra Low Power High-density Devices vector table for MDK ARM_MICRO toolchain
|
; STM32L152RE Ultra Low Power High-density Devices vector table for MDK ARM_MICRO toolchain
|
||||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
; Copyright (c) 2014, STMicroelectronics
|
; Copyright (c) 2014, STMicroelectronics
|
||||||
; All rights reserved.
|
; All rights reserved.
|
||||||
|
|
@ -39,7 +39,7 @@ Stack_Size EQU 0x00000400
|
||||||
EXPORT __initial_sp
|
EXPORT __initial_sp
|
||||||
|
|
||||||
Stack_Mem SPACE Stack_Size
|
Stack_Mem SPACE Stack_Size
|
||||||
__initial_sp EQU 0x20014000 ; Top of RAM (80 KB for STM32L152RE)
|
__initial_sp EQU 0x20014000 ; Top of RAM (80 KB)
|
||||||
|
|
||||||
|
|
||||||
; <h> Heap Configuration
|
; <h> Heap Configuration
|
||||||
|
|
@ -129,7 +129,7 @@ __Vectors DCD __initial_sp ; Top of Stack
|
||||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||||
DCD TIM6_IRQHandler ; TIM6
|
DCD TIM6_IRQHandler ; TIM6
|
||||||
DCD TIM7_IRQHandler ; TIM7
|
DCD TIM7_IRQHandler ; TIM7
|
||||||
DCD SDIO_IRQHandler ; SDIO
|
DCD 0 ; Reserved
|
||||||
DCD TIM5_IRQHandler ; TIM5
|
DCD TIM5_IRQHandler ; TIM5
|
||||||
DCD SPI3_IRQHandler ; SPI3
|
DCD SPI3_IRQHandler ; SPI3
|
||||||
DCD UART4_IRQHandler ; UART4
|
DCD UART4_IRQHandler ; UART4
|
||||||
|
|
@ -139,7 +139,7 @@ __Vectors DCD __initial_sp ; Top of Stack
|
||||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||||
DCD AES_IRQHandler ; AES
|
DCD 0 ; Reserved
|
||||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
||||||
|
|
||||||
__Vectors_End
|
__Vectors_End
|
||||||
|
|
@ -250,7 +250,6 @@ Default_Handler PROC
|
||||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK]
|
EXPORT USB_FS_WKUP_IRQHandler [WEAK]
|
||||||
EXPORT TIM6_IRQHandler [WEAK]
|
EXPORT TIM6_IRQHandler [WEAK]
|
||||||
EXPORT TIM7_IRQHandler [WEAK]
|
EXPORT TIM7_IRQHandler [WEAK]
|
||||||
EXPORT SDIO_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM5_IRQHandler [WEAK]
|
EXPORT TIM5_IRQHandler [WEAK]
|
||||||
EXPORT SPI3_IRQHandler [WEAK]
|
EXPORT SPI3_IRQHandler [WEAK]
|
||||||
EXPORT UART4_IRQHandler [WEAK]
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
|
@ -260,7 +259,6 @@ Default_Handler PROC
|
||||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
||||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
||||||
EXPORT AES_IRQHandler [WEAK]
|
|
||||||
EXPORT COMP_ACQ_IRQHandler [WEAK]
|
EXPORT COMP_ACQ_IRQHandler [WEAK]
|
||||||
|
|
||||||
WWDG_IRQHandler
|
WWDG_IRQHandler
|
||||||
|
|
@ -308,7 +306,6 @@ RTC_Alarm_IRQHandler
|
||||||
USB_FS_WKUP_IRQHandler
|
USB_FS_WKUP_IRQHandler
|
||||||
TIM6_IRQHandler
|
TIM6_IRQHandler
|
||||||
TIM7_IRQHandler
|
TIM7_IRQHandler
|
||||||
SDIO_IRQHandler
|
|
||||||
TIM5_IRQHandler
|
TIM5_IRQHandler
|
||||||
SPI3_IRQHandler
|
SPI3_IRQHandler
|
||||||
UART4_IRQHandler
|
UART4_IRQHandler
|
||||||
|
|
@ -318,7 +315,6 @@ DMA2_Channel2_IRQHandler
|
||||||
DMA2_Channel3_IRQHandler
|
DMA2_Channel3_IRQHandler
|
||||||
DMA2_Channel4_IRQHandler
|
DMA2_Channel4_IRQHandler
|
||||||
DMA2_Channel5_IRQHandler
|
DMA2_Channel5_IRQHandler
|
||||||
AES_IRQHandler
|
|
||||||
COMP_ACQ_IRQHandler
|
COMP_ACQ_IRQHandler
|
||||||
|
|
||||||
B .
|
B .
|
||||||
|
|
@ -1,4 +1,4 @@
|
||||||
; STM32L1xx Ultra Low Power High-density Devices vector table for MDK ARM_STD toolchain
|
; STM32L152RE Ultra Low Power High-density Devices vector table for MDK ARM_STD toolchain
|
||||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
; Copyright (c) 2014, STMicroelectronics
|
; Copyright (c) 2014, STMicroelectronics
|
||||||
; All rights reserved.
|
; All rights reserved.
|
||||||
|
|
@ -27,7 +27,7 @@
|
||||||
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
|
||||||
__initial_sp EQU 0x20014000 ; Top of RAM (512 KB)
|
__initial_sp EQU 0x20014000 ; Top of RAM (80 KB)
|
||||||
|
|
||||||
PRESERVE8
|
PRESERVE8
|
||||||
THUMB
|
THUMB
|
||||||
|
|
@ -102,7 +102,7 @@ __Vectors DCD __initial_sp ; Top of Stack
|
||||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||||
DCD TIM6_IRQHandler ; TIM6
|
DCD TIM6_IRQHandler ; TIM6
|
||||||
DCD TIM7_IRQHandler ; TIM7
|
DCD TIM7_IRQHandler ; TIM7
|
||||||
DCD SDIO_IRQHandler ; SDIO
|
DCD 0 ; Reserved
|
||||||
DCD TIM5_IRQHandler ; TIM5
|
DCD TIM5_IRQHandler ; TIM5
|
||||||
DCD SPI3_IRQHandler ; SPI3
|
DCD SPI3_IRQHandler ; SPI3
|
||||||
DCD UART4_IRQHandler ; UART4
|
DCD UART4_IRQHandler ; UART4
|
||||||
|
|
@ -112,7 +112,7 @@ __Vectors DCD __initial_sp ; Top of Stack
|
||||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||||
DCD AES_IRQHandler ; AES
|
DCD 0 ; Reserved
|
||||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
||||||
|
|
||||||
__Vectors_End
|
__Vectors_End
|
||||||
|
|
@ -223,7 +223,6 @@ Default_Handler PROC
|
||||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK]
|
EXPORT USB_FS_WKUP_IRQHandler [WEAK]
|
||||||
EXPORT TIM6_IRQHandler [WEAK]
|
EXPORT TIM6_IRQHandler [WEAK]
|
||||||
EXPORT TIM7_IRQHandler [WEAK]
|
EXPORT TIM7_IRQHandler [WEAK]
|
||||||
EXPORT SDIO_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM5_IRQHandler [WEAK]
|
EXPORT TIM5_IRQHandler [WEAK]
|
||||||
EXPORT SPI3_IRQHandler [WEAK]
|
EXPORT SPI3_IRQHandler [WEAK]
|
||||||
EXPORT UART4_IRQHandler [WEAK]
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
|
@ -233,7 +232,6 @@ Default_Handler PROC
|
||||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
||||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
||||||
EXPORT AES_IRQHandler [WEAK]
|
|
||||||
EXPORT COMP_ACQ_IRQHandler [WEAK]
|
EXPORT COMP_ACQ_IRQHandler [WEAK]
|
||||||
|
|
||||||
WWDG_IRQHandler
|
WWDG_IRQHandler
|
||||||
|
|
@ -281,7 +279,6 @@ RTC_Alarm_IRQHandler
|
||||||
USB_FS_WKUP_IRQHandler
|
USB_FS_WKUP_IRQHandler
|
||||||
TIM6_IRQHandler
|
TIM6_IRQHandler
|
||||||
TIM7_IRQHandler
|
TIM7_IRQHandler
|
||||||
SDIO_IRQHandler
|
|
||||||
TIM5_IRQHandler
|
TIM5_IRQHandler
|
||||||
SPI3_IRQHandler
|
SPI3_IRQHandler
|
||||||
UART4_IRQHandler
|
UART4_IRQHandler
|
||||||
|
|
@ -291,7 +288,6 @@ DMA2_Channel2_IRQHandler
|
||||||
DMA2_Channel3_IRQHandler
|
DMA2_Channel3_IRQHandler
|
||||||
DMA2_Channel4_IRQHandler
|
DMA2_Channel4_IRQHandler
|
||||||
DMA2_Channel5_IRQHandler
|
DMA2_Channel5_IRQHandler
|
||||||
AES_IRQHandler
|
|
||||||
COMP_ACQ_IRQHandler
|
COMP_ACQ_IRQHandler
|
||||||
|
|
||||||
B .
|
B .
|
||||||
|
|
@ -32,7 +32,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
// STM32F152RE
|
// STM32L152RE
|
||||||
// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
|
// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
|
||||||
// MCU Peripherals: 57 vectors = 228 bytes from 0x40 to 0x123
|
// MCU Peripherals: 57 vectors = 228 bytes from 0x40 to 0x123
|
||||||
// Total: 73 vectors = 292 bytes (0x124) to be reserved in RAM (see scatter file)
|
// Total: 73 vectors = 292 bytes (0x124) to be reserved in RAM (see scatter file)
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,121 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file hal_tick.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief Initialization of HAL tick
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
#include "hal_tick.h"
|
||||||
|
|
||||||
|
TIM_HandleTypeDef TimMasterHandle;
|
||||||
|
uint32_t PreviousVal = 0;
|
||||||
|
|
||||||
|
void us_ticker_irq_handler(void);
|
||||||
|
|
||||||
|
void timer_irq_handler(void) {
|
||||||
|
// Channel 1 for mbed timeout
|
||||||
|
if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
|
||||||
|
us_ticker_irq_handler();
|
||||||
|
}
|
||||||
|
|
||||||
|
// Channel 2 for HAL tick
|
||||||
|
if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
|
||||||
|
__HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
|
||||||
|
uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
|
||||||
|
if ((val - PreviousVal) >= HAL_TICK_DELAY) {
|
||||||
|
// Increment HAL variable
|
||||||
|
HAL_IncTick();
|
||||||
|
// Prepare next interrupt
|
||||||
|
__HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
|
||||||
|
PreviousVal = val;
|
||||||
|
#if 0 // For DEBUG only
|
||||||
|
HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Reconfigure the HAL tick using a standard timer instead of systick.
|
||||||
|
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
|
||||||
|
// Enable timer clock
|
||||||
|
TIM_MST_RCC;
|
||||||
|
|
||||||
|
// Reset timer
|
||||||
|
TIM_MST_RESET_ON;
|
||||||
|
TIM_MST_RESET_OFF;
|
||||||
|
|
||||||
|
// Update the SystemCoreClock variable
|
||||||
|
SystemCoreClockUpdate();
|
||||||
|
|
||||||
|
// Configure time base
|
||||||
|
TimMasterHandle.Instance = TIM_MST;
|
||||||
|
TimMasterHandle.Init.Period = 0xFFFFFFFF;
|
||||||
|
TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick
|
||||||
|
TimMasterHandle.Init.ClockDivision = 0;
|
||||||
|
TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
|
||||||
|
HAL_TIM_OC_Init(&TimMasterHandle);
|
||||||
|
|
||||||
|
NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
|
||||||
|
NVIC_EnableIRQ(TIM_MST_IRQ);
|
||||||
|
|
||||||
|
// Channel 1 for mbed timeout
|
||||||
|
HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
|
||||||
|
|
||||||
|
// Channel 2 for HAL tick
|
||||||
|
HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
|
||||||
|
PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
|
||||||
|
__HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
|
||||||
|
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
|
||||||
|
|
||||||
|
#if 0 // For DEBUG only
|
||||||
|
__GPIOB_CLK_ENABLE();
|
||||||
|
GPIO_InitTypeDef GPIO_InitStruct;
|
||||||
|
GPIO_InitStruct.Pin = GPIO_PIN_6;
|
||||||
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||||
|
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||||
|
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
|
||||||
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,60 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file hal_tick.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief Initialization of HAL tick
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
#ifndef __HAL_TICK_H
|
||||||
|
#define __HAL_TICK_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "stm32l1xx.h"
|
||||||
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
|
#define TIM_MST TIM5
|
||||||
|
#define TIM_MST_IRQ TIM5_IRQn
|
||||||
|
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
|
||||||
|
|
||||||
|
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
|
||||||
|
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
|
||||||
|
|
||||||
|
#define HAL_TICK_DELAY (1000) // 1 ms
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif // __HAL_TICK_H
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -1,261 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file misc.c
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @version V1.3.0
|
|
||||||
* @date 31-January-2014
|
|
||||||
* @brief This file provides all the miscellaneous firmware functions (add-on
|
|
||||||
* to CMSIS functions).
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "misc.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup MISC
|
|
||||||
* @brief MISC driver modules
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/
|
|
||||||
/* Private define ------------------------------------------------------------*/
|
|
||||||
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
|
|
||||||
|
|
||||||
/* Private macro -------------------------------------------------------------*/
|
|
||||||
/* Private variables ---------------------------------------------------------*/
|
|
||||||
/* Private function prototypes -----------------------------------------------*/
|
|
||||||
/* Private functions ---------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup MISC_Private_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/**
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
*******************************************************************************
|
|
||||||
##### Interrupts configuration functions #####
|
|
||||||
*******************************************************************************
|
|
||||||
[..] This section provide functions allowing to configure the NVIC interrupts
|
|
||||||
(IRQ).The Cortex-M3 exceptions are managed by CMSIS functions.
|
|
||||||
(#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
|
|
||||||
function according to the following table.
|
|
||||||
The table below gives the allowed values of the preemption priority
|
|
||||||
and subpriority according to the Priority Grouping configuration
|
|
||||||
performed by NVIC_PriorityGroupConfig function.
|
|
||||||
============================================================================================================================
|
|
||||||
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
|
||||||
============================================================================================================================
|
|
||||||
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for preemption priority
|
|
||||||
| | | 4 bits for subpriority
|
|
||||||
----------------------------------------------------------------------------------------------------------------------------
|
|
||||||
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for preemption priority
|
|
||||||
| | | 3 bits for subpriority
|
|
||||||
----------------------------------------------------------------------------------------------------------------------------
|
|
||||||
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for preemption priority
|
|
||||||
| | | 2 bits for subpriority
|
|
||||||
----------------------------------------------------------------------------------------------------------------------------
|
|
||||||
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for preemption priority
|
|
||||||
| | | 1 bits for subpriority
|
|
||||||
----------------------------------------------------------------------------------------------------------------------------
|
|
||||||
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for preemption priority
|
|
||||||
| | | 0 bits for subpriority
|
|
||||||
============================================================================================================================
|
|
||||||
|
|
||||||
|
|
||||||
(#) Enable and Configure the priority of the selected IRQ Channels.
|
|
||||||
|
|
||||||
-@- When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt,
|
|
||||||
the IRQ priority will be managed only by subpriority.
|
|
||||||
The sub-priority is only used to sort pending exception priorities,
|
|
||||||
and does not affect active exceptions.
|
|
||||||
-@- Lower priority values gives higher priority.
|
|
||||||
-@- Priority Order:
|
|
||||||
(#@) Lowest Preemption priority.
|
|
||||||
(#@) Lowest Subpriority.
|
|
||||||
(#@) Lowest hardware priority (IRQn position).
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Configures the priority grouping: preemption priority and subpriority.
|
|
||||||
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg NVIC_PriorityGroup_0: 0 bits for preemption priority
|
|
||||||
* 4 bits for subpriority.
|
|
||||||
* @note When NVIC_PriorityGroup_0 is selected, it will no be any nested
|
|
||||||
* interrupt. This interrupts priority is managed only with subpriority.
|
|
||||||
* @arg NVIC_PriorityGroup_1: 1 bits for preemption priority.
|
|
||||||
* 3 bits for subpriority.
|
|
||||||
* @arg NVIC_PriorityGroup_2: 2 bits for preemption priority.
|
|
||||||
* 2 bits for subpriority.
|
|
||||||
* @arg NVIC_PriorityGroup_3: 3 bits for preemption priority.
|
|
||||||
* 1 bits for subpriority.
|
|
||||||
* @arg NVIC_PriorityGroup_4: 4 bits for preemption priority.
|
|
||||||
* 0 bits for subpriority.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
|
|
||||||
|
|
||||||
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
|
|
||||||
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initializes the NVIC peripheral according to the specified
|
|
||||||
* parameters in the NVIC_InitStruct.
|
|
||||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
|
|
||||||
* function should be called before.
|
|
||||||
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
|
|
||||||
* the configuration information for the specified NVIC peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
|
|
||||||
{
|
|
||||||
uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
|
|
||||||
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
|
|
||||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
|
|
||||||
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
|
|
||||||
|
|
||||||
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
|
|
||||||
{
|
|
||||||
/* Compute the Corresponding IRQ Priority --------------------------------*/
|
|
||||||
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
|
|
||||||
tmppre = (0x4 - tmppriority);
|
|
||||||
tmpsub = tmpsub >> tmppriority;
|
|
||||||
|
|
||||||
tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
|
|
||||||
tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
|
|
||||||
tmppriority = tmppriority << 0x04;
|
|
||||||
|
|
||||||
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
|
|
||||||
|
|
||||||
/* Enable the Selected IRQ Channels --------------------------------------*/
|
|
||||||
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
|
||||||
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Disable the Selected IRQ Channels -------------------------------------*/
|
|
||||||
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
|
||||||
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Sets the vector table location and Offset.
|
|
||||||
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
|
|
||||||
* @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
|
|
||||||
* @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
|
|
||||||
assert_param(IS_NVIC_OFFSET(Offset));
|
|
||||||
|
|
||||||
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Selects the condition for the system to enter low power mode.
|
|
||||||
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
|
|
||||||
* @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
|
|
||||||
* @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
|
|
||||||
* @param NewState: new state of LP condition.
|
|
||||||
* This parameter can be: ENABLE or DISABLE.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_NVIC_LP(LowPowerMode));
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
SCB->SCR |= LowPowerMode;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Configures the SysTick clock source.
|
|
||||||
* @param SysTick_CLKSource: specifies the SysTick clock source.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
|
|
||||||
* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
|
|
||||||
|
|
||||||
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
|
|
||||||
{
|
|
||||||
SysTick->CTRL |= SysTick_CLKSource_HCLK;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,212 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file misc.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @version V1.3.0
|
|
||||||
* @date 31-January-2014
|
|
||||||
* @brief This file contains all the functions prototypes for the miscellaneous
|
|
||||||
* firmware library functions (add-on to CMSIS functions).
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef __MISC_H
|
|
||||||
#define __MISC_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32l1xx.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup MISC
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief NVIC Init Structure definition
|
|
||||||
*/
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
|
|
||||||
This parameter can be a value of @ref IRQn_Type
|
|
||||||
(For the complete STM32 Devices IRQ Channels list, please
|
|
||||||
refer to stm32l1xx.h file) */
|
|
||||||
|
|
||||||
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
|
|
||||||
specified in NVIC_IRQChannel. This parameter can be a value
|
|
||||||
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
|
|
||||||
|
|
||||||
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
|
|
||||||
in NVIC_IRQChannel. This parameter can be a value
|
|
||||||
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
|
|
||||||
|
|
||||||
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
|
|
||||||
will be enabled or disabled.
|
|
||||||
This parameter can be set either to ENABLE or DISABLE */
|
|
||||||
} NVIC_InitTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
The table below gives the allowed values of the pre-emption priority and subpriority according
|
|
||||||
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
|
|
||||||
============================================================================================================================
|
|
||||||
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
|
||||||
============================================================================================================================
|
|
||||||
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
|
|
||||||
| | | 4 bits for subpriority
|
|
||||||
----------------------------------------------------------------------------------------------------------------------------
|
|
||||||
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
|
|
||||||
| | | 3 bits for subpriority
|
|
||||||
----------------------------------------------------------------------------------------------------------------------------
|
|
||||||
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
|
|
||||||
| | | 2 bits for subpriority
|
|
||||||
----------------------------------------------------------------------------------------------------------------------------
|
|
||||||
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
|
|
||||||
| | | 1 bits for subpriority
|
|
||||||
----------------------------------------------------------------------------------------------------------------------------
|
|
||||||
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
|
|
||||||
| | | 0 bits for subpriority
|
|
||||||
============================================================================================================================
|
|
||||||
@endverbatim
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup MISC_Exported_Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup Vector_Table_Base
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
|
|
||||||
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
|
|
||||||
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
|
|
||||||
((VECTTAB) == NVIC_VectTab_FLASH))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup System_Low_Power
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
|
|
||||||
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
|
|
||||||
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
|
|
||||||
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
|
|
||||||
((LP) == NVIC_LP_SLEEPDEEP) || \
|
|
||||||
((LP) == NVIC_LP_SLEEPONEXIT))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup Preemption_Priority_Group
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
|
|
||||||
4 bits for subpriority */
|
|
||||||
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
|
|
||||||
3 bits for subpriority */
|
|
||||||
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
|
|
||||||
2 bits for subpriority */
|
|
||||||
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
|
|
||||||
1 bits for subpriority */
|
|
||||||
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
|
|
||||||
0 bits for subpriority */
|
|
||||||
|
|
||||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
|
|
||||||
((GROUP) == NVIC_PriorityGroup_1) || \
|
|
||||||
((GROUP) == NVIC_PriorityGroup_2) || \
|
|
||||||
((GROUP) == NVIC_PriorityGroup_3) || \
|
|
||||||
((GROUP) == NVIC_PriorityGroup_4))
|
|
||||||
|
|
||||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
|
||||||
|
|
||||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
|
||||||
|
|
||||||
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0005FFFF)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SysTick_clock_source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
|
||||||
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
|
||||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
|
|
||||||
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
/* Exported functions ------------------------------------------------------- */
|
|
||||||
|
|
||||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
|
|
||||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
|
|
||||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
|
|
||||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
|
|
||||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __MISC_H */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,660 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32l1xx_adc.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @version V1.3.0
|
|
||||||
* @date 31-January-2014
|
|
||||||
* @brief This file contains all the functions prototypes for the ADC firmware
|
|
||||||
* library.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef __STM32L1xx_ADC_H
|
|
||||||
#define __STM32L1xx_ADC_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32l1xx.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup ADC
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief ADC Init structure definition
|
|
||||||
*/
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion.
|
|
||||||
This parameter can be a value of @ref ADC_Resolution */
|
|
||||||
|
|
||||||
FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
|
|
||||||
Scan (multichannel) or Single (one channel) mode.
|
|
||||||
This parameter can be set to ENABLE or DISABLE */
|
|
||||||
|
|
||||||
FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
|
|
||||||
Continuous or Single mode.
|
|
||||||
This parameter can be set to ENABLE or DISABLE. */
|
|
||||||
|
|
||||||
uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the
|
|
||||||
trigger of a regular group. This parameter can be a value
|
|
||||||
of @ref ADC_external_trigger_edge_for_regular_channels_conversion */
|
|
||||||
|
|
||||||
uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
|
|
||||||
to digital conversion of regular channels. This parameter
|
|
||||||
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
|
|
||||||
|
|
||||||
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
|
|
||||||
This parameter can be a value of @ref ADC_data_align */
|
|
||||||
|
|
||||||
uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done
|
|
||||||
using the sequencer for regular channel group.
|
|
||||||
This parameter must range from 1 to 27. */
|
|
||||||
}ADC_InitTypeDef;
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t ADC_Prescaler; /*!< Selects the ADC prescaler.
|
|
||||||
This parameter can be a value
|
|
||||||
of @ref ADC_Prescaler */
|
|
||||||
}ADC_CommonInitTypeDef;
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_Exported_Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)
|
|
||||||
#define IS_ADC_DMA_PERIPH(PERIPH) ((PERIPH) == ADC1)
|
|
||||||
|
|
||||||
/** @defgroup ADC_Power_down_during_Idle_and_or_Delay_phase
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define ADC_PowerDown_Delay ((uint32_t)0x00010000)
|
|
||||||
#define ADC_PowerDown_Idle ((uint32_t)0x00020000)
|
|
||||||
#define ADC_PowerDown_Idle_Delay ((uint32_t)0x00030000)
|
|
||||||
|
|
||||||
#define IS_ADC_POWER_DOWN(DWON) (((DWON) == ADC_PowerDown_Delay) || \
|
|
||||||
((DWON) == ADC_PowerDown_Idle) || \
|
|
||||||
((DWON) == ADC_PowerDown_Idle_Delay))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup ADC_Prescaler
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define ADC_Prescaler_Div1 ((uint32_t)0x00000000)
|
|
||||||
#define ADC_Prescaler_Div2 ((uint32_t)0x00010000)
|
|
||||||
#define ADC_Prescaler_Div4 ((uint32_t)0x00020000)
|
|
||||||
|
|
||||||
#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div1) || \
|
|
||||||
((PRESCALER) == ADC_Prescaler_Div2) || \
|
|
||||||
((PRESCALER) == ADC_Prescaler_Div4))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup ADC_Resolution
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define ADC_Resolution_12b ((uint32_t)0x00000000)
|
|
||||||
#define ADC_Resolution_10b ((uint32_t)0x01000000)
|
|
||||||
#define ADC_Resolution_8b ((uint32_t)0x02000000)
|
|
||||||
#define ADC_Resolution_6b ((uint32_t)0x03000000)
|
|
||||||
|
|
||||||
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
|
|
||||||
((RESOLUTION) == ADC_Resolution_10b) || \
|
|
||||||
((RESOLUTION) == ADC_Resolution_8b) || \
|
|
||||||
((RESOLUTION) == ADC_Resolution_6b))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
|
|
||||||
#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)
|
|
||||||
#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)
|
|
||||||
#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
|
|
||||||
|
|
||||||
#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
|
|
||||||
((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
|
|
||||||
((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
|
|
||||||
((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* TIM2 */
|
|
||||||
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x02000000)
|
|
||||||
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)
|
|
||||||
#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)
|
|
||||||
|
|
||||||
/* TIM3 */
|
|
||||||
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)
|
|
||||||
#define ADC_ExternalTrigConv_T3_CC3 ((uint32_t)0x08000000)
|
|
||||||
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x04000000)
|
|
||||||
|
|
||||||
/* TIM4 */
|
|
||||||
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x05000000)
|
|
||||||
#define ADC_ExternalTrigConv_T4_TRGO ((uint32_t)0x09000000)
|
|
||||||
|
|
||||||
/* TIM6 */
|
|
||||||
#define ADC_ExternalTrigConv_T6_TRGO ((uint32_t)0x0A000000)
|
|
||||||
|
|
||||||
/* TIM9 */
|
|
||||||
#define ADC_ExternalTrigConv_T9_CC2 ((uint32_t)0x00000000)
|
|
||||||
#define ADC_ExternalTrigConv_T9_TRGO ((uint32_t)0x01000000)
|
|
||||||
|
|
||||||
/* EXTI */
|
|
||||||
#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)
|
|
||||||
|
|
||||||
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T9_CC2) || \
|
|
||||||
((REGTRIG) == ADC_ExternalTrigConv_T9_TRGO) || \
|
|
||||||
((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
|
|
||||||
((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
|
|
||||||
((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
|
|
||||||
((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
|
|
||||||
((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
|
|
||||||
((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
|
|
||||||
((REGTRIG) == ADC_ExternalTrigConv_T3_CC3) || \
|
|
||||||
((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \
|
|
||||||
((REGTRIG) == ADC_ExternalTrigConv_T6_TRGO) || \
|
|
||||||
((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_data_align
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
|
|
||||||
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
|
|
||||||
|
|
||||||
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
|
|
||||||
((ALIGN) == ADC_DataAlign_Left))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_channels
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* ADC Bank A Channels -------------------------------------------------------*/
|
|
||||||
#define ADC_Channel_0 ((uint8_t)0x00)
|
|
||||||
#define ADC_Channel_1 ((uint8_t)0x01)
|
|
||||||
#define ADC_Channel_2 ((uint8_t)0x02)
|
|
||||||
#define ADC_Channel_3 ((uint8_t)0x03)
|
|
||||||
|
|
||||||
#define ADC_Channel_6 ((uint8_t)0x06)
|
|
||||||
#define ADC_Channel_7 ((uint8_t)0x07)
|
|
||||||
#define ADC_Channel_8 ((uint8_t)0x08)
|
|
||||||
#define ADC_Channel_9 ((uint8_t)0x09)
|
|
||||||
#define ADC_Channel_10 ((uint8_t)0x0A)
|
|
||||||
#define ADC_Channel_11 ((uint8_t)0x0B)
|
|
||||||
#define ADC_Channel_12 ((uint8_t)0x0C)
|
|
||||||
|
|
||||||
|
|
||||||
/* ADC Bank B Channels -------------------------------------------------------*/
|
|
||||||
#define ADC_Channel_0b ADC_Channel_0
|
|
||||||
#define ADC_Channel_1b ADC_Channel_1
|
|
||||||
#define ADC_Channel_2b ADC_Channel_2
|
|
||||||
#define ADC_Channel_3b ADC_Channel_3
|
|
||||||
|
|
||||||
#define ADC_Channel_6b ADC_Channel_6
|
|
||||||
#define ADC_Channel_7b ADC_Channel_7
|
|
||||||
#define ADC_Channel_8b ADC_Channel_8
|
|
||||||
#define ADC_Channel_9b ADC_Channel_9
|
|
||||||
#define ADC_Channel_10b ADC_Channel_10
|
|
||||||
#define ADC_Channel_11b ADC_Channel_11
|
|
||||||
#define ADC_Channel_12b ADC_Channel_12
|
|
||||||
|
|
||||||
/* ADC Common Channels (ADC Bank A and B) ------------------------------------*/
|
|
||||||
#define ADC_Channel_4 ((uint8_t)0x04)
|
|
||||||
#define ADC_Channel_5 ((uint8_t)0x05)
|
|
||||||
|
|
||||||
#define ADC_Channel_13 ((uint8_t)0x0D)
|
|
||||||
#define ADC_Channel_14 ((uint8_t)0x0E)
|
|
||||||
#define ADC_Channel_15 ((uint8_t)0x0F)
|
|
||||||
#define ADC_Channel_16 ((uint8_t)0x10)
|
|
||||||
#define ADC_Channel_17 ((uint8_t)0x11)
|
|
||||||
#define ADC_Channel_18 ((uint8_t)0x12)
|
|
||||||
#define ADC_Channel_19 ((uint8_t)0x13)
|
|
||||||
#define ADC_Channel_20 ((uint8_t)0x14)
|
|
||||||
#define ADC_Channel_21 ((uint8_t)0x15)
|
|
||||||
#define ADC_Channel_22 ((uint8_t)0x16)
|
|
||||||
#define ADC_Channel_23 ((uint8_t)0x17)
|
|
||||||
#define ADC_Channel_24 ((uint8_t)0x18)
|
|
||||||
#define ADC_Channel_25 ((uint8_t)0x19)
|
|
||||||
|
|
||||||
#define ADC_Channel_27 ((uint8_t)0x1B)
|
|
||||||
#define ADC_Channel_28 ((uint8_t)0x1C)
|
|
||||||
#define ADC_Channel_29 ((uint8_t)0x1D)
|
|
||||||
#define ADC_Channel_30 ((uint8_t)0x1E)
|
|
||||||
#define ADC_Channel_31 ((uint8_t)0x1F)
|
|
||||||
|
|
||||||
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
|
|
||||||
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
|
|
||||||
|
|
||||||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
|
|
||||||
((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
|
|
||||||
((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
|
|
||||||
((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
|
|
||||||
((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
|
|
||||||
((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
|
|
||||||
((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
|
|
||||||
((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
|
|
||||||
((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17) || \
|
|
||||||
((CHANNEL) == ADC_Channel_18) || ((CHANNEL) == ADC_Channel_19) || \
|
|
||||||
((CHANNEL) == ADC_Channel_20) || ((CHANNEL) == ADC_Channel_21) || \
|
|
||||||
((CHANNEL) == ADC_Channel_22) || ((CHANNEL) == ADC_Channel_23) || \
|
|
||||||
((CHANNEL) == ADC_Channel_24) || ((CHANNEL) == ADC_Channel_25) || \
|
|
||||||
((CHANNEL) == ADC_Channel_27) || ((CHANNEL) == ADC_Channel_28) || \
|
|
||||||
((CHANNEL) == ADC_Channel_29) || ((CHANNEL) == ADC_Channel_30) || \
|
|
||||||
((CHANNEL) == ADC_Channel_31))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_sampling_times
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define ADC_SampleTime_4Cycles ((uint8_t)0x00)
|
|
||||||
#define ADC_SampleTime_9Cycles ((uint8_t)0x01)
|
|
||||||
#define ADC_SampleTime_16Cycles ((uint8_t)0x02)
|
|
||||||
#define ADC_SampleTime_24Cycles ((uint8_t)0x03)
|
|
||||||
#define ADC_SampleTime_48Cycles ((uint8_t)0x04)
|
|
||||||
#define ADC_SampleTime_96Cycles ((uint8_t)0x05)
|
|
||||||
#define ADC_SampleTime_192Cycles ((uint8_t)0x06)
|
|
||||||
#define ADC_SampleTime_384Cycles ((uint8_t)0x07)
|
|
||||||
|
|
||||||
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_4Cycles) || \
|
|
||||||
((TIME) == ADC_SampleTime_9Cycles) || \
|
|
||||||
((TIME) == ADC_SampleTime_16Cycles) || \
|
|
||||||
((TIME) == ADC_SampleTime_24Cycles) || \
|
|
||||||
((TIME) == ADC_SampleTime_48Cycles) || \
|
|
||||||
((TIME) == ADC_SampleTime_96Cycles) || \
|
|
||||||
((TIME) == ADC_SampleTime_192Cycles) || \
|
|
||||||
((TIME) == ADC_SampleTime_384Cycles))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_Delay_length
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define ADC_DelayLength_None ((uint8_t)0x00)
|
|
||||||
#define ADC_DelayLength_Freeze ((uint8_t)0x10)
|
|
||||||
#define ADC_DelayLength_7Cycles ((uint8_t)0x20)
|
|
||||||
#define ADC_DelayLength_15Cycles ((uint8_t)0x30)
|
|
||||||
#define ADC_DelayLength_31Cycles ((uint8_t)0x40)
|
|
||||||
#define ADC_DelayLength_63Cycles ((uint8_t)0x50)
|
|
||||||
#define ADC_DelayLength_127Cycles ((uint8_t)0x60)
|
|
||||||
#define ADC_DelayLength_255Cycles ((uint8_t)0x70)
|
|
||||||
|
|
||||||
#define IS_ADC_DELAY_LENGTH(LENGTH) (((LENGTH) == ADC_DelayLength_None) || \
|
|
||||||
((LENGTH) == ADC_DelayLength_Freeze) || \
|
|
||||||
((LENGTH) == ADC_DelayLength_7Cycles) || \
|
|
||||||
((LENGTH) == ADC_DelayLength_15Cycles) || \
|
|
||||||
((LENGTH) == ADC_DelayLength_31Cycles) || \
|
|
||||||
((LENGTH) == ADC_DelayLength_63Cycles) || \
|
|
||||||
((LENGTH) == ADC_DelayLength_127Cycles) || \
|
|
||||||
((LENGTH) == ADC_DelayLength_255Cycles))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)
|
|
||||||
#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)
|
|
||||||
#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)
|
|
||||||
#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
|
|
||||||
|
|
||||||
#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
|
|
||||||
((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
|
|
||||||
((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
|
|
||||||
((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* TIM2 */
|
|
||||||
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00020000)
|
|
||||||
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00030000)
|
|
||||||
|
|
||||||
/* TIM3 */
|
|
||||||
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00040000)
|
|
||||||
|
|
||||||
/* TIM4 */
|
|
||||||
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00050000)
|
|
||||||
#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)
|
|
||||||
#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)
|
|
||||||
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)
|
|
||||||
|
|
||||||
/* TIM7 */
|
|
||||||
#define ADC_ExternalTrigInjecConv_T7_TRGO ((uint32_t)0x000A0000)
|
|
||||||
|
|
||||||
/* TIM9 */
|
|
||||||
#define ADC_ExternalTrigInjecConv_T9_CC1 ((uint32_t)0x00000000)
|
|
||||||
#define ADC_ExternalTrigInjecConv_T9_TRGO ((uint32_t)0x00010000)
|
|
||||||
|
|
||||||
/* TIM10 */
|
|
||||||
#define ADC_ExternalTrigInjecConv_T10_CC1 ((uint32_t)0x00090000)
|
|
||||||
|
|
||||||
/* EXTI */
|
|
||||||
#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)
|
|
||||||
|
|
||||||
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T9_CC1) || \
|
|
||||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T9_TRGO) || \
|
|
||||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
|
|
||||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
|
|
||||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
|
|
||||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
|
|
||||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
|
|
||||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
|
|
||||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
|
|
||||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T10_CC1) || \
|
|
||||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T7_TRGO) || \
|
|
||||||
((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_injected_channel_selection
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define ADC_InjectedChannel_1 ((uint8_t)0x18)
|
|
||||||
#define ADC_InjectedChannel_2 ((uint8_t)0x1C)
|
|
||||||
#define ADC_InjectedChannel_3 ((uint8_t)0x20)
|
|
||||||
#define ADC_InjectedChannel_4 ((uint8_t)0x24)
|
|
||||||
|
|
||||||
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
|
|
||||||
((CHANNEL) == ADC_InjectedChannel_2) || \
|
|
||||||
((CHANNEL) == ADC_InjectedChannel_3) || \
|
|
||||||
((CHANNEL) == ADC_InjectedChannel_4))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_analog_watchdog_selection
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
|
|
||||||
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
|
|
||||||
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
|
|
||||||
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
|
|
||||||
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
|
|
||||||
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
|
|
||||||
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
|
|
||||||
|
|
||||||
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
|
|
||||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
|
|
||||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
|
|
||||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
|
|
||||||
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
|
|
||||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
|
|
||||||
((WATCHDOG) == ADC_AnalogWatchdog_None))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_interrupts_definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define ADC_IT_AWD ((uint16_t)0x0106)
|
|
||||||
#define ADC_IT_EOC ((uint16_t)0x0205)
|
|
||||||
#define ADC_IT_JEOC ((uint16_t)0x0407)
|
|
||||||
#define ADC_IT_OVR ((uint16_t)0x201A)
|
|
||||||
|
|
||||||
#define IS_ADC_IT(IT) (((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_EOC) || \
|
|
||||||
((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_flags_definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define ADC_FLAG_AWD ((uint16_t)0x0001)
|
|
||||||
#define ADC_FLAG_EOC ((uint16_t)0x0002)
|
|
||||||
#define ADC_FLAG_JEOC ((uint16_t)0x0004)
|
|
||||||
#define ADC_FLAG_JSTRT ((uint16_t)0x0008)
|
|
||||||
#define ADC_FLAG_STRT ((uint16_t)0x0010)
|
|
||||||
#define ADC_FLAG_OVR ((uint16_t)0x0020)
|
|
||||||
#define ADC_FLAG_ADONS ((uint16_t)0x0040)
|
|
||||||
#define ADC_FLAG_RCNR ((uint16_t)0x0100)
|
|
||||||
#define ADC_FLAG_JCNR ((uint16_t)0x0200)
|
|
||||||
|
|
||||||
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFC0) == 0x00) && ((FLAG) != 0x00))
|
|
||||||
|
|
||||||
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
|
|
||||||
((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
|
|
||||||
((FLAG) == ADC_FLAG_STRT) || ((FLAG)== ADC_FLAG_OVR) || \
|
|
||||||
((FLAG) == ADC_FLAG_ADONS) || ((FLAG)== ADC_FLAG_RCNR) || \
|
|
||||||
((FLAG) == ADC_FLAG_JCNR))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_thresholds
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_injected_offset
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_injected_length
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_injected_rank
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_regular_length
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 28))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_regular_rank
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1) && ((RANK) <= 28))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_regular_discontinuous_mode_number
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_Bank_Selection
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define ADC_Bank_A ((uint8_t)0x00)
|
|
||||||
#define ADC_Bank_B ((uint8_t)0x01)
|
|
||||||
#define IS_ADC_BANK(BANK) (((BANK) == ADC_Bank_A) || ((BANK) == ADC_Bank_B))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
/* Exported functions ------------------------------------------------------- */
|
|
||||||
|
|
||||||
/* Function used to set the ADC configuration to the default reset state *****/
|
|
||||||
void ADC_DeInit(ADC_TypeDef* ADCx);
|
|
||||||
|
|
||||||
/* Initialization and Configuration functions *********************************/
|
|
||||||
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
|
|
||||||
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
|
|
||||||
void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
|
|
||||||
void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
|
|
||||||
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
|
||||||
void ADC_BankSelection(ADC_TypeDef* ADCx, uint8_t ADC_Bank);
|
|
||||||
|
|
||||||
/* Power saving functions *****************************************************/
|
|
||||||
void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState);
|
|
||||||
void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength);
|
|
||||||
|
|
||||||
/* Analog Watchdog configuration functions ************************************/
|
|
||||||
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
|
|
||||||
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
|
|
||||||
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
|
||||||
|
|
||||||
/* Temperature Sensor & Vrefint (Voltage Reference internal) management function */
|
|
||||||
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
|
|
||||||
|
|
||||||
/* Regular Channels Configuration functions ***********************************/
|
|
||||||
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
|
||||||
void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
|
|
||||||
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
|
|
||||||
void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
|
||||||
void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
|
||||||
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
|
|
||||||
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
|
||||||
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
|
|
||||||
|
|
||||||
/* Regular Channels DMA Configuration functions *******************************/
|
|
||||||
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
|
||||||
void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
|
||||||
|
|
||||||
/* Injected channels Configuration functions **********************************/
|
|
||||||
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
|
||||||
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
|
|
||||||
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
|
|
||||||
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
|
|
||||||
void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
|
|
||||||
void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
|
|
||||||
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
|
|
||||||
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
|
||||||
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
|
||||||
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
|
|
||||||
|
|
||||||
/* Interrupts and flags management functions **********************************/
|
|
||||||
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
|
|
||||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);
|
|
||||||
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);
|
|
||||||
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
|
||||||
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /*__STM32L1xx_ADC_H */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,609 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32l1xx_aes.c
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @version V1.3.0
|
|
||||||
* @date 31-January-2014
|
|
||||||
* @brief This file provides firmware functions to manage the following
|
|
||||||
* functionalities of the AES peripheral:
|
|
||||||
* + Configuration
|
|
||||||
* + Read/Write operations
|
|
||||||
* + DMA transfers management
|
|
||||||
* + Interrupts and flags management
|
|
||||||
*
|
|
||||||
* @verbatim
|
|
||||||
===============================================================================
|
|
||||||
##### AES Peripheral features #####
|
|
||||||
===============================================================================
|
|
||||||
....[..]
|
|
||||||
(#) The Advanced Encryption Standard hardware accelerator (AES) can be used
|
|
||||||
to both encipher and decipher data using AES algorithm.
|
|
||||||
(#) The AES supports 4 operation modes:
|
|
||||||
(++) Encryption: It consumes 214 clock cycle when processing one 128-bit block
|
|
||||||
(++) Decryption: It consumes 214 clock cycle when processing one 128-bit block
|
|
||||||
(++) Key derivation for decryption: It consumes 80 clock cycle when processing one 128-bit block
|
|
||||||
(++) Key Derivation and decryption: It consumes 288 clock cycle when processing one 128-bit blobk
|
|
||||||
(#) Moreover 3 chaining modes are supported:
|
|
||||||
(++) Electronic codebook (ECB): Each plain text is encrypted/decrypted separately
|
|
||||||
(++) Cipher block chaining (CBC): Each block is XORed with the previous block
|
|
||||||
(++) Counter mode (CTR): A 128-bit counter is encrypted and then XORed with the
|
|
||||||
plain text to give the cipher text
|
|
||||||
(#) The AES peripheral supports data swapping: 1-bit, 8-bit, 16-bit and 32-bit.
|
|
||||||
(#) The AES peripheral supports write/read error handling with interrupt capability.
|
|
||||||
(#) Automatic data flow control with support of direct memory access (DMA) using
|
|
||||||
2 channels, one for incoming data (DMA2 Channel5), and one for outcoming data
|
|
||||||
(DMA2 Channel3).
|
|
||||||
|
|
||||||
##### How to use this driver #####
|
|
||||||
===============================================================================
|
|
||||||
[..]
|
|
||||||
(#) AES AHB clock must be enabled to get write access to AES registers
|
|
||||||
using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE).
|
|
||||||
(#) Initialize the key using AES_KeyInit().
|
|
||||||
(#) Configure the AES operation mode using AES_Init().
|
|
||||||
(#) If required, enable interrupt source using AES_ITConfig() and
|
|
||||||
enable the AES interrupt vector using NVIC_Init().
|
|
||||||
(#) If required, when using the DMA mode.
|
|
||||||
(##) Configure the DMA using DMA_Init().
|
|
||||||
(##) Enable DMA requests using AES_DMAConfig().
|
|
||||||
(#) Enable the AES peripheral using AES_Cmd().
|
|
||||||
@endverbatim
|
|
||||||
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32l1xx_aes.h"
|
|
||||||
#include "stm32l1xx_rcc.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup AES
|
|
||||||
* @brief AES driver modules
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/
|
|
||||||
/* Private define ------------------------------------------------------------*/
|
|
||||||
#define CR_CLEAR_MASK ((uint32_t)0xFFFFFF81)
|
|
||||||
|
|
||||||
/* Private macro -------------------------------------------------------------*/
|
|
||||||
/* Private variables ---------------------------------------------------------*/
|
|
||||||
/* Private function prototypes -----------------------------------------------*/
|
|
||||||
/* Private functions ---------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup AES_Private_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup AES_Group1 Initialization and configuration
|
|
||||||
* @brief Initialization and configuration.
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
===============================================================================
|
|
||||||
##### Initialization and configuration #####
|
|
||||||
===============================================================================
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Deinitializes AES peripheral registers to their default reset values.
|
|
||||||
* @param None
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void AES_DeInit(void)
|
|
||||||
{
|
|
||||||
/* Enable AES reset state */
|
|
||||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_AES, ENABLE);
|
|
||||||
/* Release AES from reset state */
|
|
||||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_AES, DISABLE);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initializes the AES peripheral according to the specified parameters
|
|
||||||
* in the AES_InitStruct:
|
|
||||||
* - AES_Operation: specifies the operation mode (encryption, decryption...).
|
|
||||||
* - AES_Chaining: specifies the chaining mode (ECB, CBC or CTR).
|
|
||||||
* - AES_DataType: specifies the data swapping type: 32-bit, 16-bit, 8-bit or 1-bit.
|
|
||||||
* @note If AES is already enabled, use AES_Cmd(DISABLE) before setting the new
|
|
||||||
* configuration (When AES is enabled, setting configuration is forbidden).
|
|
||||||
* @param AES_InitStruct: pointer to an AES_InitTypeDef structure that contains
|
|
||||||
* the configuration information for AES peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void AES_Init(AES_InitTypeDef* AES_InitStruct)
|
|
||||||
{
|
|
||||||
uint32_t tmpreg = 0;
|
|
||||||
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_AES_MODE(AES_InitStruct->AES_Operation));
|
|
||||||
assert_param(IS_AES_CHAINING(AES_InitStruct->AES_Chaining));
|
|
||||||
assert_param(IS_AES_DATATYPE(AES_InitStruct->AES_DataType));
|
|
||||||
|
|
||||||
/* Get AES CR register value */
|
|
||||||
tmpreg = AES->CR;
|
|
||||||
|
|
||||||
/* Clear DATATYPE[1:0], MODE[1:0] and CHMOD[1:0] bits */
|
|
||||||
tmpreg &= (uint32_t)CR_CLEAR_MASK;
|
|
||||||
|
|
||||||
tmpreg |= (AES_InitStruct->AES_Operation | AES_InitStruct->AES_Chaining | AES_InitStruct->AES_DataType);
|
|
||||||
|
|
||||||
AES->CR = (uint32_t) tmpreg;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initializes the AES Keys according to the specified parameters in the AES_KeyInitStruct.
|
|
||||||
* @param AES_KeyInitStruct: pointer to an AES_KeyInitTypeDef structure that
|
|
||||||
* contains the configuration information for the specified AES Keys.
|
|
||||||
* @note This function must be called while the AES is disabled.
|
|
||||||
* @note In encryption, key derivation and key derivation + decryption modes,
|
|
||||||
* AES_KeyInitStruct must contain the encryption key.
|
|
||||||
* In decryption mode, AES_KeyInitStruct must contain the decryption key.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void AES_KeyInit(AES_KeyInitTypeDef* AES_KeyInitStruct)
|
|
||||||
{
|
|
||||||
AES->KEYR0 = AES_KeyInitStruct->AES_Key0;
|
|
||||||
AES->KEYR1 = AES_KeyInitStruct->AES_Key1;
|
|
||||||
AES->KEYR2 = AES_KeyInitStruct->AES_Key2;
|
|
||||||
AES->KEYR3 = AES_KeyInitStruct->AES_Key3;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initializes the AES Initialization Vector IV according to
|
|
||||||
* the specified parameters in the AES_IVInitStruct.
|
|
||||||
* @param AES_KeyInitStruct: pointer to an AES_IVInitTypeDef structure that
|
|
||||||
* contains the configuration information for the specified AES IV.
|
|
||||||
* @note When ECB chaining mode is selected, Initialization Vector IV has no
|
|
||||||
* meaning.
|
|
||||||
* When CTR chaining mode is selected, AES_IV0 contains the CTR value.
|
|
||||||
* AES_IV1, AES_IV2 and AES_IV3 contains nonce value.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void AES_IVInit(AES_IVInitTypeDef* AES_IVInitStruct)
|
|
||||||
{
|
|
||||||
AES->IVR0 = AES_IVInitStruct->AES_IV0;
|
|
||||||
AES->IVR1 = AES_IVInitStruct->AES_IV1;
|
|
||||||
AES->IVR2 = AES_IVInitStruct->AES_IV2;
|
|
||||||
AES->IVR3 = AES_IVInitStruct->AES_IV3;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable or disable the AES peripheral.
|
|
||||||
* @param NewState: new state of the AES peripheral.
|
|
||||||
* This parameter can be: ENABLE or DISABLE.
|
|
||||||
* @note The key must be written while AES is disabled.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void AES_Cmd(FunctionalState NewState)
|
|
||||||
{
|
|
||||||
/* Check the parameter */
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
/* Enable the AES peripheral */
|
|
||||||
AES->CR |= (uint32_t) AES_CR_EN; /**< AES Enable */
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Disable the AES peripheral */
|
|
||||||
AES->CR &= (uint32_t)(~AES_CR_EN); /**< AES Disable */
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup AES_Group2 Structures initialization functions
|
|
||||||
* @brief Structures initialization.
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
===============================================================================
|
|
||||||
##### Structures initialization functions #####
|
|
||||||
===============================================================================
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Fills each AES_InitStruct member with its default value.
|
|
||||||
* @param AES_InitStruct: pointer to an AES_InitTypeDef structure which will
|
|
||||||
* be initialized.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void AES_StructInit(AES_InitTypeDef* AES_InitStruct)
|
|
||||||
{
|
|
||||||
AES_InitStruct->AES_Operation = AES_Operation_Encryp;
|
|
||||||
AES_InitStruct->AES_Chaining = AES_Chaining_ECB;
|
|
||||||
AES_InitStruct->AES_DataType = AES_DataType_32b;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Fills each AES_KeyInitStruct member with its default value.
|
|
||||||
* @param AES_KeyInitStruct: pointer to an AES_KeyInitStruct structure which
|
|
||||||
* will be initialized.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void AES_KeyStructInit(AES_KeyInitTypeDef* AES_KeyInitStruct)
|
|
||||||
{
|
|
||||||
AES_KeyInitStruct->AES_Key0 = 0x00000000;
|
|
||||||
AES_KeyInitStruct->AES_Key1 = 0x00000000;
|
|
||||||
AES_KeyInitStruct->AES_Key2 = 0x00000000;
|
|
||||||
AES_KeyInitStruct->AES_Key3 = 0x00000000;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Fills each AES_IVInitStruct member with its default value.
|
|
||||||
* @param AES_IVInitStruct: pointer to an AES_IVInitTypeDef structure which
|
|
||||||
* will be initialized.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void AES_IVStructInit(AES_IVInitTypeDef* AES_IVInitStruct)
|
|
||||||
{
|
|
||||||
AES_IVInitStruct->AES_IV0 = 0x00000000;
|
|
||||||
AES_IVInitStruct->AES_IV1 = 0x00000000;
|
|
||||||
AES_IVInitStruct->AES_IV2 = 0x00000000;
|
|
||||||
AES_IVInitStruct->AES_IV3 = 0x00000000;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup AES_Group3 AES Read and Write
|
|
||||||
* @brief AES Read and Write.
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
===============================================================================
|
|
||||||
##### AES Read and Write functions #####
|
|
||||||
===============================================================================
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Write data in DINR register to be processed by AES peripheral.
|
|
||||||
* @note To process 128-bit data (4 * 32-bit), this function must be called
|
|
||||||
* four times to write the 128-bit data in the 32-bit register DINR.
|
|
||||||
* @note When an unexpected write to DOUTR register is detected, WRERR flag is
|
|
||||||
* set.
|
|
||||||
* @param Data: The data to be processed.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void AES_WriteSubData(uint32_t Data)
|
|
||||||
{
|
|
||||||
/* Write Data */
|
|
||||||
AES->DINR = Data;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Returns the data in DOUTR register processed by AES peripheral.
|
|
||||||
* @note This function must be called four times to get the 128-bit data.
|
|
||||||
* @note When an unexpected read of DINR register is detected, RDERR flag is
|
|
||||||
* set.
|
|
||||||
* @retval The processed data.
|
|
||||||
*/
|
|
||||||
uint32_t AES_ReadSubData(void)
|
|
||||||
{
|
|
||||||
/* Read Data */
|
|
||||||
return AES->DOUTR;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Read the Key value.
|
|
||||||
* @param AES_KeyInitStruct: pointer to an AES_KeyInitTypeDef structure which
|
|
||||||
* will contain the key.
|
|
||||||
* @note When the key derivation mode is selected, AES must be disabled
|
|
||||||
* (AES_Cmd(DISABLE)) before reading the decryption key.
|
|
||||||
* Reading the key while the AES is enabled will return unpredictable
|
|
||||||
* value.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void AES_ReadKey(AES_KeyInitTypeDef* AES_KeyInitStruct)
|
|
||||||
{
|
|
||||||
AES_KeyInitStruct->AES_Key0 = AES->KEYR0;
|
|
||||||
AES_KeyInitStruct->AES_Key1 = AES->KEYR1;
|
|
||||||
AES_KeyInitStruct->AES_Key2 = AES->KEYR2;
|
|
||||||
AES_KeyInitStruct->AES_Key3 = AES->KEYR3;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Read the Initialization Vector IV value.
|
|
||||||
* @param AES_IVInitStruct: pointer to an AES_IVInitTypeDef structure which
|
|
||||||
* will contain the Initialization Vector IV.
|
|
||||||
* @note When the AES is enabled Reading the Initialization Vector IV value
|
|
||||||
* will return 0. The AES must be disabled using AES_Cmd(DISABLE)
|
|
||||||
* to get the right value.
|
|
||||||
* @note When ECB chaining mode is selected, Initialization Vector IV has no
|
|
||||||
* meaning.
|
|
||||||
* When CTR chaining mode is selected, AES_IV0 contains 32-bit Counter value.
|
|
||||||
* AES_IV1, AES_IV2 and AES_IV3 contains nonce value.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void AES_ReadIV(AES_IVInitTypeDef* AES_IVInitStruct)
|
|
||||||
{
|
|
||||||
AES_IVInitStruct->AES_IV0 = AES->IVR0;
|
|
||||||
AES_IVInitStruct->AES_IV1 = AES->IVR1;
|
|
||||||
AES_IVInitStruct->AES_IV2 = AES->IVR2;
|
|
||||||
AES_IVInitStruct->AES_IV3 = AES->IVR3;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup AES_Group4 DMA transfers management functions
|
|
||||||
* @brief DMA transfers management function.
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
===============================================================================
|
|
||||||
##### DMA transfers management functions #####
|
|
||||||
===============================================================================
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Configures the AES DMA interface.
|
|
||||||
* @param AES_DMATransfer: Specifies the AES DMA transfer.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg AES_DMATransfer_In: When selected, DMA manages the data input phase.
|
|
||||||
* @arg AES_DMATransfer_Out: When selected, DMA manages the data output phase.
|
|
||||||
* @arg AES_DMATransfer_InOut: When selected, DMA manages both the data input/output phases.
|
|
||||||
* @param NewState Indicates the new state of the AES DMA interface.
|
|
||||||
* This parameter can be: ENABLE or DISABLE.
|
|
||||||
* @note The DMA has no action in key derivation mode.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void AES_DMAConfig(uint32_t AES_DMATransfer, FunctionalState NewState)
|
|
||||||
{
|
|
||||||
/* Check the parameter */
|
|
||||||
assert_param(IS_AES_DMA_TRANSFER(AES_DMATransfer));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
/* Enable the DMA transfer */
|
|
||||||
AES->CR |= (uint32_t) AES_DMATransfer;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Disable the DMA transfer */
|
|
||||||
AES->CR &= (uint32_t)(~AES_DMATransfer);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup AES_Group5 Interrupts and flags management functions
|
|
||||||
* @brief Interrupts and flags management functions.
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
|
|
||||||
===============================================================================
|
|
||||||
##### Interrupts and flags management functions #####
|
|
||||||
===============================================================================
|
|
||||||
@endverbatim
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables or disables the specified AES interrupt.
|
|
||||||
* @param AES_IT: Specifies the AES interrupt source to enable/disable.
|
|
||||||
* This parameter can be any combinations of the following values:
|
|
||||||
* @arg AES_IT_CC: Computation Complete Interrupt. If enabled, once CCF
|
|
||||||
* flag is set an interrupt is generated.
|
|
||||||
* @arg AES_IT_ERR: Error Interrupt. If enabled, once a read error
|
|
||||||
* flags (RDERR) or write error flag (WRERR) is set,
|
|
||||||
* an interrupt is generated.
|
|
||||||
* @param NewState: The new state of the AES interrupt source.
|
|
||||||
* This parameter can be: ENABLE or DISABLE.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void AES_ITConfig(uint32_t AES_IT, FunctionalState NewState)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
||||||
assert_param(IS_AES_IT(AES_IT));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
AES->CR |= (uint32_t) AES_IT; /**< AES_IT Enable */
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
AES->CR &= (uint32_t)(~AES_IT); /**< AES_IT Disable */
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Checks whether the specified AES flag is set or not.
|
|
||||||
* @param AES_FLAG specifies the flag to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg AES_FLAG_CCF: Computation Complete Flag is set by hardware when
|
|
||||||
* he computation phase is completed.
|
|
||||||
* @arg AES_FLAG_RDERR: Read Error Flag is set when an unexpected read
|
|
||||||
* operation of DOUTR register is detected.
|
|
||||||
* @arg AES_FLAG_WRERR: Write Error Flag is set when an unexpected write
|
|
||||||
* operation in DINR is detected.
|
|
||||||
* @retval FlagStatus (SET or RESET)
|
|
||||||
*/
|
|
||||||
FlagStatus AES_GetFlagStatus(uint32_t AES_FLAG)
|
|
||||||
{
|
|
||||||
FlagStatus bitstatus = RESET;
|
|
||||||
|
|
||||||
/* Check parameters */
|
|
||||||
assert_param(IS_AES_FLAG(AES_FLAG));
|
|
||||||
|
|
||||||
if ((AES->SR & AES_FLAG) != (uint32_t)RESET)
|
|
||||||
{
|
|
||||||
bitstatus = SET;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
bitstatus = RESET;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Return the AES_FLAG status */
|
|
||||||
return bitstatus;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clears the AES flags.
|
|
||||||
* @param AES_FLAG: specifies the flag to clear.
|
|
||||||
* This parameter can be:
|
|
||||||
* @arg AES_FLAG_CCF: Computation Complete Flag is cleared by setting CCFC
|
|
||||||
* bit in CR register.
|
|
||||||
* @arg AES_FLAG_RDERR: Read Error is cleared by setting ERRC bit in
|
|
||||||
* CR register.
|
|
||||||
* @arg AES_FLAG_WRERR: Write Error is cleared by setting ERRC bit in
|
|
||||||
* CR register.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void AES_ClearFlag(uint32_t AES_FLAG)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_AES_FLAG(AES_FLAG));
|
|
||||||
|
|
||||||
/* Check if AES_FLAG is AES_FLAG_CCF */
|
|
||||||
if (AES_FLAG == AES_FLAG_CCF)
|
|
||||||
{
|
|
||||||
/* Clear CCF flag by setting CCFC bit */
|
|
||||||
AES->CR |= (uint32_t) AES_CR_CCFC;
|
|
||||||
}
|
|
||||||
else /* AES_FLAG is AES_FLAG_RDERR or AES_FLAG_WRERR */
|
|
||||||
{
|
|
||||||
/* Clear RDERR and WRERR flags by setting ERRC bit */
|
|
||||||
AES->CR |= (uint32_t) AES_CR_ERRC;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Checks whether the specified AES interrupt has occurred or not.
|
|
||||||
* @param AES_IT: Specifies the AES interrupt pending bit to check.
|
|
||||||
* This parameter can be:
|
|
||||||
* @arg AES_IT_CC: Computation Complete Interrupt.
|
|
||||||
* @arg AES_IT_ERR: Error Interrupt.
|
|
||||||
* @retval ITStatus The new state of AES_IT (SET or RESET).
|
|
||||||
*/
|
|
||||||
ITStatus AES_GetITStatus(uint32_t AES_IT)
|
|
||||||
{
|
|
||||||
ITStatus itstatus = RESET;
|
|
||||||
uint32_t cciebitstatus = RESET, ccfbitstatus = RESET;
|
|
||||||
|
|
||||||
/* Check parameters */
|
|
||||||
assert_param(IS_AES_GET_IT(AES_IT));
|
|
||||||
|
|
||||||
cciebitstatus = AES->CR & AES_CR_CCIE;
|
|
||||||
ccfbitstatus = AES->SR & AES_SR_CCF;
|
|
||||||
|
|
||||||
/* Check if AES_IT is AES_IT_CC */
|
|
||||||
if (AES_IT == AES_IT_CC)
|
|
||||||
{
|
|
||||||
/* Check the status of the specified AES interrupt */
|
|
||||||
if (((cciebitstatus) != (uint32_t)RESET) && ((ccfbitstatus) != (uint32_t)RESET))
|
|
||||||
{
|
|
||||||
/* Interrupt occurred */
|
|
||||||
itstatus = SET;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Interrupt didn't occur */
|
|
||||||
itstatus = RESET;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else /* AES_IT is AES_IT_ERR */
|
|
||||||
{
|
|
||||||
/* Check the status of the specified AES interrupt */
|
|
||||||
if ((AES->CR & AES_CR_ERRIE) != RESET)
|
|
||||||
{
|
|
||||||
/* Check if WRERR or RDERR flags are set */
|
|
||||||
if ((AES->SR & (uint32_t)(AES_SR_WRERR | AES_SR_RDERR)) != (uint16_t)RESET)
|
|
||||||
{
|
|
||||||
/* Interrupt occurred */
|
|
||||||
itstatus = SET;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Interrupt didn't occur */
|
|
||||||
itstatus = RESET;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Interrupt didn't occur */
|
|
||||||
itstatus = (ITStatus) RESET;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Return the AES_IT status */
|
|
||||||
return itstatus;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clears the AES's interrupt pending bits.
|
|
||||||
* @param AES_IT: specifies the interrupt pending bit to clear.
|
|
||||||
* This parameter can be any combinations of the following values:
|
|
||||||
* @arg AES_IT_CC: Computation Complete Interrupt.
|
|
||||||
* @arg AES_IT_ERR: Error Interrupt.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void AES_ClearITPendingBit(uint32_t AES_IT)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_AES_IT(AES_IT));
|
|
||||||
|
|
||||||
/* Clear the interrupt pending bit */
|
|
||||||
AES->CR |= (uint32_t) (AES_IT >> (uint32_t) 0x00000002);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,246 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32l1xx_aes.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @version V1.3.0
|
|
||||||
* @date 31-January-2014
|
|
||||||
* @brief This file contains all the functions prototypes for the AES firmware
|
|
||||||
* library.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef __STM32L1xx_AES_H
|
|
||||||
#define __STM32L1xx_AES_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32l1xx.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup AES
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AES Init structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t AES_Operation; /*!< Specifies the AES mode of operation.
|
|
||||||
This parameter can be a value of @ref AES_possible_Operation_modes */
|
|
||||||
uint32_t AES_Chaining; /*!< Specifies the AES Chaining modes: ECB, CBC or CTR.
|
|
||||||
This parameter can be a value of @ref AES_possible_chaining_modes */
|
|
||||||
uint32_t AES_DataType; /*!< Specifies the AES data swapping: 32-bit, 16-bit, 8-bit or 1-bit.
|
|
||||||
This parameter can be a value of @ref AES_Data_Types */
|
|
||||||
}AES_InitTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AES Key(s) structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t AES_Key0; /*!< Key[31:0] */
|
|
||||||
uint32_t AES_Key1; /*!< Key[63:32] */
|
|
||||||
uint32_t AES_Key2; /*!< Key[95:64] */
|
|
||||||
uint32_t AES_Key3; /*!< Key[127:96] */
|
|
||||||
}AES_KeyInitTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AES Initialization Vectors (IV) structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t AES_IV0; /*!< Init Vector IV[31:0] */
|
|
||||||
uint32_t AES_IV1; /*!< Init Vector IV[63:32] */
|
|
||||||
uint32_t AES_IV2; /*!< Init Vector IV[95:64] */
|
|
||||||
uint32_t AES_IV3; /*!< Init Vector IV[127:96] */
|
|
||||||
}AES_IVInitTypeDef;
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup AES_Exported_Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup AES_possible_Operation_modes
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define AES_Operation_Encryp ((uint32_t)0x00000000) /*!< AES in Encryption mode */
|
|
||||||
#define AES_Operation_KeyDeriv AES_CR_MODE_0 /*!< AES in Key Derivation mode */
|
|
||||||
#define AES_Operation_Decryp AES_CR_MODE_1 /*!< AES in Decryption mode */
|
|
||||||
#define AES_Operation_KeyDerivAndDecryp AES_CR_MODE /*!< AES in Key Derivation and Decryption mode */
|
|
||||||
|
|
||||||
#define IS_AES_MODE(OPERATION) (((OPERATION) == AES_Operation_Encryp) || \
|
|
||||||
((OPERATION) == AES_Operation_KeyDeriv) || \
|
|
||||||
((OPERATION) == AES_Operation_Decryp) || \
|
|
||||||
((OPERATION) == AES_Operation_KeyDerivAndDecryp))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup AES_possible_chaining_modes
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define AES_Chaining_ECB ((uint32_t)0x00000000) /*!< AES in ECB chaining mode */
|
|
||||||
#define AES_Chaining_CBC AES_CR_CHMOD_0 /*!< AES in CBC chaining mode */
|
|
||||||
#define AES_Chaining_CTR AES_CR_CHMOD_1 /*!< AES in CTR chaining mode */
|
|
||||||
|
|
||||||
#define IS_AES_CHAINING(CHAINING) (((CHAINING) == AES_Chaining_ECB) || \
|
|
||||||
((CHAINING) == AES_Chaining_CBC) || \
|
|
||||||
((CHAINING) == AES_Chaining_CTR))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup AES_Data_Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define AES_DataType_32b ((uint32_t)0x00000000) /*!< 32-bit data. No swapping */
|
|
||||||
#define AES_DataType_16b AES_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
|
|
||||||
#define AES_DataType_8b AES_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
|
|
||||||
#define AES_DataType_1b AES_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
|
|
||||||
|
|
||||||
#define IS_AES_DATATYPE(DATATYPE) (((DATATYPE) == AES_DataType_32b) || \
|
|
||||||
((DATATYPE) == AES_DataType_16b)|| \
|
|
||||||
((DATATYPE) == AES_DataType_8b) || \
|
|
||||||
((DATATYPE) == AES_DataType_1b))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup AES_Flags
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define AES_FLAG_CCF AES_SR_CCF /*!< Computation Complete Flag */
|
|
||||||
#define AES_FLAG_RDERR AES_SR_RDERR /*!< Read Error Flag */
|
|
||||||
#define AES_FLAG_WRERR AES_SR_WRERR /*!< Write Error Flag */
|
|
||||||
|
|
||||||
#define IS_AES_FLAG(FLAG) (((FLAG) == AES_FLAG_CCF) || \
|
|
||||||
((FLAG) == AES_FLAG_RDERR) || \
|
|
||||||
((FLAG) == AES_FLAG_WRERR))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup AES_Interrupts
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define AES_IT_CC AES_CR_CCIE /*!< Computation Complete interrupt */
|
|
||||||
#define AES_IT_ERR AES_CR_ERRIE /*!< Error interrupt */
|
|
||||||
|
|
||||||
#define IS_AES_IT(IT) ((((IT) & (uint32_t)0xFFFFF9FF) == 0x00) && ((IT) != 0x00))
|
|
||||||
#define IS_AES_GET_IT(IT) (((IT) == AES_IT_CC) || ((IT) == AES_IT_ERR))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup AES_DMA_Transfer_modes
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define AES_DMATransfer_In AES_CR_DMAINEN /*!< DMA requests enabled for input transfer phase */
|
|
||||||
#define AES_DMATransfer_Out AES_CR_DMAOUTEN /*!< DMA requests enabled for input transfer phase */
|
|
||||||
#define AES_DMATransfer_InOut (AES_CR_DMAINEN | AES_CR_DMAOUTEN) /*!< DMA requests enabled for both input and output phases */
|
|
||||||
|
|
||||||
#define IS_AES_DMA_TRANSFER(TRANSFER) (((TRANSFER) == AES_DMATransfer_In) || \
|
|
||||||
((TRANSFER) == AES_DMATransfer_Out) || \
|
|
||||||
((TRANSFER) == AES_DMATransfer_InOut))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
/* Exported functions ------------------------------------------------------- */
|
|
||||||
|
|
||||||
/* Initialization and configuration functions *********************************/
|
|
||||||
void AES_DeInit(void);
|
|
||||||
void AES_Init(AES_InitTypeDef* AES_InitStruct);
|
|
||||||
void AES_KeyInit(AES_KeyInitTypeDef* AES_KeyInitStruct);
|
|
||||||
void AES_IVInit(AES_IVInitTypeDef* AES_IVInitStruct);
|
|
||||||
void AES_Cmd(FunctionalState NewState);
|
|
||||||
|
|
||||||
/* Structures initialization functions ****************************************/
|
|
||||||
void AES_StructInit(AES_InitTypeDef* AES_InitStruct);
|
|
||||||
void AES_KeyStructInit(AES_KeyInitTypeDef* AES_KeyInitStruct);
|
|
||||||
void AES_IVStructInit(AES_IVInitTypeDef* AES_IVInitStruct);
|
|
||||||
|
|
||||||
/* AES Read and Write functions **********************************************/
|
|
||||||
void AES_WriteSubData(uint32_t Data);
|
|
||||||
uint32_t AES_ReadSubData(void);
|
|
||||||
void AES_ReadKey(AES_KeyInitTypeDef* AES_KeyInitStruct);
|
|
||||||
void AES_ReadIV(AES_IVInitTypeDef* AES_IVInitStruct);
|
|
||||||
|
|
||||||
/* DMA transfers management function ******************************************/
|
|
||||||
void AES_DMAConfig(uint32_t AES_DMATransfer, FunctionalState NewState);
|
|
||||||
|
|
||||||
/* Interrupts and flags management functions **********************************/
|
|
||||||
void AES_ITConfig(uint32_t AES_IT, FunctionalState NewState);
|
|
||||||
FlagStatus AES_GetFlagStatus(uint32_t AES_FLAG);
|
|
||||||
void AES_ClearFlag(uint32_t AES_FLAG);
|
|
||||||
ITStatus AES_GetITStatus(uint32_t AES_IT);
|
|
||||||
void AES_ClearITPendingBit(uint32_t AES_IT);
|
|
||||||
|
|
||||||
/* High Level AES functions **************************************************/
|
|
||||||
ErrorStatus AES_ECB_Encrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output);
|
|
||||||
ErrorStatus AES_ECB_Decrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output);
|
|
||||||
ErrorStatus AES_CBC_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
|
|
||||||
ErrorStatus AES_CBC_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
|
|
||||||
ErrorStatus AES_CTR_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
|
|
||||||
ErrorStatus AES_CTR_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /*__STM32L1xx_AES_H */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,689 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32l1xx_aes_util.c
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @version V1.3.0
|
|
||||||
* @date 31-January-2014
|
|
||||||
* @brief This file provides high level functions to encrypt and decrypt an
|
|
||||||
* input message using AES in ECB/CBC/CTR modes.
|
|
||||||
*
|
|
||||||
* @verbatim
|
|
||||||
|
|
||||||
================================================================================
|
|
||||||
##### How to use this driver #####
|
|
||||||
================================================================================
|
|
||||||
[..]
|
|
||||||
(#) Enable The AES controller clock using
|
|
||||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE); function.
|
|
||||||
|
|
||||||
(#) Use AES_ECB_Encrypt() function to encrypt an input message in ECB mode.
|
|
||||||
(#) Use AES_ECB_Decrypt() function to decrypt an input message in ECB mode.
|
|
||||||
|
|
||||||
(#) Use AES_CBC_Encrypt() function to encrypt an input message in CBC mode.
|
|
||||||
(#) Use AES_CBC_Decrypt() function to decrypt an input message in CBC mode.
|
|
||||||
|
|
||||||
(#) Use AES_CTR_Encrypt() function to encrypt an input message in CTR mode.
|
|
||||||
(#) Use AES_CTR_Decrypt() function to decrypt an input message in CTR mode.
|
|
||||||
|
|
||||||
* @endverbatim
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32l1xx_aes.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup AES
|
|
||||||
* @brief AES driver modules
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/
|
|
||||||
/* Private define ------------------------------------------------------------*/
|
|
||||||
#define AES_CC_TIMEOUT ((uint32_t) 0x00010000)
|
|
||||||
|
|
||||||
/* Private macro -------------------------------------------------------------*/
|
|
||||||
/* Private variables ---------------------------------------------------------*/
|
|
||||||
/* Private function prototypes -----------------------------------------------*/
|
|
||||||
/* Private functions ---------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup AES_Private_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup AES_Group6 High Level AES functions
|
|
||||||
* @brief High Level AES functions
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
================================================================================
|
|
||||||
##### High Level AES functions #####
|
|
||||||
================================================================================
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Encrypt using AES in ECB Mode
|
|
||||||
* @param Key: Key used for AES algorithm.
|
|
||||||
* @param Input: pointer to the Input buffer.
|
|
||||||
* @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.
|
|
||||||
* @param Output: pointer to the returned buffer.
|
|
||||||
* @retval An ErrorStatus enumeration value:
|
|
||||||
* - SUCCESS: Operation done
|
|
||||||
* - ERROR: Operation failed
|
|
||||||
*/
|
|
||||||
ErrorStatus AES_ECB_Encrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output)
|
|
||||||
{
|
|
||||||
AES_InitTypeDef AES_InitStructure;
|
|
||||||
AES_KeyInitTypeDef AES_KeyInitStructure;
|
|
||||||
ErrorStatus status = SUCCESS;
|
|
||||||
uint32_t keyaddr = (uint32_t)Key;
|
|
||||||
uint32_t inputaddr = (uint32_t)Input;
|
|
||||||
uint32_t outputaddr = (uint32_t)Output;
|
|
||||||
__IO uint32_t counter = 0;
|
|
||||||
uint32_t ccstatus = 0;
|
|
||||||
uint32_t i = 0;
|
|
||||||
|
|
||||||
/* AES Key initialisation */
|
|
||||||
AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
keyaddr += 4;
|
|
||||||
AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
keyaddr += 4;
|
|
||||||
AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
keyaddr += 4;
|
|
||||||
AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
AES_KeyInit(&AES_KeyInitStructure);
|
|
||||||
|
|
||||||
/* AES configuration */
|
|
||||||
AES_InitStructure.AES_Operation = AES_Operation_Encryp;
|
|
||||||
AES_InitStructure.AES_Chaining = AES_Chaining_ECB;
|
|
||||||
AES_InitStructure.AES_DataType = AES_DataType_8b;
|
|
||||||
AES_Init(&AES_InitStructure);
|
|
||||||
|
|
||||||
/* Enable AES */
|
|
||||||
AES_Cmd(ENABLE);
|
|
||||||
|
|
||||||
for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
|
|
||||||
{
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
|
|
||||||
/* Wait for CCF flag to be set */
|
|
||||||
counter = 0;
|
|
||||||
do
|
|
||||||
{
|
|
||||||
ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
|
|
||||||
counter++;
|
|
||||||
}while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
|
|
||||||
|
|
||||||
if (ccstatus == RESET)
|
|
||||||
{
|
|
||||||
status = ERROR;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Clear CCF flag */
|
|
||||||
AES_ClearFlag(AES_FLAG_CCF);
|
|
||||||
/* Read cipher text */
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Disable AES before starting new processing */
|
|
||||||
AES_Cmd(DISABLE);
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Decrypt using AES in ECB Mode
|
|
||||||
* @param Key: Key used for AES algorithm.
|
|
||||||
* @param Input: pointer to the Input buffer.
|
|
||||||
* @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.
|
|
||||||
* @param Output: pointer to the returned buffer.
|
|
||||||
* @retval An ErrorStatus enumeration value:
|
|
||||||
* - SUCCESS: Operation done
|
|
||||||
* - ERROR: Operation failed
|
|
||||||
*/
|
|
||||||
ErrorStatus AES_ECB_Decrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output)
|
|
||||||
{
|
|
||||||
AES_InitTypeDef AES_InitStructure;
|
|
||||||
AES_KeyInitTypeDef AES_KeyInitStructure;
|
|
||||||
ErrorStatus status = SUCCESS;
|
|
||||||
uint32_t keyaddr = (uint32_t)Key;
|
|
||||||
uint32_t inputaddr = (uint32_t)Input;
|
|
||||||
uint32_t outputaddr = (uint32_t)Output;
|
|
||||||
__IO uint32_t counter = 0;
|
|
||||||
uint32_t ccstatus = 0;
|
|
||||||
uint32_t i = 0;
|
|
||||||
|
|
||||||
/* AES Key initialisation */
|
|
||||||
AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
keyaddr += 4;
|
|
||||||
AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
keyaddr += 4;
|
|
||||||
AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
keyaddr += 4;
|
|
||||||
AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
AES_KeyInit(&AES_KeyInitStructure);
|
|
||||||
|
|
||||||
/* AES configuration */
|
|
||||||
AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;
|
|
||||||
AES_InitStructure.AES_Chaining = AES_Chaining_ECB;
|
|
||||||
AES_InitStructure.AES_DataType = AES_DataType_8b;
|
|
||||||
AES_Init(&AES_InitStructure);
|
|
||||||
|
|
||||||
/* Enable AES */
|
|
||||||
AES_Cmd(ENABLE);
|
|
||||||
|
|
||||||
for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
|
|
||||||
{
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
|
|
||||||
/* Wait for CCF flag to be set */
|
|
||||||
counter = 0;
|
|
||||||
do
|
|
||||||
{
|
|
||||||
ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
|
|
||||||
counter++;
|
|
||||||
}while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
|
|
||||||
|
|
||||||
if (ccstatus == RESET)
|
|
||||||
{
|
|
||||||
status = ERROR;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Clear CCF flag */
|
|
||||||
AES_ClearFlag(AES_FLAG_CCF);
|
|
||||||
|
|
||||||
/* Read cipher text */
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Disable AES before starting new processing */
|
|
||||||
AES_Cmd(DISABLE);
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Encrypt using AES in CBC Mode
|
|
||||||
* @param InitVectors: Initialisation Vectors used for AES algorithm.
|
|
||||||
* @param Key: Key used for AES algorithm.
|
|
||||||
* @param Input: pointer to the Input buffer.
|
|
||||||
* @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.
|
|
||||||
* @param Output: pointer to the returned buffer.
|
|
||||||
* @retval An ErrorStatus enumeration value:
|
|
||||||
* - SUCCESS: Operation done
|
|
||||||
* - ERROR: Operation failed
|
|
||||||
*/
|
|
||||||
ErrorStatus AES_CBC_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
|
|
||||||
{
|
|
||||||
AES_InitTypeDef AES_InitStructure;
|
|
||||||
AES_KeyInitTypeDef AES_KeyInitStructure;
|
|
||||||
AES_IVInitTypeDef AES_IVInitStructure;
|
|
||||||
ErrorStatus status = SUCCESS;
|
|
||||||
uint32_t keyaddr = (uint32_t)Key;
|
|
||||||
uint32_t inputaddr = (uint32_t)Input;
|
|
||||||
uint32_t outputaddr = (uint32_t)Output;
|
|
||||||
uint32_t ivaddr = (uint32_t)InitVectors;
|
|
||||||
__IO uint32_t counter = 0;
|
|
||||||
uint32_t ccstatus = 0;
|
|
||||||
uint32_t i = 0;
|
|
||||||
|
|
||||||
/* AES Key initialisation*/
|
|
||||||
AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
keyaddr += 4;
|
|
||||||
AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
keyaddr += 4;
|
|
||||||
AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
keyaddr += 4;
|
|
||||||
AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
AES_KeyInit(&AES_KeyInitStructure);
|
|
||||||
|
|
||||||
/* AES Initialization Vectors */
|
|
||||||
AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
|
|
||||||
ivaddr += 4;
|
|
||||||
AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));
|
|
||||||
ivaddr += 4;
|
|
||||||
AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
|
|
||||||
ivaddr += 4;
|
|
||||||
AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));
|
|
||||||
AES_IVInit(&AES_IVInitStructure);
|
|
||||||
|
|
||||||
/* AES configuration */
|
|
||||||
AES_InitStructure.AES_Operation = AES_Operation_Encryp;
|
|
||||||
AES_InitStructure.AES_Chaining = AES_Chaining_CBC;
|
|
||||||
AES_InitStructure.AES_DataType = AES_DataType_8b;
|
|
||||||
AES_Init(&AES_InitStructure);
|
|
||||||
|
|
||||||
/* Enable AES */
|
|
||||||
AES_Cmd(ENABLE);
|
|
||||||
|
|
||||||
for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
|
|
||||||
{
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
|
|
||||||
/* Wait for CCF flag to be set */
|
|
||||||
counter = 0;
|
|
||||||
do
|
|
||||||
{
|
|
||||||
ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
|
|
||||||
counter++;
|
|
||||||
}while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
|
|
||||||
|
|
||||||
if (ccstatus == RESET)
|
|
||||||
{
|
|
||||||
status = ERROR;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Clear CCF flag */
|
|
||||||
AES_ClearFlag(AES_FLAG_CCF);
|
|
||||||
|
|
||||||
/* Read cipher text */
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Disable AES before starting new processing */
|
|
||||||
AES_Cmd(DISABLE);
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Decrypt using AES in CBC Mode
|
|
||||||
* @param InitVectors: Initialisation Vectors used for AES algorithm.
|
|
||||||
* @param Key: Key used for AES algorithm.
|
|
||||||
* @param Input: pointer to the Input buffer.
|
|
||||||
* @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.
|
|
||||||
* @param Output: pointer to the returned buffer.
|
|
||||||
* @retval An ErrorStatus enumeration value:
|
|
||||||
* - SUCCESS: Operation done
|
|
||||||
* - ERROR: Operation failed
|
|
||||||
*/
|
|
||||||
ErrorStatus AES_CBC_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
|
|
||||||
{
|
|
||||||
AES_InitTypeDef AES_InitStructure;
|
|
||||||
AES_KeyInitTypeDef AES_KeyInitStructure;
|
|
||||||
AES_IVInitTypeDef AES_IVInitStructure;
|
|
||||||
ErrorStatus status = SUCCESS;
|
|
||||||
uint32_t keyaddr = (uint32_t)Key;
|
|
||||||
uint32_t inputaddr = (uint32_t)Input;
|
|
||||||
uint32_t outputaddr = (uint32_t)Output;
|
|
||||||
uint32_t ivaddr = (uint32_t)InitVectors;
|
|
||||||
__IO uint32_t counter = 0;
|
|
||||||
uint32_t ccstatus = 0;
|
|
||||||
uint32_t i = 0;
|
|
||||||
|
|
||||||
/* AES Key initialisation*/
|
|
||||||
AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
keyaddr += 4;
|
|
||||||
AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
keyaddr += 4;
|
|
||||||
AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
keyaddr += 4;
|
|
||||||
AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
AES_KeyInit(&AES_KeyInitStructure);
|
|
||||||
|
|
||||||
/* AES Initialization Vectors */
|
|
||||||
AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
|
|
||||||
ivaddr += 4;
|
|
||||||
AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));
|
|
||||||
ivaddr += 4;
|
|
||||||
AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
|
|
||||||
ivaddr += 4;
|
|
||||||
AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));
|
|
||||||
AES_IVInit(&AES_IVInitStructure);
|
|
||||||
|
|
||||||
/* AES configuration */
|
|
||||||
AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;
|
|
||||||
AES_InitStructure.AES_Chaining = AES_Chaining_CBC;
|
|
||||||
AES_InitStructure.AES_DataType = AES_DataType_8b;
|
|
||||||
AES_Init(&AES_InitStructure);
|
|
||||||
|
|
||||||
/* Enable AES */
|
|
||||||
AES_Cmd(ENABLE);
|
|
||||||
|
|
||||||
for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
|
|
||||||
{
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
|
|
||||||
/* Wait for CCF flag to be set */
|
|
||||||
counter = 0;
|
|
||||||
do
|
|
||||||
{
|
|
||||||
ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
|
|
||||||
counter++;
|
|
||||||
}while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
|
|
||||||
|
|
||||||
if (ccstatus == RESET)
|
|
||||||
{
|
|
||||||
status = ERROR;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Clear CCF flag */
|
|
||||||
AES_ClearFlag(AES_FLAG_CCF);
|
|
||||||
|
|
||||||
/* Read cipher text */
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Disable AES before starting new processing */
|
|
||||||
AES_Cmd(DISABLE);
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Encrypt using AES in CTR Mode
|
|
||||||
* @param InitVectors: Initialisation Vectors used for AES algorithm.
|
|
||||||
* @param Key: Key used for AES algorithm.
|
|
||||||
* @param Input: pointer to the Input buffer.
|
|
||||||
* @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.
|
|
||||||
* @param Output: pointer to the returned buffer.
|
|
||||||
* @retval An ErrorStatus enumeration value:
|
|
||||||
* - SUCCESS: Operation done
|
|
||||||
* - ERROR: Operation failed
|
|
||||||
*/
|
|
||||||
ErrorStatus AES_CTR_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
|
|
||||||
{
|
|
||||||
AES_InitTypeDef AES_InitStructure;
|
|
||||||
AES_KeyInitTypeDef AES_KeyInitStructure;
|
|
||||||
AES_IVInitTypeDef AES_IVInitStructure;
|
|
||||||
|
|
||||||
ErrorStatus status = SUCCESS;
|
|
||||||
uint32_t keyaddr = (uint32_t)Key;
|
|
||||||
uint32_t inputaddr = (uint32_t)Input;
|
|
||||||
uint32_t outputaddr = (uint32_t)Output;
|
|
||||||
uint32_t ivaddr = (uint32_t)InitVectors;
|
|
||||||
__IO uint32_t counter = 0;
|
|
||||||
uint32_t ccstatus = 0;
|
|
||||||
uint32_t i = 0;
|
|
||||||
|
|
||||||
/* AES key initialisation*/
|
|
||||||
AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
keyaddr += 4;
|
|
||||||
AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
keyaddr += 4;
|
|
||||||
AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
keyaddr += 4;
|
|
||||||
AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
AES_KeyInit(&AES_KeyInitStructure);
|
|
||||||
|
|
||||||
/* AES Initialization Vectors */
|
|
||||||
AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
|
|
||||||
ivaddr += 4;
|
|
||||||
AES_IVInitStructure.AES_IV2= __REV(*(uint32_t*)(ivaddr));
|
|
||||||
ivaddr += 4;
|
|
||||||
AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
|
|
||||||
ivaddr += 4;
|
|
||||||
AES_IVInitStructure.AES_IV0= __REV(*(uint32_t*)(ivaddr));
|
|
||||||
AES_IVInit(&AES_IVInitStructure);
|
|
||||||
|
|
||||||
/* AES configuration */
|
|
||||||
AES_InitStructure.AES_Operation = AES_Operation_Encryp;
|
|
||||||
AES_InitStructure.AES_Chaining = AES_Chaining_CTR;
|
|
||||||
AES_InitStructure.AES_DataType = AES_DataType_8b;
|
|
||||||
AES_Init(&AES_InitStructure);
|
|
||||||
|
|
||||||
/* Enable AES */
|
|
||||||
AES_Cmd(ENABLE);
|
|
||||||
|
|
||||||
for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
|
|
||||||
{
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
|
|
||||||
/* Wait for CCF flag to be set */
|
|
||||||
counter = 0;
|
|
||||||
do
|
|
||||||
{
|
|
||||||
ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
|
|
||||||
counter++;
|
|
||||||
}while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
|
|
||||||
|
|
||||||
if (ccstatus == RESET)
|
|
||||||
{
|
|
||||||
status = ERROR;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Clear CCF flag */
|
|
||||||
AES_ClearFlag(AES_FLAG_CCF);
|
|
||||||
|
|
||||||
/* Read cipher text */
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Disable AES before starting new processing */
|
|
||||||
AES_Cmd(DISABLE);
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Decrypt using AES in CTR Mode
|
|
||||||
* @param InitVectors: Initialisation Vectors used for AES algorithm.
|
|
||||||
* @param Key: Key used for AES algorithm.
|
|
||||||
* @param Input: pointer to the Input buffer.
|
|
||||||
* @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.
|
|
||||||
* @param Output: pointer to the returned buffer.
|
|
||||||
* @retval An ErrorStatus enumeration value:
|
|
||||||
* - SUCCESS: Operation done
|
|
||||||
* - ERROR: Operation failed
|
|
||||||
*/
|
|
||||||
ErrorStatus AES_CTR_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
|
|
||||||
{
|
|
||||||
AES_InitTypeDef AES_InitStructure;
|
|
||||||
AES_KeyInitTypeDef AES_KeyInitStructure;
|
|
||||||
AES_IVInitTypeDef AES_IVInitStructure;
|
|
||||||
|
|
||||||
ErrorStatus status = SUCCESS;
|
|
||||||
uint32_t keyaddr = (uint32_t)Key;
|
|
||||||
uint32_t inputaddr = (uint32_t)Input;
|
|
||||||
uint32_t outputaddr = (uint32_t)Output;
|
|
||||||
uint32_t ivaddr = (uint32_t)InitVectors;
|
|
||||||
__IO uint32_t counter = 0;
|
|
||||||
uint32_t ccstatus = 0;
|
|
||||||
uint32_t i = 0;
|
|
||||||
|
|
||||||
/* AES Key initialisation*/
|
|
||||||
AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
keyaddr += 4;
|
|
||||||
AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
keyaddr += 4;
|
|
||||||
AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
keyaddr += 4;
|
|
||||||
AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
|
|
||||||
AES_KeyInit(&AES_KeyInitStructure);
|
|
||||||
|
|
||||||
/* AES Initialization Vectors */
|
|
||||||
AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
|
|
||||||
ivaddr += 4;
|
|
||||||
AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));
|
|
||||||
ivaddr += 4;
|
|
||||||
AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
|
|
||||||
ivaddr += 4;
|
|
||||||
AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));
|
|
||||||
AES_IVInit(&AES_IVInitStructure);
|
|
||||||
|
|
||||||
/* AES configuration */
|
|
||||||
AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;
|
|
||||||
AES_InitStructure.AES_Chaining = AES_Chaining_CTR;
|
|
||||||
AES_InitStructure.AES_DataType = AES_DataType_8b;
|
|
||||||
AES_Init(&AES_InitStructure);
|
|
||||||
|
|
||||||
/* Enable AES */
|
|
||||||
AES_Cmd(ENABLE);
|
|
||||||
|
|
||||||
for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
|
|
||||||
{
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
|
||||||
inputaddr += 4;
|
|
||||||
|
|
||||||
/* Wait for CCF flag to be set */
|
|
||||||
counter = 0;
|
|
||||||
do
|
|
||||||
{
|
|
||||||
ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
|
|
||||||
counter++;
|
|
||||||
}while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
|
|
||||||
|
|
||||||
if (ccstatus == RESET)
|
|
||||||
{
|
|
||||||
status = ERROR;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Clear CCF flag */
|
|
||||||
AES_ClearFlag(AES_FLAG_CCF);
|
|
||||||
|
|
||||||
/* Read cipher text */
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
|
||||||
outputaddr += 4;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Disable AES before starting new processing */
|
|
||||||
AES_Cmd(DISABLE);
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
||||||
|
|
@ -1,388 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32l1xx_comp.c
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @version V1.3.0
|
|
||||||
* @date 31-January-2014
|
|
||||||
* @brief This file provides firmware functions to manage the following
|
|
||||||
* functionalities of the comparators (COMP1 and COMP2) peripheral:
|
|
||||||
* + Comparators configuration
|
|
||||||
* + Window mode control
|
|
||||||
* + Internal Reference Voltage (VREFINT) output
|
|
||||||
*
|
|
||||||
* @verbatim
|
|
||||||
===============================================================================
|
|
||||||
##### How to use this driver #####
|
|
||||||
===============================================================================
|
|
||||||
[..] The device integrates two analog comparators COMP1 and COMP2:
|
|
||||||
(+) COMP1 is a fixed threshold (VREFINT) that shares the non inverting
|
|
||||||
input with the ADC channels.
|
|
||||||
(+) COMP2 is a rail-to-rail comparator whose the inverting input can be
|
|
||||||
selected among: DAC_OUT1, DAC_OUT2, 1/4 VREFINT, 1/2 VERFINT, 3/4
|
|
||||||
VREFINT, VREFINT, PB3 and whose the output can be redirected to
|
|
||||||
embedded timers: TIM2, TIM3, TIM4, TIM10.
|
|
||||||
|
|
||||||
(+) The two comparators COMP1 and COMP2 can be combined in window mode.
|
|
||||||
|
|
||||||
-@-
|
|
||||||
(#@) Comparator APB clock must be enabled to get write access
|
|
||||||
to comparator register using
|
|
||||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE).
|
|
||||||
|
|
||||||
(#@) COMP1 comparator and ADC can't be used at the same time since
|
|
||||||
they share the same ADC switch matrix (analog switches).
|
|
||||||
|
|
||||||
(#@) When an I/O is used as comparator input, the corresponding GPIO
|
|
||||||
registers should be configured in analog mode.
|
|
||||||
|
|
||||||
(#@) Comparators outputs (CMP1OUT and CMP2OUT) are not mapped on
|
|
||||||
GPIO pin. They are only internal.
|
|
||||||
To get the comparator output level, use COMP_GetOutputLevel().
|
|
||||||
|
|
||||||
(#@) COMP1 and COMP2 outputs are internally connected to EXTI Line 21
|
|
||||||
and EXTI Line 22 respectively.
|
|
||||||
Interrupts can be used by configuring the EXTI Line using the
|
|
||||||
EXTI peripheral driver.
|
|
||||||
|
|
||||||
(#@) After enabling the comparator (COMP1 or COMP2), user should wait
|
|
||||||
for start-up time (tSTART) to get right output levels.
|
|
||||||
Please refer to product datasheet for more information on tSTART.
|
|
||||||
|
|
||||||
(#@) Comparators cannot be used to exit the device from Sleep or Stop
|
|
||||||
mode when the internal reference voltage is switched off using
|
|
||||||
the PWR_UltraLowPowerCmd() function (ULP bit in the PWR_CR register).
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32l1xx_comp.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP
|
|
||||||
* @brief COMP driver modules.
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/
|
|
||||||
/* Private define ------------------------------------------------------------*/
|
|
||||||
/* Private macro -------------------------------------------------------------*/
|
|
||||||
/* Private variables ---------------------------------------------------------*/
|
|
||||||
/* Private function prototypes -----------------------------------------------*/
|
|
||||||
/* Private functions ---------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_Private_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_Group1 Initialization and Configuration functions
|
|
||||||
* @brief Initialization and Configuration functions.
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
===============================================================================
|
|
||||||
##### Initialization and Configuration functions #####
|
|
||||||
===============================================================================
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Deinitializes COMP peripheral registers to their default reset values.
|
|
||||||
* @param None
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void COMP_DeInit(void)
|
|
||||||
{
|
|
||||||
COMP->CSR = ((uint32_t)0x00000000); /*!< Set COMP->CSR to reset value */
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initializes the COMP2 peripheral according to the specified parameters
|
|
||||||
* in the COMP_InitStruct.
|
|
||||||
* @note This function configures only COMP2.
|
|
||||||
* @note COMP2 comparator is enabled as soon as the INSEL[2:0] bits are
|
|
||||||
* different from "000".
|
|
||||||
* @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains
|
|
||||||
* the configuration information for the specified COMP peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void COMP_Init(COMP_InitTypeDef* COMP_InitStruct)
|
|
||||||
{
|
|
||||||
uint32_t tmpreg = 0;
|
|
||||||
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));
|
|
||||||
assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_OutputSelect));
|
|
||||||
assert_param(IS_COMP_SPEED(COMP_InitStruct->COMP_Speed));
|
|
||||||
|
|
||||||
/*!< Get the COMP CSR value */
|
|
||||||
tmpreg = COMP->CSR;
|
|
||||||
|
|
||||||
/*!< Clear the INSEL[2:0], OUTSEL[1:0] and SPEED bits */
|
|
||||||
tmpreg &= (uint32_t) (~(uint32_t) (COMP_CSR_OUTSEL | COMP_CSR_INSEL | COMP_CSR_SPEED));
|
|
||||||
|
|
||||||
/*!< Configure COMP: speed, inversion input selection and output redirection */
|
|
||||||
/*!< Set SPEED bit according to COMP_InitStruct->COMP_Speed value */
|
|
||||||
/*!< Set INSEL bits according to COMP_InitStruct->COMP_InvertingInput value */
|
|
||||||
/*!< Set OUTSEL bits according to COMP_InitStruct->COMP_OutputSelect value */
|
|
||||||
tmpreg |= (uint32_t)((COMP_InitStruct->COMP_Speed | COMP_InitStruct->COMP_InvertingInput
|
|
||||||
| COMP_InitStruct->COMP_OutputSelect));
|
|
||||||
|
|
||||||
/*!< The COMP2 comparator is enabled as soon as the INSEL[2:0] bits value are
|
|
||||||
different from "000" */
|
|
||||||
/*!< Write to COMP_CSR register */
|
|
||||||
COMP->CSR = tmpreg;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable or disable the COMP1 peripheral.
|
|
||||||
* @note After enabling COMP1, the following functions should be called to
|
|
||||||
* connect the selected GPIO input to COMP1 non inverting input:
|
|
||||||
* @note Enable switch control mode using SYSCFG_RISwitchControlModeCmd()
|
|
||||||
* @note Close VCOMP switch using SYSCFG_RIIOSwitchConfig()
|
|
||||||
* @note Close the I/O switch number n corresponding to the I/O
|
|
||||||
* using SYSCFG_RIIOSwitchConfig()
|
|
||||||
* @param NewState: new state of the COMP1 peripheral.
|
|
||||||
* This parameter can be: ENABLE or DISABLE.
|
|
||||||
* @note This function enables/disables only the COMP1.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void COMP_Cmd(FunctionalState NewState)
|
|
||||||
{
|
|
||||||
/* Check the parameter */
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
/* Enable the COMP1 */
|
|
||||||
COMP->CSR |= (uint32_t) COMP_CSR_CMP1EN;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Disable the COMP1 */
|
|
||||||
COMP->CSR &= (uint32_t)(~COMP_CSR_CMP1EN);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Return the output level (high or low) of the selected comparator.
|
|
||||||
* @note Comparator output is low when the noninverting input is at a lower
|
|
||||||
* voltage than the inverting input.
|
|
||||||
* @note Comparator output is high when the noninverting input is at a higher
|
|
||||||
* voltage than the inverting input.
|
|
||||||
* @note Comparators outputs aren't available on GPIO (outputs levels are
|
|
||||||
* only internal). The COMP1 and COMP2 outputs are connected internally
|
|
||||||
* to the EXTI Line 21 and Line 22 respectively.
|
|
||||||
* @param COMP_Selection: the selected comparator.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg COMP_Selection_COMP1: COMP1 selected
|
|
||||||
* @arg COMP_Selection_COMP2: COMP2 selected
|
|
||||||
* @retval Returns the selected comparator output level.
|
|
||||||
*/
|
|
||||||
uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection)
|
|
||||||
{
|
|
||||||
uint8_t compout = 0x0;
|
|
||||||
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
|
||||||
|
|
||||||
/* Check if Comparator 1 is selected */
|
|
||||||
if(COMP_Selection == COMP_Selection_COMP1)
|
|
||||||
{
|
|
||||||
/* Check if comparator 1 output level is high */
|
|
||||||
if((COMP->CSR & COMP_CSR_CMP1OUT) != (uint8_t) RESET)
|
|
||||||
{
|
|
||||||
/* Get Comparator 1 output level */
|
|
||||||
compout = (uint8_t) COMP_OutputLevel_High;
|
|
||||||
}
|
|
||||||
/* comparator 1 output level is low */
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Get Comparator 1 output level */
|
|
||||||
compout = (uint8_t) COMP_OutputLevel_Low;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/* Comparator 2 is selected */
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Check if comparator 2 output level is high */
|
|
||||||
if((COMP->CSR & COMP_CSR_CMP2OUT) != (uint8_t) RESET)
|
|
||||||
{
|
|
||||||
/* Get Comparator output level */
|
|
||||||
compout = (uint8_t) COMP_OutputLevel_High;
|
|
||||||
}
|
|
||||||
/* comparator 2 output level is low */
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Get Comparator 2 output level */
|
|
||||||
compout = (uint8_t) COMP_OutputLevel_Low;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/* Return the comparator output level */
|
|
||||||
return (uint8_t)(compout);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Close or Open the SW1 switch.
|
|
||||||
* @param NewState: new state of the SW1 switch.
|
|
||||||
* This parameter can be: ENABLE or DISABLE.
|
|
||||||
* @note ENABLE to close the SW1 switch
|
|
||||||
* @note DISABLE to open the SW1 switch
|
|
||||||
* @retval None.
|
|
||||||
*/
|
|
||||||
void COMP_SW1SwitchConfig(FunctionalState NewState)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
/* Close SW1 switch */
|
|
||||||
COMP->CSR |= (uint32_t) COMP_CSR_SW1;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Open SW1 switch */
|
|
||||||
COMP->CSR &= (uint32_t)(~COMP_CSR_SW1);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_Group2 Window mode control function
|
|
||||||
* @brief Window mode control function.
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
===============================================================================
|
|
||||||
##### Window mode control function #####
|
|
||||||
===============================================================================
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables or disables the window mode.
|
|
||||||
* In window mode:
|
|
||||||
* @note COMP1 inverting input is fixed to VREFINT defining the first
|
|
||||||
* threshold.
|
|
||||||
* @note COMP2 inverting input is configurable (DAC_OUT1, DAC_OUT2, VREFINT
|
|
||||||
* sub-multiples, PB3) defining the second threshold.
|
|
||||||
* @note COMP1 and COMP2 non inverting inputs are connected together.
|
|
||||||
* @note In window mode, only the Group 6 (PB4 or PB5) can be used as
|
|
||||||
* noninverting inputs.
|
|
||||||
* @param NewState: new state of the window mode.
|
|
||||||
* This parameter can be ENABLE or DISABLE.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void COMP_WindowCmd(FunctionalState NewState)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
/* Enable the window mode */
|
|
||||||
COMP->CSR |= (uint32_t) COMP_CSR_WNDWE;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Disable the window mode */
|
|
||||||
COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWE);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_Group3 Internal Reference Voltage output function
|
|
||||||
* @brief Internal Reference Voltage (VREFINT) output function.
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
===============================================================================
|
|
||||||
##### Internal Reference Voltage (VREFINT) output function #####
|
|
||||||
===============================================================================
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables or disables the output of internal reference voltage (VREFINT).
|
|
||||||
* The VREFINT output can be routed to any I/O in group 3: CH8 (PB0) or
|
|
||||||
* CH9 (PB1).
|
|
||||||
* To correctly use this function, the SYSCFG_RIIOSwitchConfig() function
|
|
||||||
* should be called after.
|
|
||||||
* @param NewState: new state of the Vrefint output.
|
|
||||||
* This parameter can be: ENABLE or DISABLE.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void COMP_VrefintOutputCmd(FunctionalState NewState)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
/* Enable the output of internal reference voltage */
|
|
||||||
COMP->CSR |= (uint32_t) COMP_CSR_VREFOUTEN;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Disable the output of internal reference voltage */
|
|
||||||
COMP->CSR &= (uint32_t) (~COMP_CSR_VREFOUTEN);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,197 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32l1xx_comp.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @version V1.3.0
|
|
||||||
* @date 31-January-2014
|
|
||||||
* @brief This file contains all the functions prototypes for the COMP firmware
|
|
||||||
* library.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef __STM32L1xx_COMP_H
|
|
||||||
#define __STM32L1xx_COMP_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32l1xx.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup COMP
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief COMP Init structure definition
|
|
||||||
*/
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t COMP_Speed; /*!< Defines the speed of comparator 2.
|
|
||||||
This parameter can be a value of @ref COMP_Speed */
|
|
||||||
uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator 2.
|
|
||||||
This parameter can be a value of @ref COMP_InvertingInput */
|
|
||||||
uint32_t COMP_OutputSelect; /*!< Selects the output redirection of the comparator 2.
|
|
||||||
This parameter can be a value of @ref COMP_OutputSelect */
|
|
||||||
|
|
||||||
}COMP_InitTypeDef;
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_Exported_Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define COMP_OutputLevel_High ((uint32_t)0x00000001)
|
|
||||||
#define COMP_OutputLevel_Low ((uint32_t)0x00000000)
|
|
||||||
|
|
||||||
/** @defgroup COMP_Selection
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define COMP_Selection_COMP1 ((uint32_t)0x00000001)
|
|
||||||
#define COMP_Selection_COMP2 ((uint32_t)0x00000002)
|
|
||||||
|
|
||||||
#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
|
|
||||||
((PERIPH) == COMP_Selection_COMP2))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_InvertingInput
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define COMP_InvertingInput_None ((uint32_t)0x00000000) /* COMP2 is disabled when this parameter is selected */
|
|
||||||
#define COMP_InvertingInput_IO ((uint32_t)0x00040000)
|
|
||||||
#define COMP_InvertingInput_VREFINT ((uint32_t)0x00080000)
|
|
||||||
#define COMP_InvertingInput_3_4VREFINT ((uint32_t)0x000C0000)
|
|
||||||
#define COMP_InvertingInput_1_2VREFINT ((uint32_t)0x00100000)
|
|
||||||
#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00140000)
|
|
||||||
#define COMP_InvertingInput_DAC1 ((uint32_t)0x00180000)
|
|
||||||
#define COMP_InvertingInput_DAC2 ((uint32_t)0x001C0000)
|
|
||||||
|
|
||||||
#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_None) || \
|
|
||||||
((INPUT) == COMP_InvertingInput_IO) || \
|
|
||||||
((INPUT) == COMP_InvertingInput_VREFINT) || \
|
|
||||||
((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
|
|
||||||
((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
|
|
||||||
((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
|
|
||||||
((INPUT) == COMP_InvertingInput_DAC1) || \
|
|
||||||
((INPUT) == COMP_InvertingInput_DAC2))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_OutputSelect
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define COMP_OutputSelect_TIM2IC4 ((uint32_t)0x00000000)
|
|
||||||
#define COMP_OutputSelect_TIM2OCREFCLR ((uint32_t)0x00200000)
|
|
||||||
#define COMP_OutputSelect_TIM3IC4 ((uint32_t)0x00400000)
|
|
||||||
#define COMP_OutputSelect_TIM3OCREFCLR ((uint32_t)0x00600000)
|
|
||||||
#define COMP_OutputSelect_TIM4IC4 ((uint32_t)0x00800000)
|
|
||||||
#define COMP_OutputSelect_TIM4OCREFCLR ((uint32_t)0x00A00000)
|
|
||||||
#define COMP_OutputSelect_TIM10IC1 ((uint32_t)0x00C00000)
|
|
||||||
#define COMP_OutputSelect_None ((uint32_t)0x00E00000)
|
|
||||||
|
|
||||||
#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OutputSelect_TIM2IC4) || \
|
|
||||||
((OUTPUT) == COMP_OutputSelect_TIM2OCREFCLR) || \
|
|
||||||
((OUTPUT) == COMP_OutputSelect_TIM3IC4) || \
|
|
||||||
((OUTPUT) == COMP_OutputSelect_TIM3OCREFCLR) || \
|
|
||||||
((OUTPUT) == COMP_OutputSelect_TIM4IC4) || \
|
|
||||||
((OUTPUT) == COMP_OutputSelect_TIM4OCREFCLR) || \
|
|
||||||
((OUTPUT) == COMP_OutputSelect_TIM10IC1) || \
|
|
||||||
((OUTPUT) == COMP_OutputSelect_None))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_Speed
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define COMP_Speed_Slow ((uint32_t)0x00000000)
|
|
||||||
#define COMP_Speed_Fast ((uint32_t)0x00001000)
|
|
||||||
|
|
||||||
#define IS_COMP_SPEED(SPEED) (((SPEED) == COMP_Speed_Slow) || \
|
|
||||||
((SPEED) == COMP_Speed_Fast))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
/* Exported functions ------------------------------------------------------- */
|
|
||||||
|
|
||||||
/* Function used to set the COMP configuration to the default reset state ****/
|
|
||||||
void COMP_DeInit(void);
|
|
||||||
|
|
||||||
/* Initialization and Configuration functions *********************************/
|
|
||||||
void COMP_Init(COMP_InitTypeDef* COMP_InitStruct);
|
|
||||||
void COMP_Cmd(FunctionalState NewState);
|
|
||||||
uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection);
|
|
||||||
void COMP_SW1SwitchConfig(FunctionalState NewState);
|
|
||||||
|
|
||||||
/* Window mode control function ***********************************************/
|
|
||||||
void COMP_WindowCmd(FunctionalState NewState);
|
|
||||||
|
|
||||||
/* Internal Reference Voltage (VREFINT) output function ***********************/
|
|
||||||
void COMP_VrefintOutputCmd(FunctionalState NewState);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /*__STM32L1xx_COMP_H */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,697 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32l1xx_dac.c
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @version V1.3.0
|
|
||||||
* @date 31-January-2014
|
|
||||||
* @brief This file provides firmware functions to manage the following
|
|
||||||
* functionalities of the Digital-to-Analog Converter (DAC) peripheral:
|
|
||||||
* + DAC channels configuration: trigger, output buffer, data format
|
|
||||||
* + DMA management
|
|
||||||
* + Interrupts and flags management
|
|
||||||
|
|
||||||
* @verbatim
|
|
||||||
*
|
|
||||||
===============================================================================
|
|
||||||
##### DAC Peripheral features #####
|
|
||||||
===============================================================================
|
|
||||||
[..] The device integrates two 12-bit Digital Analog Converters that can
|
|
||||||
be used independently or simultaneously (dual mode):
|
|
||||||
(#) DAC channel1 with DAC_OUT1 (PA4) as output.
|
|
||||||
(#) DAC channel2 with DAC_OUT2 (PA5) as output.
|
|
||||||
|
|
||||||
[..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None
|
|
||||||
and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using
|
|
||||||
DAC_SetChannel1Data()/DAC_SetChannel2Data.
|
|
||||||
|
|
||||||
[..] Digital to Analog conversion can be triggered by:
|
|
||||||
(#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
|
|
||||||
The used pin (GPIOx_Pin9) must be configured in input mode.
|
|
||||||
(#) Timers TRGO: TIM2, TIM4, TIM6, TIM7 and TIM9
|
|
||||||
(DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...).
|
|
||||||
The timer TRGO event should be selected using TIM_SelectOutputTrigger()
|
|
||||||
(#) Software using DAC_Trigger_Software.
|
|
||||||
|
|
||||||
[..] Each DAC channel integrates an output buffer that can be used to
|
|
||||||
reduce the output impedance, and to drive external loads directly
|
|
||||||
without having to add an external operational amplifier.
|
|
||||||
To enable, the output buffer use
|
|
||||||
DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
|
|
||||||
|
|
||||||
[..] Refer to the device datasheet for more details about output impedance
|
|
||||||
value with and without output buffer.
|
|
||||||
|
|
||||||
[..] Both DAC channels can be used to generate:
|
|
||||||
(#) Noise wave using DAC_WaveGeneration_Noise
|
|
||||||
(#) Triangle wave using DAC_WaveGeneration_Triangle
|
|
||||||
|
|
||||||
[..] Wave generation can be disabled using DAC_WaveGeneration_None.
|
|
||||||
|
|
||||||
[..] The DAC data format can be:
|
|
||||||
(#) 8-bit right alignment using DAC_Align_8b_R
|
|
||||||
(#) 12-bit left alignment using DAC_Align_12b_L
|
|
||||||
(#) 12-bit right alignment using DAC_Align_12b_R
|
|
||||||
|
|
||||||
[..] The analog output voltage on each DAC channel pin is determined
|
|
||||||
by the following equation: DAC_OUTx = VREF+ * DOR / 4095
|
|
||||||
with DOR is the Data Output Register.
|
|
||||||
VEF+ is the input voltage reference (refer to the device datasheet)
|
|
||||||
e.g. To set DAC_OUT1 to 0.7V, use
|
|
||||||
DAC_SetChannel1Data(DAC_Align_12b_R, 868);
|
|
||||||
Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V.
|
|
||||||
|
|
||||||
[..] A DMA1 request can be generated when an external trigger (but not
|
|
||||||
a software trigger) occurs if DMA1 requests are enabled using
|
|
||||||
DAC_DMACmd()
|
|
||||||
[..] DMA1 requests are mapped as following:
|
|
||||||
(#) DAC channel1 is mapped on DMA1 channel3 which must be already
|
|
||||||
configured.
|
|
||||||
(#) DAC channel2 is mapped on DMA1 channel4 which must be already
|
|
||||||
configured.
|
|
||||||
|
|
||||||
##### How to use this driver #####
|
|
||||||
===============================================================================
|
|
||||||
[..]
|
|
||||||
(+) DAC APB clock must be enabled to get write access to DAC registers using
|
|
||||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
|
|
||||||
(+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
|
|
||||||
(+) Configure the DAC channel using DAC_Init()
|
|
||||||
(+) Enable the DAC channel using DAC_Cmd()
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32l1xx_dac.h"
|
|
||||||
#include "stm32l1xx_rcc.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC
|
|
||||||
* @brief DAC driver modules
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/
|
|
||||||
/* Private define ------------------------------------------------------------*/
|
|
||||||
/* CR register Mask */
|
|
||||||
#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
|
|
||||||
|
|
||||||
/* DAC Dual Channels SWTRIG masks */
|
|
||||||
#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
|
|
||||||
#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
|
|
||||||
|
|
||||||
/* DHR registers offsets */
|
|
||||||
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
|
|
||||||
#define DHR12R2_OFFSET ((uint32_t)0x00000014)
|
|
||||||
#define DHR12RD_OFFSET ((uint32_t)0x00000020)
|
|
||||||
|
|
||||||
/* DOR register offset */
|
|
||||||
#define DOR_OFFSET ((uint32_t)0x0000002C)
|
|
||||||
|
|
||||||
/* Private macro -------------------------------------------------------------*/
|
|
||||||
/* Private variables ---------------------------------------------------------*/
|
|
||||||
/* Private function prototypes -----------------------------------------------*/
|
|
||||||
/* Private functions ---------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_Private_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_Group1 DAC channels configuration
|
|
||||||
* @brief DAC channels configuration: trigger, output buffer, data format.
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
===============================================================================
|
|
||||||
##### DAC channels configuration: trigger, output buffer, data format #####
|
|
||||||
===============================================================================
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Deinitializes the DAC peripheral registers to their default reset values.
|
|
||||||
* @param None
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DAC_DeInit(void)
|
|
||||||
{
|
|
||||||
/* Enable DAC reset state */
|
|
||||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
|
|
||||||
/* Release DAC from reset state */
|
|
||||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initializes the DAC peripheral according to the specified
|
|
||||||
* parameters in the DAC_InitStruct.
|
|
||||||
* @param DAC_Channel: the selected DAC channel.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg DAC_Channel_1: DAC Channel1 selected.
|
|
||||||
* @arg DAC_Channel_2: DAC Channel2 selected.
|
|
||||||
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
|
|
||||||
* contains the configuration information for the specified DAC channel.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
|
|
||||||
{
|
|
||||||
uint32_t tmpreg1 = 0, tmpreg2 = 0;
|
|
||||||
|
|
||||||
/* Check the DAC parameters */
|
|
||||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
|
||||||
assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
|
|
||||||
assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
|
|
||||||
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
|
|
||||||
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
|
|
||||||
|
|
||||||
/*---------------------------- DAC CR Configuration --------------------------*/
|
|
||||||
/* Get the DAC CR value */
|
|
||||||
tmpreg1 = DAC->CR;
|
|
||||||
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
|
|
||||||
tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
|
|
||||||
/* Configure for the selected DAC channel: buffer output, trigger, wave generation,
|
|
||||||
mask/amplitude for wave generation */
|
|
||||||
/* Set TSELx and TENx bits according to DAC_Trigger value */
|
|
||||||
/* Set WAVEx bits according to DAC_WaveGeneration value */
|
|
||||||
/* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
|
|
||||||
/* Set BOFFx bit according to DAC_OutputBuffer value */
|
|
||||||
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
|
|
||||||
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
|
|
||||||
/* Calculate CR register value depending on DAC_Channel */
|
|
||||||
tmpreg1 |= tmpreg2 << DAC_Channel;
|
|
||||||
/* Write to DAC CR */
|
|
||||||
DAC->CR = tmpreg1;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Fills each DAC_InitStruct member with its default value.
|
|
||||||
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will
|
|
||||||
* be initialized.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
|
|
||||||
{
|
|
||||||
/*--------------- Reset DAC init structure parameters values -----------------*/
|
|
||||||
/* Initialize the DAC_Trigger member */
|
|
||||||
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
|
|
||||||
/* Initialize the DAC_WaveGeneration member */
|
|
||||||
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
|
|
||||||
/* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
|
|
||||||
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
|
|
||||||
/* Initialize the DAC_OutputBuffer member */
|
|
||||||
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables or disables the specified DAC channel.
|
|
||||||
* @param DAC_Channel: The selected DAC channel.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
|
||||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
|
||||||
* @param NewState: new state of the DAC channel.
|
|
||||||
* This parameter can be: ENABLE or DISABLE.
|
|
||||||
* @note When the DAC channel is enabled the trigger source can no more
|
|
||||||
* be modified.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
/* Enable the selected DAC channel */
|
|
||||||
DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Disable the selected DAC channel */
|
|
||||||
DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables or disables the selected DAC channel software trigger.
|
|
||||||
* @param DAC_Channel: the selected DAC channel.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
|
||||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
|
||||||
* @param NewState: new state of the selected DAC channel software trigger.
|
|
||||||
* This parameter can be: ENABLE or DISABLE.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
/* Enable software trigger for the selected DAC channel */
|
|
||||||
DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Disable software trigger for the selected DAC channel */
|
|
||||||
DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables or disables simultaneously the two DAC channels software
|
|
||||||
* triggers.
|
|
||||||
* @param NewState: new state of the DAC channels software triggers.
|
|
||||||
* This parameter can be: ENABLE or DISABLE.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
/* Enable software trigger for both DAC channels */
|
|
||||||
DAC->SWTRIGR |= DUAL_SWTRIG_SET;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Disable software trigger for both DAC channels */
|
|
||||||
DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables or disables the selected DAC channel wave generation.
|
|
||||||
* @param DAC_Channel: the selected DAC channel.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
|
||||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
|
||||||
* @param DAC_Wave: Specifies the wave type to enable or disable.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg DAC_Wave_Noise: noise wave generation
|
|
||||||
* @arg DAC_Wave_Triangle: triangle wave generation
|
|
||||||
* @param NewState: new state of the selected DAC channel wave generation.
|
|
||||||
* This parameter can be: ENABLE or DISABLE.
|
|
||||||
* @note
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
|
||||||
assert_param(IS_DAC_WAVE(DAC_Wave));
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
/* Enable the selected wave generation for the selected DAC channel */
|
|
||||||
DAC->CR |= DAC_Wave << DAC_Channel;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Disable the selected wave generation for the selected DAC channel */
|
|
||||||
DAC->CR &= ~(DAC_Wave << DAC_Channel);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Set the specified data holding register value for DAC channel1.
|
|
||||||
* @param DAC_Align: Specifies the data alignment for DAC channel1.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
|
||||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
|
||||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
|
||||||
* @param Data : Data to be loaded in the selected data holding register.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
|
|
||||||
{
|
|
||||||
__IO uint32_t tmp = 0;
|
|
||||||
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
|
||||||
assert_param(IS_DAC_DATA(Data));
|
|
||||||
|
|
||||||
tmp = (uint32_t)DAC_BASE;
|
|
||||||
tmp += DHR12R1_OFFSET + DAC_Align;
|
|
||||||
|
|
||||||
/* Set the DAC channel1 selected data holding register */
|
|
||||||
*(__IO uint32_t *) tmp = Data;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Set the specified data holding register value for DAC channel2.
|
|
||||||
* @param DAC_Align: Specifies the data alignment for DAC channel2.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
|
||||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
|
||||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
|
||||||
* @param Data : Data to be loaded in the selected data holding register.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
|
|
||||||
{
|
|
||||||
__IO uint32_t tmp = 0;
|
|
||||||
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
|
||||||
assert_param(IS_DAC_DATA(Data));
|
|
||||||
|
|
||||||
tmp = (uint32_t)DAC_BASE;
|
|
||||||
tmp += DHR12R2_OFFSET + DAC_Align;
|
|
||||||
|
|
||||||
/* Set the DAC channel2 selected data holding register */
|
|
||||||
*(__IO uint32_t *)tmp = Data;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Set the specified data holding register value for dual channel DAC.
|
|
||||||
* @param DAC_Align: Specifies the data alignment for dual channel DAC.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
|
||||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
|
||||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
|
||||||
* @param Data2: Data for DAC Channel2 to be loaded in the selected data
|
|
||||||
* holding register.
|
|
||||||
* @param Data1: Data for DAC Channel1 to be loaded in the selected data
|
|
||||||
* holding register.
|
|
||||||
* @note In dual mode, a unique register access is required to write in both
|
|
||||||
* DAC channels at the same time.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
|
|
||||||
{
|
|
||||||
uint32_t data = 0, tmp = 0;
|
|
||||||
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
|
||||||
assert_param(IS_DAC_DATA(Data1));
|
|
||||||
assert_param(IS_DAC_DATA(Data2));
|
|
||||||
|
|
||||||
/* Calculate and set dual DAC data holding register value */
|
|
||||||
if (DAC_Align == DAC_Align_8b_R)
|
|
||||||
{
|
|
||||||
data = ((uint32_t)Data2 << 8) | Data1;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
data = ((uint32_t)Data2 << 16) | Data1;
|
|
||||||
}
|
|
||||||
|
|
||||||
tmp = (uint32_t)DAC_BASE;
|
|
||||||
tmp += DHR12RD_OFFSET + DAC_Align;
|
|
||||||
|
|
||||||
/* Set the dual DAC selected data holding register */
|
|
||||||
*(__IO uint32_t *)tmp = data;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Returns the last data output value of the selected DAC channel.
|
|
||||||
* @param DAC_Channel: the selected DAC channel.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
|
||||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
|
||||||
* @retval The selected DAC channel data output value.
|
|
||||||
*/
|
|
||||||
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
|
|
||||||
{
|
|
||||||
__IO uint32_t tmp = 0;
|
|
||||||
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
|
||||||
|
|
||||||
tmp = (uint32_t) DAC_BASE ;
|
|
||||||
tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
|
|
||||||
|
|
||||||
/* Returns the DAC channel data output register value */
|
|
||||||
return (uint16_t) (*(__IO uint32_t*) tmp);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_Group2 DMA management functions
|
|
||||||
* @brief DMA management functions
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
===============================================================================
|
|
||||||
##### DMA management functions #####
|
|
||||||
===============================================================================
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables or disables the specified DAC channel DMA request.
|
|
||||||
* When enabled DMA1 is generated when an external trigger (EXTI Line9,
|
|
||||||
* TIM2, TIM4, TIM6, TIM7 or TIM9 but not a software trigger) occurs.
|
|
||||||
* @param DAC_Channel: the selected DAC channel.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
|
||||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
|
||||||
* @param NewState: new state of the selected DAC channel DMA request.
|
|
||||||
* This parameter can be: ENABLE or DISABLE.
|
|
||||||
* @note The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which
|
|
||||||
* must be already configured.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
/* Enable the selected DAC channel DMA request */
|
|
||||||
DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Disable the selected DAC channel DMA request */
|
|
||||||
DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_Group3 Interrupts and flags management functions
|
|
||||||
* @brief Interrupts and flags management functions
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
===============================================================================
|
|
||||||
##### Interrupts and flags management functions #####
|
|
||||||
===============================================================================
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables or disables the specified DAC interrupts.
|
|
||||||
* @param DAC_Channel: the selected DAC channel.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
|
||||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
|
||||||
* @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
|
|
||||||
* This parameter can be the following value:
|
|
||||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
|
||||||
* @note The DMA underrun occurs when a second external trigger arrives before
|
|
||||||
* the acknowledgement for the first external trigger is received (first request).
|
|
||||||
* @param NewState: new state of the specified DAC interrupts.
|
|
||||||
* This parameter can be: ENABLE or DISABLE.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
||||||
assert_param(IS_DAC_IT(DAC_IT));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
/* Enable the selected DAC interrupts */
|
|
||||||
DAC->CR |= (DAC_IT << DAC_Channel);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Disable the selected DAC interrupts */
|
|
||||||
DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Checks whether the specified DAC flag is set or not.
|
|
||||||
* @param DAC_Channel: thee selected DAC channel.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
|
||||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
|
||||||
* @param DAC_FLAG: specifies the flag to check.
|
|
||||||
* This parameter can be only of the following value:
|
|
||||||
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
|
||||||
* @note The DMA underrun occurs when a second external trigger arrives before
|
|
||||||
* the acknowledgement for the first external trigger is received (first request).
|
|
||||||
* @retval The new state of DAC_FLAG (SET or RESET).
|
|
||||||
*/
|
|
||||||
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
|
|
||||||
{
|
|
||||||
FlagStatus bitstatus = RESET;
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
|
||||||
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
|
||||||
|
|
||||||
/* Check the status of the specified DAC flag */
|
|
||||||
if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
|
|
||||||
{
|
|
||||||
/* DAC_FLAG is set */
|
|
||||||
bitstatus = SET;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* DAC_FLAG is reset */
|
|
||||||
bitstatus = RESET;
|
|
||||||
}
|
|
||||||
/* Return the DAC_FLAG status */
|
|
||||||
return bitstatus;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clears the DAC channel's pending flags.
|
|
||||||
* @param DAC_Channel: the selected DAC channel.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
|
||||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
|
||||||
* @param DAC_FLAG: specifies the flag to clear.
|
|
||||||
* This parameter can be the following value:
|
|
||||||
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
|
||||||
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
|
||||||
|
|
||||||
/* Clear the selected DAC flags */
|
|
||||||
DAC->SR = (DAC_FLAG << DAC_Channel);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Checks whether the specified DAC interrupt has occurred or not.
|
|
||||||
* @param DAC_Channel: the selected DAC channel.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
|
||||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
|
||||||
* @param DAC_IT: specifies the DAC interrupt source to check.
|
|
||||||
* This parameter can be the following values:
|
|
||||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
|
||||||
* @note The DMA underrun occurs when a second external trigger arrives before
|
|
||||||
* the acknowledgement for the first external trigger is received (first request).
|
|
||||||
* @retval The new state of DAC_IT (SET or RESET).
|
|
||||||
*/
|
|
||||||
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
|
|
||||||
{
|
|
||||||
ITStatus bitstatus = RESET;
|
|
||||||
uint32_t enablestatus = 0;
|
|
||||||
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
|
||||||
assert_param(IS_DAC_IT(DAC_IT));
|
|
||||||
|
|
||||||
/* Get the DAC_IT enable bit status */
|
|
||||||
enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
|
|
||||||
|
|
||||||
/* Check the status of the specified DAC interrupt */
|
|
||||||
if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
|
|
||||||
{
|
|
||||||
/* DAC_IT is set */
|
|
||||||
bitstatus = SET;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* DAC_IT is reset */
|
|
||||||
bitstatus = RESET;
|
|
||||||
}
|
|
||||||
/* Return the DAC_IT status */
|
|
||||||
return bitstatus;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clears the DAC channel's interrupt pending bits.
|
|
||||||
* @param DAC_Channel: the selected DAC channel.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
|
||||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
|
||||||
* @param DAC_IT: specifies the DAC interrupt pending bit to clear.
|
|
||||||
* This parameter can be the following values:
|
|
||||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
|
||||||
assert_param(IS_DAC_IT(DAC_IT));
|
|
||||||
|
|
||||||
/* Clear the selected DAC interrupt pending bits */
|
|
||||||
DAC->SR = (DAC_IT << DAC_Channel);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,315 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32l1xx_dac.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @version V1.3.0
|
|
||||||
* @date 31-January-2014
|
|
||||||
* @brief This file contains all the functions prototypes for the DAC firmware
|
|
||||||
* library.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef __STM32L1xx_DAC_H
|
|
||||||
#define __STM32L1xx_DAC_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32l1xx.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup DAC
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief DAC Init structure definition
|
|
||||||
*/
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
|
||||||
This parameter can be a value of @ref DAC_trigger_selection */
|
|
||||||
|
|
||||||
uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
|
|
||||||
are generated, or whether no wave is generated.
|
|
||||||
This parameter can be a value of @ref DAC_wave_generation */
|
|
||||||
|
|
||||||
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
|
|
||||||
the maximum amplitude triangle generation for the DAC channel.
|
|
||||||
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
|
|
||||||
|
|
||||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
|
||||||
This parameter can be a value of @ref DAC_output_buffer */
|
|
||||||
}DAC_InitTypeDef;
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_Exported_Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_trigger_selection
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
|
||||||
has been loaded, and not by external trigger */
|
|
||||||
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
|
||||||
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
|
||||||
#define DAC_Trigger_T9_TRGO ((uint32_t)0x0000001C) /*!< TIM9 TRGO selected as external conversion trigger for DAC channel */
|
|
||||||
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
|
||||||
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
|
||||||
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
|
||||||
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
|
|
||||||
|
|
||||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
|
|
||||||
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
|
|
||||||
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
|
|
||||||
((TRIGGER) == DAC_Trigger_T9_TRGO) || \
|
|
||||||
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
|
|
||||||
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
|
|
||||||
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
|
|
||||||
((TRIGGER) == DAC_Trigger_Software))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_wave_generation
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
|
|
||||||
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
|
|
||||||
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
|
|
||||||
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
|
|
||||||
((WAVE) == DAC_WaveGeneration_Noise) || \
|
|
||||||
((WAVE) == DAC_WaveGeneration_Triangle))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_lfsrunmask_triangleamplitude
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
|
||||||
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
|
||||||
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
|
|
||||||
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
|
|
||||||
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
|
|
||||||
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
|
|
||||||
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
|
|
||||||
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
|
|
||||||
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
|
|
||||||
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
|
|
||||||
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
|
|
||||||
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
|
|
||||||
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
|
|
||||||
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
|
|
||||||
|
|
||||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
|
|
||||||
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
|
|
||||||
((VALUE) == DAC_TriangleAmplitude_1) || \
|
|
||||||
((VALUE) == DAC_TriangleAmplitude_3) || \
|
|
||||||
((VALUE) == DAC_TriangleAmplitude_7) || \
|
|
||||||
((VALUE) == DAC_TriangleAmplitude_15) || \
|
|
||||||
((VALUE) == DAC_TriangleAmplitude_31) || \
|
|
||||||
((VALUE) == DAC_TriangleAmplitude_63) || \
|
|
||||||
((VALUE) == DAC_TriangleAmplitude_127) || \
|
|
||||||
((VALUE) == DAC_TriangleAmplitude_255) || \
|
|
||||||
((VALUE) == DAC_TriangleAmplitude_511) || \
|
|
||||||
((VALUE) == DAC_TriangleAmplitude_1023) || \
|
|
||||||
((VALUE) == DAC_TriangleAmplitude_2047) || \
|
|
||||||
((VALUE) == DAC_TriangleAmplitude_4095))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_output_buffer
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
|
|
||||||
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
|
|
||||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
|
|
||||||
((STATE) == DAC_OutputBuffer_Disable))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_Channel_selection
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DAC_Channel_1 ((uint32_t)0x00000000)
|
|
||||||
#define DAC_Channel_2 ((uint32_t)0x00000010)
|
|
||||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
|
|
||||||
((CHANNEL) == DAC_Channel_2))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_data_alignment
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DAC_Align_12b_R ((uint32_t)0x00000000)
|
|
||||||
#define DAC_Align_12b_L ((uint32_t)0x00000004)
|
|
||||||
#define DAC_Align_8b_R ((uint32_t)0x00000008)
|
|
||||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
|
|
||||||
((ALIGN) == DAC_Align_12b_L) || \
|
|
||||||
((ALIGN) == DAC_Align_8b_R))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_wave_generation
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DAC_Wave_Noise ((uint32_t)0x00000040)
|
|
||||||
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
|
|
||||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
|
|
||||||
((WAVE) == DAC_Wave_Triangle))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_data
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_interrupts_definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
|
|
||||||
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup DAC_flags_definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
|
|
||||||
|
|
||||||
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
/* Exported functions ------------------------------------------------------- */
|
|
||||||
|
|
||||||
/* Function used to set the DAC configuration to the default reset state *****/
|
|
||||||
void DAC_DeInit(void);
|
|
||||||
|
|
||||||
/* DAC channels configuration: trigger, output buffer, data format functions */
|
|
||||||
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
|
|
||||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
|
|
||||||
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
|
|
||||||
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
|
|
||||||
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
|
|
||||||
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
|
|
||||||
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
|
|
||||||
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
|
|
||||||
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
|
|
||||||
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
|
|
||||||
|
|
||||||
/* DMA management functions ***************************************************/
|
|
||||||
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
|
|
||||||
|
|
||||||
/* Interrupts and flags management functions **********************************/
|
|
||||||
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
|
|
||||||
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
|
||||||
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
|
||||||
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
|
|
||||||
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /*__STM32L1xx_DAC_H */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,191 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32l1xx_dbgmcu.c
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @version V1.3.0
|
|
||||||
* @date 31-January-2014
|
|
||||||
* @brief This file provides all the DBGMCU firmware functions.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32l1xx_dbgmcu.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DBGMCU
|
|
||||||
* @brief DBGMCU driver modules
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/
|
|
||||||
/* Private define ------------------------------------------------------------*/
|
|
||||||
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
|
|
||||||
|
|
||||||
/* Private macro -------------------------------------------------------------*/
|
|
||||||
/* Private variables ---------------------------------------------------------*/
|
|
||||||
/* Private function prototypes -----------------------------------------------*/
|
|
||||||
/* Private functions ---------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup DBGMCU_Private_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Returns the device revision identifier.
|
|
||||||
* @param None
|
|
||||||
* @retval Device revision identifier
|
|
||||||
*/
|
|
||||||
uint32_t DBGMCU_GetREVID(void)
|
|
||||||
{
|
|
||||||
return(DBGMCU->IDCODE >> 16);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Returns the device identifier.
|
|
||||||
* @param None
|
|
||||||
* @retval Device identifier
|
|
||||||
*/
|
|
||||||
uint32_t DBGMCU_GetDEVID(void)
|
|
||||||
{
|
|
||||||
return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Configures low power mode behavior when the MCU is in Debug mode.
|
|
||||||
* @param DBGMCU_Periph: specifies the low power mode.
|
|
||||||
* This parameter can be any combination of the following values:
|
|
||||||
* @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
|
|
||||||
* @arg DBGMCU_STOP: Keep debugger connection during STOP mode
|
|
||||||
* @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
|
|
||||||
* @param NewState: new state of the specified low power mode in Debug mode.
|
|
||||||
* This parameter can be: ENABLE or DISABLE.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
DBGMCU->CR |= DBGMCU_Periph;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
DBGMCU->CR &= ~DBGMCU_Periph;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
|
|
||||||
* @param DBGMCU_Periph: specifies the APB1 peripheral.
|
|
||||||
* This parameter can be any combination of the following values:
|
|
||||||
* @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
|
|
||||||
* @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
|
|
||||||
* @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
|
|
||||||
* @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
|
|
||||||
* @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
|
|
||||||
* @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
|
|
||||||
* @arg DBGMCU_RTC_STOP:
|
|
||||||
* + On STM32L1xx Medium-density devices: RTC Wakeup counter stopped when
|
|
||||||
* Core is halted.
|
|
||||||
* + On STM32L1xx High-density and Medium-density Plus devices: RTC Calendar
|
|
||||||
* and Wakeup counter stopped when Core is halted.
|
|
||||||
* @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
|
|
||||||
* @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
|
|
||||||
* @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is
|
|
||||||
* halted
|
|
||||||
* @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is
|
|
||||||
* halted
|
|
||||||
* @param NewState: new state of the specified APB1 peripheral in Debug mode.
|
|
||||||
* This parameter can be: ENABLE or DISABLE.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
DBGMCU->APB1FZ |= DBGMCU_Periph;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
DBGMCU->APB1FZ &= ~DBGMCU_Periph;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
|
|
||||||
* @param DBGMCU_Periph: specifies the APB2 peripheral.
|
|
||||||
* This parameter can be any combination of the following values:
|
|
||||||
* @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
|
|
||||||
* @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
|
|
||||||
* @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
|
|
||||||
* @param NewState: new state of the specified APB2 peripheral in Debug mode.
|
|
||||||
* This parameter can be: ENABLE or DISABLE.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
DBGMCU->APB2FZ |= DBGMCU_Periph;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
DBGMCU->APB2FZ &= ~DBGMCU_Periph;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,876 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32l1xx_dma.c
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @version V1.3.0
|
|
||||||
* @date 31-January-2014
|
|
||||||
* @brief This file provides firmware functions to manage the following
|
|
||||||
* functionalities of the Direct Memory Access controller (DMA):
|
|
||||||
* + Initialization and Configuration
|
|
||||||
* + Data Counter
|
|
||||||
* + Interrupts and flags management
|
|
||||||
*
|
|
||||||
* @verbatim
|
|
||||||
==============================================================================
|
|
||||||
##### How to use this driver #####
|
|
||||||
==============================================================================
|
|
||||||
[..]
|
|
||||||
(#) Enable The DMA controller clock using
|
|
||||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1 or
|
|
||||||
using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) function for DMA2.
|
|
||||||
(#) Enable and configure the peripheral to be connected to the DMA channel
|
|
||||||
(except for internal SRAM / FLASH memories: no initialization is
|
|
||||||
necessary).
|
|
||||||
(#) For a given Channel, program the Source and Destination addresses,
|
|
||||||
the transfer Direction, the Buffer Size, the Peripheral and Memory
|
|
||||||
Incrementation mode and Data Size, the Circular or Normal mode,
|
|
||||||
the channel transfer Priority and the Memory-to-Memory transfer
|
|
||||||
mode (if needed) using the DMA_Init() function.
|
|
||||||
(#) Enable the NVIC and the corresponding interrupt(s) using the function
|
|
||||||
DMA_ITConfig() if you need to use DMA interrupts.
|
|
||||||
(#) Enable the DMA channel using the DMA_Cmd() function.
|
|
||||||
(#) Activate the needed channel Request using PPP_DMACmd() function for
|
|
||||||
any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
|
|
||||||
The function allowing this operation is provided in each PPP peripheral
|
|
||||||
driver (ie. SPI_DMACmd for SPI peripheral).
|
|
||||||
(#) Optionally, you can configure the number of data to be transferred
|
|
||||||
when the channel is disabled (ie. after each Transfer Complete event
|
|
||||||
or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
|
|
||||||
And you can get the number of remaining data to be transferred using
|
|
||||||
the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
|
|
||||||
enabled and running).
|
|
||||||
(#) To control DMA events you can use one of the following two methods:
|
|
||||||
(##) Check on DMA channel flags using the function DMA_GetFlagStatus().
|
|
||||||
(##) Use DMA interrupts through the function DMA_ITConfig() at initialization
|
|
||||||
phase and DMA_GetITStatus() function into interrupt routines in
|
|
||||||
communication phase.
|
|
||||||
After checking on a flag you should clear it using DMA_ClearFlag()
|
|
||||||
function. And after checking on an interrupt event you should
|
|
||||||
clear it using DMA_ClearITPendingBit() function.
|
|
||||||
@endverbatim
|
|
||||||
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32l1xx_dma.h"
|
|
||||||
#include "stm32l1xx_rcc.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA
|
|
||||||
* @brief DMA driver modules
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/
|
|
||||||
/* Private define ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/* DMA1 Channelx interrupt pending bit masks */
|
|
||||||
#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
|
|
||||||
#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
|
|
||||||
#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
|
|
||||||
#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
|
|
||||||
#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
|
|
||||||
#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
|
|
||||||
#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
|
|
||||||
|
|
||||||
/* DMA2 Channelx interrupt pending bit masks */
|
|
||||||
#define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
|
|
||||||
#define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
|
|
||||||
#define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
|
|
||||||
#define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
|
|
||||||
#define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
|
|
||||||
|
|
||||||
/* DMA FLAG mask */
|
|
||||||
#define FLAG_MASK ((uint32_t)0x10000000)
|
|
||||||
|
|
||||||
/* DMA registers Masks */
|
|
||||||
#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F)
|
|
||||||
|
|
||||||
/* Private macro -------------------------------------------------------------*/
|
|
||||||
/* Private variables ---------------------------------------------------------*/
|
|
||||||
/* Private function prototypes -----------------------------------------------*/
|
|
||||||
/* Private functions ---------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup DMA_Private_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_Group1 Initialization and Configuration functions
|
|
||||||
* @brief Initialization and Configuration functions
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
===============================================================================
|
|
||||||
##### Initialization and Configuration functions #####
|
|
||||||
===============================================================================
|
|
||||||
[..] This subsection provides functions allowing to initialize the DMA channel
|
|
||||||
source and destination addresses, incrementation and data sizes, transfer
|
|
||||||
direction, buffer size, circular/normal mode selection, memory-to-memory
|
|
||||||
mode selection and channel priority value.
|
|
||||||
[..] The DMA_Init() function follows the DMA configuration procedures as described
|
|
||||||
in reference manual (RM0038).
|
|
||||||
@endverbatim
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Deinitializes the DMAy Channelx registers to their default reset
|
|
||||||
* values.
|
|
||||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
|
|
||||||
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
|
||||||
|
|
||||||
/* Disable the selected DMAy Channelx */
|
|
||||||
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
|
|
||||||
|
|
||||||
/* Reset DMAy Channelx control register */
|
|
||||||
DMAy_Channelx->CCR = 0;
|
|
||||||
|
|
||||||
/* Reset DMAy Channelx remaining bytes register */
|
|
||||||
DMAy_Channelx->CNDTR = 0;
|
|
||||||
|
|
||||||
/* Reset DMAy Channelx peripheral address register */
|
|
||||||
DMAy_Channelx->CPAR = 0;
|
|
||||||
|
|
||||||
/* Reset DMAy Channelx memory address register */
|
|
||||||
DMAy_Channelx->CMAR = 0;
|
|
||||||
|
|
||||||
if (DMAy_Channelx == DMA1_Channel1)
|
|
||||||
{
|
|
||||||
/* Reset interrupt pending bits for DMA1 Channel1 */
|
|
||||||
DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
|
|
||||||
}
|
|
||||||
else if (DMAy_Channelx == DMA1_Channel2)
|
|
||||||
{
|
|
||||||
/* Reset interrupt pending bits for DMA1 Channel2 */
|
|
||||||
DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
|
|
||||||
}
|
|
||||||
else if (DMAy_Channelx == DMA1_Channel3)
|
|
||||||
{
|
|
||||||
/* Reset interrupt pending bits for DMA1 Channel3 */
|
|
||||||
DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
|
|
||||||
}
|
|
||||||
else if (DMAy_Channelx == DMA1_Channel4)
|
|
||||||
{
|
|
||||||
/* Reset interrupt pending bits for DMA1 Channel4 */
|
|
||||||
DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
|
|
||||||
}
|
|
||||||
else if (DMAy_Channelx == DMA1_Channel5)
|
|
||||||
{
|
|
||||||
/* Reset interrupt pending bits for DMA1 Channel5 */
|
|
||||||
DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
|
|
||||||
}
|
|
||||||
else if (DMAy_Channelx == DMA1_Channel6)
|
|
||||||
{
|
|
||||||
/* Reset interrupt pending bits for DMA1 Channel6 */
|
|
||||||
DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
|
|
||||||
}
|
|
||||||
else if (DMAy_Channelx == DMA1_Channel7)
|
|
||||||
{
|
|
||||||
/* Reset interrupt pending bits for DMA1 Channel7 */
|
|
||||||
DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
|
|
||||||
}
|
|
||||||
else if (DMAy_Channelx == DMA2_Channel1)
|
|
||||||
{
|
|
||||||
/* Reset interrupt pending bits for DMA2 Channel1 */
|
|
||||||
DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK;
|
|
||||||
}
|
|
||||||
else if (DMAy_Channelx == DMA2_Channel2)
|
|
||||||
{
|
|
||||||
/* Reset interrupt pending bits for DMA2 Channel2 */
|
|
||||||
DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK;
|
|
||||||
}
|
|
||||||
else if (DMAy_Channelx == DMA2_Channel3)
|
|
||||||
{
|
|
||||||
/* Reset interrupt pending bits for DMA2 Channel3 */
|
|
||||||
DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK;
|
|
||||||
}
|
|
||||||
else if (DMAy_Channelx == DMA2_Channel4)
|
|
||||||
{
|
|
||||||
/* Reset interrupt pending bits for DMA2 Channel4 */
|
|
||||||
DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
if (DMAy_Channelx == DMA2_Channel5)
|
|
||||||
{
|
|
||||||
/* Reset interrupt pending bits for DMA2 Channel5 */
|
|
||||||
DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initializes the DMAy Channelx according to the specified
|
|
||||||
* parameters in the DMA_InitStruct.
|
|
||||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
|
|
||||||
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
|
||||||
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
|
|
||||||
* contains the configuration information for the specified DMA Channel.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
|
|
||||||
{
|
|
||||||
uint32_t tmpreg = 0;
|
|
||||||
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
|
||||||
assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
|
|
||||||
assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
|
|
||||||
assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
|
|
||||||
assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
|
|
||||||
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
|
|
||||||
assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
|
|
||||||
assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
|
|
||||||
assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
|
|
||||||
assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
|
|
||||||
|
|
||||||
/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
|
|
||||||
/* Get the DMAy_Channelx CCR value */
|
|
||||||
tmpreg = DMAy_Channelx->CCR;
|
|
||||||
/* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
|
|
||||||
tmpreg &= CCR_CLEAR_MASK;
|
|
||||||
/* Configure DMAy Channelx: data transfer, data size, priority level and mode */
|
|
||||||
/* Set DIR bit according to DMA_DIR value */
|
|
||||||
/* Set CIRC bit according to DMA_Mode value */
|
|
||||||
/* Set PINC bit according to DMA_PeripheralInc value */
|
|
||||||
/* Set MINC bit according to DMA_MemoryInc value */
|
|
||||||
/* Set PSIZE bits according to DMA_PeripheralDataSize value */
|
|
||||||
/* Set MSIZE bits according to DMA_MemoryDataSize value */
|
|
||||||
/* Set PL bits according to DMA_Priority value */
|
|
||||||
/* Set the MEM2MEM bit according to DMA_M2M value */
|
|
||||||
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
|
|
||||||
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
|
|
||||||
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
|
|
||||||
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
|
|
||||||
|
|
||||||
/* Write to DMAy Channelx CCR */
|
|
||||||
DMAy_Channelx->CCR = tmpreg;
|
|
||||||
|
|
||||||
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
|
|
||||||
/* Write to DMAy Channelx CNDTR */
|
|
||||||
DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
|
|
||||||
|
|
||||||
/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
|
|
||||||
/* Write to DMAy Channelx CPAR */
|
|
||||||
DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
|
|
||||||
|
|
||||||
/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
|
|
||||||
/* Write to DMAy Channelx CMAR */
|
|
||||||
DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Fills each DMA_InitStruct member with its default value.
|
|
||||||
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
|
|
||||||
* be initialized.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
|
|
||||||
{
|
|
||||||
/*-------------- Reset DMA init structure parameters values ------------------*/
|
|
||||||
/* Initialize the DMA_PeripheralBaseAddr member */
|
|
||||||
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
|
|
||||||
/* Initialize the DMA_MemoryBaseAddr member */
|
|
||||||
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
|
|
||||||
/* Initialize the DMA_DIR member */
|
|
||||||
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
|
|
||||||
/* Initialize the DMA_BufferSize member */
|
|
||||||
DMA_InitStruct->DMA_BufferSize = 0;
|
|
||||||
/* Initialize the DMA_PeripheralInc member */
|
|
||||||
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
|
||||||
/* Initialize the DMA_MemoryInc member */
|
|
||||||
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
|
|
||||||
/* Initialize the DMA_PeripheralDataSize member */
|
|
||||||
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
|
||||||
/* Initialize the DMA_MemoryDataSize member */
|
|
||||||
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
|
||||||
/* Initialize the DMA_Mode member */
|
|
||||||
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
|
|
||||||
/* Initialize the DMA_Priority member */
|
|
||||||
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
|
|
||||||
/* Initialize the DMA_M2M member */
|
|
||||||
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables or disables the specified DMAy Channelx.
|
|
||||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
|
|
||||||
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
|
||||||
* @param NewState: new state of the DMAy Channelx.
|
|
||||||
* This parameter can be: ENABLE or DISABLE.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
/* Enable the selected DMAy Channelx */
|
|
||||||
DMAy_Channelx->CCR |= DMA_CCR1_EN;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Disable the selected DMAy Channelx */
|
|
||||||
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_Group2 Data Counter functions
|
|
||||||
* @brief Data Counter functions
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
===============================================================================
|
|
||||||
##### Data Counter functions #####
|
|
||||||
===============================================================================
|
|
||||||
[..] This subsection provides function allowing to configure and read the buffer
|
|
||||||
size (number of data to be transferred).The DMA data counter can be written
|
|
||||||
only when the DMA channel is disabled (ie. after transfer complete event).
|
|
||||||
[..] The following function can be used to write the Channel data counter value:
|
|
||||||
(+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t
|
|
||||||
DataNumber).
|
|
||||||
-@- It is advised to use this function rather than DMA_Init() in situations
|
|
||||||
where only the Data buffer needs to be reloaded.
|
|
||||||
[..] The DMA data counter can be read to indicate the number of remaining transfers
|
|
||||||
for the relative DMA channel. This counter is decremented at the end of each
|
|
||||||
data transfer and when the transfer is complete:
|
|
||||||
(+) If Normal mode is selected: the counter is set to 0.
|
|
||||||
(+) If Circular mode is selected: the counter is reloaded with the initial
|
|
||||||
value(configured before enabling the DMA channel).
|
|
||||||
[..] The following function can be used to read the Channel data counter value:
|
|
||||||
(+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Sets the number of data units in the current DMAy Channelx transfer.
|
|
||||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
|
|
||||||
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
|
||||||
* @param DataNumber: The number of data units in the current DMAy Channelx
|
|
||||||
* transfer.
|
|
||||||
* @note This function can only be used when the DMAy_Channelx is disabled.
|
|
||||||
* @retval None.
|
|
||||||
*/
|
|
||||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
|
||||||
|
|
||||||
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
|
|
||||||
/* Write to DMAy Channelx CNDTR */
|
|
||||||
DMAy_Channelx->CNDTR = DataNumber;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Returns the number of remaining data units in the current
|
|
||||||
* DMAy Channelx transfer.
|
|
||||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
|
|
||||||
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
|
||||||
* @retval The number of remaining data units in the current DMAy Channelx
|
|
||||||
* transfer.
|
|
||||||
*/
|
|
||||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
|
||||||
/* Return the number of remaining data units for DMAy Channelx */
|
|
||||||
return ((uint16_t)(DMAy_Channelx->CNDTR));
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_Group3 Interrupts and flags management functions
|
|
||||||
* @brief Interrupts and flags management functions
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
===============================================================================
|
|
||||||
##### Interrupts and flags management functions #####
|
|
||||||
===============================================================================
|
|
||||||
[..] This subsection provides functions allowing to configure the DMA Interrupts
|
|
||||||
sources and check or clear the flags or pending bits status.
|
|
||||||
The user should identify which mode will be used in his application to manage
|
|
||||||
the DMA controller events: Polling mode or Interrupt mode.
|
|
||||||
*** Polling Mode ***
|
|
||||||
====================
|
|
||||||
[..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller
|
|
||||||
number x : DMA channel number ).
|
|
||||||
(#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
|
|
||||||
(#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
|
|
||||||
(#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
|
|
||||||
(#) DMAy_FLAG_GLx : to indicate that at least one of the events described
|
|
||||||
above occurred.
|
|
||||||
-@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the
|
|
||||||
same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
|
|
||||||
[..]In this Mode it is advised to use the following functions:
|
|
||||||
(+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
|
|
||||||
(+) void DMA_ClearFlag(uint32_t DMA_FLAG);
|
|
||||||
|
|
||||||
*** Interrupt Mode ***
|
|
||||||
======================
|
|
||||||
[..] Each DMA channel can be managed through 4 Interrupts:
|
|
||||||
(+) Interrupt Source
|
|
||||||
(##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete
|
|
||||||
event.
|
|
||||||
(##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete
|
|
||||||
event.
|
|
||||||
(##) DMA_IT_TE : specifies the interrupt source for the transfer errors event.
|
|
||||||
(##) DMA_IT_GL : to indicate that at least one of the interrupts described
|
|
||||||
above occurred.
|
|
||||||
-@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of
|
|
||||||
the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
|
|
||||||
[..]In this Mode it is advised to use the following functions:
|
|
||||||
(+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT,
|
|
||||||
FunctionalState NewState);
|
|
||||||
(+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
|
|
||||||
(+) void DMA_ClearITPendingBit(uint32_t DMA_IT);
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables or disables the specified DMAy Channelx interrupts.
|
|
||||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
|
|
||||||
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
|
||||||
* @param DMA_IT: specifies the DMA interrupts sources to be enabled
|
|
||||||
* or disabled.
|
|
||||||
* This parameter can be any combination of the following values:
|
|
||||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
|
||||||
* @arg DMA_IT_HT: Half transfer interrupt mask
|
|
||||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
|
||||||
* @param NewState: new state of the specified DMA interrupts.
|
|
||||||
* This parameter can be: ENABLE or DISABLE.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
|
||||||
assert_param(IS_DMA_CONFIG_IT(DMA_IT));
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
/* Enable the selected DMA interrupts */
|
|
||||||
DMAy_Channelx->CCR |= DMA_IT;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Disable the selected DMA interrupts */
|
|
||||||
DMAy_Channelx->CCR &= ~DMA_IT;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Checks whether the specified DMAy Channelx flag is set or not.
|
|
||||||
* @param DMAy_FLAG: specifies the flag to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
|
|
||||||
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
|
|
||||||
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
|
|
||||||
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
|
|
||||||
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
|
|
||||||
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
|
|
||||||
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
|
|
||||||
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
|
|
||||||
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
|
|
||||||
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
|
|
||||||
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
|
|
||||||
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
|
|
||||||
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
|
|
||||||
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
|
|
||||||
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
|
|
||||||
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
|
|
||||||
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
|
|
||||||
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
|
|
||||||
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
|
|
||||||
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
|
|
||||||
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
|
|
||||||
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
|
|
||||||
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
|
|
||||||
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
|
|
||||||
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
|
|
||||||
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
|
|
||||||
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
|
|
||||||
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
|
|
||||||
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
|
|
||||||
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
|
|
||||||
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
|
|
||||||
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
|
|
||||||
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
|
|
||||||
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
|
|
||||||
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
|
|
||||||
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
|
|
||||||
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
|
|
||||||
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
|
|
||||||
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
|
|
||||||
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
|
|
||||||
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
|
|
||||||
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
|
|
||||||
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
|
|
||||||
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
|
|
||||||
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
|
|
||||||
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
|
|
||||||
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
|
|
||||||
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
|
|
||||||
*
|
|
||||||
* @note
|
|
||||||
* The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags
|
|
||||||
* relative to the same channel is set (Transfer Complete, Half-transfer
|
|
||||||
* Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or
|
|
||||||
* DMAy_FLAG_TEx).
|
|
||||||
*
|
|
||||||
* @retval The new state of DMAy_FLAG (SET or RESET).
|
|
||||||
*/
|
|
||||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
|
|
||||||
{
|
|
||||||
FlagStatus bitstatus = RESET;
|
|
||||||
uint32_t tmpreg = 0;
|
|
||||||
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
|
|
||||||
|
|
||||||
/* Calculate the used DMAy */
|
|
||||||
if ((DMAy_FLAG & FLAG_MASK) == (uint32_t)RESET)
|
|
||||||
{
|
|
||||||
/* Get DMA1 ISR register value */
|
|
||||||
tmpreg = DMA1->ISR;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Get DMA2 ISR register value */
|
|
||||||
tmpreg = DMA2->ISR;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Check the status of the specified DMAy flag */
|
|
||||||
if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
|
|
||||||
{
|
|
||||||
/* DMAy_FLAG is set */
|
|
||||||
bitstatus = SET;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* DMAy_FLAG is reset */
|
|
||||||
bitstatus = RESET;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Return the DMAy_FLAG status */
|
|
||||||
return bitstatus;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clears the DMAy Channelx's pending flags.
|
|
||||||
* @param DMAy_FLAG: specifies the flag to clear.
|
|
||||||
* This parameter can be any combination (for the same DMA) of the following values:
|
|
||||||
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
|
|
||||||
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
|
|
||||||
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
|
|
||||||
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
|
|
||||||
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
|
|
||||||
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
|
|
||||||
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
|
|
||||||
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
|
|
||||||
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
|
|
||||||
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
|
|
||||||
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
|
|
||||||
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
|
|
||||||
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
|
|
||||||
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
|
|
||||||
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
|
|
||||||
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
|
|
||||||
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
|
|
||||||
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
|
|
||||||
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
|
|
||||||
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
|
|
||||||
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
|
|
||||||
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
|
|
||||||
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
|
|
||||||
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
|
|
||||||
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
|
|
||||||
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
|
|
||||||
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
|
|
||||||
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
|
|
||||||
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
|
|
||||||
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
|
|
||||||
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
|
|
||||||
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
|
|
||||||
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
|
|
||||||
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
|
|
||||||
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
|
|
||||||
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
|
|
||||||
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
|
|
||||||
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
|
|
||||||
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
|
|
||||||
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
|
|
||||||
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
|
|
||||||
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
|
|
||||||
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
|
|
||||||
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
|
|
||||||
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
|
|
||||||
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
|
|
||||||
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
|
|
||||||
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
|
|
||||||
*
|
|
||||||
* @note
|
|
||||||
* Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
|
|
||||||
* relative to the same channel (Transfer Complete, Half-transfer Complete and
|
|
||||||
* Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
|
|
||||||
*
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DMA_ClearFlag(uint32_t DMAy_FLAG)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
|
|
||||||
|
|
||||||
if ((DMAy_FLAG & FLAG_MASK) == (uint32_t)RESET)
|
|
||||||
{
|
|
||||||
/* Clear the selected DMAy flags */
|
|
||||||
DMA1->IFCR = DMAy_FLAG;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Clear the selected DMAy flags */
|
|
||||||
DMA2->IFCR = DMAy_FLAG;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
|
|
||||||
* @param DMAy_IT: specifies the DMAy interrupt source to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
|
||||||
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
|
||||||
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
|
||||||
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
|
||||||
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
|
||||||
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
|
||||||
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
|
||||||
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
|
||||||
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
|
||||||
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
|
||||||
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
|
||||||
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
|
||||||
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
|
||||||
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
|
||||||
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
|
||||||
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
|
||||||
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
|
||||||
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
|
||||||
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
|
||||||
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
|
||||||
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
|
|
||||||
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
|
|
||||||
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
|
|
||||||
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
|
|
||||||
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
|
|
||||||
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
|
|
||||||
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
|
|
||||||
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
|
|
||||||
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
|
|
||||||
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
|
|
||||||
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
|
|
||||||
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
|
|
||||||
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
|
|
||||||
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
|
|
||||||
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
|
|
||||||
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
|
|
||||||
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
|
|
||||||
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
|
|
||||||
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
|
|
||||||
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
|
|
||||||
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
|
|
||||||
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
|
|
||||||
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
|
|
||||||
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
|
|
||||||
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
|
|
||||||
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
|
|
||||||
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
|
|
||||||
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
|
|
||||||
*
|
|
||||||
* @note
|
|
||||||
* The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other
|
|
||||||
* interrupts relative to the same channel is set (Transfer Complete,
|
|
||||||
* Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx,
|
|
||||||
* DMAy_IT_HTx or DMAy_IT_TEx).
|
|
||||||
*
|
|
||||||
* @retval The new state of DMAy_IT (SET or RESET).
|
|
||||||
*/
|
|
||||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
|
|
||||||
{
|
|
||||||
ITStatus bitstatus = RESET;
|
|
||||||
uint32_t tmpreg = 0;
|
|
||||||
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DMA_GET_IT(DMAy_IT));
|
|
||||||
|
|
||||||
/* Calculate the used DMAy */
|
|
||||||
if ((DMAy_IT & FLAG_MASK) == (uint32_t)RESET)
|
|
||||||
{
|
|
||||||
/* Get DMA1 ISR register value */
|
|
||||||
tmpreg = DMA1->ISR;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Get DMA2 ISR register value */
|
|
||||||
tmpreg = DMA2->ISR;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Check the status of the specified DMAy interrupt */
|
|
||||||
if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
|
|
||||||
{
|
|
||||||
/* DMAy_IT is set */
|
|
||||||
bitstatus = SET;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* DMAy_IT is reset */
|
|
||||||
bitstatus = RESET;
|
|
||||||
}
|
|
||||||
/* Return the DMAy_IT status */
|
|
||||||
return bitstatus;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clears the DMAy Channelx's interrupt pending bits.
|
|
||||||
* @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
|
|
||||||
* This parameter can be any combination (for the same DMA) of the following values:
|
|
||||||
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
|
||||||
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
|
||||||
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
|
||||||
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
|
||||||
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
|
||||||
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
|
||||||
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
|
||||||
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
|
||||||
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
|
||||||
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
|
||||||
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
|
||||||
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
|
||||||
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
|
||||||
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
|
||||||
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
|
||||||
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
|
||||||
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
|
||||||
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
|
||||||
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
|
||||||
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
|
||||||
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
|
|
||||||
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
|
|
||||||
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
|
|
||||||
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
|
|
||||||
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
|
|
||||||
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
|
|
||||||
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
|
|
||||||
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
|
|
||||||
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
|
|
||||||
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
|
|
||||||
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
|
|
||||||
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
|
|
||||||
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
|
|
||||||
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
|
|
||||||
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
|
|
||||||
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
|
|
||||||
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
|
|
||||||
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
|
|
||||||
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
|
|
||||||
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
|
|
||||||
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
|
|
||||||
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
|
|
||||||
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
|
|
||||||
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
|
|
||||||
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
|
|
||||||
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
|
|
||||||
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
|
|
||||||
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
|
|
||||||
*
|
|
||||||
* @note
|
|
||||||
* Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other
|
|
||||||
* interrupts relative to the same channel (Transfer Complete, Half-transfer
|
|
||||||
* Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and
|
|
||||||
* DMAy_IT_TEx).
|
|
||||||
*
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
|
|
||||||
|
|
||||||
/* Calculate the used DMAy */
|
|
||||||
if ((DMAy_IT & FLAG_MASK) == (uint32_t)RESET)
|
|
||||||
{
|
|
||||||
/* Clear the selected DMAy interrupt pending bits */
|
|
||||||
DMA1->IFCR = DMAy_IT;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Clear the selected DMAy interrupt pending bits */
|
|
||||||
DMA2->IFCR = DMAy_IT;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,445 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32l1xx_dma.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @version V1.3.0
|
|
||||||
* @date 31-January-2014
|
|
||||||
* @brief This file contains all the functions prototypes for the DMA firmware
|
|
||||||
* library.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef __STM32L1xx_DMA_H
|
|
||||||
#define __STM32L1xx_DMA_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32l1xx.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup DMA
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief DMA Init structure definition
|
|
||||||
*/
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
|
|
||||||
|
|
||||||
uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
|
|
||||||
|
|
||||||
uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
|
|
||||||
This parameter can be a value of @ref DMA_data_transfer_direction */
|
|
||||||
|
|
||||||
uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
|
|
||||||
The data unit is equal to the configuration set in DMA_PeripheralDataSize
|
|
||||||
or DMA_MemoryDataSize members depending in the transfer direction. */
|
|
||||||
|
|
||||||
uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
|
|
||||||
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
|
|
||||||
|
|
||||||
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
|
|
||||||
This parameter can be a value of @ref DMA_memory_incremented_mode */
|
|
||||||
|
|
||||||
uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
|
|
||||||
This parameter can be a value of @ref DMA_peripheral_data_size */
|
|
||||||
|
|
||||||
uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
|
|
||||||
This parameter can be a value of @ref DMA_memory_data_size */
|
|
||||||
|
|
||||||
uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
|
||||||
This parameter can be a value of @ref DMA_circular_normal_mode
|
|
||||||
@note: The circular buffer mode cannot be used if the memory-to-memory
|
|
||||||
data transfer is configured on the selected Channel */
|
|
||||||
|
|
||||||
uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
|
||||||
This parameter can be a value of @ref DMA_priority_level */
|
|
||||||
|
|
||||||
uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
|
|
||||||
This parameter can be a value of @ref DMA_memory_to_memory */
|
|
||||||
}DMA_InitTypeDef;
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_Exported_Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
|
|
||||||
((PERIPH) == DMA1_Channel2) || \
|
|
||||||
((PERIPH) == DMA1_Channel3) || \
|
|
||||||
((PERIPH) == DMA1_Channel4) || \
|
|
||||||
((PERIPH) == DMA1_Channel5) || \
|
|
||||||
((PERIPH) == DMA1_Channel6) || \
|
|
||||||
((PERIPH) == DMA1_Channel7) || \
|
|
||||||
((PERIPH) == DMA2_Channel1) || \
|
|
||||||
((PERIPH) == DMA2_Channel2) || \
|
|
||||||
((PERIPH) == DMA2_Channel3) || \
|
|
||||||
((PERIPH) == DMA2_Channel4) || \
|
|
||||||
((PERIPH) == DMA2_Channel5))
|
|
||||||
|
|
||||||
/** @defgroup DMA_data_transfer_direction
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
|
|
||||||
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
|
|
||||||
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
|
|
||||||
((DIR) == DMA_DIR_PeripheralSRC))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_peripheral_incremented_mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
|
|
||||||
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
|
|
||||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
|
|
||||||
((STATE) == DMA_PeripheralInc_Disable))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_memory_incremented_mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
|
|
||||||
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
|
|
||||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
|
|
||||||
((STATE) == DMA_MemoryInc_Disable))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_peripheral_data_size
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
|
|
||||||
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
|
|
||||||
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
|
|
||||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
|
|
||||||
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
|
|
||||||
((SIZE) == DMA_PeripheralDataSize_Word))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_memory_data_size
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
|
|
||||||
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
|
|
||||||
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
|
|
||||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
|
|
||||||
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
|
|
||||||
((SIZE) == DMA_MemoryDataSize_Word))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_circular_normal_mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DMA_Mode_Circular ((uint32_t)0x00000020)
|
|
||||||
#define DMA_Mode_Normal ((uint32_t)0x00000000)
|
|
||||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_priority_level
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
|
|
||||||
#define DMA_Priority_High ((uint32_t)0x00002000)
|
|
||||||
#define DMA_Priority_Medium ((uint32_t)0x00001000)
|
|
||||||
#define DMA_Priority_Low ((uint32_t)0x00000000)
|
|
||||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
|
|
||||||
((PRIORITY) == DMA_Priority_High) || \
|
|
||||||
((PRIORITY) == DMA_Priority_Medium) || \
|
|
||||||
((PRIORITY) == DMA_Priority_Low))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_memory_to_memory
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DMA_M2M_Enable ((uint32_t)0x00004000)
|
|
||||||
#define DMA_M2M_Disable ((uint32_t)0x00000000)
|
|
||||||
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_interrupts_definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DMA_IT_TC ((uint32_t)0x00000002)
|
|
||||||
#define DMA_IT_HT ((uint32_t)0x00000004)
|
|
||||||
#define DMA_IT_TE ((uint32_t)0x00000008)
|
|
||||||
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
|
|
||||||
|
|
||||||
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
|
|
||||||
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
|
|
||||||
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
|
|
||||||
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
|
|
||||||
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
|
|
||||||
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
|
|
||||||
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
|
|
||||||
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
|
|
||||||
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
|
|
||||||
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
|
|
||||||
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
|
|
||||||
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
|
|
||||||
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
|
|
||||||
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
|
|
||||||
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
|
|
||||||
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
|
|
||||||
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
|
|
||||||
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
|
|
||||||
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
|
|
||||||
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
|
|
||||||
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
|
|
||||||
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
|
|
||||||
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
|
|
||||||
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
|
|
||||||
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
|
|
||||||
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
|
|
||||||
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
|
|
||||||
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
|
|
||||||
|
|
||||||
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
|
|
||||||
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
|
|
||||||
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
|
|
||||||
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
|
|
||||||
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
|
|
||||||
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
|
|
||||||
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
|
|
||||||
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
|
|
||||||
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
|
|
||||||
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
|
|
||||||
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
|
|
||||||
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
|
|
||||||
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
|
|
||||||
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
|
|
||||||
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
|
|
||||||
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
|
|
||||||
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
|
|
||||||
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
|
|
||||||
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
|
|
||||||
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
|
|
||||||
|
|
||||||
#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
|
|
||||||
|
|
||||||
#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
|
|
||||||
((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
|
|
||||||
((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
|
|
||||||
((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
|
|
||||||
((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
|
|
||||||
((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
|
|
||||||
((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
|
|
||||||
((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
|
|
||||||
((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
|
|
||||||
((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
|
|
||||||
((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
|
|
||||||
((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
|
|
||||||
((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
|
|
||||||
((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
|
|
||||||
((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
|
|
||||||
((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
|
|
||||||
((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
|
|
||||||
((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
|
|
||||||
((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
|
|
||||||
((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
|
|
||||||
((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
|
|
||||||
((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
|
|
||||||
((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
|
|
||||||
((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_flags_definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
|
|
||||||
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
|
|
||||||
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
|
|
||||||
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
|
|
||||||
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
|
|
||||||
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
|
|
||||||
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
|
|
||||||
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
|
|
||||||
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
|
|
||||||
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
|
|
||||||
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
|
|
||||||
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
|
|
||||||
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
|
|
||||||
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
|
|
||||||
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
|
|
||||||
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
|
|
||||||
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
|
|
||||||
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
|
|
||||||
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
|
|
||||||
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
|
|
||||||
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
|
|
||||||
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
|
|
||||||
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
|
|
||||||
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
|
|
||||||
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
|
|
||||||
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
|
|
||||||
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
|
|
||||||
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
|
|
||||||
|
|
||||||
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
|
|
||||||
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
|
|
||||||
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
|
|
||||||
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
|
|
||||||
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
|
|
||||||
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
|
|
||||||
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
|
|
||||||
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
|
|
||||||
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
|
|
||||||
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
|
|
||||||
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
|
|
||||||
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
|
|
||||||
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
|
|
||||||
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
|
|
||||||
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
|
|
||||||
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
|
|
||||||
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
|
|
||||||
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
|
|
||||||
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
|
|
||||||
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
|
|
||||||
|
|
||||||
#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
|
|
||||||
|
|
||||||
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
|
|
||||||
((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
|
|
||||||
((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
|
|
||||||
((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
|
|
||||||
((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
|
|
||||||
((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
|
|
||||||
((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
|
|
||||||
((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
|
|
||||||
((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
|
|
||||||
((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
|
|
||||||
((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
|
|
||||||
((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
|
|
||||||
((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
|
|
||||||
((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
|
|
||||||
((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
|
|
||||||
((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
|
|
||||||
((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
|
|
||||||
((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
|
|
||||||
((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
|
|
||||||
((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
|
|
||||||
((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
|
|
||||||
((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
|
|
||||||
((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
|
|
||||||
((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_Buffer_Size
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
/* Exported functions ------------------------------------------------------- */
|
|
||||||
|
|
||||||
/* Function used to set the DMA configuration to the default reset state *****/
|
|
||||||
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
|
|
||||||
|
|
||||||
/* Initialization and Configuration functions *********************************/
|
|
||||||
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
|
|
||||||
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
|
|
||||||
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
|
|
||||||
|
|
||||||
/* Data Counter functions *****************************************************/
|
|
||||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
|
|
||||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
|
|
||||||
|
|
||||||
/* Interrupts and flags management functions **********************************/
|
|
||||||
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
|
|
||||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
|
|
||||||
void DMA_ClearFlag(uint32_t DMAy_FLAG);
|
|
||||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
|
|
||||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /*__STM32L1xx_DMA_H */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,325 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32l1xx_exti.c
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @version V1.3.0
|
|
||||||
* @date 31-January-2014
|
|
||||||
* @brief This file provides firmware functions to manage the following
|
|
||||||
* functionalities of the EXTI peripheral:
|
|
||||||
* + Initialization and Configuration
|
|
||||||
* + Interrupts and flags management
|
|
||||||
*
|
|
||||||
* @verbatim
|
|
||||||
==============================================================================
|
|
||||||
##### EXTI features #####
|
|
||||||
==============================================================================
|
|
||||||
[..] External interrupt/event lines are mapped as following:
|
|
||||||
(#) All available GPIO pins are connected to the 16 external
|
|
||||||
interrupt/event lines from EXTI0 to EXTI15.
|
|
||||||
(#) EXTI line 16 is connected to the PVD output.
|
|
||||||
(#) EXTI line 17 is connected to the RTC Alarm event.
|
|
||||||
(#) EXTI line 18 is connected to the USB Device FS wakeup event.
|
|
||||||
(#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events.
|
|
||||||
(#) EXTI line 20 is connected to the RTC Wakeup event.
|
|
||||||
(#) EXTI line 21 is connected to the Comparator 1 wakeup event.
|
|
||||||
(#) EXTI line 22 is connected to the Comparator 2 wakeup event.
|
|
||||||
(#) EXTI line 23 is connected to the Comparator channel acquisition wakeup event.
|
|
||||||
|
|
||||||
|
|
||||||
##### How to use this driver #####
|
|
||||||
==============================================================================
|
|
||||||
[..] In order to use an I/O pin as an external interrupt source, follow
|
|
||||||
steps below:
|
|
||||||
(#) Configure the I/O in input mode using GPIO_Init()
|
|
||||||
(#) Select the input source pin for the EXTI line using
|
|
||||||
SYSCFG_EXTILineConfig()
|
|
||||||
(#) Select the mode(interrupt, event) and configure the trigger
|
|
||||||
selection (Rising, falling or both) using EXTI_Init()
|
|
||||||
(#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
|
|
||||||
[..]
|
|
||||||
(@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
|
|
||||||
registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
|
||||||
|
|
||||||
* @endverbatim
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32l1xx_exti.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup EXTI
|
|
||||||
* @brief EXTI driver modules
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/
|
|
||||||
/* Private define ------------------------------------------------------------*/
|
|
||||||
#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
|
|
||||||
|
|
||||||
/* Private macro -------------------------------------------------------------*/
|
|
||||||
/* Private variables ---------------------------------------------------------*/
|
|
||||||
/* Private function prototypes -----------------------------------------------*/
|
|
||||||
/* Private functions ---------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup EXTI_Private_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup EXTI_Group1 Initialization and Configuration functions
|
|
||||||
* @brief Initialization and Configuration functions
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
==============================================================================
|
|
||||||
##### Initialization and Configuration functions #####
|
|
||||||
==============================================================================
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Deinitializes the EXTI peripheral registers to their default reset values.
|
|
||||||
* @param None
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void EXTI_DeInit(void)
|
|
||||||
{
|
|
||||||
EXTI->IMR = 0x00000000;
|
|
||||||
EXTI->EMR = 0x00000000;
|
|
||||||
EXTI->RTSR = 0x00000000;
|
|
||||||
EXTI->FTSR = 0x00000000;
|
|
||||||
EXTI->PR = 0x00FFFFFF;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initializes the EXTI peripheral according to the specified
|
|
||||||
* parameters in the EXTI_InitStruct.
|
|
||||||
* EXTI_Line specifies the EXTI line (EXTI0....EXTI23).
|
|
||||||
* EXTI_Mode specifies which EXTI line is used as interrupt or an event.
|
|
||||||
* EXTI_Trigger selects the trigger. When the trigger occurs, interrupt
|
|
||||||
* pending bit will be set.
|
|
||||||
* EXTI_LineCmd controls (Enable/Disable) the EXTI line.
|
|
||||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
|
|
||||||
* that contains the configuration information for the EXTI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
|
|
||||||
{
|
|
||||||
uint32_t tmp = 0;
|
|
||||||
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
|
|
||||||
assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
|
|
||||||
assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
|
|
||||||
|
|
||||||
tmp = (uint32_t)EXTI_BASE;
|
|
||||||
|
|
||||||
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
|
|
||||||
{
|
|
||||||
/* Clear EXTI line configuration */
|
|
||||||
EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
|
|
||||||
EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
|
|
||||||
|
|
||||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
|
||||||
|
|
||||||
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
|
|
||||||
|
|
||||||
/* Clear Rising Falling edge configuration */
|
|
||||||
EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
|
|
||||||
EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
|
|
||||||
|
|
||||||
/* Select the trigger for the selected external interrupts */
|
|
||||||
if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
|
|
||||||
{
|
|
||||||
/* Rising Falling edge */
|
|
||||||
EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
|
|
||||||
EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
tmp = (uint32_t)EXTI_BASE;
|
|
||||||
tmp += EXTI_InitStruct->EXTI_Trigger;
|
|
||||||
|
|
||||||
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
|
||||||
|
|
||||||
/* Disable the selected external lines */
|
|
||||||
*(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Fills each EXTI_InitStruct member with its reset value.
|
|
||||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
|
|
||||||
* be initialized.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
|
|
||||||
{
|
|
||||||
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
|
|
||||||
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
|
|
||||||
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
|
|
||||||
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Generates a Software interrupt on selected EXTI line.
|
|
||||||
* @param EXTI_Line: specifies the EXTI line on which the software interrupt
|
|
||||||
* will be generated.
|
|
||||||
* This parameter can be any combination of EXTI_Linex where x can be (0..23).
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
|
||||||
|
|
||||||
EXTI->SWIER |= EXTI_Line;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup EXTI_Group2 Interrupts and flags management functions
|
|
||||||
* @brief Interrupts and flags management functions
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
==============================================================================
|
|
||||||
##### Interrupts and flags management functions #####
|
|
||||||
==============================================================================
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
|
||||||
* @param EXTI_Line: specifies the EXTI line flag to check.
|
|
||||||
* This parameter can be:
|
|
||||||
* EXTI_Linex: External interrupt line x where x(0..23).
|
|
||||||
* @retval The new state of EXTI_Line (SET or RESET).
|
|
||||||
*/
|
|
||||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
|
|
||||||
{
|
|
||||||
FlagStatus bitstatus = RESET;
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
|
||||||
|
|
||||||
if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
|
|
||||||
{
|
|
||||||
bitstatus = SET;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
bitstatus = RESET;
|
|
||||||
}
|
|
||||||
return bitstatus;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clears the EXTI's line pending flags.
|
|
||||||
* @param EXTI_Line: specifies the EXTI lines flags to clear.
|
|
||||||
* This parameter can be any combination of EXTI_Linex where x can be (0..23).
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void EXTI_ClearFlag(uint32_t EXTI_Line)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
|
||||||
|
|
||||||
EXTI->PR = EXTI_Line;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
|
||||||
* @param EXTI_Line: specifies the EXTI line to check.
|
|
||||||
* This parameter can be:
|
|
||||||
* EXTI_Linex: External interrupt line x where x(0..23).
|
|
||||||
* @retval The new state of EXTI_Line (SET or RESET).
|
|
||||||
*/
|
|
||||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
|
|
||||||
{
|
|
||||||
FlagStatus bitstatus = RESET;
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
|
||||||
|
|
||||||
if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
|
|
||||||
{
|
|
||||||
bitstatus = SET;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
bitstatus = RESET;
|
|
||||||
}
|
|
||||||
return bitstatus;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clears the EXTI's line pending bits.
|
|
||||||
* @param EXTI_Line: specifies the EXTI lines to clear.
|
|
||||||
* This parameter can be any combination of EXTI_Linex where x can be (0..23).
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
|
||||||
|
|
||||||
EXTI->PR = EXTI_Line;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,209 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32l1xx_exti.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @version V1.3.0
|
|
||||||
* @date 31-January-2014
|
|
||||||
* @brief This file contains all the functions prototypes for the EXTI firmware
|
|
||||||
* library.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef __STM32L1xx_EXTI_H
|
|
||||||
#define __STM32L1xx_EXTI_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32l1xx.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup EXTI
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief EXTI mode enumeration
|
|
||||||
*/
|
|
||||||
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
EXTI_Mode_Interrupt = 0x00,
|
|
||||||
EXTI_Mode_Event = 0x04
|
|
||||||
}EXTIMode_TypeDef;
|
|
||||||
|
|
||||||
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief EXTI Trigger enumeration
|
|
||||||
*/
|
|
||||||
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
EXTI_Trigger_Rising = 0x08,
|
|
||||||
EXTI_Trigger_Falling = 0x0C,
|
|
||||||
EXTI_Trigger_Rising_Falling = 0x10
|
|
||||||
}EXTITrigger_TypeDef;
|
|
||||||
|
|
||||||
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
|
|
||||||
((TRIGGER) == EXTI_Trigger_Falling) || \
|
|
||||||
((TRIGGER) == EXTI_Trigger_Rising_Falling))
|
|
||||||
/**
|
|
||||||
* @brief EXTI Init Structure definition
|
|
||||||
*/
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
|
|
||||||
This parameter can be any combination of @ref EXTI_Lines */
|
|
||||||
|
|
||||||
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
|
|
||||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
|
||||||
|
|
||||||
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
|
|
||||||
This parameter can be a value of @ref EXTITrigger_TypeDef */
|
|
||||||
|
|
||||||
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
|
|
||||||
This parameter can be set either to ENABLE or DISABLE */
|
|
||||||
}EXTI_InitTypeDef;
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup EXTI_Exported_Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup EXTI_Lines
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */
|
|
||||||
#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */
|
|
||||||
#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */
|
|
||||||
#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */
|
|
||||||
#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */
|
|
||||||
#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */
|
|
||||||
#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */
|
|
||||||
#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */
|
|
||||||
#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */
|
|
||||||
#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */
|
|
||||||
#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */
|
|
||||||
#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */
|
|
||||||
#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */
|
|
||||||
#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */
|
|
||||||
#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */
|
|
||||||
#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */
|
|
||||||
#define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16
|
|
||||||
Connected to the PVD Output */
|
|
||||||
#define EXTI_Line17 ((uint32_t)0x00020000) /*!< External interrupt line 17
|
|
||||||
Connected to the RTC Alarm
|
|
||||||
event */
|
|
||||||
#define EXTI_Line18 ((uint32_t)0x00040000) /*!< External interrupt line 18
|
|
||||||
Connected to the USB Device
|
|
||||||
FS Wakeup from suspend event */
|
|
||||||
#define EXTI_Line19 ((uint32_t)0x00080000) /*!< External interrupt line 19
|
|
||||||
Connected to the RTC Tamper
|
|
||||||
and Time Stamp events */
|
|
||||||
#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20
|
|
||||||
Connected to the RTC Wakeup
|
|
||||||
event */
|
|
||||||
#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21
|
|
||||||
Connected to the Comparator 1
|
|
||||||
event */
|
|
||||||
|
|
||||||
#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22
|
|
||||||
Connected to the Comparator 2
|
|
||||||
event */
|
|
||||||
|
|
||||||
#define EXTI_Line23 ((uint32_t)0x00800000) /*!< External interrupt line 23
|
|
||||||
Comparator channel acquisition event */
|
|
||||||
|
|
||||||
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF000000) == 0x00) && ((LINE) != (uint16_t)0x00))
|
|
||||||
|
|
||||||
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
|
|
||||||
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
|
|
||||||
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
|
|
||||||
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
|
|
||||||
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
|
|
||||||
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
|
|
||||||
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
|
|
||||||
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
|
|
||||||
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
|
|
||||||
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
|
|
||||||
((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
|
|
||||||
((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
/* Exported functions ------------------------------------------------------- */
|
|
||||||
/* Function used to set the EXTI configuration to the default reset state *****/
|
|
||||||
void EXTI_DeInit(void);
|
|
||||||
|
|
||||||
/* Initialization and Configuration functions *********************************/
|
|
||||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
|
|
||||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
|
|
||||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
|
|
||||||
|
|
||||||
/* Interrupts and flags management functions **********************************/
|
|
||||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
|
|
||||||
void EXTI_ClearFlag(uint32_t EXTI_Line);
|
|
||||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
|
|
||||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __STM32L1xx_EXTI_H */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,492 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32l1xx_flash.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @version V1.3.0
|
|
||||||
* @date 31-January-2014
|
|
||||||
* @brief This file contains all the functions prototypes for the FLASH
|
|
||||||
* firmware library.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef __STM32L1xx_FLASH_H
|
|
||||||
#define __STM32L1xx_FLASH_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32l1xx.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup FLASH
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief FLASH Status
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
FLASH_BUSY = 1,
|
|
||||||
FLASH_ERROR_WRP,
|
|
||||||
FLASH_ERROR_PROGRAM,
|
|
||||||
FLASH_COMPLETE,
|
|
||||||
FLASH_TIMEOUT
|
|
||||||
}FLASH_Status;
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup FLASH_Exported_Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup FLASH_Latency
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define FLASH_Latency_0 ((uint8_t)0x00) /*!< FLASH Zero Latency cycle */
|
|
||||||
#define FLASH_Latency_1 ((uint8_t)0x01) /*!< FLASH One Latency cycle */
|
|
||||||
|
|
||||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
|
|
||||||
((LATENCY) == FLASH_Latency_1))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup FLASH_Interrupts
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define FLASH_IT_EOP FLASH_PECR_EOPIE /*!< End of programming interrupt source */
|
|
||||||
#define FLASH_IT_ERR FLASH_PECR_ERRIE /*!< Error interrupt source */
|
|
||||||
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFCFFFF) == 0x00000000) && (((IT) != 0x00000000)))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup FLASH_Address
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_FLASH_DATA_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08080000) && ((ADDRESS) <= 0x08083FFF))
|
|
||||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0807FFFF))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup Option_Bytes_Write_Protection
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define OB_WRP_Pages0to15 ((uint32_t)0x00000001) /* Write protection of Sector0 */
|
|
||||||
#define OB_WRP_Pages16to31 ((uint32_t)0x00000002) /* Write protection of Sector1 */
|
|
||||||
#define OB_WRP_Pages32to47 ((uint32_t)0x00000004) /* Write protection of Sector2 */
|
|
||||||
#define OB_WRP_Pages48to63 ((uint32_t)0x00000008) /* Write protection of Sector3 */
|
|
||||||
#define OB_WRP_Pages64to79 ((uint32_t)0x00000010) /* Write protection of Sector4 */
|
|
||||||
#define OB_WRP_Pages80to95 ((uint32_t)0x00000020) /* Write protection of Sector5 */
|
|
||||||
#define OB_WRP_Pages96to111 ((uint32_t)0x00000040) /* Write protection of Sector6 */
|
|
||||||
#define OB_WRP_Pages112to127 ((uint32_t)0x00000080) /* Write protection of Sector7 */
|
|
||||||
#define OB_WRP_Pages128to143 ((uint32_t)0x00000100) /* Write protection of Sector8 */
|
|
||||||
#define OB_WRP_Pages144to159 ((uint32_t)0x00000200) /* Write protection of Sector9 */
|
|
||||||
#define OB_WRP_Pages160to175 ((uint32_t)0x00000400) /* Write protection of Sector10 */
|
|
||||||
#define OB_WRP_Pages176to191 ((uint32_t)0x00000800) /* Write protection of Sector11 */
|
|
||||||
#define OB_WRP_Pages192to207 ((uint32_t)0x00001000) /* Write protection of Sector12 */
|
|
||||||
#define OB_WRP_Pages208to223 ((uint32_t)0x00002000) /* Write protection of Sector13 */
|
|
||||||
#define OB_WRP_Pages224to239 ((uint32_t)0x00004000) /* Write protection of Sector14 */
|
|
||||||
#define OB_WRP_Pages240to255 ((uint32_t)0x00008000) /* Write protection of Sector15 */
|
|
||||||
#define OB_WRP_Pages256to271 ((uint32_t)0x00010000) /* Write protection of Sector16 */
|
|
||||||
#define OB_WRP_Pages272to287 ((uint32_t)0x00020000) /* Write protection of Sector17 */
|
|
||||||
#define OB_WRP_Pages288to303 ((uint32_t)0x00040000) /* Write protection of Sector18 */
|
|
||||||
#define OB_WRP_Pages304to319 ((uint32_t)0x00080000) /* Write protection of Sector19 */
|
|
||||||
#define OB_WRP_Pages320to335 ((uint32_t)0x00100000) /* Write protection of Sector20 */
|
|
||||||
#define OB_WRP_Pages336to351 ((uint32_t)0x00200000) /* Write protection of Sector21 */
|
|
||||||
#define OB_WRP_Pages352to367 ((uint32_t)0x00400000) /* Write protection of Sector22 */
|
|
||||||
#define OB_WRP_Pages368to383 ((uint32_t)0x00800000) /* Write protection of Sector23 */
|
|
||||||
#define OB_WRP_Pages384to399 ((uint32_t)0x01000000) /* Write protection of Sector24 */
|
|
||||||
#define OB_WRP_Pages400to415 ((uint32_t)0x02000000) /* Write protection of Sector25 */
|
|
||||||
#define OB_WRP_Pages416to431 ((uint32_t)0x04000000) /* Write protection of Sector26 */
|
|
||||||
#define OB_WRP_Pages432to447 ((uint32_t)0x08000000) /* Write protection of Sector27 */
|
|
||||||
#define OB_WRP_Pages448to463 ((uint32_t)0x10000000) /* Write protection of Sector28 */
|
|
||||||
#define OB_WRP_Pages464to479 ((uint32_t)0x20000000) /* Write protection of Sector29 */
|
|
||||||
#define OB_WRP_Pages480to495 ((uint32_t)0x40000000) /* Write protection of Sector30 */
|
|
||||||
#define OB_WRP_Pages496to511 ((uint32_t)0x80000000) /* Write protection of Sector31 */
|
|
||||||
|
|
||||||
#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
|
|
||||||
|
|
||||||
#define OB_WRP1_Pages512to527 ((uint32_t)0x00000001) /* Write protection of Sector32 */
|
|
||||||
#define OB_WRP1_Pages528to543 ((uint32_t)0x00000002) /* Write protection of Sector33 */
|
|
||||||
#define OB_WRP1_Pages544to559 ((uint32_t)0x00000004) /* Write protection of Sector34 */
|
|
||||||
#define OB_WRP1_Pages560to575 ((uint32_t)0x00000008) /* Write protection of Sector35 */
|
|
||||||
#define OB_WRP1_Pages576to591 ((uint32_t)0x00000010) /* Write protection of Sector36 */
|
|
||||||
#define OB_WRP1_Pages592to607 ((uint32_t)0x00000020) /* Write protection of Sector37 */
|
|
||||||
#define OB_WRP1_Pages608to623 ((uint32_t)0x00000040) /* Write protection of Sector38 */
|
|
||||||
#define OB_WRP1_Pages624to639 ((uint32_t)0x00000080) /* Write protection of Sector39 */
|
|
||||||
#define OB_WRP1_Pages640to655 ((uint32_t)0x00000100) /* Write protection of Sector40 */
|
|
||||||
#define OB_WRP1_Pages656to671 ((uint32_t)0x00000200) /* Write protection of Sector41 */
|
|
||||||
#define OB_WRP1_Pages672to687 ((uint32_t)0x00000400) /* Write protection of Sector42 */
|
|
||||||
#define OB_WRP1_Pages688to703 ((uint32_t)0x00000800) /* Write protection of Sector43 */
|
|
||||||
#define OB_WRP1_Pages704to719 ((uint32_t)0x00001000) /* Write protection of Sector44 */
|
|
||||||
#define OB_WRP1_Pages720to735 ((uint32_t)0x00002000) /* Write protection of Sector45 */
|
|
||||||
#define OB_WRP1_Pages736to751 ((uint32_t)0x00004000) /* Write protection of Sector46 */
|
|
||||||
#define OB_WRP1_Pages752to767 ((uint32_t)0x00008000) /* Write protection of Sector47 */
|
|
||||||
#define OB_WRP1_Pages768to783 ((uint32_t)0x00010000) /* Write protection of Sector48 */
|
|
||||||
#define OB_WRP1_Pages784to799 ((uint32_t)0x00020000) /* Write protection of Sector49 */
|
|
||||||
#define OB_WRP1_Pages800to815 ((uint32_t)0x00040000) /* Write protection of Sector50 */
|
|
||||||
#define OB_WRP1_Pages816to831 ((uint32_t)0x00080000) /* Write protection of Sector51 */
|
|
||||||
#define OB_WRP1_Pages832to847 ((uint32_t)0x00100000) /* Write protection of Sector52 */
|
|
||||||
#define OB_WRP1_Pages848to863 ((uint32_t)0x00200000) /* Write protection of Sector53 */
|
|
||||||
#define OB_WRP1_Pages864to879 ((uint32_t)0x00400000) /* Write protection of Sector54 */
|
|
||||||
#define OB_WRP1_Pages880to895 ((uint32_t)0x00800000) /* Write protection of Sector55 */
|
|
||||||
#define OB_WRP1_Pages896to911 ((uint32_t)0x01000000) /* Write protection of Sector56 */
|
|
||||||
#define OB_WRP1_Pages912to927 ((uint32_t)0x02000000) /* Write protection of Sector57 */
|
|
||||||
#define OB_WRP1_Pages928to943 ((uint32_t)0x04000000) /* Write protection of Sector58 */
|
|
||||||
#define OB_WRP1_Pages944to959 ((uint32_t)0x08000000) /* Write protection of Sector59 */
|
|
||||||
#define OB_WRP1_Pages960to975 ((uint32_t)0x10000000) /* Write protection of Sector60 */
|
|
||||||
#define OB_WRP1_Pages976to991 ((uint32_t)0x20000000) /* Write protection of Sector61 */
|
|
||||||
#define OB_WRP1_Pages992to1007 ((uint32_t)0x40000000) /* Write protection of Sector62 */
|
|
||||||
#define OB_WRP1_Pages1008to1023 ((uint32_t)0x80000000) /* Write protection of Sector63 */
|
|
||||||
|
|
||||||
#define OB_WRP1_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
|
|
||||||
|
|
||||||
#define OB_WRP2_Pages1024to1039 ((uint32_t)0x00000001) /* Write protection of Sector64 */
|
|
||||||
#define OB_WRP2_Pages1040to1055 ((uint32_t)0x00000002) /* Write protection of Sector65 */
|
|
||||||
#define OB_WRP2_Pages1056to1071 ((uint32_t)0x00000004) /* Write protection of Sector66 */
|
|
||||||
#define OB_WRP2_Pages1072to1087 ((uint32_t)0x00000008) /* Write protection of Sector67 */
|
|
||||||
#define OB_WRP2_Pages1088to1103 ((uint32_t)0x00000010) /* Write protection of Sector68 */
|
|
||||||
#define OB_WRP2_Pages1104to1119 ((uint32_t)0x00000020) /* Write protection of Sector69 */
|
|
||||||
#define OB_WRP2_Pages1120to1135 ((uint32_t)0x00000040) /* Write protection of Sector70 */
|
|
||||||
#define OB_WRP2_Pages1136to1151 ((uint32_t)0x00000080) /* Write protection of Sector71 */
|
|
||||||
#define OB_WRP2_Pages1152to1167 ((uint32_t)0x00000100) /* Write protection of Sector72 */
|
|
||||||
#define OB_WRP2_Pages1168to1183 ((uint32_t)0x00000200) /* Write protection of Sector73 */
|
|
||||||
#define OB_WRP2_Pages1184to1199 ((uint32_t)0x00000400) /* Write protection of Sector74 */
|
|
||||||
#define OB_WRP2_Pages1200to1215 ((uint32_t)0x00000800) /* Write protection of Sector75 */
|
|
||||||
#define OB_WRP2_Pages1216to1231 ((uint32_t)0x00001000) /* Write protection of Sector76 */
|
|
||||||
#define OB_WRP2_Pages1232to1247 ((uint32_t)0x00002000) /* Write protection of Sector77 */
|
|
||||||
#define OB_WRP2_Pages1248to1263 ((uint32_t)0x00004000) /* Write protection of Sector78 */
|
|
||||||
#define OB_WRP2_Pages1264to1279 ((uint32_t)0x00008000) /* Write protection of Sector79 */
|
|
||||||
#define OB_WRP2_Pages1280to1295 ((uint32_t)0x00010000) /* Write protection of Sector80 */
|
|
||||||
#define OB_WRP2_Pages1296to1311 ((uint32_t)0x00020000) /* Write protection of Sector81 */
|
|
||||||
#define OB_WRP2_Pages1312to1327 ((uint32_t)0x00040000) /* Write protection of Sector82 */
|
|
||||||
#define OB_WRP2_Pages1328to1343 ((uint32_t)0x00080000) /* Write protection of Sector83 */
|
|
||||||
#define OB_WRP2_Pages1344to1359 ((uint32_t)0x00100000) /* Write protection of Sector84 */
|
|
||||||
#define OB_WRP2_Pages1360to1375 ((uint32_t)0x00200000) /* Write protection of Sector85 */
|
|
||||||
#define OB_WRP2_Pages1376to1391 ((uint32_t)0x00400000) /* Write protection of Sector86 */
|
|
||||||
#define OB_WRP2_Pages1392to1407 ((uint32_t)0x00800000) /* Write protection of Sector87 */
|
|
||||||
#define OB_WRP2_Pages1408to1423 ((uint32_t)0x01000000) /* Write protection of Sector88 */
|
|
||||||
#define OB_WRP2_Pages1424to1439 ((uint32_t)0x02000000) /* Write protection of Sector89 */
|
|
||||||
#define OB_WRP2_Pages1440to1455 ((uint32_t)0x04000000) /* Write protection of Sector90 */
|
|
||||||
#define OB_WRP2_Pages1456to1471 ((uint32_t)0x08000000) /* Write protection of Sector91 */
|
|
||||||
#define OB_WRP2_Pages1472to1487 ((uint32_t)0x10000000) /* Write protection of Sector92 */
|
|
||||||
#define OB_WRP2_Pages1488to1503 ((uint32_t)0x20000000) /* Write protection of Sector93 */
|
|
||||||
#define OB_WRP2_Pages1504to1519 ((uint32_t)0x40000000) /* Write protection of Sector94 */
|
|
||||||
#define OB_WRP2_Pages1520to1535 ((uint32_t)0x80000000) /* Write protection of Sector95 */
|
|
||||||
|
|
||||||
#define OB_WRP2_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
|
|
||||||
|
|
||||||
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup Selection_Protection_Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define OB_PcROP_Enable ((uint16_t)0x0100) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
|
|
||||||
#define OB_PcROP_Disable ((uint16_t)0x0000) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */
|
|
||||||
#define IS_OB_PCROP_SELECT(OB_PcROP) (((OB_PcROP) == OB_PcROP_Enable) || ((OB_PcROP) == OB_PcROP_Disable))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup Option_Bytes_Read_Protection
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Read Protection Level
|
|
||||||
*/
|
|
||||||
#define OB_RDP_Level_0 ((uint8_t)0xAA)
|
|
||||||
#define OB_RDP_Level_1 ((uint8_t)0xBB)
|
|
||||||
/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
|
|
||||||
it's no more possible to go back to level 1 or 0 */
|
|
||||||
|
|
||||||
#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
|
|
||||||
((LEVEL) == OB_RDP_Level_1))/*||\
|
|
||||||
((LEVEL) == OB_RDP_Level_2))*/
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup Option_Bytes_IWatchdog
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define OB_IWDG_SW ((uint8_t)0x10) /*!< Software WDG selected */
|
|
||||||
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */
|
|
||||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup Option_Bytes_nRST_STOP
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define OB_STOP_NoRST ((uint8_t)0x20) /*!< No reset generated when entering in STOP */
|
|
||||||
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
|
|
||||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup Option_Bytes_nRST_STDBY
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define OB_STDBY_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */
|
|
||||||
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
|
|
||||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup Option_Bytes_BOOT
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define OB_BOOT_BANK2 ((uint8_t)0x00) /*!< At startup, if boot pins are set in boot from user Flash position
|
|
||||||
and this parameter is selected the device will boot from Bank 2
|
|
||||||
or Bank 1, depending on the activation of the bank */
|
|
||||||
#define OB_BOOT_BANK1 ((uint8_t)0x80) /*!< At startup, if boot pins are set in boot from user Flash position
|
|
||||||
and this parameter is selected the device will boot from Bank1(Default) */
|
|
||||||
#define IS_OB_BOOT_BANK(BANK) (((BANK) == OB_BOOT_BANK2) || ((BANK) == OB_BOOT_BANK1))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup Option_Bytes_BOR_Level
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define OB_BOR_OFF ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD
|
|
||||||
power supply reaches the PDR(Power Down Reset) threshold (1.5V) */
|
|
||||||
#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */
|
|
||||||
#define OB_BOR_LEVEL2 ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */
|
|
||||||
#define OB_BOR_LEVEL3 ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */
|
|
||||||
#define OB_BOR_LEVEL4 ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */
|
|
||||||
#define OB_BOR_LEVEL5 ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */
|
|
||||||
|
|
||||||
#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_OFF) || \
|
|
||||||
((LEVEL) == OB_BOR_LEVEL1) || \
|
|
||||||
((LEVEL) == OB_BOR_LEVEL2) || \
|
|
||||||
((LEVEL) == OB_BOR_LEVEL3) || \
|
|
||||||
((LEVEL) == OB_BOR_LEVEL4) || \
|
|
||||||
((LEVEL) == OB_BOR_LEVEL5))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup FLASH_Flags
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
|
||||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
|
|
||||||
#define FLASH_FLAG_ENDHV FLASH_SR_ENHV /*!< FLASH End of High Voltage flag */
|
|
||||||
#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */
|
|
||||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
|
|
||||||
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
|
|
||||||
#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
|
|
||||||
#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */
|
|
||||||
#define FLASH_FLAG_OPTVERRUSR FLASH_SR_OPTVERRUSR /*!< FLASH Option User Validity error flag */
|
|
||||||
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protected error flag
|
|
||||||
(available only in STM32L1XX_MDP devices) */
|
|
||||||
|
|
||||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFC0FD) == 0x00000000) && ((FLAG) != 0x00000000))
|
|
||||||
|
|
||||||
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
|
|
||||||
((FLAG) == FLASH_FLAG_ENDHV) || ((FLAG) == FLASH_FLAG_READY ) || \
|
|
||||||
((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR ) || \
|
|
||||||
((FLAG) == FLASH_FLAG_SIZERR) || ((FLAG) == FLASH_FLAG_OPTVERR) || \
|
|
||||||
((FLAG) == FLASH_FLAG_OPTVERRUSR) || ((FLAG) == FLASH_FLAG_RDERR))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup FLASH_Keys
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define FLASH_PDKEY1 ((uint32_t)0x04152637) /*!< Flash power down key1 */
|
|
||||||
#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1
|
|
||||||
to unlock the RUN_PD bit in FLASH_ACR */
|
|
||||||
|
|
||||||
#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEF) /*!< Flash program erase key1 */
|
|
||||||
#define FLASH_PEKEY2 ((uint32_t)0x02030405) /*!< Flash program erase key: used with FLASH_PEKEY2
|
|
||||||
to unlock the write access to the FLASH_PECR register and
|
|
||||||
data EEPROM */
|
|
||||||
|
|
||||||
#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF) /*!< Flash program memory key1 */
|
|
||||||
#define FLASH_PRGKEY2 ((uint32_t)0x13141516) /*!< Flash program memory key2: used with FLASH_PRGKEY2
|
|
||||||
to unlock the program memory */
|
|
||||||
|
|
||||||
#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8) /*!< Flash option key1 */
|
|
||||||
#define FLASH_OPTKEY2 ((uint32_t)0x24252627) /*!< Flash option key2: used with FLASH_OPTKEY1 to
|
|
||||||
unlock the write access to the option byte block */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup Timeout_definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x8000)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CMSIS_Legacy
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#if defined ( __ICCARM__ )
|
|
||||||
#define InterruptType_ACTLR_DISMCYCINT_Msk IntType_ACTLR_DISMCYCINT_Msk
|
|
||||||
#endif
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
/* Exported functions ------------------------------------------------------- */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief FLASH memory functions that can be executed from FLASH.
|
|
||||||
*/
|
|
||||||
/* FLASH Interface configuration functions ************************************/
|
|
||||||
void FLASH_SetLatency(uint32_t FLASH_Latency);
|
|
||||||
void FLASH_PrefetchBufferCmd(FunctionalState NewState);
|
|
||||||
void FLASH_ReadAccess64Cmd(FunctionalState NewState);
|
|
||||||
void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);
|
|
||||||
|
|
||||||
/* FLASH Memory Programming functions *****************************************/
|
|
||||||
void FLASH_Unlock(void);
|
|
||||||
void FLASH_Lock(void);
|
|
||||||
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
|
|
||||||
FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);
|
|
||||||
|
|
||||||
/* DATA EEPROM Programming functions ******************************************/
|
|
||||||
void DATA_EEPROM_Unlock(void);
|
|
||||||
void DATA_EEPROM_Lock(void);
|
|
||||||
void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState);
|
|
||||||
FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address);
|
|
||||||
FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address);
|
|
||||||
FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);
|
|
||||||
FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);
|
|
||||||
FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);
|
|
||||||
FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);
|
|
||||||
FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);
|
|
||||||
FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);
|
|
||||||
FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);
|
|
||||||
|
|
||||||
/* Option Bytes Programming functions *****************************************/
|
|
||||||
void FLASH_OB_Unlock(void);
|
|
||||||
void FLASH_OB_Lock(void);
|
|
||||||
void FLASH_OB_Launch(void);
|
|
||||||
FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
|
|
||||||
FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState);
|
|
||||||
FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState);
|
|
||||||
FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
|
|
||||||
FLASH_Status FLASH_OB_PCROPConfig(uint32_t OB_WRP, FunctionalState NewState);
|
|
||||||
FLASH_Status FLASH_OB_PCROP1Config(uint32_t OB_WRP1, FunctionalState NewState);
|
|
||||||
FLASH_Status FLASH_OB_PCROPSelectionConfig(uint16_t OB_PcROP);
|
|
||||||
FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
|
|
||||||
FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);
|
|
||||||
FLASH_Status FLASH_OB_BootConfig(uint8_t OB_BOOT);
|
|
||||||
uint8_t FLASH_OB_GetUser(void);
|
|
||||||
uint32_t FLASH_OB_GetWRP(void);
|
|
||||||
uint32_t FLASH_OB_GetWRP1(void);
|
|
||||||
uint32_t FLASH_OB_GetWRP2(void);
|
|
||||||
FlagStatus FLASH_OB_GetRDP(void);
|
|
||||||
FlagStatus FLASH_OB_GetSPRMOD(void);
|
|
||||||
uint8_t FLASH_OB_GetBOR(void);
|
|
||||||
|
|
||||||
/* Interrupts and flags management functions **********************************/
|
|
||||||
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
|
|
||||||
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
|
|
||||||
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
|
|
||||||
FLASH_Status FLASH_GetStatus(void);
|
|
||||||
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief FLASH memory functions that should be executed from internal SRAM.
|
|
||||||
* These functions are defined inside the "stm32l1xx_flash_ramfunc.c"
|
|
||||||
* file.
|
|
||||||
*/
|
|
||||||
__RAM_FUNC FLASH_RUNPowerDownCmd(FunctionalState NewState);
|
|
||||||
__RAM_FUNC FLASH_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2);
|
|
||||||
__RAM_FUNC FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer);
|
|
||||||
__RAM_FUNC FLASH_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2);
|
|
||||||
__RAM_FUNC DATA_EEPROM_EraseDoubleWord(uint32_t Address);
|
|
||||||
__RAM_FUNC DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __STM32L1xx_FLASH_H */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,295 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32l1xx_fsmc.c
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @version V1.3.0
|
|
||||||
* @date 31-January-2014
|
|
||||||
* @brief This file provides firmware functions to manage the following
|
|
||||||
* functionalities of the FSMC peripheral:
|
|
||||||
* + Initialization
|
|
||||||
* + Interrupts and flags management
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32l1xx_fsmc.h"
|
|
||||||
#include "stm32l1xx_rcc.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup FSMC
|
|
||||||
* @brief FSMC driver modules
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/
|
|
||||||
/* Private define ------------------------------------------------------------*/
|
|
||||||
/* Private macro -------------------------------------------------------------*/
|
|
||||||
/* Private variables ---------------------------------------------------------*/
|
|
||||||
/* Private function prototypes -----------------------------------------------*/
|
|
||||||
/* Private functions ---------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup FSMC_Private_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup FSMC_Group1 NOR/SRAM Controller functions
|
|
||||||
* @brief NOR/SRAM Controller functions
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
==============================================================================
|
|
||||||
##### NOR-SRAM Controller functions #####
|
|
||||||
==============================================================================
|
|
||||||
[..] The following sequence should be followed to configure the FSMC to
|
|
||||||
interface with SRAM, PSRAM, NOR or OneNAND memory connected to the
|
|
||||||
NOR/SRAM Bank:
|
|
||||||
(#) Enable the clock for the FSMC and associated GPIOs using the following
|
|
||||||
functions:
|
|
||||||
(++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
|
|
||||||
(++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);
|
|
||||||
(#) FSMC pins configuration
|
|
||||||
(++) Connect the involved FSMC pins to AF12 using the following function
|
|
||||||
GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
|
|
||||||
(++) Configure these FSMC pins in alternate function mode by calling the
|
|
||||||
function GPIO_Init();
|
|
||||||
(#) Declare a FSMC_NORSRAMInitTypeDef structure, for example:
|
|
||||||
FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; and fill the
|
|
||||||
FSMC_NORSRAMInitStructure variable with the allowed values of the
|
|
||||||
structure member.
|
|
||||||
(#) Initialize the NOR/SRAM Controller by calling the function
|
|
||||||
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
|
|
||||||
(#) Then enable the NOR/SRAM Bank, for example:
|
|
||||||
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
|
|
||||||
(#) At this stage you can read/write from/to the memory connected to the
|
|
||||||
NOR/SRAM Bank.
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
|
|
||||||
* reset values.
|
|
||||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
|
|
||||||
* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
|
|
||||||
* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
|
|
||||||
* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
|
|
||||||
{
|
|
||||||
/* Check the parameter */
|
|
||||||
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
|
|
||||||
|
|
||||||
/* FSMC_Bank1_NORSRAM1 */
|
|
||||||
if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
|
|
||||||
{
|
|
||||||
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
|
|
||||||
}
|
|
||||||
/* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
|
|
||||||
else
|
|
||||||
{
|
|
||||||
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
|
|
||||||
}
|
|
||||||
FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
|
|
||||||
FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initializes the FSMC NOR/SRAM Banks according to the specified
|
|
||||||
* parameters in the FSMC_NORSRAMInitStruct.
|
|
||||||
* @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
|
|
||||||
* structure that contains the configuration information for
|
|
||||||
* the FSMC NOR/SRAM specified Banks.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
|
|
||||||
{
|
|
||||||
/* Check the parameters */
|
|
||||||
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
|
|
||||||
assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
|
|
||||||
assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
|
|
||||||
assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
|
|
||||||
assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
|
|
||||||
assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
|
|
||||||
assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
|
|
||||||
assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
|
|
||||||
assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
|
|
||||||
assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
|
|
||||||
assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
|
|
||||||
assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
|
|
||||||
assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
|
|
||||||
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
|
|
||||||
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
|
|
||||||
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
|
|
||||||
assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
|
|
||||||
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
|
|
||||||
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
|
|
||||||
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
|
|
||||||
|
|
||||||
/* Bank1 NOR/SRAM control register configuration */
|
|
||||||
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
|
|
||||||
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_MemoryType |
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WrapMode |
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
|
|
||||||
|
|
||||||
if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
|
|
||||||
{
|
|
||||||
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)FSMC_BCR1_FACCEN;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Bank1 NOR/SRAM timing register configuration */
|
|
||||||
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
|
|
||||||
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
|
|
||||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
|
|
||||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
|
|
||||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
|
|
||||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
|
|
||||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
|
|
||||||
|
|
||||||
|
|
||||||
/* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
|
|
||||||
if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
|
|
||||||
{
|
|
||||||
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
|
|
||||||
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
|
|
||||||
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
|
|
||||||
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
|
|
||||||
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
|
|
||||||
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
|
|
||||||
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
|
|
||||||
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
|
|
||||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
|
|
||||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
|
|
||||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
|
|
||||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
|
|
||||||
* @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
|
|
||||||
* structure which will be initialized.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
|
|
||||||
{
|
|
||||||
/* Reset NOR/SRAM Init structure parameters values */
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
|
|
||||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables or disables the specified NOR/SRAM Memory Bank.
|
|
||||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
|
|
||||||
* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
|
|
||||||
* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
|
|
||||||
* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
|
|
||||||
* @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
|
||||||
{
|
|
||||||
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
|
|
||||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
||||||
|
|
||||||
if (NewState != DISABLE)
|
|
||||||
{
|
|
||||||
/* Enable the selected NOR/SRAM Bank by setting the MBKEN bit in the BCRx register */
|
|
||||||
FSMC_Bank1->BTCR[FSMC_Bank] |= FSMC_BCR1_MBKEN;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Disable the selected NOR/SRAM Bank by clearing the MBKEN bit in the BCRx register */
|
|
||||||
FSMC_Bank1->BTCR[FSMC_Bank] &= (uint32_t)(~FSMC_BCR1_MBKEN);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue