mirror of https://github.com/ARMmbed/mbed-os.git
Sync 802.15.4 RF drivers from master repos
-Sync STM S2LP with v0.0.6 in master repo -Sync Atmel with v3.0.8 in master repo -Sync MCR20A with v1.0.6 in master repopull/10624/head
Arto Kinnunen
parent
9687f59555
commit
f03e51a23d
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@ -79,7 +79,6 @@ extern void (*fhss_bc_switch)(void);
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#define MAC_TYPE_ACK (2)
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#define MAC_TYPE_COMMAND (3)
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#define MAC_DATA_PENDING 0x10
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#define MAC_FRAME_VERSION_2 (2)
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#define FC_DST_MODE 0x0C
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#define FC_SRC_MODE 0xC0
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#define FC_DST_ADDR_NONE 0x00
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@ -99,8 +98,6 @@ extern void (*fhss_bc_switch)(void);
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#define CS_SELECT() {rf->CS = 0;}
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#define CS_RELEASE() {rf->CS = 1;}
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extern const uint8_t ADDR_UNSPECIFIED[16];
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typedef enum {
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RF_MODE_NORMAL = 0,
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RF_MODE_SNIFFER = 1
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@ -183,6 +180,7 @@ static void rf_backup_timer_stop(void);
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static void rf_rx_ready_handler(void);
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static uint32_t read_irq_status(void);
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static bool rf_rx_filter(uint8_t *mac_header, uint8_t *mac_64bit_addr, uint8_t *mac_16bit_addr, uint8_t *pan_id);
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static void rf_cca_timer_start(uint32_t slots);
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static RFPins *rf;
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static phy_device_driver_s device_driver;
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@ -210,6 +208,7 @@ static uint8_t s2lp_MAC[8];
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static rf_mode_e rf_mode = RF_MODE_NORMAL;
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static bool rf_update_config = false;
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static uint16_t cur_packet_len = 0xffff;
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static uint32_t receiver_ready_timestamp;
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/* Channel configurations for sub-GHz */
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static phy_rf_channel_configuration_s phy_subghz = {
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@ -748,16 +747,26 @@ static void rf_start_tx(void)
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rf_backup_timer_start(MAX_PACKET_SENDING_TIME);
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}
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static int rf_cca_check(void)
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{
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uint32_t time_from_receiver_ready = rf_get_timestamp() - receiver_ready_timestamp;
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if (time_from_receiver_ready < RSSI_SETTLING_TIME) {
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wait_us(RSSI_SETTLING_TIME - time_from_receiver_ready);
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}
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return (rf_read_register(LINK_QUALIF1) & CARRIER_SENSE);
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}
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static void rf_cca_timer_interrupt(void)
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{
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if (device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_PREPARE, 0, 0) != 0) {
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int8_t status = device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_PREPARE, 0, 0);
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if (status == PHY_TX_NOT_ALLOWED) {
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rf_flush_tx_fifo();
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if (rf_state == RF_CSMA_STARTED) {
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rf_state = RF_IDLE;
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}
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return;
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}
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if ((cca_enabled == true) && ((rf_state != RF_CSMA_STARTED && rf_state != RF_IDLE) || (read_irq_status() & (1 << SYNC_WORD)) || (rf_read_register(LINK_QUALIF1) & CARRIER_SENSE))) {
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if ((cca_enabled == true) && ((rf_state != RF_CSMA_STARTED && rf_state != RF_IDLE) || (read_irq_status() & (1 << SYNC_WORD)) || rf_cca_check())) {
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if (rf_state == RF_CSMA_STARTED) {
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rf_state = RF_IDLE;
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}
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@ -767,9 +776,23 @@ static void rf_cca_timer_interrupt(void)
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device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 0, 0);
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}
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} else {
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rf_start_tx();
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rf_state = RF_TX_STARTED;
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TEST_TX_STARTED
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if (status == PHY_RESTART_CSMA) {
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if (device_driver.phy_tx_done_cb) {
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device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_OK, 0, 0);
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}
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if (tx_time) {
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uint32_t backoff_time = tx_time - rf_get_timestamp();
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// Max. time to TX can be 65ms, otherwise time has passed already -> send immediately
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if (backoff_time > 65000) {
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backoff_time = 1;
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}
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rf_cca_timer_start(backoff_time);
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}
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} else {
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rf_start_tx();
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rf_state = RF_TX_STARTED;
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TEST_TX_STARTED
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}
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}
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}
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@ -931,6 +954,8 @@ static void rf_sync_detected_handler(void)
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rf_state = RF_RX_STARTED;
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TEST_RX_STARTED
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rf_disable_interrupt(SYNC_WORD);
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rf_enable_interrupt(RX_FIFO_ALMOST_FULL);
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rf_enable_interrupt(RX_DATA_READY);
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rf_backup_timer_start(MAX_PACKET_SENDING_TIME);
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}
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@ -953,15 +978,14 @@ static void rf_receive(uint8_t rx_channel)
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rf_rx_channel = rf_new_channel = rx_channel;
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}
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rf_send_command(S2LP_CMD_RX);
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rf_poll_state_change(S2LP_STATE_RX);
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rf_enable_interrupt(SYNC_WORD);
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rf_enable_interrupt(RX_FIFO_ALMOST_FULL);
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rf_enable_interrupt(RX_DATA_READY);
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rf_enable_interrupt(RX_FIFO_UNF_OVF);
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rx_data_length = 0;
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if (rf_state != RF_CSMA_STARTED) {
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rf_state = RF_IDLE;
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}
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rf_poll_state_change(S2LP_STATE_RX);
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receiver_ready_timestamp = rf_get_timestamp();
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rf_unlock();
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}
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@ -1158,14 +1182,25 @@ int8_t NanostackRfPhys2lp::rf_register()
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error("Multiple registrations of NanostackRfPhyAtmel not supported");
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return -1;
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}
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if (memcmp(_mac_addr, ADDR_UNSPECIFIED, 8) == 0) {
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if (!_mac_set) {
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#ifdef AT24MAC
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int ret = _mac.read_eui64((void *)s2lp_MAC);
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if (ret < 0) {
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rf = NULL;
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rf_unlock();
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return -1;
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}
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#else
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randLIB_seed_random();
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randLIB_get_n_bytes_random(s2lp_MAC, 8);
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s2lp_MAC[0] |= 2; //Set Local Bit
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s2lp_MAC[0] &= ~1; //Clear multicast bit
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tr_info("Generated random MAC %s", trace_array(s2lp_MAC, 8));
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#endif
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set_mac_address(s2lp_MAC);
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tr_info("MAC address: %s", trace_array(_mac_addr, 8));
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}
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rf = _rf;
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int8_t radio_id = rf_device_register(_mac_addr);
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@ -1188,12 +1223,20 @@ void NanostackRfPhys2lp::rf_unregister()
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rf_unlock();
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}
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NanostackRfPhys2lp::NanostackRfPhys2lp(PinName spi_sdi, PinName spi_sdo, PinName spi_sclk, PinName spi_cs, PinName spi_sdn,
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NanostackRfPhys2lp::NanostackRfPhys2lp(PinName spi_sdi, PinName spi_sdo, PinName spi_sclk, PinName spi_cs, PinName spi_sdn
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#ifdef TEST_GPIOS_ENABLED
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PinName spi_test1, PinName spi_test2, PinName spi_test3, PinName spi_test4, PinName spi_test5,
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,PinName spi_test1, PinName spi_test2, PinName spi_test3, PinName spi_test4, PinName spi_test5
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#endif //TEST_GPIOS_ENABLED
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PinName spi_gpio0, PinName spi_gpio1, PinName spi_gpio2, PinName spi_gpio3)
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: _mac_addr(), _rf(NULL), _mac_set(false),
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,PinName spi_gpio0, PinName spi_gpio1, PinName spi_gpio2, PinName spi_gpio3
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#ifdef AT24MAC
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,PinName i2c_sda, PinName i2c_scl
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#endif //AT24MAC
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)
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:
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#ifdef AT24MAC
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_mac(i2c_sda, i2c_scl),
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#endif //AT24MAC
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_mac_addr(), _rf(NULL), _mac_set(false),
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_spi_sdi(spi_sdi), _spi_sdo(spi_sdo), _spi_sclk(spi_sclk), _spi_cs(spi_cs), _spi_sdn(spi_sdn),
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#ifdef TEST_GPIOS_ENABLED
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_spi_test1(spi_test1), _spi_test2(spi_test2), _spi_test3(spi_test3), _spi_test4(spi_test4), _spi_test5(spi_test5),
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@ -1236,20 +1279,6 @@ static bool rf_panid_filter_common(uint8_t *panid_start, uint8_t *pan_id, uint8_
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return retval;
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}
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static bool rf_panid_v2_filter(uint8_t *ptr, uint8_t *pan_id, uint8_t dst_mode, uint8_t src_mode, uint8_t seq_compressed, uint8_t panid_compressed, uint8_t frame_type)
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{
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if ((dst_mode == FC_DST_ADDR_NONE) && (frame_type == MAC_TYPE_DATA || frame_type == MAC_TYPE_COMMAND)) {
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return true;
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}
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if ((dst_mode == FC_DST_64_BITS) && (src_mode == FC_SRC_64_BITS) && panid_compressed) {
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return true;
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}
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if (seq_compressed) {
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ptr--;
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}
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return rf_panid_filter_common(ptr, pan_id, frame_type);
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}
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static bool rf_panid_v1_v0_filter(uint8_t *ptr, uint8_t *pan_id, uint8_t frame_type)
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{
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return rf_panid_filter_common(ptr, pan_id, frame_type);
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@ -1298,17 +1327,6 @@ static bool rf_addr_filter_common(uint8_t *ptr, uint8_t addr_mode, uint8_t *mac_
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return retval;
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}
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static bool rf_addr_v2_filter(uint8_t *ptr, uint8_t *mac_64bit_addr, uint8_t *mac_16bit_addr, uint8_t dst_mode, uint8_t seq_compressed, uint8_t panid_compressed)
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{
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if (seq_compressed) {
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ptr--;
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}
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if (panid_compressed) {
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ptr -= 2;
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}
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return rf_addr_filter_common(ptr, dst_mode, mac_64bit_addr, mac_16bit_addr);
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}
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static bool rf_addr_v1_v0_filter(uint8_t *ptr, uint8_t *mac_64bit_addr, uint8_t *mac_16bit_addr, uint8_t dst_mode)
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{
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return rf_addr_filter_common(ptr, dst_mode, mac_64bit_addr, mac_16bit_addr);
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@ -1317,19 +1335,9 @@ static bool rf_addr_v1_v0_filter(uint8_t *ptr, uint8_t *mac_64bit_addr, uint8_t
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static bool rf_rx_filter(uint8_t *mac_header, uint8_t *mac_64bit_addr, uint8_t *mac_16bit_addr, uint8_t *pan_id)
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{
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uint8_t dst_mode = (mac_header[1] & FC_DST_MODE);
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uint8_t src_mode = (mac_header[1] & FC_SRC_MODE);
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uint8_t seq_compressed = ((mac_header[1] & FC_SEQUENCE_COMPRESSION) >> SHIFT_SEQ_COMP_FIELD);
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uint8_t panid_compressed = ((mac_header[0] & FC_PAN_ID_COMPRESSION) >> SHIFT_PANID_COMP_FIELD);
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uint8_t frame_type = mac_header[0] & MAC_FRAME_TYPE_MASK;
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uint8_t version = ((mac_header[1] & VERSION_FIELD_MASK) >> SHIFT_VERSION_FIELD);
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if (version == MAC_FRAME_VERSION_2) {
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if (!rf_panid_v2_filter(mac_header + OFFSET_DST_PAN_ID, pan_id, dst_mode, src_mode, seq_compressed, panid_compressed, frame_type)) {
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return false;
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}
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if (!rf_addr_v2_filter(mac_header + OFFSET_DST_ADDR, mac_64bit_addr, mac_16bit_addr, dst_mode, seq_compressed, panid_compressed)) {
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return false;
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}
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} else {
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if (version != MAC_FRAME_VERSION_2) {
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if (!rf_panid_v1_v0_filter(mac_header + OFFSET_DST_PAN_ID, pan_id, frame_type)) {
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return false;
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}
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@ -1474,11 +1482,15 @@ static void rf_print_registers(void)
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#if MBED_CONF_S2LP_PROVIDE_DEFAULT
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NanostackRfPhy &NanostackRfPhy::get_default_instance()
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{
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static NanostackRfPhys2lp rf_phy(S2LP_SPI_SDI, S2LP_SPI_SDO, S2LP_SPI_SCLK, S2LP_SPI_CS, S2LP_SPI_SDN,
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static NanostackRfPhys2lp rf_phy(S2LP_SPI_SDI, S2LP_SPI_SDO, S2LP_SPI_SCLK, S2LP_SPI_CS, S2LP_SPI_SDN
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#ifdef TEST_GPIOS_ENABLED
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S2LP_SPI_TEST1, S2LP_SPI_TEST2, S2LP_SPI_TEST3, S2LP_SPI_TEST4, S2LP_SPI_TEST5,
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,S2LP_SPI_TEST1, S2LP_SPI_TEST2, S2LP_SPI_TEST3, S2LP_SPI_TEST4, S2LP_SPI_TEST5
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#endif //TEST_GPIOS_ENABLED
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S2LP_SPI_GPIO0, S2LP_SPI_GPIO1, S2LP_SPI_GPIO2, S2LP_SPI_GPIO3);
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,S2LP_SPI_GPIO0, S2LP_SPI_GPIO1, S2LP_SPI_GPIO2, S2LP_SPI_GPIO3
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#ifdef AT24MAC
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,S2LP_I2C_SDA, S2LP_I2C_SCL
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#endif //AT24MAC
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);
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return rf_phy;
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}
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#endif // MBED_CONF_S2LP_PROVIDE_DEFAULT
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@ -0,0 +1,72 @@
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/*
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* Copyright (c) 2019-2019 ARM Limited. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "NanostackRfPhys2lp.h"
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#include "at24mac_s2lp.h"
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#if DEVICE_I2C
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#ifdef AT24MAC
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/* Device addressing */
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#define AT24MAC_EEPROM_ADDRESS (0x0A<<4)
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#define AT24MAC_RW_PROTECT_ADDRESS (0x06<<4)
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#define AT24MAC_SERIAL_ADDRESS (0x0B<<4)
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/* Known memory blocks */
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#define AT24MAC_SERIAL_OFFSET (0x80)
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#define AT24MAC_EUI64_OFFSET (0x98)
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#define AT24MAC_EUI48_OFFSET (0x9A)
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#define SERIAL_LEN 16
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#define EUI64_LEN 8
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#define EUI48_LEN 6
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using namespace mbed;
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AT24Mac_s2lp::AT24Mac_s2lp(PinName sda, PinName scl) : _i2c(sda, scl)
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{
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// Do nothing
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}
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int AT24Mac_s2lp::read_serial(void *buf)
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{
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char offset = AT24MAC_SERIAL_OFFSET;
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if (_i2c.write(AT24MAC_SERIAL_ADDRESS, &offset, 1, true)) {
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return -1; //No ACK
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}
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return _i2c.read(AT24MAC_SERIAL_ADDRESS, (char *)buf, SERIAL_LEN);
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}
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int AT24Mac_s2lp::read_eui64(void *buf)
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{
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char offset = AT24MAC_EUI64_OFFSET;
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if (_i2c.write(AT24MAC_SERIAL_ADDRESS, &offset, 1, true)) {
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return -1; //No ACK
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}
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return _i2c.read(AT24MAC_SERIAL_ADDRESS, (char *)buf, EUI64_LEN);
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}
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int AT24Mac_s2lp::read_eui48(void *buf)
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{
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char offset = AT24MAC_EUI48_OFFSET;
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if (_i2c.write(AT24MAC_SERIAL_ADDRESS, &offset, 1, true)) {
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return -1; //No ACK
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}
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return _i2c.read(AT24MAC_SERIAL_ADDRESS, (char *)buf, EUI48_LEN);
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}
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#endif /* AT24MAC */
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#endif /* DEVICE_I2C */
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@ -0,0 +1,71 @@
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/*
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* Copyright (c) 2019-2019 ARM Limited. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
|
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* You may obtain a copy of the License at
|
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
|
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* Unless required by applicable law or agreed to in writing, software
|
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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* See the License for the specific language governing permissions and
|
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* limitations under the License.
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*/
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#ifndef AT24MAC_S2LP_H
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#define AT24MAC_S2LP_H
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#include "PinNames.h"
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#if DEVICE_I2C
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#ifdef AT24MAC
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#include "I2C.h"
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#include "drivers/DigitalInOut.h"
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#include "platform/mbed_wait_api.h"
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/*
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* AT24MAC drivers.
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*
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* This is a EEPROM chip designed to contain factory programmed read-only EUI-64 or EUI-48,
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* a 128bit serial number and some user programmable EEPROM.
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*
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* AT24MAC602 contains EUI-64, use read_eui64()
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* AT24MAC402 contains EUI-64, use read_eui48()
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*
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* NOTE: You cannot use both EUI-64 and EUI-48. Chip contains only one of those.
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*/
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class AT24Mac_s2lp {
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public:
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AT24Mac_s2lp(PinName sda, PinName scl);
|
||||
|
||||
/**
|
||||
* Read unique serial number from chip.
|
||||
* \param buf pointer to write serial number to. Must have space for 16 bytes.
|
||||
* \return zero on success, negative number on failure
|
||||
*/
|
||||
int read_serial(void *buf);
|
||||
|
||||
/**
|
||||
* Read EUI-64 from chip.
|
||||
* \param buf pointer to write EUI-64 to. Must have space for 8 bytes.
|
||||
* \return zero on success, negative number on failure
|
||||
*/
|
||||
int read_eui64(void *buf);
|
||||
|
||||
/**
|
||||
* Read EUI-48 from chip.
|
||||
* \param buf pointer to write EUI-48 to. Must have space for 6 bytes.
|
||||
* \return zero on success, negative number on failure
|
||||
*/
|
||||
int read_eui48(void *buf);
|
||||
|
||||
private:
|
||||
mbed::I2C _i2c;
|
||||
};
|
||||
|
||||
#endif /* AT24MAC */
|
||||
#endif /* DEVICE_I2C */
|
||||
#endif /* AT24MAC_S2LP_H */
|
||||
|
|
@ -25,6 +25,7 @@ extern "C" {
|
|||
#define VERSION 0xC1
|
||||
#define FIFO_SIZE 128
|
||||
#define SPI_HEADER_LENGTH 2
|
||||
#define RSSI_SETTLING_TIME 250
|
||||
|
||||
#define S2LP_GPIO0 0
|
||||
#define S2LP_GPIO1 1
|
||||
|
|
|
|||
|
|
@ -28,6 +28,42 @@
|
|||
// Uncomment to use testing gpios attached to TX/RX processes
|
||||
//#define TEST_GPIOS_ENABLED
|
||||
|
||||
#if defined(TARGET_MTB_STM_S2LP)
|
||||
#if !defined(S2LP_SPI_SDI)
|
||||
#define S2LP_SPI_SDI PA_7
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_SDO)
|
||||
#define S2LP_SPI_SDO PA_6
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_SCLK)
|
||||
#define S2LP_SPI_SCLK PA_5
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_CS)
|
||||
#define S2LP_SPI_CS PC_0
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_SDN)
|
||||
#define S2LP_SPI_SDN PF_13
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_GPIO0)
|
||||
#define S2LP_SPI_GPIO0 PA_3
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_GPIO1)
|
||||
#define S2LP_SPI_GPIO1 PC_3
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_GPIO2)
|
||||
#define S2LP_SPI_GPIO2 PF_3
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_GPIO3)
|
||||
#define S2LP_SPI_GPIO3 PF_10
|
||||
#endif
|
||||
#if !defined(S2LP_I2C_SDA)
|
||||
#define S2LP_I2C_SDA PB_7
|
||||
#endif
|
||||
#if !defined(S2LP_I2C_SCL)
|
||||
#define S2LP_I2C_SCL PB_6
|
||||
#endif
|
||||
#define AT24MAC
|
||||
#else
|
||||
#if !defined(S2LP_SPI_SDI)
|
||||
#define S2LP_SPI_SDI D11
|
||||
#endif
|
||||
|
|
@ -70,17 +106,23 @@
|
|||
#if !defined(S2LP_SPI_GPIO3)
|
||||
#define S2LP_SPI_GPIO3 A5
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#include "at24mac_s2lp.h"
|
||||
|
||||
class RFPins;
|
||||
|
||||
class NanostackRfPhys2lp : public NanostackRfPhy {
|
||||
public:
|
||||
NanostackRfPhys2lp(PinName spi_sdi, PinName spi_sdo,
|
||||
PinName spi_sclk, PinName spi_cs, PinName spi_sdn,
|
||||
NanostackRfPhys2lp(PinName spi_sdi, PinName spi_sdo, PinName spi_sclk, PinName spi_cs, PinName spi_sdn
|
||||
#ifdef TEST_GPIOS_ENABLED
|
||||
PinName spi_test1, PinName spi_test2, PinName spi_test3, PinName spi_test4, PinName spi_test5,
|
||||
,PinName spi_test1, PinName spi_test2, PinName spi_test3, PinName spi_test4, PinName spi_test5
|
||||
#endif //TEST_GPIOS_ENABLED
|
||||
PinName spi_gpio0, PinName spi_gpio1, PinName spi_gpio2, PinName spi_gpio3);
|
||||
,PinName spi_gpio0, PinName spi_gpio1, PinName spi_gpio2, PinName spi_gpio3
|
||||
#ifdef AT24MAC
|
||||
,PinName i2c_sda, PinName i2c_scl
|
||||
#endif //AT24MAC
|
||||
);
|
||||
virtual ~NanostackRfPhys2lp();
|
||||
virtual int8_t rf_register();
|
||||
virtual void rf_unregister();
|
||||
|
|
@ -88,6 +130,9 @@ public:
|
|||
virtual void set_mac_address(uint8_t *mac);
|
||||
|
||||
private:
|
||||
#ifdef AT24MAC
|
||||
AT24Mac_s2lp _mac;
|
||||
#endif //AT24MAC
|
||||
uint8_t _mac_addr[8];
|
||||
RFPins *_rf;
|
||||
bool _mac_set;
|
||||
|
|
|
|||
Loading…
Reference in New Issue