From cbebd63a2cc18895ec8b43ac1abd0beed5625c9f Mon Sep 17 00:00:00 2001 From: Anders Lindvall Date: Mon, 12 Jan 2015 14:20:11 +0100 Subject: [PATCH 01/25] Added LPC4088_DM HAL --- .../{ => TARGET_LPC4088}/PeripheralNames.h | 0 .../{ => TARGET_LPC4088}/PinNames.h | 0 .../{ => TARGET_LPC4088}/analogin_api.c | 0 .../{ => TARGET_LPC4088}/can_api.c | 0 .../{ => TARGET_LPC4088}/i2c_api.c | 0 .../{ => TARGET_LPC4088}/pwmout_api.c | 0 .../{ => TARGET_LPC4088}/serial_api.c | 0 .../{ => TARGET_LPC4088}/spi_api.c | 0 .../TARGET_LPC4088_DM/PeripheralNames.h | 111 +++++ .../TARGET_LPC4088_DM/PinNames.h | 106 +++++ .../TARGET_LPC4088_DM/analogin_api.c | 119 ++++++ .../TARGET_LPC4088_DM/can_api.c | 388 +++++++++++++++++ .../TARGET_LPC4088_DM/i2c_api.c | 404 ++++++++++++++++++ .../TARGET_LPC4088_DM/pwmout_api.c | 163 +++++++ .../TARGET_LPC4088_DM/serial_api.c | 317 ++++++++++++++ .../TARGET_LPC4088_DM/spi_api.c | 206 +++++++++ 16 files changed, 1814 insertions(+) rename libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/{ => TARGET_LPC4088}/PeripheralNames.h (100%) rename libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/{ => TARGET_LPC4088}/PinNames.h (100%) rename libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/{ => TARGET_LPC4088}/analogin_api.c (100%) rename libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/{ => TARGET_LPC4088}/can_api.c (100%) rename libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/{ => TARGET_LPC4088}/i2c_api.c (100%) rename libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/{ => TARGET_LPC4088}/pwmout_api.c (100%) rename libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/{ => TARGET_LPC4088}/serial_api.c (100%) rename libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/{ => TARGET_LPC4088}/spi_api.c (100%) create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PeripheralNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PinNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/analogin_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/can_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/pwmout_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/serial_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/spi_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/PinNames.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/analogin_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/analogin_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/analogin_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/analogin_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/can_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/can_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/can_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/can_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/i2c_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/i2c_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/i2c_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/i2c_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/pwmout_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/pwmout_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/pwmout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/serial_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/serial_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/serial_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/spi_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PeripheralNames.h new file mode 100644 index 0000000000..9d13fced6b --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PeripheralNames.h @@ -0,0 +1,111 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = (int)LPC_UART0_BASE, + UART_1 = (int)LPC_UART1_BASE, + UART_2 = (int)LPC_UART2_BASE, + UART_3 = (int)LPC_UART3_BASE, + UART_4 = (int)LPC_UART4_BASE +} UARTName; + +typedef enum { + ADC0_0 = 0, + ADC0_1, + ADC0_2, + ADC0_3, + ADC0_4, + ADC0_5, + ADC0_6, + ADC0_7 +} ADCName; + +typedef enum { + DAC_0 = 0 +} DACName; + +typedef enum { + SPI_0 = (int)LPC_SSP0_BASE, + SPI_1 = (int)LPC_SSP1_BASE, + SPI_2 = (int)LPC_SSP2_BASE +} SPIName; + +typedef enum { + I2C_0 = (int)LPC_I2C0_BASE, + I2C_1 = (int)LPC_I2C1_BASE, + I2C_2 = (int)LPC_I2C2_BASE +} I2CName; + +typedef enum { + PWM0_1 = 1, + PWM0_2, + PWM0_3, + PWM0_4, + PWM0_5, + PWM0_6, + PWM1_1, + PWM1_2, + PWM1_3, + PWM1_4, + PWM1_5, + PWM1_6 +} PWMName; + +typedef enum { + CAN_1 = (int)LPC_CAN1_BASE, + CAN_2 = (int)LPC_CAN2_BASE +} CANName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +// Default peripherals +#define MBED_SPI0 p7, p8, p9 +#define MBED_SPI1 p46, p44, p42, p45 +#define MBED_SPI2 p15, p16, p17, p18 + +#define MBED_UART3 p29, p30 +#define MBED_UART4 p19, p18 +#define MBED_UARTUSB USBTX, USBRX + +#define MBED_I2C1 p12, p13 + +#define MBED_CAN1 p12, p13 +#define MBED_CAN2 p41, p43 + +#define MBED_ANALOGOUT0 p30 + +#define MBED_ANALOGIN2 p29 +#define MBED_ANALOGIN3 p30 + +#define MBED_PWMOUT0 p9 +#define MBED_PWMOUT1 p8 +#define MBED_PWMOUT2 p7 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PinNames.h new file mode 100644 index 0000000000..357899b4f3 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PinNames.h @@ -0,0 +1,106 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 5 + +typedef enum { + // LPC Pin Names + P0_0 = /*LPC_GPIO0_BASE*/0, + P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31, + P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31, + P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31, + P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31, + P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31, + P5_0, P5_1, P5_2, P5_3, P5_4, + + // mbed DIP Pin Names + p1 = P0_30, + p2 = P2_14, + p3 = P0_29, + p4 = P2_15, + + p7 = P1_24, + p8 = P1_23, + p9 = P1_20, + p10 = P1_19, + p11 = P0_21, + p12 = P0_0, + p13 = P0_1, + p14 = P2_10, + p15 = P5_0, + p16 = P5_1, + p17 = P5_2, + p18 = P5_3, + p19 = P5_4, + p20 = P2_22, + p21 = P2_23, + p22 = P2_25, + p23 = P2_26, + p24 = P2_27, + p25 = P0_2, + p26 = P0_3, + + p29 = P0_25, + p30 = P0_26, + + p41 = P0_4, + p42 = P0_7, + p43 = P0_5, + p44 = P0_8, + p45 = P0_6, + p46 = P0_9, + + // Other mbed Pin Names + LED1 = P1_18, + LED2 = P0_13, + LED3 = P1_13, + LED4 = P2_19, + + USBTX = P0_2, + USBRX = P0_3, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullUp = 2, + PullDown = 1, + PullNone = 0, + OpenDrain = 4, + PullDefault = PullDown +} PinMode; + + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/analogin_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/analogin_api.c new file mode 100644 index 0000000000..e893fb60ba --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/analogin_api.c @@ -0,0 +1,119 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "analogin_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" + +#define ANALOGIN_MEDIAN_FILTER 1 + +#define ADC_10BIT_RANGE 0x3FF +#define ADC_12BIT_RANGE 0xFFF + +static inline int div_round_up(int x, int y) { + return (x + (y - 1)) / y; +} + +static const PinMap PinMap_ADC[] = { + {P0_25, ADC0_2, 0x01}, + {P0_26, ADC0_3, 0x01}, + {NC , NC , 0 } +}; + +#define ADC_RANGE ADC_12BIT_RANGE + +void analogin_init(analogin_t *obj, PinName pin) { + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName)NC); + + // ensure power is turned on + LPC_SC->PCONP |= (1 << 12); + + uint32_t PCLK = PeripheralClock; + + // calculate minimum clock divider + // clkdiv = divider - 1 + uint32_t MAX_ADC_CLK = 12400000; + uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1; + + // Set the generic software-controlled ADC settings + LPC_ADC->CR = (0 << 0) // SEL: 0 = no channels selected + | (clkdiv << 8) // CLKDIV: + | (0 << 16) // BURST: 0 = software control + | (1 << 21) // PDN: 1 = operational + | (0 << 24) // START: 0 = no start + | (0 << 27); // EDGE: not applicable + + // must enable analog mode (ADMODE = 0) + __IO uint32_t *reg = (__IO uint32_t*) (LPC_IOCON_BASE + 4 * pin); + *reg &= ~(1 << 7); + + pinmap_pinout(pin, PinMap_ADC); +} + +static inline uint32_t adc_read(analogin_t *obj) { + // Select the appropriate channel and start conversion + LPC_ADC->CR &= ~0xFF; + LPC_ADC->CR |= 1 << (int)obj->adc; + LPC_ADC->CR |= 1 << 24; + + // Repeatedly get the sample data until DONE bit + unsigned int data; + do { + data = LPC_ADC->GDR; + } while ((data & ((unsigned int)1 << 31)) == 0); + + // Stop conversion + LPC_ADC->CR &= ~(1 << 24); + + return (data >> 4) & ADC_RANGE; // 12 bit +} + +static inline void order(uint32_t *a, uint32_t *b) { + if (*a > *b) { + uint32_t t = *a; + *a = *b; + *b = t; + } +} + +static inline uint32_t adc_read_u32(analogin_t *obj) { + uint32_t value; +#if ANALOGIN_MEDIAN_FILTER + uint32_t v1 = adc_read(obj); + uint32_t v2 = adc_read(obj); + uint32_t v3 = adc_read(obj); + order(&v1, &v2); + order(&v2, &v3); + order(&v1, &v2); + value = v2; +#else + value = adc_read(obj); +#endif + return value; +} + +uint16_t analogin_read_u16(analogin_t *obj) { + uint32_t value = adc_read_u32(obj); + + return (value << 4) | ((value >> 8) & 0x000F); // 12 bit +} + +float analogin_read(analogin_t *obj) { + uint32_t value = adc_read_u32(obj); + return (float)value * (1.0f / (float)ADC_RANGE); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/can_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/can_api.c new file mode 100644 index 0000000000..676bc27401 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/can_api.c @@ -0,0 +1,388 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "can_api.h" + +#include "cmsis.h" +#include "pinmap.h" + +#include +#include + +#define CAN_NUM 2 + +/* Acceptance filter mode in AFMR register */ +#define ACCF_OFF 0x01 +#define ACCF_BYPASS 0x02 +#define ACCF_ON 0x00 +#define ACCF_FULLCAN 0x04 + +/* There are several bit timing calculators on the internet. +http://www.port.de/engl/canprod/sv_req_form.html +http://www.kvaser.com/can/index.htm +*/ + +static const PinMap PinMap_CAN_RD[] = { + {P0_0 , CAN_1, 1}, + {P0_4 , CAN_2, 2}, + {P0_21, CAN_1, 4}, + {NC , NC , 0} +}; + +static const PinMap PinMap_CAN_TD[] = { + {P0_1 , CAN_1, 1}, + {P0_5 , CAN_2, 2}, + {NC , NC , 0} +}; + +// Type definition to hold a CAN message +struct CANMsg { + unsigned int reserved1 : 16; + unsigned int dlc : 4; // Bits 16..19: DLC - Data Length Counter + unsigned int reserved0 : 10; + unsigned int rtr : 1; // Bit 30: Set if this is a RTR message + unsigned int type : 1; // Bit 31: Set if this is a 29-bit ID message + unsigned int id; // CAN Message ID (11-bit or 29-bit) + unsigned char data[8]; // CAN Message Data Bytes 0-7 +}; +typedef struct CANMsg CANMsg; + +static uint32_t can_irq_ids[CAN_NUM] = {0}; +static can_irq_handler irq_handler; + +static uint32_t can_disable(can_t *obj) { + uint32_t sm = obj->dev->MOD; + obj->dev->MOD |= 1; + return sm; +} + +static inline void can_enable(can_t *obj) { + if (obj->dev->MOD & 1) { + obj->dev->MOD &= ~(1); + } +} + +int can_mode(can_t *obj, CanMode mode) +{ + return 0; // not implemented +} + +int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) { + return 0; // not implemented +} + +static inline void can_irq(uint32_t icr, uint32_t index) { + uint32_t i; + + for(i = 0; i < 8; i++) + { + if((can_irq_ids[index] != 0) && (icr & (1 << i))) + { + switch (i) { + case 0: irq_handler(can_irq_ids[index], IRQ_RX); break; + case 1: irq_handler(can_irq_ids[index], IRQ_TX); break; + case 2: irq_handler(can_irq_ids[index], IRQ_ERROR); break; + case 3: irq_handler(can_irq_ids[index], IRQ_OVERRUN); break; + case 4: irq_handler(can_irq_ids[index], IRQ_WAKEUP); break; + case 5: irq_handler(can_irq_ids[index], IRQ_PASSIVE); break; + case 6: irq_handler(can_irq_ids[index], IRQ_ARB); break; + case 7: irq_handler(can_irq_ids[index], IRQ_BUS); break; + case 8: irq_handler(can_irq_ids[index], IRQ_READY); break; + } + } + } +} + +// Have to check that the CAN block is active before reading the Interrupt +// Control Register, or the mbed hangs +void can_irq_n() { + uint32_t icr; + + if(LPC_SC->PCONP & (1 << 13)) { + icr = LPC_CAN1->ICR & 0x1FF; + can_irq(icr, 0); + } + + if(LPC_SC->PCONP & (1 << 14)) { + icr = LPC_CAN2->ICR & 0x1FF; + can_irq(icr, 1); + } +} + +// Register CAN object's irq handler +void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) { + irq_handler = handler; + can_irq_ids[obj->index] = id; +} + +// Unregister CAN object's irq handler +void can_irq_free(can_t *obj) { + obj->dev->IER &= ~(1); + can_irq_ids[obj->index] = 0; + + if ((can_irq_ids[0] == 0) && (can_irq_ids[1] == 0)) { + NVIC_DisableIRQ(CAN_IRQn); + } +} + +// Clear or set a irq +void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) { + uint32_t ier; + + switch (type) { + case IRQ_RX: ier = (1 << 0); break; + case IRQ_TX: ier = (1 << 1); break; + case IRQ_ERROR: ier = (1 << 2); break; + case IRQ_OVERRUN: ier = (1 << 3); break; + case IRQ_WAKEUP: ier = (1 << 4); break; + case IRQ_PASSIVE: ier = (1 << 5); break; + case IRQ_ARB: ier = (1 << 6); break; + case IRQ_BUS: ier = (1 << 7); break; + case IRQ_READY: ier = (1 << 8); break; + default: return; + } + + obj->dev->MOD |= 1; + if(enable == 0) { + obj->dev->IER &= ~ier; + } + else { + obj->dev->IER |= ier; + } + obj->dev->MOD &= ~(1); + + // Enable NVIC if at least 1 interrupt is active + if(((LPC_SC->PCONP & (1 << 13)) && LPC_CAN1->IER) || ((LPC_SC->PCONP & (1 << 14)) && LPC_CAN2->IER)) { + NVIC_SetVector(CAN_IRQn, (uint32_t) &can_irq_n); + NVIC_EnableIRQ(CAN_IRQn); + } + else { + NVIC_DisableIRQ(CAN_IRQn); + } +} + +// This table has the sampling points as close to 75% as possible. The first +// value is TSEG1, the second TSEG2. +static const int timing_pts[23][2] = { + {0x0, 0x0}, // 2, 50% + {0x1, 0x0}, // 3, 67% + {0x2, 0x0}, // 4, 75% + {0x3, 0x0}, // 5, 80% + {0x3, 0x1}, // 6, 67% + {0x4, 0x1}, // 7, 71% + {0x5, 0x1}, // 8, 75% + {0x6, 0x1}, // 9, 78% + {0x6, 0x2}, // 10, 70% + {0x7, 0x2}, // 11, 73% + {0x8, 0x2}, // 12, 75% + {0x9, 0x2}, // 13, 77% + {0x9, 0x3}, // 14, 71% + {0xA, 0x3}, // 15, 73% + {0xB, 0x3}, // 16, 75% + {0xC, 0x3}, // 17, 76% + {0xD, 0x3}, // 18, 78% + {0xD, 0x4}, // 19, 74% + {0xE, 0x4}, // 20, 75% + {0xF, 0x4}, // 21, 76% + {0xF, 0x5}, // 22, 73% + {0xF, 0x6}, // 23, 70% + {0xF, 0x7}, // 24, 67% +}; + +static unsigned int can_speed(unsigned int pclk, unsigned int cclk, unsigned char psjw) { + uint32_t btr; + uint16_t brp = 0; + uint32_t calcbit; + uint32_t bitwidth; + int hit = 0; + int bits; + + bitwidth = (pclk / cclk); + + brp = bitwidth / 0x18; + while ((!hit) && (brp < bitwidth / 4)) { + brp++; + for (bits = 22; bits > 0; bits--) { + calcbit = (bits + 3) * (brp + 1); + if (calcbit == bitwidth) { + hit = 1; + break; + } + } + } + + if (hit) { + btr = ((timing_pts[bits][1] << 20) & 0x00700000) + | ((timing_pts[bits][0] << 16) & 0x000F0000) + | ((psjw << 14) & 0x0000C000) + | ((brp << 0) & 0x000003FF); + } else { + btr = 0xFFFFFFFF; + } + + return btr; + +} + +void can_init(can_t *obj, PinName rd, PinName td) { + CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD); + CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD); + obj->dev = (LPC_CAN_TypeDef *)pinmap_merge(can_rd, can_td); + MBED_ASSERT((int)obj->dev != NC); + + switch ((int)obj->dev) { + case CAN_1: LPC_SC->PCONP |= 1 << 13; break; + case CAN_2: LPC_SC->PCONP |= 1 << 14; break; + } + + pinmap_pinout(rd, PinMap_CAN_RD); + pinmap_pinout(td, PinMap_CAN_TD); + + switch ((int)obj->dev) { + case CAN_1: obj->index = 0; break; + case CAN_2: obj->index = 1; break; + } + + can_reset(obj); + obj->dev->IER = 0; // Disable Interrupts + can_frequency(obj, 100000); + + LPC_CANAF->AFMR = ACCF_BYPASS; // Bypass Filter +} + +void can_free(can_t *obj) { + switch ((int)obj->dev) { + case CAN_1: LPC_SC->PCONP &= ~(1 << 13); break; + case CAN_2: LPC_SC->PCONP &= ~(1 << 14); break; + } +} + +int can_frequency(can_t *obj, int f) { + int pclk = PeripheralClock; + + int btr = can_speed(pclk, (unsigned int)f, 1); + + if (btr > 0) { + uint32_t modmask = can_disable(obj); + obj->dev->BTR = btr; + obj->dev->MOD = modmask; + return 1; + } else { + return 0; + } +} + +int can_write(can_t *obj, CAN_Message msg, int cc) { + unsigned int CANStatus; + CANMsg m; + + can_enable(obj); + + m.id = msg.id ; + m.dlc = msg.len & 0xF; + m.rtr = msg.type; + m.type = msg.format; + memcpy(m.data, msg.data, msg.len); + const unsigned int *buf = (const unsigned int *)&m; + + CANStatus = obj->dev->SR; + if (CANStatus & 0x00000004) { + obj->dev->TFI1 = buf[0] & 0xC00F0000; + obj->dev->TID1 = buf[1]; + obj->dev->TDA1 = buf[2]; + obj->dev->TDB1 = buf[3]; + if(cc) { + obj->dev->CMR = 0x30; + } else { + obj->dev->CMR = 0x21; + } + return 1; + + } else if (CANStatus & 0x00000400) { + obj->dev->TFI2 = buf[0] & 0xC00F0000; + obj->dev->TID2 = buf[1]; + obj->dev->TDA2 = buf[2]; + obj->dev->TDB2 = buf[3]; + if (cc) { + obj->dev->CMR = 0x50; + } else { + obj->dev->CMR = 0x41; + } + return 1; + + } else if (CANStatus & 0x00040000) { + obj->dev->TFI3 = buf[0] & 0xC00F0000; + obj->dev->TID3 = buf[1]; + obj->dev->TDA3 = buf[2]; + obj->dev->TDB3 = buf[3]; + if (cc) { + obj->dev->CMR = 0x90; + } else { + obj->dev->CMR = 0x81; + } + return 1; + } + + return 0; +} + +int can_read(can_t *obj, CAN_Message *msg, int handle) { + CANMsg x; + unsigned int *i = (unsigned int *)&x; + + can_enable(obj); + + if (obj->dev->GSR & 0x1) { + *i++ = obj->dev->RFS; // Frame + *i++ = obj->dev->RID; // ID + *i++ = obj->dev->RDA; // Data A + *i++ = obj->dev->RDB; // Data B + obj->dev->CMR = 0x04; // release receive buffer + + msg->id = x.id; + msg->len = x.dlc; + msg->format = (x.type)? CANExtended : CANStandard; + msg->type = (x.rtr)? CANRemote: CANData; + memcpy(msg->data,x.data,x.dlc); + return 1; + } + + return 0; +} + +void can_reset(can_t *obj) { + can_disable(obj); + obj->dev->GSR = 0; // Reset error counter when CAN1MOD is in reset +} + +unsigned char can_rderror(can_t *obj) { + return (obj->dev->GSR >> 16) & 0xFF; +} + +unsigned char can_tderror(can_t *obj) { + return (obj->dev->GSR >> 24) & 0xFF; +} + +void can_monitor(can_t *obj, int silent) { + uint32_t mod_mask = can_disable(obj); + if (silent) { + obj->dev->MOD |= (1 << 1); + } else { + obj->dev->MOD &= ~(1 << 1); + } + if (!(mod_mask & 1)) { + can_enable(obj); + } +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c new file mode 100644 index 0000000000..3a2621097f --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c @@ -0,0 +1,404 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "i2c_api.h" +#include "cmsis.h" +#include "pinmap.h" + +static const PinMap PinMap_I2C_SDA[] = { + {P0_0 , I2C_1, 3}, + {P0_27, I2C_0, 1}, + {P2_14, I2C_1, 2}, + {P5_2, I2C_0, 5}, + {NC , NC , 0} +}; + +static const PinMap PinMap_I2C_SCL[] = { + {P0_1 , I2C_1, 3}, + {P0_28, I2C_0, 1}, + {P2_15, I2C_1, 2}, + {P5_3, I2C_0, 5}, + {NC , NC, 0} +}; + +#define I2C_CONSET(x) (x->i2c->CONSET) +#define I2C_CONCLR(x) (x->i2c->CONCLR) +#define I2C_STAT(x) (x->i2c->STAT) +#define I2C_DAT(x) (x->i2c->DAT) +#define I2C_SCLL(x, val) (x->i2c->SCLL = val) +#define I2C_SCLH(x, val) (x->i2c->SCLH = val) + +static const uint32_t I2C_addr_offset[2][4] = { + {0x0C, 0x20, 0x24, 0x28}, + {0x30, 0x34, 0x38, 0x3C} +}; + +static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) { + I2C_CONCLR(obj) = (start << 5) + | (stop << 4) + | (interrupt << 3) + | (acknowledge << 2); +} + +static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) { + I2C_CONSET(obj) = (start << 5) + | (stop << 4) + | (interrupt << 3) + | (acknowledge << 2); +} + +// Clear the Serial Interrupt (SI) +static inline void i2c_clear_SI(i2c_t *obj) { + i2c_conclr(obj, 0, 0, 1, 0); +} + +static inline int i2c_status(i2c_t *obj) { + return I2C_STAT(obj); +} + +// Wait until the Serial Interrupt (SI) is set +static int i2c_wait_SI(i2c_t *obj) { + int timeout = 0; + while (!(I2C_CONSET(obj) & (1 << 3))) { + timeout++; + if (timeout > 100000) return -1; + } + return 0; +} + +static inline void i2c_interface_enable(i2c_t *obj) { + I2C_CONSET(obj) = 0x40; +} + +static inline void i2c_power_enable(i2c_t *obj) { + switch ((int)obj->i2c) { + case I2C_0: LPC_SC->PCONP |= 1 << 7; break; + case I2C_1: LPC_SC->PCONP |= 1 << 19; break; + case I2C_2: LPC_SC->PCONP |= 1 << 26; break; + } +} + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) { + // determine the SPI to use + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)obj->i2c != NC); + + // enable power + i2c_power_enable(obj); + + // set default frequency at 100k + i2c_frequency(obj, 100000); + i2c_conclr(obj, 1, 1, 1, 1); + i2c_interface_enable(obj); + + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + + // OpenDrain must explicitly be enabled for p0.0 and p0.1 + if (sda == P0_0) { + pin_mode(sda, OpenDrain); + } + if (scl == P0_1) { + pin_mode(scl, OpenDrain); + } + +} + +inline int i2c_start(i2c_t *obj) { + int status = 0; + // 8.1 Before master mode can be entered, I2CON must be initialised to: + // - I2EN STA STO SI AA - - + // - 1 0 0 0 x - - + // if AA = 0, it can't enter slave mode + i2c_conclr(obj, 1, 1, 1, 1); + + // The master mode may now be entered by setting the STA bit + // this will generate a start condition when the bus becomes free + i2c_conset(obj, 1, 0, 0, 1); + + i2c_wait_SI(obj); + status = i2c_status(obj); + + // Clear start bit now transmitted, and interrupt bit + i2c_conclr(obj, 1, 0, 0, 0); + return status; +} + +inline int i2c_stop(i2c_t *obj) { + int timeout = 0; + + // write the stop bit + i2c_conset(obj, 0, 1, 0, 0); + i2c_clear_SI(obj); + + // wait for STO bit to reset + while(I2C_CONSET(obj) & (1 << 4)) { + timeout ++; + if (timeout > 100000) return 1; + } + + return 0; +} + + +static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) { + // write the data + I2C_DAT(obj) = value; + + // clear SI to init a send + i2c_clear_SI(obj); + + // wait and return status + i2c_wait_SI(obj); + return i2c_status(obj); +} + +static inline int i2c_do_read(i2c_t *obj, int last) { + // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack) + if(last) { + i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK + } else { + i2c_conset(obj, 0, 0, 0, 1); // send a ACK + } + + // accept byte + i2c_clear_SI(obj); + + // wait for it to arrive + i2c_wait_SI(obj); + + // return the data + return (I2C_DAT(obj) & 0xFF); +} + +void i2c_frequency(i2c_t *obj, int hz) { + uint32_t PCLK = PeripheralClock; + uint32_t pulse = PCLK / (hz * 2); + + // I2C Rate + I2C_SCLL(obj, pulse); + I2C_SCLH(obj, pulse); +} + +// The I2C does a read or a write as a whole operation +// There are two types of error conditions it can encounter +// 1) it can not obtain the bus +// 2) it gets error responses at part of the transmission +// +// We tackle them as follows: +// 1) we retry until we get the bus. we could have a "timeout" if we can not get it +// which basically turns it in to a 2) +// 2) on error, we use the standard error mechanisms to report/debug +// +// Therefore an I2C transaction should always complete. If it doesn't it is usually +// because something is setup wrong (e.g. wiring), and we don't need to programatically +// check for that +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { + int count, status; + + status = i2c_start(obj); + + if ((status != 0x10) && (status != 0x08)) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + + status = i2c_do_write(obj, (address | 0x01), 1); + if (status != 0x40) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + // Read in all except last byte + for (count = 0; count < (length - 1); count++) { + int value = i2c_do_read(obj, 0); + status = i2c_status(obj); + if (status != 0x50) { + i2c_stop(obj); + return count; + } + data[count] = (char) value; + } + + // read in last byte + int value = i2c_do_read(obj, 1); + status = i2c_status(obj); + if (status != 0x58) { + i2c_stop(obj); + return length - 1; + } + + data[count] = (char) value; + + // If not repeated start, send stop. + if (stop) { + i2c_stop(obj); + } + + return length; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { + int i, status; + + status = i2c_start(obj); + + if ((status != 0x10) && (status != 0x08)) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + + status = i2c_do_write(obj, (address & 0xFE), 1); + if (status != 0x18) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + for (i=0; i= 0) && (idx <= 3)) { + addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx]; + *((uint32_t *) addr) = address & 0xFF; + addr = ((uint32_t)obj->i2c) + I2C_addr_offset[1][idx]; + *((uint32_t *) addr) = mask & 0xFE; + } +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/pwmout_api.c new file mode 100644 index 0000000000..86651ba601 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/pwmout_api.c @@ -0,0 +1,163 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pwmout_api.h" +#include "cmsis.h" +#include "pinmap.h" + +#define TCR_CNT_EN 0x00000001 +#define TCR_RESET 0x00000002 + +// PORT ID, PWM ID, Pin function +static const PinMap PinMap_PWM[] = { + {P1_5, PWM0_3, 3}, + {P1_20, PWM1_2, 2}, + {P1_23, PWM1_4, 2}, + {P1_24, PWM1_5, 2}, + {NC, NC, 0} +}; + +static const uint32_t PWM_mr_offset[7] = { + 0x18, 0x1C, 0x20, 0x24, 0x40, 0x44, 0x48 +}; + +#define TCR_PWM_EN 0x00000008 +static unsigned int pwm_clock_mhz; + +void pwmout_init(pwmout_t* obj, PinName pin) { + // determine the channel + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + MBED_ASSERT(pwm != (PWMName)NC); + + obj->channel = pwm; + obj->pwm = LPC_PWM0; + + if (obj->channel > 6) { // PWM1 is used if pwm > 6 + obj->channel -= 6; + obj->pwm = LPC_PWM1; + } + + obj->MR = (__IO uint32_t *)((uint32_t)obj->pwm + PWM_mr_offset[obj->channel]); + + // ensure the power is on + if (obj->pwm == LPC_PWM0) { + LPC_SC->PCONP |= 1 << 5; + } else { + LPC_SC->PCONP |= 1 << 6; + } + + obj->pwm->PR = 0; // no pre-scale + + // ensure single PWM mode + obj->pwm->MCR = 1 << 1; // reset TC on match 0 + + // enable the specific PWM output + obj->pwm->PCR |= 1 << (8 + obj->channel); + + pwm_clock_mhz = PeripheralClock / 1000000; + + // default to 20ms: standard for servos, and fine for e.g. brightness control + pwmout_period_ms(obj, 20); + pwmout_write (obj, 0); + + // Wire pinout + pinmap_pinout(pin, PinMap_PWM); +} + +void pwmout_free(pwmout_t* obj) { + // [TODO] +} + +void pwmout_write(pwmout_t* obj, float value) { + if (value < 0.0f) { + value = 0.0; + } else if (value > 1.0f) { + value = 1.0; + } + + // set channel match to percentage + uint32_t v = (uint32_t)((float)(obj->pwm->MR0) * value); + + // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout + if (v == obj->pwm->MR0) { + v++; + } + + *obj->MR = v; + + // accept on next period start + obj->pwm->LER |= 1 << obj->channel; +} + +float pwmout_read(pwmout_t* obj) { + float v = (float)(*obj->MR) / (float)(obj->pwm->MR0); + return (v > 1.0f) ? (1.0f) : (v); +} + +void pwmout_period(pwmout_t* obj, float seconds) { + pwmout_period_us(obj, seconds * 1000000.0f); +} + +void pwmout_period_ms(pwmout_t* obj, int ms) { + pwmout_period_us(obj, ms * 1000); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t* obj, int us) { + // calculate number of ticks + uint32_t ticks = pwm_clock_mhz * us; + + // set reset + obj->pwm->TCR = TCR_RESET; + + // set the global match register + obj->pwm->MR0 = ticks; + + // Scale the pulse width to preserve the duty ratio + if (obj->pwm->MR0 > 0) { + *obj->MR = (*obj->MR * ticks) / obj->pwm->MR0; + } + + // set the channel latch to update value at next period start + obj->pwm->LER |= 1 << 0; + + // enable counter and pwm, clear reset + obj->pwm->TCR = TCR_CNT_EN | TCR_PWM_EN; +} + +void pwmout_pulsewidth(pwmout_t* obj, float seconds) { + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t* obj, int us) { + // calculate number of ticks + uint32_t v = pwm_clock_mhz * us; + + // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout + if (v == obj->pwm->MR0) { + v++; + } + + // set the match register value + *obj->MR = v; + + // set the channel latch to update value at next period start + obj->pwm->LER |= 1 << obj->channel; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/serial_api.c new file mode 100644 index 0000000000..f3dd6c51b4 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/serial_api.c @@ -0,0 +1,317 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// math.h required for floating point operations for baud rate calculation +#include +#include +#include + +#include "serial_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" + +/****************************************************************************** + * INITIALIZATION + ******************************************************************************/ +static const PinMap PinMap_UART_TX[] = { + {P0_0, UART_3, 2}, + {P0_2, UART_0, 1}, + {P0_25, UART_3, 3}, + {P4_22, UART_2, 2}, + {P5_4, UART_4, 4}, + {NC , NC , 0} +}; + +static const PinMap PinMap_UART_RX[] = { + {P0_1 , UART_3, 2}, + {P0_3 , UART_0, 1}, + {P0_26, UART_3, 3}, + {P4_23, UART_2, 2}, + {P5_3, UART_4, 4}, + {NC , NC , 0} +}; + +#define UART_NUM 5 + +static uint32_t serial_irq_ids[UART_NUM] = {0}; +static uart_irq_handler irq_handler; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +void serial_init(serial_t *obj, PinName tx, PinName rx) { + int is_stdio_uart = 0; + + // determine the UART to use + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)uart != NC); + + obj->uart = (LPC_UART_TypeDef *)uart; + // enable power + switch (uart) { + case UART_0: LPC_SC->PCONP |= 1 << 3; break; + case UART_1: LPC_SC->PCONP |= 1 << 4; break; + case UART_2: LPC_SC->PCONP |= 1 << 24; break; + case UART_3: LPC_SC->PCONP |= 1 << 25; break; + case UART_4: LPC_SC->PCONP |= 1 << 8; break; + } + + // enable fifos and default rx trigger level + obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled + | 0 << 1 // Rx Fifo Reset + | 0 << 2 // Tx Fifo Reset + | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars + + // disable irqs + obj->uart->IER = 0 << 0 // Rx Data available irq enable + | 0 << 1 // Tx Fifo empty irq enable + | 0 << 2; // Rx Line Status irq enable + + // set default baud rate and format + serial_baud (obj, 9600); + serial_format(obj, 8, ParityNone, 1); + + // pinout the chosen uart + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + // set rx/tx pins in PullUp mode + if (tx != NC) { + pin_mode(tx, PullUp); + } + if (rx != NC) { + pin_mode(rx, PullUp); + } + + switch (uart) { + case UART_0: obj->index = 0; break; + case UART_1: obj->index = 1; break; + case UART_2: obj->index = 2; break; + case UART_3: obj->index = 3; break; + case UART_4: obj->index = 4; break; + } + + is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); + + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) { + serial_irq_ids[obj->index] = 0; +} + +// serial_baud +// set the baud rate, taking in to account the current SystemFrequency +void serial_baud(serial_t *obj, int baudrate) { + uint32_t PCLK = PeripheralClock; + + // First we check to see if the basic divide with no DivAddVal/MulVal + // ratio gives us an integer result. If it does, we set DivAddVal = 0, + // MulVal = 1. Otherwise, we search the valid ratio value range to find + // the closest match. This could be more elegant, using search methods + // and/or lookup tables, but the brute force method is not that much + // slower, and is more maintainable. + uint16_t DL = PCLK / (16 * baudrate); + + uint8_t DivAddVal = 0; + uint8_t MulVal = 1; + int hit = 0; + uint16_t dlv; + uint8_t mv, dav; + if ((PCLK % (16 * baudrate)) != 0) { // Checking for zero remainder + int err_best = baudrate, b; + for (mv = 1; mv < 16 && !hit; mv++) + { + for (dav = 0; dav < mv; dav++) + { + // baudrate = PCLK / (16 * dlv * (1 + (DivAdd / Mul)) + // solving for dlv, we get dlv = mul * PCLK / (16 * baudrate * (divadd + mul)) + // mul has 4 bits, PCLK has 27 so we have 1 bit headroom which can be used for rounding + // for many values of mul and PCLK we have 2 or more bits of headroom which can be used to improve precision + // note: X / 32 doesn't round correctly. Instead, we use ((X / 16) + 1) / 2 for correct rounding + + if ((mv * PCLK * 2) & 0x80000000) // 1 bit headroom + dlv = ((((2 * mv * PCLK) / (baudrate * (dav + mv))) / 16) + 1) / 2; + else // 2 bits headroom, use more precision + dlv = ((((4 * mv * PCLK) / (baudrate * (dav + mv))) / 32) + 1) / 2; + + // datasheet says if DLL==DLM==0, then 1 is used instead since divide by zero is ungood + if (dlv == 0) + dlv = 1; + + // datasheet says if dav > 0 then DL must be >= 2 + if ((dav > 0) && (dlv < 2)) + dlv = 2; + + // integer rearrangement of the baudrate equation (with rounding) + b = ((PCLK * mv / (dlv * (dav + mv) * 8)) + 1) / 2; + + // check to see how we went + b = abs(b - baudrate); + if (b < err_best) + { + err_best = b; + + DL = dlv; + MulVal = mv; + DivAddVal = dav; + + if (b == baudrate) + { + hit = 1; + break; + } + } + } + } + } + + // set LCR[DLAB] to enable writing to divider registers + obj->uart->LCR |= (1 << 7); + + // set divider values + obj->uart->DLM = (DL >> 8) & 0xFF; + obj->uart->DLL = (DL >> 0) & 0xFF; + obj->uart->FDR = (uint32_t) DivAddVal << 0 + | (uint32_t) MulVal << 4; + + // clear LCR[DLAB] + obj->uart->LCR &= ~(1 << 7); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits + MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || + (parity == ParityForced1) || (parity == ParityForced0)); + + stop_bits -= 1; + data_bits -= 5; + + int parity_enable, parity_select; + switch (parity) { + case ParityNone: parity_enable = 0; parity_select = 0; break; + case ParityOdd : parity_enable = 1; parity_select = 0; break; + case ParityEven: parity_enable = 1; parity_select = 1; break; + case ParityForced1: parity_enable = 1; parity_select = 2; break; + case ParityForced0: parity_enable = 1; parity_select = 3; break; + default: + break; + } + + obj->uart->LCR = data_bits << 0 + | stop_bits << 2 + | parity_enable << 3 + | parity_select << 4; +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ +static inline void uart_irq(uint32_t iir, uint32_t index) { + // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling + SerialIrq irq_type; + switch (iir) { + case 1: irq_type = TxIrq; break; + case 2: irq_type = RxIrq; break; + default: return; + } + + if (serial_irq_ids[index] != 0) + irq_handler(serial_irq_ids[index], irq_type); +} + +void uart0_irq() {uart_irq((LPC_UART0->IIR >> 1) & 0x7, 0);} +void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1);} +void uart2_irq() {uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2);} +void uart3_irq() {uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3);} +void uart4_irq() {uart_irq((LPC_UART4->IIR >> 1) & 0x7, 4);} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { + IRQn_Type irq_n = (IRQn_Type)0; + uint32_t vector = 0; + switch ((int)obj->uart) { + case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break; + case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break; + case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break; + case UART_3: irq_n=UART3_IRQn; vector = (uint32_t)&uart3_irq; break; + case UART_4: irq_n=UART4_IRQn; vector = (uint32_t)&uart4_irq; break; + } + + if (enable) { + obj->uart->IER |= 1 << irq; + NVIC_SetVector(irq_n, vector); + NVIC_EnableIRQ(irq_n); + } else { // disable + int all_disabled = 0; + SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); + obj->uart->IER &= ~(1 << irq); + all_disabled = (obj->uart->IER & (1 << other_irq)) == 0; + if (all_disabled) + NVIC_DisableIRQ(irq_n); + } +} + +/****************************************************************************** + * READ/WRITE + ******************************************************************************/ +int serial_getc(serial_t *obj) { + while (!serial_readable(obj)); + return obj->uart->RBR; +} + +void serial_putc(serial_t *obj, int c) { + while (!serial_writable(obj)); + obj->uart->THR = c; +} + +int serial_readable(serial_t *obj) { + return obj->uart->LSR & 0x01; +} + +int serial_writable(serial_t *obj) { + return obj->uart->LSR & 0x20; +} + +void serial_clear(serial_t *obj) { + obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled + | 1 << 1 // rx FIFO reset + | 1 << 2 // tx FIFO reset + | 0 << 6; // interrupt depth +} + +void serial_pinout_tx(PinName tx) { + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) { + obj->uart->LCR |= (1 << 6); +} + +void serial_break_clear(serial_t *obj) { + obj->uart->LCR &= ~(1 << 6); +} + diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/spi_api.c new file mode 100644 index 0000000000..203404d0a4 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/spi_api.c @@ -0,0 +1,206 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "spi_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" + +static const PinMap PinMap_SPI_SCLK[] = { + {P0_7 , SPI_1, 2}, + {P1_19, SPI_1, 5}, + {P1_20, SPI_0, 5}, + {P2_22, SPI_0, 2}, + {P5_2, SPI_2, 2}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MOSI[] = { + {P0_9 , SPI_1, 2}, + {P1_24, SPI_0, 5}, + {P2_27, SPI_0, 2}, + {P5_0, SPI_2, 2}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {P0_8 , SPI_1, 2}, + {P1_23, SPI_0, 5}, + {P2_26, SPI_0, 2}, + {P5_1, SPI_2, 2}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {P0_6 , SPI_1, 2}, + {P2_23, SPI_0, 2}, + {P5_3, SPI_2, 2}, + {NC , NC , 0} +}; + +static inline int ssp_disable(spi_t *obj); +static inline int ssp_enable(spi_t *obj); + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { + // determine the SPI to use + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj->spi != NC); + + // enable power and clocking + switch ((int)obj->spi) { + case SPI_0: LPC_SC->PCONP |= 1 << 21; break; + case SPI_1: LPC_SC->PCONP |= 1 << 10; break; + case SPI_2: LPC_SC->PCONP |= 1 << 20; break; + } + + // set default format and frequency + if (ssel == NC) { + spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master + } else { + spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave + } + spi_frequency(obj, 1000000); + + // enable the ssp channel + ssp_enable(obj); + + // pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } +} + +void spi_free(spi_t *obj) {} + +void spi_format(spi_t *obj, int bits, int mode, int slave) { + MBED_ASSERT(((bits >= 4) && (bits <= 16)) && ((mode >= 0) && (mode <= 3))); + ssp_disable(obj); + + int polarity = (mode & 0x2) ? 1 : 0; + int phase = (mode & 0x1) ? 1 : 0; + + // set it up + int DSS = bits - 1; // DSS (data select size) + int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity + int SPH = (phase) ? 1 : 0; // SPH - clock out phase + + int FRF = 0; // FRF (frame format) = SPI + uint32_t tmp = obj->spi->CR0; + tmp &= ~(0xFFFF); + tmp |= DSS << 0 + | FRF << 4 + | SPO << 6 + | SPH << 7; + obj->spi->CR0 = tmp; + + tmp = obj->spi->CR1; + tmp &= ~(0xD); + tmp |= 0 << 0 // LBM - loop back mode - off + | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave + | 0 << 3; // SOD - slave output disable - na + obj->spi->CR1 = tmp; + ssp_enable(obj); +} + +void spi_frequency(spi_t *obj, int hz) { + ssp_disable(obj); + + uint32_t PCLK = PeripheralClock; + + int prescaler; + + for (prescaler = 2; prescaler <= 254; prescaler += 2) { + int prescale_hz = PCLK / prescaler; + + // calculate the divider + int divider = floor(((float)prescale_hz / (float)hz) + 0.5f); + + // check we can support the divider + if (divider < 256) { + // prescaler + obj->spi->CPSR = prescaler; + + // divider + obj->spi->CR0 &= ~(0xFFFF << 8); + obj->spi->CR0 |= (divider - 1) << 8; + ssp_enable(obj); + return; + } + } + error("Couldn't setup requested SPI frequency"); +} + +static inline int ssp_disable(spi_t *obj) { + return obj->spi->CR1 &= ~(1 << 1); +} + +static inline int ssp_enable(spi_t *obj) { + return obj->spi->CR1 |= (1 << 1); +} + +static inline int ssp_readable(spi_t *obj) { + return obj->spi->SR & (1 << 2); +} + +static inline int ssp_writeable(spi_t *obj) { + return obj->spi->SR & (1 << 1); +} + +static inline void ssp_write(spi_t *obj, int value) { + while (!ssp_writeable(obj)); + obj->spi->DR = value; +} + +static inline int ssp_read(spi_t *obj) { + while (!ssp_readable(obj)); + return obj->spi->DR; +} + +static inline int ssp_busy(spi_t *obj) { + return (obj->spi->SR & (1 << 4)) ? (1) : (0); +} + +int spi_master_write(spi_t *obj, int value) { + ssp_write(obj, value); + return ssp_read(obj); +} + +int spi_slave_receive(spi_t *obj) { + return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); +} + +int spi_slave_read(spi_t *obj) { + return obj->spi->DR; +} + +void spi_slave_write(spi_t *obj, int value) { + while (ssp_writeable(obj) == 0) ; + obj->spi->DR = value; +} + +int spi_busy(spi_t *obj) { + return ssp_busy(obj); +} From be14d7d1950c25cfbb4eb988c1e035a11c241d28 Mon Sep 17 00:00:00 2001 From: Anders Lindvall Date: Mon, 12 Jan 2015 16:26:33 +0100 Subject: [PATCH 02/25] Added LPC4088_DM in workspace_tools --- workspace_tools/targets.py | 6 ++++++ workspace_tools/tests.py | 6 +++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index d6769343ed..2a655e0353 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -306,6 +306,11 @@ class LPC4088(LPCTarget): t_self.debug("Generated custom binary file (internal flash + SPIFI)") LPCTarget.lpc_patch(t_self, resources, elf, binf) +class LPC4088_DM(LPC4088): + def __init__(self): + LPC4088.__init__(self) + self.extra_labels.append('LPC4088_DM') + class LPC4330_M4(LPCTarget): def __init__(self): LPCTarget.__init__(self) @@ -866,6 +871,7 @@ TARGETS = [ LPC824(), SSCI824(), # LPC824 LPC4088(), + LPC4088_DM(), LPC4330_M4(), LPC4330_M0(), LPC4337(), diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py index e3185b5c88..fa27816a0a 100644 --- a/workspace_tools/tests.py +++ b/workspace_tools/tests.py @@ -222,14 +222,14 @@ TESTS = [ "source_dir": join(TEST_DIR, "mbed", "spifi1"), "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB], "automated": True, - "mcu": ["LPC4088"] + "mcu": ["LPC4088","LPC4088_DM"] }, { "id": "MBED_A23", "description": "SPIFI for LPC4088 (test 2)", "source_dir": join(TEST_DIR, "mbed", "spifi2"), "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB], "automated": True, - "mcu": ["LPC4088"] + "mcu": ["LPC4088","LPC4088_DM"] }, { "id": "MBED_A24", "description": "Serial echo with RTS/CTS flow control", @@ -341,7 +341,7 @@ TESTS = [ "source_dir": join(TEST_DIR, "mbed", "sleep"), "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB], "duration": 30, - "mcu": ["LPC1768", "LPC11U24", "LPC4088","NRF51822"] + "mcu": ["LPC1768", "LPC11U24", "LPC4088","LPC4088_DM","NRF51822"] }, { "id": "MBED_5", "description": "PWM", From f463f6249806adea86856c28606963fb9f711aa6 Mon Sep 17 00:00:00 2001 From: Anders Lindvall Date: Tue, 13 Jan 2015 09:02:02 +0100 Subject: [PATCH 03/25] Added LPC4088_DM to exporters --- workspace_tools/export_test.py | 4 ++++ workspace_tools/targets.py | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/workspace_tools/export_test.py b/workspace_tools/export_test.py index c6106caffb..e24ff5c772 100755 --- a/workspace_tools/export_test.py +++ b/workspace_tools/export_test.py @@ -112,6 +112,7 @@ if __name__ == '__main__': ('uvision', 'LPC1347'), ('uvision', 'LPC1114'), ('uvision', 'LPC4088'), + ('uvision', 'LPC4088_DM'), ('uvision', 'LPC4337'), ('uvision', 'HRM1017'), @@ -131,6 +132,7 @@ if __name__ == '__main__': ('lpcxpresso', 'LPC1768'), ('lpcxpresso', 'LPC4088'), + ('lpcxpresso', 'LPC4088_DM'), ('lpcxpresso', 'LPC1114'), ('lpcxpresso', 'LPC11U35_401'), ('lpcxpresso', 'LPC11U35_501'), @@ -144,6 +146,7 @@ if __name__ == '__main__': # Linux path: /home/emimon01/bin/gcc-arm/bin/ # Windows path: C:/arm-none-eabi-gcc-4_7/bin/ ('gcc_arm', 'LPC1768'), + ('gcc_arm', 'LPC4088_DM'), ('gcc_arm', 'LPC1549'), ('gcc_arm', 'LPC1114'), ('gcc_arm', 'LPC11U35_401'), @@ -168,6 +171,7 @@ if __name__ == '__main__': ('ds5_5', 'LPC1768'), ('ds5_5', 'LPC11U24'), ('iar', 'LPC1768'), + ('iar', 'LPC4088_DM'), ('iar', 'LPC1347'), ('iar', 'NUCLEO_F030R8'), diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 2a655e0353..6c349db08d 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -944,7 +944,7 @@ for t in TARGETS: TARGET_NAMES = TARGET_MAP.keys() # Some targets with different name have the same exporters -EXPORT_MAP = {} +EXPORT_MAP = { "LPC4088_DM" : "LPC4088"} # Detection APIs def get_target_detect_codes(): From 6b0765c2fc7ae10cff18873c0410f3850684b60c Mon Sep 17 00:00:00 2001 From: Anders Lindvall Date: Tue, 13 Jan 2015 09:06:29 +0100 Subject: [PATCH 04/25] Increased duration for spifi tests (MBED_A22 and MBED_A23) --- workspace_tools/tests.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py index fa27816a0a..a0e23b8d71 100644 --- a/workspace_tools/tests.py +++ b/workspace_tools/tests.py @@ -222,6 +222,7 @@ TESTS = [ "source_dir": join(TEST_DIR, "mbed", "spifi1"), "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB], "automated": True, + "duration": 30, "mcu": ["LPC4088","LPC4088_DM"] }, { @@ -229,6 +230,7 @@ TESTS = [ "source_dir": join(TEST_DIR, "mbed", "spifi2"), "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB], "automated": True, + "duration": 30, "mcu": ["LPC4088","LPC4088_DM"] }, { From 4a2f3e00fe7b49e05e22b67b0c6c72dd10813211 Mon Sep 17 00:00:00 2001 From: Anders Lindvall Date: Wed, 21 Jan 2015 10:22:02 +0100 Subject: [PATCH 05/25] Fixed review comments --- .../hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c | 2 -- libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/rtc_api.c | 2 -- 2 files changed, 4 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c index 3a2621097f..ef3b3ac882 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c @@ -22,7 +22,6 @@ static const PinMap PinMap_I2C_SDA[] = { {P0_0 , I2C_1, 3}, {P0_27, I2C_0, 1}, {P2_14, I2C_1, 2}, - {P5_2, I2C_0, 5}, {NC , NC , 0} }; @@ -30,7 +29,6 @@ static const PinMap PinMap_I2C_SCL[] = { {P0_1 , I2C_1, 3}, {P0_28, I2C_0, 1}, {P2_15, I2C_1, 2}, - {P5_3, I2C_0, 5}, {NC , NC, 0} }; diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/rtc_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/rtc_api.c index c1156c3697..c75bf263d8 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/rtc_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/rtc_api.c @@ -28,7 +28,6 @@ * Clock Control Register * RTC_CCR[0] : Enable - 0 = Disabled, 1 = Enabled * RTC_CCR[1] : Reset - 0 = Normal, 1 = Reset - * RTC_CCR[4] : Clock Source - 0 = Prescaler, 1 = 32k Xtal * * The RTC may already be running, so we should set it up * without impacting if it is the case @@ -37,7 +36,6 @@ void rtc_init(void) { LPC_SC->PCONP |= 0x200; // Ensure power is on LPC_RTC->CCR = 0x00; -// clock source on 2368 is special test mode on 1768! LPC_RTC->CCR |= 1 << 0; // Ensure the RTC is enabled } From 627714908dd545d964d4c1d2bf869545d54f74bf Mon Sep 17 00:00:00 2001 From: Anders Lindvall Date: Sat, 24 Jan 2015 12:33:02 +0100 Subject: [PATCH 06/25] Removed the mbed_mac_address override as it is not needed on the LPC4088_DM --- .../{ => TARGET_LPC4088}/ethernet_api.c | 0 .../TARGET_LPC4088_DM/ethernet_api.c | 964 ++++++++++++++++++ 2 files changed, 964 insertions(+) rename libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/{ => TARGET_LPC4088}/ethernet_api.c (100%) create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/ethernet_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/ethernet_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c new file mode 100644 index 0000000000..5cde358b9a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c @@ -0,0 +1,964 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "ethernet_api.h" +#include "cmsis.h" +#include "mbed_interface.h" +#include "toolchain.h" +#include "mbed_error.h" + +#define NEW_LOGIC 0 +#define NEW_ETH_BUFFER 0 + +#if NEW_ETH_BUFFER + +#define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets) +#define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets) + +#define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size +#define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length) + +#else + +// Memfree calculation: +// (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) + +// (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556 +/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ +#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ +#define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */ +//#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ + +//#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ +#define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */ +#define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */ + +const int ethernet_MTU_SIZE = 0x300; + +#endif + +#define ETHERNET_ADDR_SIZE 6 + +PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */ + unsigned int Packet; + unsigned int Ctrl; +}; +typedef struct RX_DESC_TypeDef RX_DESC_TypeDef; + +PACKED struct RX_STAT_TypeDef { /* RX Status struct */ + unsigned int Info; + unsigned int HashCRC; +}; +typedef struct RX_STAT_TypeDef RX_STAT_TypeDef; + +PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */ + unsigned int Packet; + unsigned int Ctrl; +}; +typedef struct TX_DESC_TypeDef TX_DESC_TypeDef; + +PACKED struct TX_STAT_TypeDef { /* TX Status struct */ + unsigned int Info; +}; +typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; + +/* MAC Configuration Register 1 */ +#define MAC1_REC_EN 0x00000001 /* Receive Enable */ +#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ +#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ +#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ +#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ +#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ +#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ +#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ +#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ +#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ +#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ + +/* MAC Configuration Register 2 */ +#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ +#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ +#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ +#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ +#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ +#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ +#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ +#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ +#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ +#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ +#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ +#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ +#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ + +/* Back-to-Back Inter-Packet-Gap Register */ +#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ +#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ + +/* Non Back-to-Back Inter-Packet-Gap Register */ +#define IPGR_DEF 0x00000012 /* Recommended value */ + +/* Collision Window/Retry Register */ +#define CLRT_DEF 0x0000370F /* Default value */ + +/* PHY Support Register */ +#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ +//#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ +#define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */ + +/* Test Register */ +#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ +#define TEST_TST_PAUSE 0x00000002 /* Test Pause */ +#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ + +/* MII Management Configuration Register */ +#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ +#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ +#define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */ +#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ + +/* MII Management Command Register */ +#define MCMD_READ 0x00000001 /* MII Read */ +#define MCMD_SCAN 0x00000002 /* MII Scan continuously */ + +#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ +#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ + +/* MII Management Address Register */ +#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ +#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ + +/* MII Management Indicators Register */ +#define MIND_BUSY 0x00000001 /* MII is Busy */ +#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ +#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ +#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ + +/* Command Register */ +#define CR_RX_EN 0x00000001 /* Enable Receive */ +#define CR_TX_EN 0x00000002 /* Enable Transmit */ +#define CR_REG_RES 0x00000008 /* Reset Host Registers */ +#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ +#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ +#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ +#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ +#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ +#define CR_RMII 0x00000200 /* Reduced MII Interface */ +#define CR_FULL_DUP 0x00000400 /* Full Duplex */ + +/* Status Register */ +#define SR_RX_EN 0x00000001 /* Enable Receive */ +#define SR_TX_EN 0x00000002 /* Enable Transmit */ + +/* Transmit Status Vector 0 Register */ +#define TSV0_CRC_ERR 0x00000001 /* CRC error */ +#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ +#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ +#define TSV0_DONE 0x00000008 /* Tramsmission Completed */ +#define TSV0_MCAST 0x00000010 /* Multicast Destination */ +#define TSV0_BCAST 0x00000020 /* Broadcast Destination */ +#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ +#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ +#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ +#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ +#define TSV0_GIANT 0x00000400 /* Giant Frame */ +#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ +#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ +#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ +#define TSV0_PAUSE 0x20000000 /* Pause Frame */ +#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ +#define TSV0_VLAN 0x80000000 /* VLAN Frame */ + +/* Transmit Status Vector 1 Register */ +#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ +#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ + +/* Receive Status Vector Register */ +#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ +#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ +#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ +#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ +#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ +#define RSV_CRC_ERR 0x00100000 /* CRC Error */ +#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ +#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ +#define RSV_REC_OK 0x00800000 /* Frame Received OK */ +#define RSV_MCAST 0x01000000 /* Multicast Frame */ +#define RSV_BCAST 0x02000000 /* Broadcast Frame */ +#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ +#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ +#define RSV_PAUSE 0x10000000 /* Pause Frame */ +#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ +#define RSV_VLAN 0x40000000 /* VLAN Frame */ + +/* Flow Control Counter Register */ +#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ +#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ + +/* Flow Control Status Register */ +#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ + +/* Receive Filter Control Register */ +#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ +#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ +#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ +#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ +#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ +#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ +#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ +#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ + +/* Receive Filter WoL Status/Clear Registers */ +#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ +#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ +#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ +#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ +#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ +#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ +#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ +#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ + +/* Interrupt Status/Enable/Clear/Set Registers */ +#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ +#define INT_RX_ERR 0x00000002 /* Receive Error */ +#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ +#define INT_RX_DONE 0x00000008 /* Receive Done */ +#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ +#define INT_TX_ERR 0x00000020 /* Transmit Error */ +#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ +#define INT_TX_DONE 0x00000080 /* Transmit Done */ +#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ +#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ + +/* Power Down Register */ +#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ + +/* RX Descriptor Control Word */ +#define RCTRL_SIZE 0x000007FF /* Buffer size mask */ +#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ + +/* RX Status Hash CRC Word */ +#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ +#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ + +/* RX Status Information Word */ +#define RINFO_SIZE 0x000007FF /* Data size in bytes */ +#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ +#define RINFO_VLAN 0x00080000 /* VLAN Frame */ +#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ +#define RINFO_MCAST 0x00200000 /* Multicast Frame */ +#define RINFO_BCAST 0x00400000 /* Broadcast Frame */ +#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ +#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ +#define RINFO_LEN_ERR 0x02000000 /* Length Error */ +#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ +#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ +#define RINFO_OVERRUN 0x10000000 /* Receive overrun */ +#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ +#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ +#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +//#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) +#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \ + RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) + + +/* TX Descriptor Control Word */ +#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ +#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ +#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ +#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ +#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ +#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ +#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ + +/* TX Status Information Word */ +#define TINFO_COL_CNT 0x01E00000 /* Collision Count */ +#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ +#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ +#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ +#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ +#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ +#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ +#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +/* ENET Device Revision ID */ +#define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ + +/* DP83848C PHY Registers */ +#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ +#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ +#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ +#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ +#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ +#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ +#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ +#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ + +/* PHY Extended Registers */ +#define PHY_REG_STS 0x10 /* Status Register */ +#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ +#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ +#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ +#define PHY_REG_RECR 0x15 /* Receive Error Counter */ +#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ +#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ +#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ +#define PHY_REG_PHYCR 0x19 /* PHY Control Register */ +#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ +#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ +#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ + +#define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */ + +#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ +#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ +#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ +#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ +#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ + +#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ +#define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */ + +#define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */ + +#define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */ +#define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */ +#define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */ + +#define PHY_BMCR_RESET 0x8000 /* PHY Reset */ + +#define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */ + +#define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */ +#define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */ + + +static int phy_read(unsigned int PhyReg); +static int phy_write(unsigned int PhyReg, unsigned short Data); + +static void txdscr_init(void); +static void rxdscr_init(void); + +#if defined (__ICCARM__) +# define AHBSRAM1 +#elif defined(TOOLCHAIN_GCC_CR) +# define AHBSRAM1 __attribute__((section(".data.$RamPeriph32"))) +#else +# define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned)) +#endif + +AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE]; +AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE]; +AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG]; +AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG]; +AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG]; +AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG]; + + +#if NEW_LOGIC +static int rx_consume_offset = -1; +static int tx_produce_offset = -1; +#else +static int send_doff = 0; +static int send_idx = -1; +static int send_size = 0; + +static int receive_soff = 0; +static int receive_idx = -1; +#endif + +static uint32_t phy_id = 0; + +static inline int rinc(int idx, int mod) { + ++idx; + idx %= mod; + return idx; +} + +//extern unsigned int SystemFrequency; +static inline unsigned int clockselect() { + if(SystemCoreClock < 10000000) { + return 1; + } else if(SystemCoreClock < 15000000) { + return 2; + } else if(SystemCoreClock < 20000000) { + return 3; + } else if(SystemCoreClock < 25000000) { + return 4; + } else if(SystemCoreClock < 35000000) { + return 5; + } else if(SystemCoreClock < 50000000) { + return 6; + } else if(SystemCoreClock < 70000000) { + return 7; + } else if(SystemCoreClock < 80000000) { + return 8; + } else if(SystemCoreClock < 90000000) { + return 9; + } else if(SystemCoreClock < 100000000) { + return 10; + } else if(SystemCoreClock < 120000000) { + return 11; + } else if(SystemCoreClock < 130000000) { + return 12; + } else if(SystemCoreClock < 140000000) { + return 13; + } else if(SystemCoreClock < 150000000) { + return 15; + } else if(SystemCoreClock < 160000000) { + return 16; + } else { + return 0; + } +} + +#ifndef min +#define min(x, y) (((x)<(y))?(x):(y)) +#endif + +/*---------------------------------------------------------------------------- + Ethernet Device initialize + *----------------------------------------------------------------------------*/ +int ethernet_init() { + int regv, tout; + char mac[ETHERNET_ADDR_SIZE]; + unsigned int clock = clockselect(); + + LPC_SC->PCONP |= 0x40000000; /* Power Up the EMAC controller. */ + + LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */ + LPC_IOCON->P1_0 |= 0x01; /* ENET_TXD0 */ + LPC_IOCON->P1_1 &= ~0x07; + LPC_IOCON->P1_1 |= 0x01; /* ENET_TXD1 */ + LPC_IOCON->P1_4 &= ~0x07; + LPC_IOCON->P1_4 |= 0x01; /* ENET_TXEN */ + LPC_IOCON->P1_8 &= ~0x07; + LPC_IOCON->P1_8 |= 0x01; /* ENET_CRS */ + LPC_IOCON->P1_9 &= ~0x07; + LPC_IOCON->P1_9 |= 0x01; /* ENET_RXD0 */ + LPC_IOCON->P1_10 &= ~0x07; + LPC_IOCON->P1_10 |= 0x01; /* ENET_RXD1 */ + LPC_IOCON->P1_14 &= ~0x07; + LPC_IOCON->P1_14 |= 0x01; /* ENET_RX_ER */ + LPC_IOCON->P1_15 &= ~0x07; + LPC_IOCON->P1_15 |= 0x01; /* ENET_REF_CLK */ + LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */ + LPC_IOCON->P1_16 |= 0x01; /* ENET_MDC */ + LPC_IOCON->P1_17 &= ~0x07; + LPC_IOCON->P1_17 |= 0x01; /* ENET_MDIO */ + + /* Reset all EMAC internal modules. */ + LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | + MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES; + LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM; + + for(tout = 100; tout; tout--) __NOP(); /* A short delay after reset. */ + + LPC_EMAC->MAC1 = MAC1_PASS_ALL; /* Initialize MAC control registers. */ + LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; + LPC_EMAC->MAXF = ETH_MAX_FLEN; + LPC_EMAC->CLRT = CLRT_DEF; + LPC_EMAC->IPGR = IPGR_DEF; + + LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; /* Enable Reduced MII interface. */ + + LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; /* Set clock */ + LPC_EMAC->MCFG |= MCFG_RES_MII; /* and reset */ + + for(tout = 100; tout; tout--) __NOP(); /* A short delay */ + + LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; + LPC_EMAC->MCMD = 0; + + LPC_EMAC->SUPP = SUPP_RES_RMII; /* Reset Reduced MII Logic. */ + + for (tout = 100; tout; tout--) __NOP(); /* A short delay */ + + LPC_EMAC->SUPP = 0; + + phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */ + for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */ + regv = phy_read(PHY_REG_BMCR); + if(regv < 0 || tout == 0) { + return -1; /* Error */ + } + if(!(regv & PHY_BMCR_RESET)) { + break; /* Reset complete. */ + } + } + + phy_id = (phy_read(PHY_REG_IDR1) << 16); + phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0); + + if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) { + error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id); + } + + ethernet_set_link(-1, 0); + + /* Set the Ethernet MAC Address registers */ + ethernet_address(mac); + LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4]; + LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2]; + LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0]; + + txdscr_init(); /* initialize DMA TX Descriptor */ + rxdscr_init(); /* initialize DMA RX Descriptor */ + + LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN; + /* Receive Broadcast, Perfect Match Packets */ + + LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Enable EMAC interrupts. */ + LPC_EMAC->IntClear = 0xFFFF; /* Reset all interrupts */ + + LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); /* Enable receive and transmit mode of MAC Ethernet core */ + LPC_EMAC->MAC1 |= MAC1_REC_EN; + +#if NEW_LOGIC + rx_consume_offset = -1; + tx_produce_offset = -1; +#else + send_doff = 0; + send_idx = -1; + send_size = 0; + + receive_soff = 0; + receive_idx = -1; +#endif + + return 0; +} + +/*---------------------------------------------------------------------------- + Ethernet Device Uninitialize + *----------------------------------------------------------------------------*/ +void ethernet_free() { + LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE); + LPC_EMAC->IntClear = 0xFFFF; + + LPC_SC->PCONP &= ~0x40000000; /* Power down the EMAC controller. */ + + LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */ + LPC_IOCON->P1_1 &= ~0x07; + LPC_IOCON->P1_4 &= ~0x07; + LPC_IOCON->P1_8 &= ~0x07; + LPC_IOCON->P1_9 &= ~0x07; + LPC_IOCON->P1_10 &= ~0x07; + LPC_IOCON->P1_14 &= ~0x07; + LPC_IOCON->P1_15 &= ~0x07; + LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */ + LPC_IOCON->P1_17 &= ~0x07; +} + +// if(TxProduceIndex == TxConsumeIndex) buffer array is empty +// if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill +// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment +// TxConsumeIndex - The buffer that will/is beign sent by hardware + +int ethernet_write(const char *data, int slen) { + +#if NEW_LOGIC + + if(tx_produce_offset < 0) { // mark as active if not already + tx_produce_offset = 0; + } + + int index = LPC_EMAC->TxProduceIndex; + + int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum + int requested = slen; + int ncopy = min(remaining, requested); + + void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset); + void *psrc = (void *)(data); + + if(ncopy > 0 ){ + if(data != NULL) { + memcpy(pdst, psrc, ncopy); + } else { + memset(pdst, 0, ncopy); + } + } + + tx_produce_offset += ncopy; + + return ncopy; + +#else + void *pdst, *psrc; + const int dlen = ETH_FRAG_SIZE; + int copy = 0; + int soff = 0; + + if(send_idx == -1) { + send_idx = LPC_EMAC->TxProduceIndex; + } + + if(slen + send_doff > ethernet_MTU_SIZE) { + return -1; + } + + do { + copy = min(slen - soff, dlen - send_doff); + pdst = (void *)(txdesc[send_idx].Packet + send_doff); + psrc = (void *)(data + soff); + if(send_doff + copy > ETH_FRAG_SIZE) { + txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT); + send_idx = rinc(send_idx, NUM_TX_FRAG); + send_doff = 0; + } + + if(data != NULL) { + memcpy(pdst, psrc, copy); + } else { + memset(pdst, 0, copy); + } + + soff += copy; + send_doff += copy; + send_size += copy; + } while(soff != slen); + + return soff; +#endif +} + +int ethernet_send() { + +#if NEW_LOGIC + if(tx_produce_offset < 0) { // no buffer active + return -1; + } + + // ensure there is a link + if(!ethernet_link()) { + return -2; + } + + // we have been writing in to a buffer, so finalise it + int size = tx_produce_offset; + int index = LPC_EMAC->TxProduceIndex; + txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST); + + // Increment ProduceIndex to allow it to be sent + // We can only do this if the next slot is free + int next = rinc(index, NUM_TX_FRAG); + while(next == LPC_EMAC->TxConsumeIndex) { + for(int i=0; i<1000; i++) { __NOP(); } + } + + LPC_EMAC->TxProduceIndex = next; + tx_produce_offset = -1; + return size; + +#else + int s = send_size; + txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST); + send_idx = rinc(send_idx, NUM_TX_FRAG); + LPC_EMAC->TxProduceIndex = send_idx; + send_doff = 0; + send_idx = -1; + send_size = 0; + return s; +#endif +} + +// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read +// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd +// +// if(RxConsumeIndex == RxProduceIndex) buffer array is empty +// if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full + +// Recevies an arrived ethernet packet. +// Receiving an ethernet packet will drop the last received ethernet packet +// and make a new ethernet packet ready to read. +// Returns size of packet, else 0 if nothing to receive + +// We read from RxConsumeIndex from position rx_consume_offset +// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading +// rx_consume_offset = -1 // no frame +// rx_consume_offset = 0 // start of frame +// Assumption: A fragment should alway be a whole frame + +int ethernet_receive() { +#if NEW_LOGIC + + // if we are currently reading a valid RxConsume buffer, increment to the next one + if(rx_consume_offset >= 0) { + LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG); + } + + // if the buffer is empty, mark it as no valid buffer + if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) { + rx_consume_offset = -1; + return 0; + } + + uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info; + rx_consume_offset = 0; + + // check if it is not marked as last or for errors + if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) { + return -1; + } + + int size = (info & RINFO_SIZE) + 1; + return size - 4; // don't include checksum bytes + +#else + if(receive_idx == -1) { + receive_idx = LPC_EMAC->RxConsumeIndex; + } else { + while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && ((uint32_t)receive_idx != LPC_EMAC->RxProduceIndex)) { + receive_idx = rinc(receive_idx, NUM_RX_FRAG); + } + unsigned int info = rxstat[receive_idx].Info; + int slen = (info & RINFO_SIZE) + 1; + + if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) { + /* Invalid frame, ignore it and free buffer. */ + receive_idx = rinc(receive_idx, NUM_RX_FRAG); + } + receive_idx = rinc(receive_idx, NUM_RX_FRAG); + receive_soff = 0; + + LPC_EMAC->RxConsumeIndex = receive_idx; + } + + if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex) { + receive_idx = -1; + return 0; + } + + return (rxstat[receive_idx].Info & RINFO_SIZE) - 3; +#endif +} + +// Read from an recevied ethernet packet. +// After receive returnd a number bigger than 0 it is +// possible to read bytes from this packet. +// Read will write up to size bytes into data. +// It is possible to use read multible times. +// Each time read will start reading after the last read byte before. + +int ethernet_read(char *data, int dlen) { +#if NEW_LOGIC + // Check we have a valid buffer to read + if(rx_consume_offset < 0) { + return 0; + } + + // Assume 1 fragment block + uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info; + int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum + + int remaining = size - rx_consume_offset; + int requested = dlen; + int ncopy = min(remaining, requested); + + void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset); + void *pdst = (void *)(data); + + if(data != NULL && ncopy > 0) { + memcpy(pdst, psrc, ncopy); + } + + rx_consume_offset += ncopy; + + return ncopy; +#else + int slen; + int copy = 0; + unsigned int more; + unsigned int info; + void *pdst, *psrc; + int doff = 0; + + if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) { + return 0; + } + + do { + info = rxstat[receive_idx].Info; + more = !(info & RINFO_LAST_FLAG); + slen = (info & RINFO_SIZE) + 1; + + if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) { + /* Invalid frame, ignore it and free buffer. */ + receive_idx = rinc(receive_idx, NUM_RX_FRAG); + } else { + + copy = min(slen - receive_soff, dlen - doff); + psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff); + pdst = (void *)(data + doff); + + if(data != NULL) { + /* check if Buffer available */ + memcpy(pdst, psrc, copy); + } + + receive_soff += copy; + doff += copy; + + if((more && (receive_soff == slen))) { + receive_idx = rinc(receive_idx, NUM_RX_FRAG); + receive_soff = 0; + } + } + } while(more && !(doff == dlen) && !receive_soff); + + return doff; +#endif +} + +int ethernet_link(void) { + + if (phy_id == DP83848C_ID) { + return (phy_read(PHY_REG_STS) & PHY_STS_LINK); + } + else { // LAN8720_ID + return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK); + } +} + +static int phy_write(unsigned int PhyReg, unsigned short Data) { + unsigned int timeOut; + + LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; + LPC_EMAC->MWTD = Data; + + for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) { /* Wait until operation completed */ + if((LPC_EMAC->MIND & MIND_BUSY) == 0) { + return 0; + } + } + + return -1; +} + + +static int phy_read(unsigned int PhyReg) { + unsigned int timeOut; + + LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; + LPC_EMAC->MCMD = MCMD_READ; + + for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) { /* Wait until operation completed */ + if((LPC_EMAC->MIND & MIND_BUSY) == 0) { + LPC_EMAC->MCMD = 0; + return LPC_EMAC->MRDD; /* Return a 16-bit value. */ + } + } + + return -1; +} + + +static void txdscr_init() { + int i; + + for(i = 0; i < NUM_TX_FRAG; i++) { + txdesc[i].Packet = (uint32_t)&txbuf[i]; + txdesc[i].Ctrl = 0; + txstat[i].Info = 0; + } + + LPC_EMAC->TxDescriptor = (uint32_t)txdesc; /* Set EMAC Transmit Descriptor Registers. */ + LPC_EMAC->TxStatus = (uint32_t)txstat; + LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1; + + LPC_EMAC->TxProduceIndex = 0; /* Tx Descriptors Point to 0 */ +} + + +static void rxdscr_init() { + int i; + + for(i = 0; i < NUM_RX_FRAG; i++) { + rxdesc[i].Packet = (uint32_t)&rxbuf[i]; + rxdesc[i].Ctrl = RCTRL_INT | (ETH_FRAG_SIZE-1); + rxstat[i].Info = 0; + rxstat[i].HashCRC = 0; + } + + LPC_EMAC->RxDescriptor = (uint32_t)rxdesc; /* Set EMAC Receive Descriptor Registers. */ + LPC_EMAC->RxStatus = (uint32_t)rxstat; + LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1; + + LPC_EMAC->RxConsumeIndex = 0; /* Rx Descriptors Point to 0 */ +} + +void ethernet_address(char *mac) { + mbed_mac_address(mac); +} + +void ethernet_set_link(int speed, int duplex) { + unsigned short phy_data; + int tout; + + if((speed < 0) || (speed > 1)) { + phy_data = PHY_AUTO_NEG; + } else { + phy_data = (((unsigned short) speed << 13) | + ((unsigned short) duplex << 8)); + } + + phy_write(PHY_REG_BMCR, phy_data); + + for (tout = 100; tout; tout--) { __NOP(); } /* A short delay */ + + switch(phy_id) { + case DP83848C_ID: + phy_data = phy_read(PHY_REG_STS); + + if(phy_data & PHY_STS_DUPLEX) { + LPC_EMAC->MAC2 |= MAC2_FULL_DUP; + LPC_EMAC->Command |= CR_FULL_DUP; + LPC_EMAC->IPGT = IPGT_FULL_DUP; + } else { + LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP; + LPC_EMAC->Command &= ~CR_FULL_DUP; + LPC_EMAC->IPGT = IPGT_HALF_DUP; + } + + if(phy_data & PHY_STS_SPEED) { + LPC_EMAC->SUPP &= ~SUPP_SPEED; + } else { + LPC_EMAC->SUPP |= SUPP_SPEED; + } + break; + + case LAN8720_ID: + phy_data = phy_read(PHY_REG_SCSR); + + if (phy_data & PHY_SCSR_DUPLEX) { + LPC_EMAC->MAC2 |= MAC2_FULL_DUP; + LPC_EMAC->Command |= CR_FULL_DUP; + LPC_EMAC->IPGT = IPGT_FULL_DUP; + } else { + LPC_EMAC->Command &= ~CR_FULL_DUP; + LPC_EMAC->IPGT = IPGT_HALF_DUP; + } + + if(phy_data & PHY_SCSR_100MBIT) { + LPC_EMAC->SUPP |= SUPP_SPEED; + } else { + LPC_EMAC->SUPP &= ~SUPP_SPEED; + } + + break; + } +} From 25131013bda23257cf0eff4ba3209e370985f36f Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Thu, 29 Jan 2015 16:37:41 +0900 Subject: [PATCH 07/25] Add RTC function. User can use set_time() and time() by this addition. --- .../hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h | 2 +- .../TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c | 374 ++++++++++++++++++ 2 files changed, 375 insertions(+), 1 deletion(-) create mode 100644 libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h index cae2a6318f..82a80e3b6e 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h @@ -44,7 +44,7 @@ #define DEVICE_CAN 0 -#define DEVICE_RTC 0 +#define DEVICE_RTC 1 #define DEVICE_ETHERNET 1 diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c new file mode 100644 index 0000000000..e984517275 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c @@ -0,0 +1,374 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed_assert.h" +#include "device.h" + +#if DEVICE_RTC + +#include "rtc_api.h" +#include "rtc_iodefine.h" + + +#define RCR1_VAL_ON (0x08u) // AIE = 1 +#define RCR1_VAL_OFF (0x00u) +#define RCR2_VAL_ALLSTOP (0x00u) +#define RCR2_VAL_START (0x01u) // START = 1 +#define RCR2_VAL_RESET (0x02u) // RESET = 1 +#define RCR3_VAL (0x00u) +#define RCR5_VAL_EXTAL (0x01u) // RCKSEL = connect EXTAL +#define RCR5_VAL_RTCX1 (0x00u) // RCKSEL = disconnect EXTAL +#define RFRH_VAL_13333 (0x8003u) // 13.3333MHz (= 64Hz * 0x32DCD) +#define RFRL_VAL_13333 (0x2DCDu) // +#define RFRH_VAL_MAX (0x0007u) // MAX value (= 128Hz * 0x7FFFF) +#define RFRL_VAL_MAX (0xFFFFu) // + +#define MASK_00_03_POS (0x000Fu) +#define MASK_04_07_POS (0x00F0u) +#define MASK_08_11_POS (0x0F00u) +#define MASK_12_15_POS (0xF000u) +#define MASK_16_20_POS (0x000F0000u) +#define SHIFT_1_HBYTE (4u) +#define SHIFT_2_HBYTE (8u) +#define SHIFT_3_HBYTE (12u) +#define SHIFT_1BYTE (8u) +#define SHIFT_2BYTE (16u) + +#define TIME_ERROR_VAL (0xFFFFFFFFu) + +static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val); +static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val); +static uint8_t rtc_hex8_to_dec(uint8_t hex_val); +static uint16_t rtc_hex16_to_dec(uint16_t hex_val); + + +/* + * Setup the RTC based on a time structure. + * The rtc_init function should be executed first. + * [in] + * None. + * [out] + * None. + */ +void rtc_init(void) { + volatile uint8_t dummy_read; + + // Set control register + RTC.RCR2 = RCR2_VAL_ALLSTOP; + RTC.RCR1 = RCR1_VAL_ON; + RTC.RCR3 = RCR3_VAL; + RTC.RCR5 = RCR5_VAL_EXTAL; + RTC.RFRH = RFRH_VAL_13333; + RTC.RFRL = RFRL_VAL_13333; + + // Dummy read + dummy_read = RTC.RCR2; + dummy_read = RTC.RCR2; + + RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1 + + // Dummy read + dummy_read = RTC.RCR2; + dummy_read = RTC.RCR2; + + // Set timer and alarm. Default value :01-01-1970 00:00:00 + RTC.RSECCNT = 0; + RTC.RMINCNT = 0; + RTC.RHRCNT = 0; + RTC.RWKCNT = 0; + RTC.RDAYCNT = 1; + RTC.RMONCNT = 1; + RTC.RYRCNT = 0x1970; + RTC.RSECAR = 0; + RTC.RMINAR = 0; + RTC.RHRAR = 0; + RTC.RWKAR = 0; + RTC.RDAYAR = 1; + RTC.RMONAR = 1; + RTC.RYRAR = 0x1970; + + // Dummy read + dummy_read = RTC.RYRCNT; + dummy_read = RTC.RYRCNT; + +} + + +/* + * Release the RTC based on a time structure. + * [in] + * None. + * [out] + * None. + */ +void rtc_free(void) { + volatile uint8_t dummy_read; + + // Set control register + RTC.RCR2 = RCR2_VAL_ALLSTOP; + RTC.RCR1 = RCR1_VAL_OFF; + RTC.RCR3 = RCR3_VAL; + RTC.RCR5 = RCR5_VAL_RTCX1; + RTC.RFRH = RFRH_VAL_MAX; + RTC.RFRL = RFRL_VAL_MAX; + + // Dummy read + dummy_read = RTC.RCR2; + dummy_read = RTC.RCR2; + RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1 + + // Dummy read + dummy_read = RTC.RCR2; + dummy_read = RTC.RCR2; + + // Set timer and alarm. Default value :01-01-1970 00:00:00 + RTC.RSECCNT = 0; + RTC.RMINCNT = 0; + RTC.RHRCNT = 0; + RTC.RWKCNT = 0; + RTC.RDAYCNT = 1; + RTC.RMONCNT = 1; + RTC.RYRCNT = 0x1970; + RTC.RSECAR = 0; + RTC.RMINAR = 0; + RTC.RHRAR = 0; + RTC.RWKAR = 0; + RTC.RDAYAR = 1; + RTC.RMONAR = 1; + RTC.RYRAR = 0x1970; + + // Dummy read + dummy_read = RTC.RYRCNT; + dummy_read = RTC.RYRCNT; + +} + + +/* + * Check the RTC has been enabled. + * Clock Control Register RTC.RCR1(bit3): 0 = Disabled, 1 = Enabled. + * [in] + * None. + * [out] + * 0:Disabled, 1:Enabled. + */ +int rtc_isenabled(void) { + int ret_val = 0; + + if ((RTC.RCR1 & RCR1_VAL_ON) != 0) { // RTC ON ? + ret_val = 1; + } + + return ret_val; +} + + +/* + * RTC read function. + * [in] + * None. + * [out] + * UNIX timestamp value. + */ +time_t rtc_read(void) { + + struct tm timeinfo; + int err = 0; + uint8_t tmp_regdata; + time_t t; + + if (rtc_isenabled() != 0) { + RTC.RCR1 &= ~0x10u; // CIE = 0 + do { + // before reading process + tmp_regdata = RTC.RCR1; + tmp_regdata &= ~0x80u; // CF = 0 + tmp_regdata |= 0x01u; // AF = 1 + RTC.RCR1 = tmp_regdata; + + // Read RTC register + err = rtc_dec8_to_hex(RTC.RSECCNT , 0 , &timeinfo.tm_sec); + err += rtc_dec8_to_hex(RTC.RMINCNT , 0 , &timeinfo.tm_min); + err += rtc_dec8_to_hex(RTC.RHRCNT , 0 , &timeinfo.tm_hour); + err += rtc_dec8_to_hex(RTC.RDAYCNT , 0 , &timeinfo.tm_mday); + err += rtc_dec8_to_hex(RTC.RMONCNT , 1 , &timeinfo.tm_mon); + err += rtc_dec16_to_hex(RTC.RYRCNT , 1900 , &timeinfo.tm_year); + } while ((RTC.RCR1 & 0x80u) != 0); + } else { + err = 1; + } + + if (err == 0) { + // Convert to timestamp + t = mktime(&timeinfo); + } else { + // Error + t = TIME_ERROR_VAL; + } + + return t; +} + +/* + * Dec(8bit) to Hex function for RTC. + * [in] + * dec_val:Decimal value (from 0x00 to 0x99). + * offset:Subtract offset from dec_val. + * hex_val:Pointer of output hexadecimal value. + * [out] + * 0:Success + * 1:Error + */ +static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val) { + int err = 0; + uint8_t ret_val; + + if (hex_val != NULL) { + if (((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) || + ((dec_val & MASK_00_03_POS) >= 0x0A)) { + err = 1; + } else { + ret_val = ((dec_val & MASK_04_07_POS) >> SHIFT_1_HBYTE) * 10 + + (dec_val & MASK_00_03_POS); + if (ret_val < offset) { + err = 1; + } else { + *hex_val = ret_val - offset; + } + } + } else { + err = 1; + } + + return err; +} + +/* + * Dec(16bit) to Hex function for RTC + * [in] + * dec_val:Decimal value (from 0x0000 to 0x9999). + * offset:Subtract offset from dec_val. + * hex_val:Pointer of output hexadecimal value. + * [out] + * 0:Success + * 1:Error + */ +static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val) { + int err = 0; + uint16_t ret_val; + + if (hex_val != NULL) { + if (((dec_val & MASK_12_15_POS) >= (0x0A << SHIFT_3_HBYTE)) || + ((dec_val & MASK_08_11_POS) >= (0x0A << SHIFT_2_HBYTE)) || + ((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) || + ((dec_val & MASK_00_03_POS) >= 0x0A)) { + err = 1; + *hex_val = 0; + } else { + ret_val = (((dec_val & MASK_12_15_POS)) >> SHIFT_3_HBYTE) * 1000 + + (((dec_val & MASK_08_11_POS)) >> SHIFT_2_HBYTE) * 100 + + (((dec_val & MASK_04_07_POS)) >> SHIFT_1_HBYTE) * 10 + + (dec_val & MASK_00_03_POS); + if (ret_val < offset) { + err = 1; + } else { + *hex_val = ret_val - offset; + } + } + } else { + err = 1; + } + return err; +} + +/* + * RTC write function + * [in] + * t:UNIX timestamp value + * [out] + * None. + */ +void rtc_write(time_t t) { + + struct tm *timeinfo = localtime(&t); + volatile uint16_t dummy_read; + + if (rtc_isenabled() != 0) { + RTC.RCR2 = RCR2_VAL_ALLSTOP; + dummy_read = (uint16_t)RTC.RCR2; + dummy_read = (uint16_t)RTC.RCR2; + RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1 + dummy_read = (uint16_t)RTC.RCR2; + dummy_read = (uint16_t)RTC.RCR2; + + RTC.RSECCNT = rtc_hex8_to_dec(timeinfo->tm_sec); + RTC.RMINCNT = rtc_hex8_to_dec(timeinfo->tm_min); + RTC.RHRCNT = rtc_hex8_to_dec(timeinfo->tm_hour); + RTC.RDAYCNT = rtc_hex8_to_dec(timeinfo->tm_mday); + RTC.RMONCNT = rtc_hex8_to_dec(timeinfo->tm_mon + 1); + RTC.RYRCNT = rtc_hex16_to_dec(timeinfo->tm_year + 1900); + dummy_read = (uint16_t)RTC.RYRCNT; + dummy_read = (uint16_t)RTC.RYRCNT; + + RTC.RCR2 = RCR2_VAL_START; // START = 1 + + dummy_read = (uint16_t)RTC.RCR2; + dummy_read = (uint16_t)RTC.RCR2; + } +} + +/* + * HEX to Dec(8bit) function for RTC. + * [in] + * hex_val:Hexadecimal value. + * [out] + * decimal value:From 0x00 to 0x99. + */ +static uint8_t rtc_hex8_to_dec(uint8_t hex_val) { + uint32_t calc_data; + + calc_data = hex_val / 10 * 0x10; + calc_data += hex_val % 10; + + if (calc_data > 0x99) { + calc_data = 0; + } + + return (uint8_t)calc_data; +} + +/* + * HEX to Dec(16bit) function for RTC. + * [in] + * hex_val:Hexadecimal value. + * [out] + * decimal value:From 0x0000 to 0x9999. + */ +static uint16_t rtc_hex16_to_dec(uint16_t hex_val) { + uint32_t calc_data; + calc_data = hex_val / 1000 * 0x1000; + calc_data += ((hex_val / 100) % 10) * 0x100; + calc_data += ((hex_val / 10) % 10) * 0x10; + calc_data += hex_val % 10; + + if (calc_data > 0x9999) { + calc_data = 0; + } + return (uint16_t)calc_data; + +} + +#endif /* DEVICE_RTC */ From 83712b1f8308df76c2445769c4c55acc4bbe1c17 Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Thu, 29 Jan 2015 16:38:21 +0900 Subject: [PATCH 08/25] Add Serial flow control and fix a bug that parity setting is wrong. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Modifies are as below. - Add flow control - Change the range of baud rate that can be set in the baud function. 　8138 bps more -> 128 bps more - Fixed a bug that designation of parity had been reversed in format(). --- .../TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c | 371 ++++++++++++++---- 1 file changed, 289 insertions(+), 82 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c index 64048fbfc7..83b0004dee 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -30,6 +30,8 @@ /****************************************************************************** * INITIALIZATION ******************************************************************************/ +#define PCLK (66666666) // Define the peripheral clock P1 frequency. + #define UART_NUM 8 #define IRQ_NUM 2 @@ -52,35 +54,54 @@ static void uart7_rx_irq(void); static const PinMap PinMap_UART_TX[] = { - {P6_3 , UART2, 7}, {P2_14 , UART0, 6}, - {P5_0 , UART4, 5}, - {P5_3 , UART3, 5}, - {P5_6 , UART6, 5}, {P2_5 , UART1, 6}, + {P6_3 , UART2, 7}, + {P5_3 , UART3, 5}, + {P8_8 , UART3, 7}, + {P5_0 , UART4, 5}, {P8_14 , UART4, 7}, {P8_13 , UART5, 5}, - {P7_4 , UART7, 4}, {P11_10, UART5, 3}, {P6_6 , UART5, 5}, + {P5_6 , UART6, 5}, + {P11_1 , UART6, 4}, + {P7_4 , UART7, 4}, {NC , NC , 0} }; static const PinMap PinMap_UART_RX[] = { - {P6_2 , UART2, 7}, {P2_15 , UART0, 6}, - {P5_1 , UART4, 5}, - {P5_4 , UART3, 5}, - {P5_7 , UART6, 5}, {P2_6 , UART1, 6}, + {P6_2 , UART2, 7}, + {P5_4 , UART3, 5}, + {P8_9 , UART3, 7}, + {P5_1 , UART4, 5}, {P8_15 , UART4, 7}, {P8_11 , UART5, 5}, - {P7_5 , UART7, 4}, {P11_11, UART5, 3}, {P6_7 , UART5, 5}, + {P5_7 , UART6, 5}, + {P11_2 , UART6, 4}, + {P7_5 , UART7, 4}, {NC , NC , 0} }; +static const PinMap PinMap_UART_CTS[] = { + {P2_3 , UART1, 6}, + {P11_7 , UART5, 3}, + {P7_6 , UART7, 4}, + {NC , NC , 0} +}; +static const PinMap PinMap_UART_RTS[] = { + {P2_7 , UART1, 6}, + {P11_8 , UART5, 3}, + {P7_7 , UART7, 4}, + {NC , NC , 0} +}; + + + static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST; static uart_irq_handler irq_handler; @@ -141,7 +162,7 @@ static __IO uint16_t *SCFSR_MATCH[] = { void serial_init(serial_t *obj, PinName tx, PinName rx) { - volatile uint8_t dummy ; + volatile uint8_t dummy ; int is_stdio_uart = 0; // determine the UART to use uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); @@ -153,14 +174,30 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { obj->uart = (struct st_scif *)SCIF[uart]; // enable power switch (uart) { - case UART0: CPG.STBCR4 &= ~(1 << 7); break; - case UART1: CPG.STBCR4 &= ~(1 << 6); break; - case UART2: CPG.STBCR4 &= ~(1 << 5); break; - case UART3: CPG.STBCR4 &= ~(1 << 4); break; - case UART4: CPG.STBCR4 &= ~(1 << 3); break; - case UART5: CPG.STBCR4 &= ~(1 << 2); break; - case UART6: CPG.STBCR4 &= ~(1 << 1); break; - case UART7: CPG.STBCR4 &= ~(1 << 0); break; + case UART0: + CPG.STBCR4 &= ~(1 << 7); + break; + case UART1: + CPG.STBCR4 &= ~(1 << 6); + break; + case UART2: + CPG.STBCR4 &= ~(1 << 5); + break; + case UART3: + CPG.STBCR4 &= ~(1 << 4); + break; + case UART4: + CPG.STBCR4 &= ~(1 << 3); + break; + case UART5: + CPG.STBCR4 &= ~(1 << 2); + break; + case UART6: + CPG.STBCR4 &= ~(1 << 1); + break; + case UART7: + CPG.STBCR4 &= ~(1 << 0); + break; } dummy = CPG.STBCR4; @@ -181,7 +218,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { /* ORER bit clear */ obj->uart->SCLSR = 0; - /* ---- Serial extension mode register (SCEMR) setting ---- + /* ---- Serial extension mode register (SCEMR) setting ---- b7 BGDM - Baud rate generator double-speed mode : Normal mode b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */ obj->uart->SCEMR = 0x0000u; @@ -193,26 +230,49 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { /* ---- FIFO control register (SCFCR) setting ---- */ obj->uart->SCFCR = 0x0030u; - /* ---- Serial port register (SCSPTR) setting ---- + /* ---- Serial port register (SCSPTR) setting ---- b1 SPB2IO - Serial port break output : disabled b0 SPB2DT - Serial port break data : High-level */ - //obj->uart->SCSPTR |= 0x0000u; + obj->uart->SCSPTR = 0x0003u; // SPB2IO = 1, SPB2DT = 1 obj->uart->SCSCR = 0x00F0; + /* ---- Line status register (SCLSR) setting ---- + b0 ORER - Overrun error detect : clear */ + + if (obj->uart->SCLSR & 0x0001) { + obj->uart->SCLSR = 0u; // ORER clear + } + // pinout the chosen uart pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(rx, PinMap_UART_RX); switch (uart) { - case UART0: obj->index = 0; break; - case UART1: obj->index = 1; break; - case UART2: obj->index = 2; break; - case UART3: obj->index = 3; break; - case UART4: obj->index = 4; break; - case UART5: obj->index = 5; break; - case UART6: obj->index = 6; break; - case UART7: obj->index = 7; break; + case UART0: + obj->index = 0; + break; + case UART1: + obj->index = 1; + break; + case UART2: + obj->index = 2; + break; + case UART3: + obj->index = 3; + break; + case UART4: + obj->index = 4; + break; + case UART5: + obj->index = 5; + break; + case UART6: + obj->index = 6; + break; + case UART7: + obj->index = 7; + break; } uart_data[obj->index].sw_rts.pin = NC; uart_data[obj->index].sw_cts.pin = NC; @@ -232,13 +292,52 @@ void serial_free(serial_t *obj) { // serial_baud // set the baud rate, taking in to account the current SystemFrequency void serial_baud(serial_t *obj, int baudrate) { + uint16_t DL; - uint32_t PCLK = 66666666; + obj->uart->SCSMR &= ~0x0003; - uint16_t DL = (PCLK / (32 * baudrate)) -1; - - // set LCR[DLAB] to enable writing to divider registers - obj->uart->SCBRR = DL; + if (baudrate > 32552) { + obj->uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1 + DL = PCLK / (8 * baudrate); + if (DL > 0) { + DL--; + } + obj->uart->SCBRR = (uint8_t)DL; + } else if (baudrate > 16276) { + obj->uart->SCEMR = 0x0080; // BGDM = 1 + obj->uart->SCBRR = PCLK / (16 * baudrate) - 1; + } else if (baudrate > 8138) { + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = PCLK / (32 * baudrate) - 1; + } else if (baudrate > 4169) { + obj->uart->SCSMR |= 0x0001; + obj->uart->SCEMR = 0x0080; // BGDM = 1 + obj->uart->SCBRR = PCLK / (64 * baudrate) - 1; + } else if (baudrate > 2034) { + obj->uart->SCSMR |= 0x0001; + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = PCLK / (128 * baudrate) - 1; + } else if (baudrate > 1017) { + obj->uart->SCSMR |= 0x0002; + obj->uart->SCEMR = 0x0080; // BGDM = 1 + obj->uart->SCBRR = PCLK / (256 * baudrate) - 1; + } else if (baudrate > 508) { + obj->uart->SCSMR |= 0x0002; + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = PCLK / (512 * baudrate) - 1; + } else if (baudrate > 254) { + obj->uart->SCSMR |= 0x0003; + obj->uart->SCEMR = 0x0080; // BGDM = 1 + obj->uart->SCBRR = PCLK / (1024 * baudrate) - 1; + } else if (baudrate > 127) { + obj->uart->SCSMR |= 0x0003; + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = PCLK / (2048 * baudrate) - 1; + } else { + obj->uart->SCSMR |= 0x0003; + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = 0xFFu; + } } void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { @@ -246,9 +345,9 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b int parity_select; MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits - MBED_ASSERT((data_bits > 6) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits + MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 5: 5 data bits ... 3: 8 data bits MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || - (parity == ParityForced1) || (parity == ParityForced0)); + (parity == ParityForced1) || (parity == ParityForced0)); stop_bits = (stop_bits == 1)? 0: (stop_bits == 2)? 1: @@ -259,28 +358,30 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b 0; // must not to be switch (parity) { - case ParityNone: - parity_enable = 0; - parity_select = 0; - break; - case ParityOdd: - parity_enable = 1; - parity_select = 0; - break; - case ParityEven: - parity_enable = 1; - parity_select = 1; - break; - default: - parity_enable = 0; - parity_select = 0; - break; + case ParityNone: + parity_enable = 0; + parity_select = 0; + break; + case ParityOdd: + parity_enable = 1; + parity_select = 1; + break; + case ParityEven: + parity_enable = 1; + parity_select = 0; + break; + case ParityForced1: + case ParityForced0: + default: + parity_enable = 0; + parity_select = 0; + break; } obj->uart->SCSMR = data_bits << 6 - | parity_enable << 5 - | parity_select << 4 - | stop_bits << 3; + | parity_enable << 5 + | parity_select << 4 + | stop_bits << 3; } /****************************************************************************** @@ -312,23 +413,55 @@ static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) { } /* TX handler */ -static void uart0_tx_irq(void) {uart_tx_irq(SCIFTXI0_IRQn, 0);} -static void uart1_tx_irq(void) {uart_tx_irq(SCIFTXI1_IRQn, 1);} -static void uart2_tx_irq(void) {uart_tx_irq(SCIFTXI2_IRQn, 2);} -static void uart3_tx_irq(void) {uart_tx_irq(SCIFTXI3_IRQn, 3);} -static void uart4_tx_irq(void) {uart_tx_irq(SCIFTXI4_IRQn, 4);} -static void uart5_tx_irq(void) {uart_tx_irq(SCIFTXI5_IRQn, 5);} -static void uart6_tx_irq(void) {uart_tx_irq(SCIFTXI6_IRQn, 6);} -static void uart7_tx_irq(void) {uart_tx_irq(SCIFTXI7_IRQn, 7);} +static void uart0_tx_irq(void) { + uart_tx_irq(SCIFTXI0_IRQn, 0); +} +static void uart1_tx_irq(void) { + uart_tx_irq(SCIFTXI1_IRQn, 1); +} +static void uart2_tx_irq(void) { + uart_tx_irq(SCIFTXI2_IRQn, 2); +} +static void uart3_tx_irq(void) { + uart_tx_irq(SCIFTXI3_IRQn, 3); +} +static void uart4_tx_irq(void) { + uart_tx_irq(SCIFTXI4_IRQn, 4); +} +static void uart5_tx_irq(void) { + uart_tx_irq(SCIFTXI5_IRQn, 5); +} +static void uart6_tx_irq(void) { + uart_tx_irq(SCIFTXI6_IRQn, 6); +} +static void uart7_tx_irq(void) { + uart_tx_irq(SCIFTXI7_IRQn, 7); +} /* RX handler */ -static void uart0_rx_irq(void) {uart_rx_irq(SCIFRXI0_IRQn, 0);} -static void uart1_rx_irq(void) {uart_rx_irq(SCIFRXI1_IRQn, 1);} -static void uart2_rx_irq(void) {uart_rx_irq(SCIFRXI2_IRQn, 2);} -static void uart3_rx_irq(void) {uart_rx_irq(SCIFRXI3_IRQn, 3);} -static void uart4_rx_irq(void) {uart_rx_irq(SCIFRXI4_IRQn, 4);} -static void uart5_rx_irq(void) {uart_rx_irq(SCIFRXI5_IRQn, 5);} -static void uart6_rx_irq(void) {uart_rx_irq(SCIFRXI6_IRQn, 6);} -static void uart7_rx_irq(void) {uart_rx_irq(SCIFRXI7_IRQn, 7);} +static void uart0_rx_irq(void) { + uart_rx_irq(SCIFRXI0_IRQn, 0); +} +static void uart1_rx_irq(void) { + uart_rx_irq(SCIFRXI1_IRQn, 1); +} +static void uart2_rx_irq(void) { + uart_rx_irq(SCIFRXI2_IRQn, 2); +} +static void uart3_rx_irq(void) { + uart_rx_irq(SCIFRXI3_IRQn, 3); +} +static void uart4_rx_irq(void) { + uart_rx_irq(SCIFRXI4_IRQn, 4); +} +static void uart5_rx_irq(void) { + uart_rx_irq(SCIFRXI5_IRQn, 5); +} +static void uart6_rx_irq(void) { + uart_rx_irq(SCIFRXI6_IRQn, 6); +} +static void uart7_rx_irq(void) { + uart_rx_irq(SCIFRXI7_IRQn, 7); +} void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { irq_handler = handler; @@ -369,42 +502,79 @@ static void serial_flow_irq_set(serial_t *obj, uint32_t enable) { * READ/WRITE ******************************************************************************/ int serial_getc(serial_t *obj) { - uint16_t dummy_read; + uint16_t err_read; int data; + int was_masked; + was_masked = __disable_irq(); if (obj->uart->SCFSR & 0x93) { - dummy_read = obj->uart->SCFSR; - obj->uart->SCFSR = (dummy_read & ~0x93); + err_read = obj->uart->SCFSR; + obj->uart->SCFSR = (err_read & ~0x93); } obj->uart->SCSCR |= 0x0040; // Set RIE + if (!was_masked) { + __enable_irq(); + } + + if (obj->uart->SCLSR & 0x0001) { + obj->uart->SCLSR = 0u; // ORER clear + } + while (!serial_readable(obj)); data = obj->uart->SCFRDR & 0xff; - obj->uart->SCFSR &= 0xfffc; // Clear DR,RDF + + was_masked = __disable_irq(); + err_read = obj->uart->SCFSR; + obj->uart->SCFSR = (err_read & 0xfffD); // Clear RDF + if (!was_masked) { + __enable_irq(); + } + + if (err_read & 0x80) { + data = -1; //err + } return data; } void serial_putc(serial_t *obj, int c) { uint16_t dummy_read; - + int was_masked; + + was_masked = __disable_irq(); obj->uart->SCSCR |= 0x0080; // Set TIE + if (!was_masked) { + __enable_irq(); + } while (!serial_writable(obj)); obj->uart->SCFTDR = c; + was_masked = __disable_irq(); dummy_read = obj->uart->SCFSR; obj->uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE + if (!was_masked) { + __enable_irq(); + } uart_data[obj->index].count++; } int serial_readable(serial_t *obj) { - return obj->uart->SCFSR & 0x02; // RDF + return ((obj->uart->SCFSR & 0x02) != 0); // RDF } int serial_writable(serial_t *obj) { - return obj->uart->SCFSR & 0x20; // TDFE + return ((obj->uart->SCFSR & 0x20) != 0); // TDFE } void serial_clear(serial_t *obj) { - obj->uart->SCFCR = 0x06; - obj->uart->SCFCR = 0x06; + int was_masked; + was_masked = __disable_irq(); + + obj->uart->SCFCR |= 0x06; // TFRST = 1, RFRST = 1 + obj->uart->SCFCR &= ~0x06; // TFRST = 0, RFRST = 0 + obj->uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0 + + if (!was_masked) { + __enable_irq(); + } } void serial_pinout_tx(PinName tx) { @@ -412,12 +582,49 @@ void serial_pinout_tx(PinName tx) { } void serial_break_set(serial_t *obj) { + int was_masked; + was_masked = __disable_irq(); + // TxD Output(L) + obj->uart->SCSPTR &= ~0x0001u; // SPB2DT = 0 + obj->uart->SCSCR &= ~0x0020u; // TE = 0 (Output disable) + if (!was_masked) { + __enable_irq(); + } } void serial_break_clear(serial_t *obj) { + int was_masked; + was_masked = __disable_irq(); + obj->uart->SCSCR |= 0x0020u; // TE = 1 (Output enable) + obj->uart->SCSPTR |= 0x0001u; // SPB2DT = 1 + if (!was_masked) { + __enable_irq(); + } } void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { + // determine the UART to use + int was_masked; + serial_flow_irq_set(obj, 0); + + if (type == FlowControlRTSCTS) { + was_masked = __disable_irq(); + obj->uart->SCFCR = 0x0008u; // CTS/RTS enable + if (!was_masked) { + __enable_irq(); + } + pinmap_pinout(rxflow, PinMap_UART_RTS); + pinmap_pinout(txflow, PinMap_UART_CTS); + } else { + was_masked = __disable_irq(); + obj->uart->SCFCR = 0x0000u; // CTS/RTS diable + if (!was_masked) { + __enable_irq(); + } + } } + + + From 44b4fb4b41f107fa71a4ff601af0ff9fdb07a33b Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Thu, 29 Jan 2015 16:38:48 +0900 Subject: [PATCH 09/25] Modify some processing of AnalgIn. Modifies are as below. - Change the A/D conversion time to run fast. - Change the macro value of ANALOGIN_MEDIAN_FILTER 1 -> 0 --- .../TARGET_RZ_A1H/analogin_api.c | 61 +++++++++---------- 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c index cafb21ed16..eebc3c0507 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c @@ -22,20 +22,18 @@ #include "adc_iodefine.h" #include "cpg_iodefine.h" -#define ANALOGIN_MEDIAN_FILTER 1 - -#define ADC_12BIT_RANGE 0xFFF +#define ANALOGIN_MEDIAN_FILTER 0 static const PinMap PinMap_ADC[] = { {P1_8, AN0, 1}, {P1_9, AN1, 1}, {P1_10, AN2, 1}, {P1_11, AN3, 1}, - {P1_12, AN3, 1}, + {P1_12, AN3, 1}, {P1_13, AN5, 1}, - {P1_14, AN5, 1}, + {P1_14, AN5, 1}, {P1_15, AN7, 1}, - {NC, NC, 0} + {NC, NC, 0} }; static volatile uint16_t *ADCDR[] = { @@ -49,45 +47,41 @@ static volatile uint16_t *ADCDR[] = { &ADCADDRH, }; -#define ADC_RANGE ADC_12BIT_RANGE - void analogin_init(analogin_t *obj, PinName pin) { obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); MBED_ASSERT(obj->adc != (ADCName)NC); - + CPGSTBCR3 &= ~(1 << 1); CPGSTBCR6 &= ~(1 << 7); - // 000_0 000_1 00_00 0_xxx - // 15: ADFlag 14: IntEn 13: start, [12:9] Triger..0 - // [8:6] CLK 100 :: 12-bit 1054tclk - // [5:3] scanmode 000 :: single mode - // [2:0] channel select - ADCADCSR = 0x01c0 ; - - for (int i = 0; i< sizeof(PinMap_ADC)/sizeof(PinMap); i++) { - pinmap_pinout(PinMap_ADC[i].pin, PinMap_ADC); - } + // 15: ADF 14: ADIE 13: ADST, [12:9] TRGS..0 + // [8:6] CKS 000 :: 256tclk + // [5:3] MDS 000 :: single mode + // [2:0] CH 000 :: AN0 + ADCADCSR = 0x0000; - //pinmap_pinout(pin, PinMap_ADC); + pinmap_pinout(pin, PinMap_ADC); } static inline uint32_t adc_read(analogin_t *obj) { + volatile uint16_t data; + // Select the appropriate channel and start conversion - ADCADCSR &= 0xfff8; - ADCADCSR |= (1 << 13 | (obj->adc&0x7)); - - // Repeatedly get the sample data until DONE bit -#define nothing - while ((ADCADCSR & (1 << 15)) == 0 || (ADCADCSR & (1<<13)) != 0) nothing; - + ADCADCSR |= (1 << 13 | (obj->adc & 0x7)); + + // Wait end of conversion + do { + data = ADCADCSR; + } while (((data & (1 << 15)) == 0) || ((data & (1 << 13)) != 0)); + // clear flag ADCADCSR &= ~(1 << 15); - - return ((*(ADCDR[obj->adc]))>>4) & ADC_RANGE; // 12 bit + + return ((*(ADCDR[obj->adc])) >> 4) & 0x0FFF; // 12 bits range } +#if ANALOGIN_MEDIAN_FILTER static inline void order(uint32_t *a, uint32_t *b) { if (*a > *b) { uint32_t t = *a; @@ -95,6 +89,7 @@ static inline void order(uint32_t *a, uint32_t *b) { *b = t; } } +#endif static inline uint32_t adc_read_u32(analogin_t *obj) { uint32_t value; @@ -114,12 +109,12 @@ static inline uint32_t adc_read_u32(analogin_t *obj) { uint16_t analogin_read_u16(analogin_t *obj) { uint32_t value = adc_read_u32(obj); - - return value; - //(value << 4) | ((value >> 8) & 0x000F); // 12 bit + + return (value << 4) | ((value >> 8) & 0x000F); // 12-bit to 16-bit conversion } float analogin_read(analogin_t *obj) { uint32_t value = adc_read_u32(obj); - return (float)value * (1.0f / (float)ADC_RANGE); + + return (float)value * (1.0f / (float)0x0FFF); // 12 bits range } From 88604ff8fefa235023e1d8dfd173f377d5024615 Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Thu, 29 Jan 2015 16:40:16 +0900 Subject: [PATCH 10/25] Add some processing of I2C driver Changes are as below - Add STOP condition omission processing of I2C Master - Add I2C Slave processing --- .../TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c | 395 +++++++++++------- .../TARGET_RENESAS/TARGET_RZ_A1H/objects.h | 1 + 2 files changed, 253 insertions(+), 143 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c index 7232396925..e9bbc3f69a 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c @@ -34,8 +34,9 @@ volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; /* RIICnCR2 */ #define CR2_ST (1 << 1) +#define CR2_RS (1 << 2) #define CR2_SP (1 << 3) -#define CR2_NACKF (1 << 4) +#define CR2_TRS (1 << 5) #define CR2_BBSY (1 << 7) /* RIICnMR3 */ @@ -43,7 +44,14 @@ volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; #define MR3_ACKWP (1 << 4) #define MR3_WAIT (1 << 6) +/* RIICnSER */ +#define SER_SAR0E (1 << 0) + +/* RIICnSR1 */ +#define SR1_AAS0 (1 << 0) + /* RIICnSR2 */ +#define SR2_START (1 << 2) #define SR2_STOP (1 << 3) #define SR2_NACKF (1 << 4) #define SR2_RDRF (1 << 5) @@ -67,35 +75,10 @@ static const PinMap PinMap_I2C_SCL[] = { }; -/* Clear the Transmit data Empty TDRE */ -static inline int i2c_addressed(i2c_t *obj) { - volatile int sar0 = (REG(SR1.UINT8[0])&1), - trs = (REG(CR2.UINT8[0])&0x20) >> 5; - return sar0 | (trs <<1); -} - static inline int i2c_status(i2c_t *obj) { return REG(SR2.UINT8[0]); } -static inline void i2c_clear_TDRE(i2c_t *obj) { - REG(SR2.UINT32) &= ~SR2_TDRE; -} - -static inline int i2c_wait_RDRF(i2c_t *obj) { - int timeout = 0; - - /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ - while (!(i2c_status(obj) & SR2_RDRF)) { - timeout ++; - if (timeout >= TIMEOUT_1S) { - return -1; - } - } - - return 0; -} - static void i2c_reg_reset(i2c_t *obj) { /* full reset */ REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off @@ -119,7 +102,20 @@ static void i2c_reg_reset(i2c_t *obj) { REG(CR1.UINT32) &= ~CR1_RST; // CR1.IICRST negate reset } -/* Wait until the Trans Data Empty (TDRE) is set */ +static inline int i2c_wait_RDRF(i2c_t *obj) { + int timeout = 0; + + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while (!(i2c_status(obj) & SR2_RDRF)) { + timeout ++; + if (timeout >= TIMEOUT_1S) { + return -1; + } + } + + return 0; +} + static int i2c_wait_TDRE(i2c_t *obj) { int timeout = 0; @@ -149,6 +145,20 @@ static int i2c_wait_TEND(i2c_t *obj) { } +static int i2c_wait_START(i2c_t *obj) { + int timeout = 0; + + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while (!(i2c_status(obj) & SR2_START)) { + timeout ++; + if (timeout >= TIMEOUT_1S) { + return -1; + } + } + + return 0; +} + static int i2c_wait_STOP(i2c_t *obj) { int timeout = 0; @@ -163,26 +173,42 @@ static int i2c_wait_STOP(i2c_t *obj) { return 0; } -static void i2c_set_NACKF_STOP(i2c_t *obj) { +static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) { /* SR2.NACKF = 0 */ REG(SR2.UINT32) &= ~SR2_NACKF; - /* SR2.STOP = 0 */ + /* SR2.STOP = 0 */ REG(SR2.UINT32) &= ~SR2_STOP; } -static void i2c_set_err_noslave(i2c_t *obj) { - i2c_stop(obj); - (void)i2c_wait_STOP(obj); - i2c_set_NACKF_STOP(obj); +static void i2c_set_MR3_NACK(i2c_t *obj) { + /* send a NOT ACK */ + REG(MR3.UINT32) |= MR3_ACKWP; + REG(MR3.UINT32) |= MR3_ACKBT; + REG(MR3.UINT32) &= ~MR3_ACKWP; +} + +static void i2c_set_MR3_ACK(i2c_t *obj) { + /* send a ACK */ + REG(MR3.UINT32) |= MR3_ACKWP; + REG(MR3.UINT32) &= ~MR3_ACKBT; + REG(MR3.UINT32) &= ~MR3_ACKWP; } static inline void i2c_power_enable(i2c_t *obj) { volatile uint8_t dummy; switch ((int)obj->i2c) { - case I2C_0: CPGSTBCR9 &= ~(0x80); break; - case I2C_1: CPGSTBCR9 &= ~(0x40); break; - case I2C_2: CPGSTBCR9 &= ~(0x20); break; - case I2C_3: CPGSTBCR9 &= ~(0x10); break; + case I2C_0: + CPGSTBCR9 &= ~(0x80); + break; + case I2C_1: + CPGSTBCR9 &= ~(0x40); + break; + case I2C_2: + CPGSTBCR9 &= ~(0x20); + break; + case I2C_3: + CPGSTBCR9 &= ~(0x10); + break; } dummy = CPGSTBCR9; } @@ -202,6 +228,8 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) { pinmap_pinout(sda, PinMap_I2C_SDA); pinmap_pinout(scl, PinMap_I2C_SCL); + + obj->last_stop_flag = 1; } inline int i2c_start(i2c_t *obj) { @@ -210,10 +238,7 @@ inline int i2c_start(i2c_t *obj) { while (REG(CR2.UINT32) & CR2_BBSY) { timeout ++; if (timeout >= obj->bbsy_wait_cnt) { - i2c_reg_reset(obj); - /* Start Condition */ - REG(CR2.UINT8[0]) |= CR2_ST; - return 0; + break; } } /* Start Condition */ @@ -222,8 +247,17 @@ inline int i2c_start(i2c_t *obj) { return 0; } +inline int i2c_restart(i2c_t *obj) { + /* SR2.START = 0 */ + REG(SR2.UINT32) &= ~SR2_START; + /* ReStart condition */ + REG(CR2.UINT32) |= CR2_RS; + + return 0; +} + inline int i2c_stop(i2c_t *obj) { - /* SR2.STOP = 0 */ + /* SR2.STOP = 0 */ REG(SR2.UINT32) &= ~SR2_STOP; /* Stop condition */ REG(CR2.UINT32) |= CR2_SP; @@ -231,6 +265,19 @@ inline int i2c_stop(i2c_t *obj) { return 0; } +static void i2c_set_err_noslave(i2c_t *obj, int stop) { + if (stop) { + (void)i2c_stop(obj); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + } else { + (void)i2c_restart(obj); + (void)i2c_wait_START(obj); + /* SR2.START = 0 */ + REG(SR2.UINT32) &= ~SR2_START; + } +} + static inline int i2c_do_write(i2c_t *obj, int value) { int timeout = 0; @@ -259,14 +306,14 @@ static inline int i2c_do_write(i2c_t *obj, int value) { static inline int i2c_read_address_write(i2c_t *obj, int value) { int status; + status = i2c_wait_TDRE(obj); if (status == 0) { /* write the data */ REG(DRT.UINT32) = value; - return 0; - } else { - return status; } + + return status; } @@ -276,15 +323,9 @@ static inline int i2c_do_read(i2c_t *obj, int last) { /* Set MR3 WAIT bit is 1 */; REG(MR3.UINT32) |= MR3_WAIT; } else if (last == 1) { - /* send a NOT ACK */ - REG(MR3.UINT32) |= MR3_ACKWP; - REG(MR3.UINT32) |= MR3_ACKBT; - REG(MR3.UINT32) &= ~MR3_ACKWP; + i2c_set_MR3_NACK(obj); } else { - /* send a ACK */ - REG(MR3.UINT32) |= MR3_ACKWP; - REG(MR3.UINT32) &= ~MR3_ACKBT; - REG(MR3.UINT32) &= ~MR3_ACKWP; + i2c_set_MR3_ACK(obj); } /* return the data */ @@ -383,27 +424,45 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int value; volatile uint32_t work_reg = 0; - status = i2c_start(obj); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_BUS_BUSY; + if(length <= 0) { + return 0; } + i2c_set_MR3_ACK(obj); + /* There is a STOP condition for last processing */ + if (obj->last_stop_flag != 0) { + status = i2c_start(obj); + if (status != 0) { + i2c_set_err_noslave(obj, stop); + return I2C_ERROR_BUS_BUSY; + } + } + obj->last_stop_flag = stop; /* Send Slave address */ status = i2c_read_address_write(obj, (address | 0x01)); if (status != 0) { - i2c_set_err_noslave(obj); + i2c_set_err_noslave(obj, stop); return I2C_ERROR_NO_SLAVE; } - /* wati RDRF */ + /* wait RDRF */ status = i2c_wait_RDRF(obj); /* check ACK/NACK */ - if ((status != 0) || (REG(SR2.UINT32) & CR2_NACKF == 1)) { + if ((status != 0) || (REG(SR2.UINT32) & SR2_NACKF == 1)) { /* Slave sends NACK */ - i2c_stop(obj); - /* dummy read */ - value = REG(DRR.UINT32); - (void)i2c_wait_STOP(obj); - i2c_set_NACKF_STOP(obj); + /* If not repeated start, send stop. */ + if (stop) { + i2c_stop(obj); + /* dummy read */ + value = REG(DRR.UINT32); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + } else { + (void)i2c_restart(obj); + /* dummy read */ + value = REG(DRR.UINT32); + (void)i2c_wait_START(obj); + /* SR2.START = 0 */ + REG(SR2.UINT32) &= ~SR2_START; + } return I2C_ERROR_NO_SLAVE; } /* Read in all except last byte */ @@ -414,7 +473,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { /* wait for it to arrive */ status = i2c_wait_RDRF(obj); if (status != 0) { - i2c_set_err_noslave(obj); + i2c_set_err_noslave(obj, stop); return I2C_ERROR_NO_SLAVE; } /* Recieve the data */ @@ -428,60 +487,55 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { data[count] = (char)value; } } else if (length == 2) { - /* Set MR3 WATI bit is 1 */; + /* Set MR3 WATI bit is 1 */ REG(MR3.UINT32) |= MR3_WAIT; /* dummy read */ value = REG(DRR.UINT32); /* wait for it to arrive */ status = i2c_wait_RDRF(obj); if (status != 0) { - i2c_set_err_noslave(obj); + i2c_set_err_noslave(obj, stop); return I2C_ERROR_NO_SLAVE; } - /* send a NOT ACK */ - REG(MR3.UINT32) |= MR3_ACKWP; - REG(MR3.UINT32) |= MR3_ACKBT; - REG(MR3.UINT32) &= ~MR3_ACKWP; + i2c_set_MR3_NACK(obj); data[count] = (char)REG(DRR.UINT32); count++; - } else if (length == 1) { + } else { + /* length == 1 */ /* Set MR3 WATI bit is 1 */; REG(MR3.UINT32) |= MR3_WAIT; - /* send a NOT ACK */ - REG(MR3.UINT32) |= MR3_ACKWP; - REG(MR3.UINT32) |= MR3_ACKBT; - REG(MR3.UINT32) &= ~MR3_ACKWP; + i2c_set_MR3_NACK(obj); /* dummy read */ value = REG(DRR.UINT32); - } else { - return I2C_ERROR_NO_SLAVE; } /* wait for it to arrive */ status = i2c_wait_RDRF(obj); if (status != 0) { - i2c_set_err_noslave(obj); + i2c_set_err_noslave(obj, stop); return I2C_ERROR_NO_SLAVE; } + /* If not repeated start, send stop. */ if (stop) { - /* RIICnSR2.STOP = 0 */ - REG(SR2.UINT32) &= ~SR2_STOP; - /* RIICnCR2.SP = 1 */ - REG(CR2.UINT32) |= CR2_SP; + (void)i2c_stop(obj); /* RIICnDRR read */ value = REG(DRR.UINT32) & 0xFF; data[count] = (char)value; /* RIICnMR3.WAIT = 0 */ REG(MR3.UINT32) &= ~MR3_WAIT; (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); } else { + (void)i2c_restart(obj); /* RIICnDRR read */ value = REG(DRR.UINT32) & 0xFF; data[count] = (char)value; /* RIICnMR3.WAIT = 0 */ REG(MR3.UINT32) &= ~MR3_WAIT; + (void)i2c_wait_START(obj); + /* SR2.START = 0 */ + REG(SR2.UINT32) &= ~SR2_START; } - i2c_set_NACKF_STOP(obj); return length; } @@ -490,37 +544,51 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { int cnt; int status; - status = i2c_start(obj); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_BUS_BUSY; + if(length <= 0) { + return 0; } + + /* There is a STOP condition for last processing */ + if (obj->last_stop_flag != 0) { + status = i2c_start(obj); + if (status != 0) { + i2c_set_err_noslave(obj, stop); + return I2C_ERROR_BUS_BUSY; + } + } + obj->last_stop_flag = stop; /* Send Slave address */ status = i2c_do_write(obj, address); if (status != 0) { - i2c_set_err_noslave(obj); + i2c_set_err_noslave(obj, stop); return I2C_ERROR_NO_SLAVE; } /* Send Write data */ for (cnt=0; cnt> 4; + switch(status) { - case 0x3: retval = 1; break; - case 0x2: retval = 2; break; - case 0x1: retval = 3; break; - default : retval = 1; break; + case 0x01: + /* the master is writing to this slave */ + retval = 3; + break; + case 0x02: + /* the master is writing to all slave */ + retval = 2; + break; + case 0x03: + /* the master has requested a read from this slave */ + retval = 1; + break; + default : + /* no data */ + retval = 0; + break; } - return(retval); + return retval; } int i2c_slave_read(i2c_t *obj, char *data, int length) { - int count = 0; - int status; + int timeout = 0; + int count; + int break_flg = 0; - volatile int dummy = REG(DRR.UINT32) ; - - do { - i2c_wait_RDRF(obj); - status = i2c_status(obj); - if(!(status & 0x10)) { - data[count] = REG(DRR.UINT32) & 0xFF; - } - count++; - } while ( !(status & 0x10) && (count < length) ); - - if(status & 0x10) { - i2c_stop(obj); - (void)i2c_wait_STOP(obj); - i2c_set_NACKF_STOP(obj); + if(length <= 0) { + return 0; } + for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) { + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while ((i2c_status(obj) & SR2_STOP) || (!(i2c_status(obj) & SR2_RDRF))) { + /* RIICnSR2.STOP = 1 or RIICnSR2.RDRF = 0 */ + if (i2c_status(obj) & SR2_STOP) { + /* RIICnSR2.STOP = 1 */ + break_flg = 1; + break; + } + timeout ++; + if (timeout >= TIMEOUT_1S) { + return -1; + } + } + if (break_flg == 0) { + if (count == 0) { + /* dummy read */ + (void)REG(DRR.UINT32); + } else { + data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF); + } + } + } + if (break_flg == 0) { + (void)i2c_wait_STOP(obj); + } else { + if (i2c_status(obj) & SR2_RDRF) { + if (count <= 1) { + /* fail safe */ + /* dummy read */ + (void)REG(DRR.UINT32); + } else { + data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF); + } + } + } + /* SR2.STOP = 0 */ + REG(SR2.UINT32) &= ~SR2_STOP; - //i2c_clear_TDRE(obj); - - return count; + return (count - 1); } int i2c_slave_write(i2c_t *obj, const char *data, int length) { int count = 0; - int status; + int status = 0; if(length <= 0) { - return(0); + return 0; } - do { + while ((count < length) && (status == 0)) { status = i2c_do_write(obj, data[count]); count++; - } while ((count < length) && !(status & 0x10)); - - if (!(status & 0x10)) { - i2c_stop(obj); - (void)i2c_wait_STOP(obj); - i2c_set_NACKF_STOP(obj); } + if (status == 0) { + /* Wait send end */ + status = i2c_wait_TEND(obj); + if (status != 0) { + i2c_set_err_noslave(obj, 1); + return 0; + } + } + /* dummy read */ + (void)REG(DRR.UINT32); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); - i2c_clear_TDRE(obj); - - return(count); + return count; } void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { - REG(SAR0.UINT32) = address & 0xfe; + REG(SAR0.UINT32) = address & 0xfffffffe; } diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h index bb7d45b50d..c1f7c142e6 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h @@ -35,6 +35,7 @@ struct i2c_s { uint8_t width_low; uint8_t width_hi; int bbsy_wait_cnt; + int last_stop_flag; }; struct spi_s { From 4d371d2c9ed99054c1418d23a9a585d36a523d1f Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Thu, 29 Jan 2015 16:41:08 +0900 Subject: [PATCH 11/25] Add include mbed_assert.h. --- .../mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h index c87a2aec1b..8bf5b45cba 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h @@ -16,6 +16,8 @@ #ifndef MBED_GPIO_OBJECT_H #define MBED_GPIO_OBJECT_H +#include "mbed_assert.h" + #ifdef __cplusplus extern "C" { #endif From 8013d158763c35807b893f24a1c532cb13b472fb Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Thu, 29 Jan 2015 16:41:35 +0900 Subject: [PATCH 12/25] Modify ticker driver to make consistent with Pull Reqest#839 and #864. timestamp_t type had been changed from uint64_t to uint32_t by Reqest#839 and #864. --- .../TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c | 51 ++++++++++++++++--- 1 file changed, 45 insertions(+), 6 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c index 03611d2451..c7eed18125 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c @@ -61,9 +61,12 @@ void us_ticker_init(void) { GIC_EnableIRQ(US_TICKER_TIMER_IRQn); } -uint32_t us_ticker_read() { +uint64_t us_ticker_read64() { uint32_t val; - uint64_t val64; + volatile uint64_t val64; + int check_irq_masked; + + check_irq_masked = __disable_irq(); if (!us_ticker_inited) us_ticker_init(); @@ -77,14 +80,50 @@ uint32_t us_ticker_read() { val64 = ((uint64_t)wrap_arround << 32) + val; /* clock to us */ - val = (uint32_t)(val64 / count_clock); - return val; + val64 = val64 / count_clock; + + if (!check_irq_masked) { + __enable_irq(); + } + + return val64; +} + +uint32_t us_ticker_read() { + return (uint32_t)us_ticker_read64(); } void us_ticker_set_interrupt(timestamp_t timestamp) { // set match value - timestamp = (timestamp_t)(timestamp * count_clock); - OSTM1CMP = (uint32_t)(timestamp & 0xffffffff); + volatile uint64_t set_cmp_val = 0; + uint64_t timestamp_tmp; + int64_t timestamp_req; + int64_t timestamp_comp; + uint64_t timestamp_now = us_ticker_read64(); + + /* calc compare mach timestamp */ + set_cmp_val = (timestamp_now & 0xFFFFFFFF00000000) + timestamp; + + timestamp_tmp = (uint64_t)timestamp; + timestamp_req = (int64_t)timestamp_tmp; + + timestamp_tmp = (uint64_t)(timestamp_now & 0x00000000FFFFFFFF); + timestamp_comp = (int64_t)timestamp_tmp; + + if (timestamp_req <= timestamp_comp + 1) { + if (((timestamp_req - timestamp_comp) <= 1) && ((timestamp_req - timestamp_comp) >= -10)) { + /* This event was in the past */ + us_ticker_irq_handler(); + return; + } else { + /* This event is wrap arround */ + set_cmp_val += 0x100000000; + } + } + + /* calc compare mach timestamp */ + set_cmp_val = set_cmp_val * count_clock; + OSTM1CMP = (uint32_t)(set_cmp_val & 0xffffffff); GIC_EnableIRQ(US_TICKER_TIMER_IRQn); } From 60f875ac8b30ea16efcdce920981d2aa65fb0710 Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Thu, 29 Jan 2015 16:41:56 +0900 Subject: [PATCH 13/25] Modify gpio api to make consistent with Merge branch 'PrzemekWirkus-pinology'. --- .../mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c index 14831bd688..4061325fd0 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c @@ -25,9 +25,9 @@ uint32_t gpio_set(PinName pin) { void gpio_init(gpio_t *obj, PinName pin) { int group ; + obj->pin = pin; if(pin == NC) return; - obj->pin = pin; obj->mask = gpio_set(pin); group = PINGROUP(pin); From 9cbe36213c2ae31ae8fdd90850dc8161f43798f7 Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Fri, 30 Jan 2015 11:17:22 +0900 Subject: [PATCH 14/25] Modify A/D convert time. --- .../hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c index eebc3c0507..80ebd767ea 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c @@ -54,11 +54,11 @@ void analogin_init(analogin_t *obj, PinName pin) { CPGSTBCR3 &= ~(1 << 1); CPGSTBCR6 &= ~(1 << 7); - // 15: ADF 14: ADIE 13: ADST, [12:9] TRGS..0 - // [8:6] CKS 000 :: 256tclk - // [5:3] MDS 000 :: single mode - // [2:0] CH 000 :: AN0 - ADCADCSR = 0x0000; + // 15: ADF 14: ADIE 13: ADST, [12:9] TRGS..0 + // [8:6] CKS 010 :: 340tclk + // [5:3] MDS 000 :: single mode + // [2:0] CH 000 :: AN0 + ADCADCSR = 0x0080; pinmap_pinout(pin, PinMap_ADC); } From f7b083a0b9e7b38fc07dda65eec2fb3805b97702 Mon Sep 17 00:00:00 2001 From: mazgch Date: Sun, 1 Feb 2015 16:38:06 +0100 Subject: [PATCH 15/25] added new C029 target with STM32F439ZI --- .../TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.s | 445 + .../TOOLCHAIN_ARM_MICRO/stm32f439xx.sct | 48 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32f439xx.s | 467 + .../TOOLCHAIN_ARM_STD/stm32f439xx.sct | 48 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32F439ZI.ld | 154 + .../TOOLCHAIN_GCC_ARM/startup_stm32f439xx.s | 570 ++ .../TOOLCHAIN_IAR/startup_stm32f439xx.s | 698 ++ .../TOOLCHAIN_IAR/stm32f439xx_flash.icf | 34 + .../TARGET_STM32F4/TARGET_UBLOX_C029/cmsis.h | 38 + .../TARGET_UBLOX_C029/cmsis_nvic.c | 55 + .../TARGET_UBLOX_C029/cmsis_nvic.h | 55 + .../TARGET_UBLOX_C029/hal_tick.c | 124 + .../TARGET_UBLOX_C029/hal_tick.h | 60 + .../TARGET_UBLOX_C029/stm32f439xx.h | 9102 +++++++++++++++++ .../TARGET_UBLOX_C029/stm32f4xx.h | 222 + .../TARGET_UBLOX_C029/system_stm32f4xx.c | 706 ++ .../TARGET_UBLOX_C029/system_stm32f4xx.h | 124 + .../TARGET_UBLOX_C029/PeripheralNames.h | 85 + .../TARGET_UBLOX_C029/PeripheralPins.c | 165 + .../TARGET_UBLOX_C029/PinNames.h | 202 + .../TARGET_UBLOX_C029/PortNames.h | 51 + .../TARGET_STM32F4/TARGET_UBLOX_C029/device.h | 70 + .../TARGET_UBLOX_C029/objects.h | 110 + workspace_tools/targets.py | 12 +- 26 files changed, 13756 insertions(+), 1 deletion(-) create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/stm32f439xx.sct create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/startup_stm32f439xx.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/stm32f439xx.sct create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/STM32F439ZI.ld create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_IAR/startup_stm32f439xx.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_IAR/stm32f439xx_flash.icf create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis_nvic.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis_nvic.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/hal_tick.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/hal_tick.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f439xx.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f4xx.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.h create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralPins.c create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PortNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/device.h create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/objects.h diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.s new file mode 100644 index 0000000000..0a13ca0c30 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.s @@ -0,0 +1,445 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f439xx.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F439x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20030000 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYPTO + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/stm32f439xx.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/stm32f439xx.sct new file mode 100644 index 0000000000..68c246a768 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/stm32f439xx.sct @@ -0,0 +1,48 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F439ZI: 2048 KB FLASH (0x200000) + 256 KB SRAM (0x30000 + 0x10000) +LR_IROM1 0x08000000 0x200000 { ; load region size_region + + ER_IROM1 0x08000000 0x200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 107 vectors = 428 bytes (0x1AC) to be used + ; should match ER_IROM1::RESET/4 and cmsis_nvic.h::NVIC_NUM_VECTORS + RW_IRAM1 (0x20000000 + (107*4)) (0x30000 - (107*4)) { ; RW data + .ANY (+RW +ZI) + } + RW_IRAM2 (0x10000000) 0x10000 { + .ANY (+RW +ZI) + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/sys.cpp new file mode 100644 index 0000000000..bb665909b9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/startup_stm32f439xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/startup_stm32f439xx.s new file mode 100644 index 0000000000..eafa641afc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/startup_stm32f439xx.s @@ -0,0 +1,467 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f439xx.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F439x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYPTO + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/stm32f439xx.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/stm32f439xx.sct new file mode 100644 index 0000000000..31db112dbe --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/stm32f439xx.sct @@ -0,0 +1,48 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F411RE: 512 KB FLASH (0x80000) + 256 KB SRAM (0x30000 + 0x10000) +LR_IROM1 0x08000000 0x80000 { ; load region size_region + + ER_IROM1 0x08000000 0x80000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM + RW_IRAM1 (0x20000000+0x1AC) (0x30000-0x1AC) { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM1 (0x10000000) (0x10000) { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..bb665909b9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/STM32F439ZI.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/STM32F439ZI.ld new file mode 100644 index 0000000000..744a6ac357 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/STM32F439ZI.ld @@ -0,0 +1,154 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K + RAM (rwx) : ORIGIN = 0x200001AC, LENGTH = 192k - 0x1AC + RAM2 (rwx) : ORIGIN = 0x10000000, LENGTH = 64k +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.s new file mode 100644 index 0000000000..d87c5c9d7e --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.s @@ -0,0 +1,570 @@ +/** + ****************************************************************************** + * @file startup_stm32f439xx.s + * @author MCD Application Team + * @version V2.1.0 + * @date 19-June-2014 + * @brief STM32F439xx Devices vector table for Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + + + + + \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_IAR/startup_stm32f439xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_IAR/startup_stm32f439xx.s new file mode 100644 index 0000000000..4df6515542 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_IAR/startup_stm32f439xx.s @@ -0,0 +1,698 @@ +;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f439xx.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F439xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK CRYP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYP_IRQHandler + B CRYP_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_IAR/stm32f439xx_flash.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_IAR/stm32f439xx_flash.icf new file mode 100644 index 0000000000..64aaf0e0bb --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_IAR/stm32f439xx_flash.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF; +define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis.h new file mode 100644 index 0000000000..f0c2b2a907 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis_nvic.c new file mode 100644 index 0000000000..2da63fc9af --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis_nvic.c @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t *)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis_nvic.h new file mode 100644 index 0000000000..cf9d4e711b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis_nvic.h @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F439ZI +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 91 vectors = 364 bytes from 0x40 to 0x1AB +// Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM +#define NVIC_NUM_VECTORS 107 +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/hal_tick.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/hal_tick.c new file mode 100644 index 0000000000..7a7eeaeb44 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/hal_tick.c @@ -0,0 +1,124 @@ +/** + ****************************************************************************** + * @file hal_tick.c + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "hal_tick.h" + +TIM_HandleTypeDef TimMasterHandle; +uint32_t PreviousVal = 0; + +void us_ticker_irq_handler(void); + +void timer_irq_handler(void) { + // Channel 1 for mbed timeout + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); + us_ticker_irq_handler(); + } + + // Channel 2 for HAL tick + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2); + uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle); + if ((val - PreviousVal) >= HAL_TICK_DELAY) { + // Increment HAL variable + HAL_IncTick(); + // Prepare next interrupt + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY); + PreviousVal = val; +#if 0 // For DEBUG only + HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6); +#endif + } + } +} + +// Reconfigure the HAL tick using a standard timer instead of systick. +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + // Enable timer clock + TIM_MST_RCC; + + // Reset timer + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; + + // Configure time base + TimMasterHandle.Instance = TIM_MST; + TimMasterHandle.Init.Period = 0xFFFFFFFF; + if ( SystemCoreClock == 16000000 ) { + TimMasterHandle.Init.Prescaler = (uint32_t)( SystemCoreClock / 1000000) - 1; // 1 µs tick + } else { + TimMasterHandle.Init.Prescaler = (uint32_t)( SystemCoreClock / 2 / 1000000) - 1; // 1 µs tick + } + TimMasterHandle.Init.ClockDivision = 0; + TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + TimMasterHandle.Init.RepetitionCounter = 0; + HAL_TIM_OC_Init(&TimMasterHandle); + + NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler); + NVIC_EnableIRQ(TIM_MST_IRQ); + + // Channel 1 for mbed timeout + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1); + + // Channel 2 for HAL tick + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); + PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); + +#if 0 // For DEBUG only + __GPIOB_CLK_ENABLE(); + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FAST; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/hal_tick.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/hal_tick.h new file mode 100644 index 0000000000..2e6f01b8a6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/hal_tick.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM5 +#define TIM_MST_IRQ TIM5_IRQn +#define TIM_MST_RCC __TIM5_CLK_ENABLE() + +#define TIM_MST_RESET_ON __TIM5_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f439xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f439xx.h new file mode 100644 index 0000000000..41b6e65e07 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f439xx.h @@ -0,0 +1,9102 @@ +/** + ****************************************************************************** + * @file stm32f439xx.h + * @author MCD Application Team + * @version V2.1.0 + * @date 19-June-2014 + * @brief CMSIS STM32F439xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f439xx + * @{ + */ + +#ifndef __STM32F439xx_H +#define __STM32F439xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; + uint32_t RESERVED9[565]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ +} FLASH_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ + uint32_t RESERVED1; /*!< Reserved, 0x78 */ + uint32_t RESERVED2; /*!< Reserved, 0x7C */ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED3; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FMC_Bank2_3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ + __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ + __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ + __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ + __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ +} FMC_Bank4_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5_6 + */ + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ + __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ + __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ + __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Crypto Processor + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ + __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ + __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ + __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ + __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ + __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ + __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ + __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ + __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ + __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ + __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ + __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ + __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ + __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ + __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ + __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ + __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ +} CRYP_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ + +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + + +/** + * @brief __USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /* Reserved 030h*/ + __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ + __IO uint32_t CID; /* User ID Register 03Ch*/ + uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/ + __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ + __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */ +} +USB_OTG_GlobalTypeDef; + + +/** + * @brief __device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /* dev Configuration Register 800h*/ + __IO uint32_t DCTL; /* dev Control Register 804h*/ + __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ + uint32_t Reserved0C; /* Reserved 80Ch*/ + __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ + __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ + __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ + __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ + uint32_t Reserved20; /* Reserved 820h*/ + uint32_t Reserved9; /* Reserved 824h*/ + __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ + __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ + __IO uint32_t DTHRCTL; /* dev thr 830h*/ + __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ + __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ + __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ + uint32_t Reserved40; /* dedicated EP mask 840h*/ + __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ + uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ + __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ +} +USB_OTG_DeviceTypeDef; + + +/** + * @brief __IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ + __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ + __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ + __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ + uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ +} +USB_OTG_INEndpointTypeDef; + + +/** + * @brief __OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ + __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ + __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ + uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ +} +USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief __Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /* Host Configuration Register 400h*/ + __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /* Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ +} +USB_OTG_HostTypeDef; + +/** + * @brief __Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; + __IO uint32_t HCSPLT; + __IO uint32_t HCINT; + __IO uint32_t HCINTMSK; + __IO uint32_t HCTSIZ; + __IO uint32_t HCDMA; + uint32_t Reserved[2]; +} +USB_OTG_HostChannelTypeDef; +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 2 MB) base address in the alias region */ +#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ +#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ +#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ +#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ +#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ +#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */ +#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ +#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */ +#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000) +#define SPI6_BASE (APB2PERIPH_BASE + 0x5400) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) +#define LTDC_BASE (APB2PERIPH_BASE + 0x6800) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) +#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400) +#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) +#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000) + +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) +#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) +#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) +#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) + +/*!< FMC Bankx registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) +#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060) +#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t )0xE0042000) + +/*!< USB registers base address */ +#define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000) +#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000) + +#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000) +#define USB_OTG_DEVICE_BASE ((uint32_t )0x800) +#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900) +#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00) +#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20) +#define USB_OTG_HOST_BASE ((uint32_t )0x400) +#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440) +#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500) +#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20) +#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00) +#define USB_OTG_FIFO_BASE ((uint32_t )0x1000) +#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE) +#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE) +#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint32_t)0x00000001) /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx + * @{ + */ + +#ifndef __STM32F4xx_H +#define __STM32F4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ + !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ + !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) + /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ + /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ + /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ + /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ + /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */ + /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */ + /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, + STM32F439NI, STM32F429IG and STM32F429II Devices */ +#define STM32F439xx /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, + STM32F439NI, STM32F439IG and STM32F439II Devices */ + /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ + /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ + /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ +#define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V2.1.0 + */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ + |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\ + |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\ + |(__STM32F4xx_CMSIS_DEVICE_VERSION)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F405xx) + #include "stm32f405xx.h" +#elif defined(STM32F415xx) + #include "stm32f415xx.h" +#elif defined(STM32F407xx) + #include "stm32f407xx.h" +#elif defined(STM32F417xx) + #include "stm32f417xx.h" +#elif defined(STM32F427xx) + #include "stm32f427xx.h" +#elif defined(STM32F437xx) + #include "stm32f437xx.h" +#elif defined(STM32F429xx) + #include "stm32f429xx.h" +#elif defined(STM32F439xx) + #include "stm32f439xx.h" +#elif defined(STM32F401xC) + #include "stm32f401xc.h" +#elif defined(STM32F401xE) + #include "stm32f401xe.h" +#elif defined(STM32F411xE) + #include "stm32f411xe.h" +#else + #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macro + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f4xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F4xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c new file mode 100644 index 0000000000..efb6464a73 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c @@ -0,0 +1,706 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @version V2.1.0 + * @date 19-June-2014 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI + * | (external 8 MHz clock) | (internal 16 MHz) + * | 2- PLL_HSE_XTAL | + * | (external 8 MHz xtal) | + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 100 | 100 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 100 | 100 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 50 | 50 + *----------------------------------------------------------------------------- + * APB2CLK (MHz) | 100 | 100 + *----------------------------------------------------------------------------- + * USB capable (48 MHz precise clock) | NO | NO + *----------------------------------------------------------------------------- + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" +#include "hal_tick.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted + on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) + #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ +#define USE_PLL_HSE_EXTC (1) /* Use external clock */ +#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif + +uint8_t SetSysClock_PLL_HSI(void); + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + + /* Configure the Cube driver */ + SystemCoreClock = 16000000; // At this stage the HSI is used as system clock + HAL_Init(); + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings */ + SetSysClock(); + + /* Reset the timer to avoid issues after the RAM initialization */ + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration ------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + + /* Configure and enable SDRAM bank1 */ + FMC_Bank5_6->SDCR[0] = 0x000019E0; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +} +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + /* 1- Try to start with HSE and external clock */ +#if USE_PLL_HSE_EXTC != 0 + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { + /* 2- If fail try to start with HSE and external xtal */ + #if USE_PLL_HSE_XTAL != 0 + if (SetSysClock_PLL_HSE(0) == 0) + #endif + { + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) + { + while(1) + { + // [TODO] Put something here to tell the user that a problem occured... + } + } + } + } + + /* Output clock on MCO2 pin(PC9) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz +} + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + + /* Enable HSE oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) + { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ + } + else + { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ + } + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) + //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) + RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4) + RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) + RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) + { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + + //if (bypass == 0) + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal + //else + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock + + return 1; // OK +} +#endif + +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + + /* Enable HSI oscillator and activate PLL with HSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) + //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) + RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) + RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) + RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) + { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz + + return 1; // OK +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.h new file mode 100644 index 0000000000..a015696a76 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.h @@ -0,0 +1,124 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.h + * @author MCD Application Team + * @version V2.1.0 + * @date 19-June-2014 + * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F4XX_H +#define __SYSTEM_STM32F4XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F4xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F4xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F4XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h new file mode 100644 index 0000000000..c93835f25a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h @@ -0,0 +1,85 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE, + ADC_2 = (int)ADC2_BASE, + ADC_3 = (int)ADC3_BASE +} ADCName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_6 = (int)USART6_BASE +} UARTName; + +#define STDIO_UART_TX PD_8 +#define STDIO_UART_RX PD_9 +#define STDIO_UART UART_3 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE, + SPI_4 = (int)SPI4_BASE, + SPI_5 = (int)SPI5_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_9 = (int)TIM9_BASE, + PWM_10 = (int)TIM10_BASE, + PWM_11 = (int)TIM11_BASE +} PWMName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralPins.c new file mode 100644 index 0000000000..b139dafcc6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralPins.c @@ -0,0 +1,165 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN15 + + {PF_6, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN4 + {PF_7, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN5 + {PF_8, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN6 + {PF_9, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN7 + {PF_10,ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN8 + {PF_3, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN9 + {PF_4, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN14 + {PF_5, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN15 + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH2 + {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH4 +// {PA_3, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 + {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 + {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N - ARDUINO +// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO + {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 + + {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 + {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 + {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 - ARDUINO + {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - ARDUINO + {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1 - ARDUINO + {PB_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3 +// {PB_8, PWM_10,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4 +// {PB_9, PWM_11,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 - ARDUINO + {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N + {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N + + {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 + {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO + {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 + {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {NC, NC, 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h new file mode 100644 index 0000000000..a34b2caecd --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h @@ -0,0 +1,202 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_MODE_INPUT (0) +#define STM_MODE_OUTPUT_PP (1) +#define STM_MODE_OUTPUT_OD (2) +#define STM_MODE_AF_PP (3) +#define STM_MODE_AF_OD (4) +#define STM_MODE_ANALOG (5) +#define STM_MODE_IT_RISING (6) +#define STM_MODE_IT_FALLING (7) +#define STM_MODE_IT_RISING_FALLING (8) +#define STM_MODE_EVT_RISING (9) +#define STM_MODE_EVT_FALLING (10) +#define STM_MODE_EVT_RISING_FALLING (11) +#define STM_MODE_IT_EVT_RESET (12) + +// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H) +// Low nibble = pin number +#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF) +#define STM_PIN(X) ((uint32_t)(X) & 0xF) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, PA_3 = 0x03, + PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07, + PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B, + PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, + + PB_0 = 0x10, PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13, + PB_4 = 0x14, PB_5 = 0x15, PB_6 = 0x16, PB_7 = 0x17, + PB_8 = 0x18, PB_9 = 0x19, PB_10 = 0x1A, PB_11 = 0x1B, + PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F, + + PC_0 = 0x20, PC_1 = 0x21, PC_2 = 0x22, PC_3 = 0x23, + PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, PC_7 = 0x27, + PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, PC_11 = 0x2B, + PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, PC_15 = 0x2F, + + PD_0 = 0x30, PD_1 = 0x31, PD_2 = 0x32, PD_3 = 0x33, + PD_4 = 0x34, PD_5 = 0x35, PD_6 = 0x36, PD_7 = 0x37, + PD_8 = 0x38, PD_9 = 0x39, PD_10 = 0x3A, PD_11 = 0x3B, + PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F, + + PE_0 = 0x40, PE_1 = 0x41, PE_2 = 0x42, PE_3 = 0x43, + PE_4 = 0x44, PE_5 = 0x45, PE_6 = 0x46, PE_7 = 0x47, + PE_8 = 0x48, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B, + PE_12 = 0x4C, PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F, + + PF_0 = 0x50, PF_1 = 0x51, PF_2 = 0x52, PF_3 = 0x53, + PF_4 = 0x54, PF_5 = 0x55, PF_6 = 0x56, PF_7 = 0x57, + PF_8 = 0x58, PF_9 = 0x59, PF_10 = 0x5A, PF_11 = 0x5B, + PF_12 = 0x5C, PF_13 = 0x5D, PF_14 = 0x5E, PF_15 = 0x5F, + + PG_0 = 0x60, PG_1 = 0x61, PG_2 = 0x62, PG_3 = 0x63, + PG_4 = 0x64, PG_5 = 0x65, PG_6 = 0x66, PG_7 = 0x67, + PG_8 = 0x68, PG_9 = 0x69, PG_10 = 0x6A, PG_11 = 0x6B, + PG_12 = 0x6C, PG_13 = 0x6D, PG_14 = 0x6E, PG_15 = 0x6F, + + PH_0 = 0x70, PH_1 = 0x71, PH_2 = 0x72, PH_3 = 0x73, + PH_4 = 0x74, PH_5 = 0x75, PH_6 = 0x76, PH_7 = 0x77, + PH_8 = 0x78, PH_9 = 0x79, PH_10 = 0x7A, PH_11 = 0x7B, + PH_12 = 0x7C, PH_13 = 0x7D, PH_14 = 0x7E, PH_15 = 0x7F, + + // Module Pins + // A + P_A5 = PC_2, + P_A6 = PF_3, + P_A7 = PG_15, + P_A8 = PB_6, + P_A9 = PB_8, + P_A10 = PA_11, + P_A11 = PA_9, // D2 TX + P_A12 = PA_12, + P_A13 = PA_10, // D8 RX + P_A14 = PD_9, // D1 RX USB CDC + P_A15 = PD_8, // D0 TX USB CDC + P_A16 = PD_11, + P_A17 = PD_12, + P_A18 = PA_3, + // B + P_C5 = PF_14, + P_C6 = PE_13, // D12 MISO + P_C8 = PE_12, // D8 SCK + P_C10 = PE_14, // D11 MOSI + P_C11 = PE_11, // D10 SSEL + P_C12 = PE_9, + P_C13 = PF_8, // ETH RSTn + P_C14 = PC_1, // ETH MDC + P_C15 = PA_2, // ETH MDIO + P_C16 = PF_7, + P_C17 = PF_1, // D15 SCL + P_C18 = PF_0, // D14 SDA + // D + P_D1 = PB_12, // ETH TXD0 + P_D2 = PB_13, // ETH TXD1 + P_D3 = PB_11, // ETH TXEN + P_D4 = PA_7, // ETH CRSDV + P_D5 = PC_4, // ETH RXD0 + P_D6 = PC_5, // ETH RXD1 + P_D8 = PA_1, // ETH REFCLK + // TP + P_TP5 = PB_4, // NTRST + P_TP7 = PA_13, // TMS SWDIO + P_TP8 = PA_15, // TDI + P_TP9 = PA_14, // TCK SWCLK + P_TP10 = PB_3, // TDO + + // Board Pins + // A0-A5 + A0 = PC_2, + A1 = PF_3, + A2 = PA_3, + A3 = PF_7, + A4 = PF_14, // not AI + A5 = PG_15, // not AI + // D0-D15 + D0 = PD_8, // TX + D1 = PD_9, // RX + D2 = PA_9, // TX + D3 = PA_11, + D4 = PA_12, + D5 = PB_8, + D6 = PD_11, + D7 = PD_12, + D8 = PA_10, // RX + D9 = PB_6, + D10 = PE_11, // SSEL + D11 = PE_14, // MOSI + D12 = PE_13, // MISO + D13 = PE_12, // SCK + D14 = PF_0, // SDA + D15 = PF_1, // SCL + // Internal + LED_GRE = PB_4, // Green + LED_YEL = PE_9, // Yellow, CS_CARD + LED_RED = PB_3, // Red + BTN = PA_15 + USBRXD = PD_9, // RX + USBTXD = PD_8, // TX + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + OpenDrain = 3, + PullDefault = PullNone +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PortNames.h new file mode 100644 index 0000000000..4f9af48f2c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PortNames.h @@ -0,0 +1,51 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, + PortE = 4, + PortF = 5, + PortG = 6, + PortH = 7 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/device.h new file mode 100644 index 0000000000..ceec65dab5 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/device.h @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 // Not present on this device + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 0 // MAMM Not present on this module 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/objects.h new file mode 100644 index 0000000000..82dcfc6868 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/objects.h @@ -0,0 +1,110 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct analogin_s { + ADCName adc; + PinName pin; +}; + +struct dac_s { + DACName dac; + PinName channel; +}; + +struct serial_s { + UARTName uart; + int index; // Used by irq + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + PinName pin_tx; + PinName pin_rx; +}; + +struct spi_s { + SPIName spi; + uint32_t bits; + uint32_t cpol; + uint32_t cpha; + uint32_t mode; + uint32_t nss; + uint32_t br_presc; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; +}; + +struct i2c_s { + I2CName i2c; + uint32_t slave; +}; + +struct pwmout_s { + PWMName pwm; + PinName pin; + uint32_t period; + uint32_t pulse; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index a1d9c44163..cde9037306 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -688,6 +688,15 @@ class DISCO_F401VC(Target): self.supported_toolchains = ["GCC_ARM"] self.default_toolchain = "GCC_ARM" +class UBLOX_C029(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['STM', 'STM32F4', 'STM32F439', 'STM32F439ZI'] + self.macros = ['HSE_VALUE=24000000', 'HSE_STARTUP_TIMEOUT=5000'] + self.supported_toolchains = ["uARM"] + self.default_toolchain = "uARM" + self.supported_form_factors = ["ARDUINO"] ### Nordic ### @@ -942,7 +951,8 @@ TARGETS = [ MTS_MDOT_F411RE(), MTS_DRAGONFLY_F411RE(), DISCO_F401VC(), - + UBLOX_C029(), # STM32F439 + ### Nordic ### NRF51822(), NRF51822_OTA(), # nRF51822 From c11f753afc9a67c5d829399871c7abc8494c4308 Mon Sep 17 00:00:00 2001 From: mazgch Date: Sun, 1 Feb 2015 16:49:39 +0100 Subject: [PATCH 16/25] comment fixed --- .../TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/stm32f439xx.sct | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/stm32f439xx.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/stm32f439xx.sct index 31db112dbe..c80c9d6b33 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/stm32f439xx.sct +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/stm32f439xx.sct @@ -27,7 +27,7 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; STM32F411RE: 512 KB FLASH (0x80000) + 256 KB SRAM (0x30000 + 0x10000) +; STM32F439ZI: 512 KB FLASH (0x80000) + 256 KB SRAM (0x30000 + 0x10000) LR_IROM1 0x08000000 0x80000 { ; load region size_region ER_IROM1 0x08000000 0x80000 { ; load address = execution address From e140fd1e45d8d0111738648e73a71ec40f5d9378 Mon Sep 17 00:00:00 2001 From: mazgch Date: Sun, 1 Feb 2015 16:54:57 +0100 Subject: [PATCH 17/25] add more toolchains --- workspace_tools/targets.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index cde9037306..a75f22ddd1 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -694,7 +694,7 @@ class UBLOX_C029(Target): self.core = "Cortex-M4F" self.extra_labels = ['STM', 'STM32F4', 'STM32F439', 'STM32F439ZI'] self.macros = ['HSE_VALUE=24000000', 'HSE_STARTUP_TIMEOUT=5000'] - self.supported_toolchains = ["uARM"] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"] self.default_toolchain = "uARM" self.supported_form_factors = ["ARDUINO"] From 3e17cacc768ed1e1b25e5e1d11a6657a7826b913 Mon Sep 17 00:00:00 2001 From: mazgch Date: Sun, 1 Feb 2015 17:51:52 +0100 Subject: [PATCH 18/25] fixed peripheral/port names and pin list --- .../TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h | 7 +++++++ .../TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h | 2 +- .../TARGET_STM32F4/TARGET_UBLOX_C029/PortNames.h | 5 ++++- 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h index c93835f25a..c2de03ab09 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h @@ -42,10 +42,17 @@ typedef enum { ADC_3 = (int)ADC3_BASE } ADCName; +typedef enum { + DAC_0 = 0, + DAC_1 +} DACName; + typedef enum { UART_1 = (int)USART1_BASE, UART_2 = (int)USART2_BASE, UART_3 = (int)USART3_BASE, + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE, UART_6 = (int)USART6_BASE } UARTName; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h index a34b2caecd..ae2c6437ac 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h @@ -179,7 +179,7 @@ typedef enum { LED_GRE = PB_4, // Green LED_YEL = PE_9, // Yellow, CS_CARD LED_RED = PB_3, // Red - BTN = PA_15 + BTN = PA_15, USBRXD = PD_9, // RX USBTXD = PD_8, // TX diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PortNames.h index 4f9af48f2c..0c563dd148 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PortNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PortNames.h @@ -42,7 +42,10 @@ typedef enum { PortE = 4, PortF = 5, PortG = 6, - PortH = 7 + PortH = 7, + PortI = 8, + PortJ = 9, + PortK = 10 } PortName; #ifdef __cplusplus From 0682571c5b554aefb75cacba687f9caf3be4c470 Mon Sep 17 00:00:00 2001 From: mazgch Date: Sun, 1 Feb 2015 18:11:26 +0100 Subject: [PATCH 19/25] add module pin comments --- .../TARGET_UBLOX_C029/PinNames.h | 69 ++++++++++--------- 1 file changed, 35 insertions(+), 34 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h index ae2c6437ac..5f5f79984a 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h @@ -108,41 +108,42 @@ typedef enum { // Module Pins // A - P_A5 = PC_2, - P_A6 = PF_3, - P_A7 = PG_15, - P_A8 = PB_6, - P_A9 = PB_8, - P_A10 = PA_11, - P_A11 = PA_9, // D2 TX - P_A12 = PA_12, - P_A13 = PA_10, // D8 RX - P_A14 = PD_9, // D1 RX USB CDC - P_A15 = PD_8, // D0 TX USB CDC - P_A16 = PD_11, - P_A17 = PD_12, - P_A18 = PA_3, + P_A5 = PC_2, // UART-DTR + P_A6 = PF_3, // Switch-0 + P_A7 = PG_15, // Red, Mode + P_A8 = PB_6, // Green, Switch-1 + P_A9 = PB_8, // Blue + P_A10 = PA_11, // UART-CTS + P_A11 = PA_9, // UART-TXD + P_A12 = PA_12, // UART-RTS + P_A13 = PA_10, // UART-RXD + P_A14 = PD_9, // GPIO-0 + P_A15 = PD_8, // GPIO-1 + P_A16 = PD_11, // GPIO-2 + P_A17 = PD_12, // GPIO-3 + P_A18 = PA_3, // UART-DSR // B - P_C5 = PF_14, - P_C6 = PE_13, // D12 MISO - P_C8 = PE_12, // D8 SCK - P_C10 = PE_14, // D11 MOSI - P_C11 = PE_11, // D10 SSEL - P_C12 = PE_9, - P_C13 = PF_8, // ETH RSTn - P_C14 = PC_1, // ETH MDC - P_C15 = PA_2, // ETH MDIO - P_C16 = PF_7, - P_C17 = PF_1, // D15 SCL - P_C18 = PF_0, // D14 SDA - // D - P_D1 = PB_12, // ETH TXD0 - P_D2 = PB_13, // ETH TXD1 - P_D3 = PB_11, // ETH TXEN - P_D4 = PA_7, // ETH CRSDV - P_D5 = PC_4, // ETH RXD0 - P_D6 = PC_5, // ETH RXD1 - P_D8 = PA_1, // ETH REFCLK + // C + P_C5 = PF_14, // SPI-IRQ + P_C6 = PE_13, // SPI-MISO + P_C8 = PE_12, // Res + P_C10 = PE_14, // SPI-MOSI + P_C11 = PE_11, // SPI-CS0 + P_C12 = PE_9, // Res + P_C13 = PF_8, // GPIO-4, RMII-RSTn + P_C14 = PC_1, // RMII-MDC + P_C15 = PA_2, // RMII-MDIO + P_C16 = PF_7, // GPIO-7 + P_C17 = PF_1, // I2C-SCL + P_C18 = PF_0, // I2C-SDA + // D + P_D1 = PB_12, // RMII-TXD0 + P_D2 = PB_13, // RMII-TXD1 + P_D3 = PB_11, // RMII-TXEN + P_D4 = PA_7, // RMII-CRSDV + P_D5 = PC_4, // RMII-RXD0 + P_D6 = PC_5, // RMII-RXD1 + P_D8 = PA_1, // RMII-REFCLK // TP P_TP5 = PB_4, // NTRST P_TP7 = PA_13, // TMS SWDIO From 5bd982c17184ae6613289b13f3cfa2db0d1ecd99 Mon Sep 17 00:00:00 2001 From: 0xc0170 Date: Mon, 2 Feb 2015 15:22:55 +0000 Subject: [PATCH 20/25] Targets - gpio_is_connected() for STM targets where it was not implemented --- .../hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_object.h | 4 ++++ .../hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h | 5 +++++ .../hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_object.h | 4 ++++ .../hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_object.h | 4 ++++ .../hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_object.h | 4 ++++ .../hal/TARGET_STM/TARGET_NUCLEO_L053R8/gpio_object.h | 4 ++++ .../hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_object.h | 4 ++++ .../targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_object.h | 4 ++++ .../targets/hal/TARGET_STM/TARGET_STM32F4XX/gpio_object.h | 4 ++++ 9 files changed, 37 insertions(+) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_object.h index fdc6112cb6..684d968757 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h index fdc6112cb6..e49e172b72 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h @@ -64,6 +64,11 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_object.h index 5569efc465..bebf7db0c7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_object.h index 5569efc465..bebf7db0c7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_object.h index 5569efc465..bebf7db0c7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/gpio_object.h index fdc6112cb6..684d968757 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_object.h index fdc6112cb6..684d968757 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_object.h index 75013b4188..4391135e3b 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_object.h @@ -62,6 +62,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/gpio_object.h index fcf499289e..f43f2f8530 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/gpio_object.h @@ -46,6 +46,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif From 134a67aab259d410373367cb96b73420b390d385 Mon Sep 17 00:00:00 2001 From: 0xc0170 Date: Tue, 3 Feb 2015 15:00:42 +0000 Subject: [PATCH 21/25] mbed header file - mbed lib revision - 93 --- libraries/mbed/api/mbed.h | 2 +- workspace_tools/build_release.py | 1 + workspace_tools/targets.py | 6 ++---- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/libraries/mbed/api/mbed.h b/libraries/mbed/api/mbed.h index 4c5efae3e2..ef1393a0eb 100644 --- a/libraries/mbed/api/mbed.h +++ b/libraries/mbed/api/mbed.h @@ -16,7 +16,7 @@ #ifndef MBED_H #define MBED_H -#define MBED_LIBRARY_VERSION 92 +#define MBED_LIBRARY_VERSION 93 #include "platform.h" diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 1f513e4cdb..0f47f42d6b 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -37,6 +37,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('SSCI824', ('uARM',)), ('LPC1347', ('ARM','IAR')), ('LPC4088', ('ARM', 'GCC_ARM', 'GCC_CR', 'IAR')), + ('LPC4088_DM', ('ARM', 'GCC_ARM', 'GCC_CR', 'IAR')), ('LPC1114', ('uARM','GCC_ARM', 'IAR')), ('LPC11U35_401', ('ARM', 'uARM','GCC_ARM','GCC_CR', 'IAR')), ('LPC11U35_501', ('ARM', 'uARM','GCC_ARM','GCC_CR', 'IAR')), diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index fa4b8cb65c..20f1b6475f 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -307,9 +307,7 @@ class LPC4088(LPCTarget): LPCTarget.lpc_patch(t_self, resources, elf, binf) class LPC4088_DM(LPC4088): - def __init__(self): - LPC4088.__init__(self) - self.extra_labels.append('LPC4088_DM') + pass class LPC4330_M4(LPCTarget): def __init__(self): @@ -406,7 +404,7 @@ class TEENSY3_1(Target): self.extra_labels = ['Freescale', 'K20XX', 'K20DX256'] self.supported_toolchains = ["GCC_ARM", "ARM"] self.is_disk_virtual = True - self.detect_code = ["0230"] + self.detect_code = ["0230"] OUTPUT_EXT = '.hex' From 61d1204e05b600d4be9945fb35a4c55dbdc0cbb5 Mon Sep 17 00:00:00 2001 From: GustavWi Date: Wed, 4 Feb 2015 11:29:31 +0100 Subject: [PATCH 22/25] Added IAR support for NRF51822. IAR's linker can not merge hex files as a section only binarys. I added a binary under TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR that represents the soft_device. I added support in the python scripts to also copy binaries to the build/mbed dir and also added support for the exporter to copy binaries from resources into the exported zip file. --- .../TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf | 43 + .../startup_NRF51822_IAR.s | 237 +++++ .../TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf | 43 + .../startup_NRF51822_IAR.s | 237 +++++ .../s110_nrf51822_7.1.0_softdevice.bin | Bin 0 -> 86540 bytes workspace_tools/build_api.py | 1 + workspace_tools/build_release.py | 2 +- workspace_tools/export/exporters.py | 2 +- workspace_tools/export/iar.py | 1 + workspace_tools/export/iar_nrf51822.ewp.tmpl | 958 ++++++++++++++++++ workspace_tools/targets.py | 4 +- workspace_tools/toolchains/__init__.py | 6 + 12 files changed, 1530 insertions(+), 4 deletions(-) create mode 100644 libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf create mode 100644 libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf create mode 100644 libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/s110_nrf51822_7.1.0_softdevice.bin create mode 100644 workspace_tools/export/iar_nrf51822.ewp.tmpl diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf new file mode 100644 index 0000000000..22e3abd0be --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf @@ -0,0 +1,43 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00016000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x000160c0; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20002000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_heap__ = 0xF00; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __code_start_soft_device__ = 0x0; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, + block HEAP }; + +/*This is used for mbed applications build inside the Embedded workbench +Applications build with the python scritps use a hex merge so need to merge it +inside the linker. The linker can only use binary files so the hex merge is not possible +through the linker. That is why a binary is used instead of a hex image for the embedded project. +*/ +if(isdefinedsymbol(SOFT_DEVICE_BIN)) +{ + place at address mem:__code_start_soft_device__ { section .noinit_softdevice }; +} \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.s b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.s new file mode 100644 index 0000000000..b1e263009c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.s @@ -0,0 +1,237 @@ +;; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. +;; The information contained herein is confidential property of Nordic +;; Semiconductor ASA.Terms and conditions of usage are described in detail +;; in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. +;; Licensees are granted free, non-transferable use of the information. NO +;; WARRANTY of ANY KIND is provided. This heading must NOT be removed from +;; the file. + +;; Description message + + MODULE ?cstartup + + ;; Stack size default : 1024 + ;; Heap size default : 2048 + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +;__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK + DCD RADIO_IRQHandler ;RADIO + DCD UART0_IRQHandler ;UART0 + DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0 + DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1 + DCD 0 ;Reserved + DCD GPIOTE_IRQHandler ;GPIOTE + DCD ADC_IRQHandler ;ADC + DCD TIMER0_IRQHandler ;TIMER0 + DCD TIMER1_IRQHandler ;TIMER1 + DCD TIMER2_IRQHandler ;TIMER2 + DCD RTC0_IRQHandler ;RTC0 + DCD TEMP_IRQHandler ;TEMP + DCD RNG_IRQHandler ;RNG + DCD ECB_IRQHandler ;ECB + DCD CCM_AAR_IRQHandler ;CCM_AAR + DCD WDT_IRQHandler ;WDT + DCD RTC1_IRQHandler ;RTC1 + DCD QDEC_IRQHandler ;QDEC + DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP + DCD SWI0_IRQHandler ;SWI0 + DCD SWI1_IRQHandler ;SWI1 + DCD SWI2_IRQHandler ;SWI2 + DCD SWI3_IRQHandler ;SWI3 + DCD SWI4_IRQHandler ;SWI4 + DCD SWI5_IRQHandler ;SWI5 + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors +NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address +NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask + +; Default handlers. + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =NRF_POWER_RAMON_ADDRESS + LDR R2, [R0] + MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk + ORRS R2, R2, R1 + STR R2, [R0] + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + ; Dummy exception handlers + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + ; Dummy interrupt handlers + + PUBWEAK POWER_CLOCK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +POWER_CLOCK_IRQHandler + B . + PUBWEAK RADIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RADIO_IRQHandler + B . + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_IRQHandler + B . + PUBWEAK SPI0_TWI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI0_TWI0_IRQHandler + B . + PUBWEAK SPI1_TWI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_TWI1_IRQHandler + B . + PUBWEAK GPIOTE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE_IRQHandler + B . + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B . + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B . + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B . + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER2_IRQHandler + B . + PUBWEAK RTC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC0_IRQHandler + B . + PUBWEAK TEMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TEMP_IRQHandler + B . + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RNG_IRQHandler + B . + PUBWEAK ECB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ECB_IRQHandler + B . + PUBWEAK CCM_AAR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CCM_AAR_IRQHandler + B . + PUBWEAK WDT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT_IRQHandler + B . + PUBWEAK RTC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC1_IRQHandler + B . + PUBWEAK QDEC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QDEC_IRQHandler + B . + PUBWEAK LPCOMP_COMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPCOMP_COMP_IRQHandler + B . + PUBWEAK SWI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI0_IRQHandler + B . + PUBWEAK SWI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI1_IRQHandler + B . + PUBWEAK SWI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI2_IRQHandler + B . + PUBWEAK SWI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI3_IRQHandler + B . + PUBWEAK SWI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI4_IRQHandler + B . + PUBWEAK SWI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI5_IRQHandler + B . + + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf new file mode 100644 index 0000000000..4a169b0e78 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf @@ -0,0 +1,43 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00016000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x000160c0; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20002000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x1000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __code_start_soft_device__ = 0x0; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, + block HEAP }; + +/*This is used for mbed applications build inside the Embedded workbench +Applications build with the python scritps use a hex merge so need to merge it +inside the linker. The linker can only use binary files so the hex merge is not possible +through the linker. That is why a binary is used instead of a hex image for the embedded project. +*/ +if(isdefinedsymbol(SOFT_DEVICE_BIN)) +{ + place at address mem:__code_start_soft_device__ { section .noinit_softdevice }; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.s b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.s new file mode 100644 index 0000000000..c0a2b08eab --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.s @@ -0,0 +1,237 @@ +;; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. +;; The information contained herein is confidential property of Nordic +;; Semiconductor ASA.Terms and conditions of usage are described in detail +;; in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. +;; Licensees are granted free, non-transferable use of the information. NO +;; WARRANTY of ANY KIND is provided. This heading must NOT be removed from +;; the file. + +;; Description message + + MODULE ?cstartup + + ;; Stack size default : 1024 + ;; Heap size default : 2048 + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +;__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK + DCD RADIO_IRQHandler ;RADIO + DCD UART0_IRQHandler ;UART0 + DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0 + DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1 + DCD 0 ;Reserved + DCD GPIOTE_IRQHandler ;GPIOTE + DCD ADC_IRQHandler ;ADC + DCD TIMER0_IRQHandler ;TIMER0 + DCD TIMER1_IRQHandler ;TIMER1 + DCD TIMER2_IRQHandler ;TIMER2 + DCD RTC0_IRQHandler ;RTC0 + DCD TEMP_IRQHandler ;TEMP + DCD RNG_IRQHandler ;RNG + DCD ECB_IRQHandler ;ECB + DCD CCM_AAR_IRQHandler ;CCM_AAR + DCD WDT_IRQHandler ;WDT + DCD RTC1_IRQHandler ;RTC1 + DCD QDEC_IRQHandler ;QDEC + DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP + DCD SWI0_IRQHandler ;SWI0 + DCD SWI1_IRQHandler ;SWI1 + DCD SWI2_IRQHandler ;SWI2 + DCD SWI3_IRQHandler ;SWI3 + DCD SWI4_IRQHandler ;SWI4 + DCD SWI5_IRQHandler ;SWI5 + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors +NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address +NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask + +; Default handlers. + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =NRF_POWER_RAMON_ADDRESS + LDR R2, [R0] + MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk + ORRS R2, R2, R1 + STR R2, [R0] + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + ; Dummy exception handlers + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + ; Dummy interrupt handlers + + PUBWEAK POWER_CLOCK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +POWER_CLOCK_IRQHandler + B . + PUBWEAK RADIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RADIO_IRQHandler + B . + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_IRQHandler + B . + PUBWEAK SPI0_TWI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI0_TWI0_IRQHandler + B . + PUBWEAK SPI1_TWI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_TWI1_IRQHandler + B . + PUBWEAK GPIOTE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE_IRQHandler + B . + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B . + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B . + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B . + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER2_IRQHandler + B . + PUBWEAK RTC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC0_IRQHandler + B . + PUBWEAK TEMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TEMP_IRQHandler + B . + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RNG_IRQHandler + B . + PUBWEAK ECB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ECB_IRQHandler + B . + PUBWEAK CCM_AAR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CCM_AAR_IRQHandler + B . + PUBWEAK WDT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT_IRQHandler + B . + PUBWEAK RTC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC1_IRQHandler + B . + PUBWEAK QDEC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QDEC_IRQHandler + B . + PUBWEAK LPCOMP_COMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPCOMP_COMP_IRQHandler + B . + PUBWEAK SWI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI0_IRQHandler + B . + PUBWEAK SWI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI1_IRQHandler + B . + PUBWEAK SWI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI2_IRQHandler + B . + PUBWEAK SWI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI3_IRQHandler + B . + PUBWEAK SWI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI4_IRQHandler + B . + PUBWEAK SWI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI5_IRQHandler + B . + + + END \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/s110_nrf51822_7.1.0_softdevice.bin b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/s110_nrf51822_7.1.0_softdevice.bin new file mode 100644 index 0000000000000000000000000000000000000000..151801682bba504439ea4361758e0fd3c64855ad GIT binary patch literal 86540 zcmeEvdwdkt+5efn&Tej-gi8`anB62~69R1TLO{Sx)(*2FAfUFWv`zr)M7(SQ;wB*O zhTA6E8t_sOea(8QL9qrTN~_V}?FCEU&Ju00Xq~9I+SWR1HJi(3f8R6NAolJ1{(isz z8$Pph=FGV~=Q+=L&T~6MubGgD2^S&c5bpom-wKo+|2u=kSzKS>8pNe%2uZ^=8J8W` z3|trCx)hfe*A=*ajOzwm4Y)Sr+JWmHT>Ef6hU*zzFW@?c>$kYx!Sw;I&v1Q>D~`*o zBP0{o6kNr)rgiu7y*yFB7&3Ha9GTX`a@Tk*l4TXUxRU!(GPQuaDw%R~E0d|qxaG-| zz%5OtYPluJ)N)Qprmp1pWNH=XNv2kFRmqgdElQ@=aSM_uiJO;9-NemJrhMFm$<#(} zPBP`^W+ziyxS7dRfGbO;wsX#8D#R5hQ+IQP$y7VXB~$lt1uK@;?1 z9H*CDBa&DCSd%4@vSFD)`t4+zI3n6RIr;2ctacmubbc~VicHF*uV<`nL2KKB zwhsvIdUrk($>3s9!hIVZ?Kbe7q$fn3J7hG>sP0T2(j-G2%!CGf~cv3dhUbhlhP-W zC^797d?lY4cq}mocV=H=;OB|Mgr8+%nj?vU%M*IwfT*9vhYMJ*0KKnLU% zUys_|+O-mx)wiz{0#cCZ_p&*F#n*XnSvX5VPu9Q3gL{Hg|isFSxyYRI68)> ztAMAAfT#TlGBaJ~1iqdVwo8j8JMTj26Qd45MpH*dFbMtq*31{os?dA#}%G2{7xpO`3 zZd;F@w{@p@_M0;zhO)Fi_PFgt*0jf}V{*=K?7s*baCX5bn% z{i%L;zBhl$6m#UeG!xlV@MR>2xApiI(|@*ZqMCt42GE_6au(C^<_dXU-{Qo;FmN|K zLVCDY;?YUo$+bn&-PI|PNhrCmIyEwJ$;6s$F-Nj_L)D+lRwY{qe9eZkmgFqX(DJRw z@0V#_I#P!B(*>QRvs*nn@mlnw=Rb&!^SA{5NGc%{DDG{505A{(;no|q6jx*G*5`T_U7wP5AHMYfO@WAppS(1&8pxd~_ShIiC-o>ORj<%N= zXp?9YZPTRd$VPr$L9u^b{?pZlzO_HTmVA`sdMRh|R34lOaL{rTrhota8w3Bwz`rr@ zZw&k!1OLXrzcKLtgMrXg!u4OykbMgYS&aMt_P1jBckgL=di5ahHC*G*|9n4j-n-u? z)9>JZ23P-i@BX>o_;VCxKL20J5mgtZkx~a`Hu~w1nF}fBk!c(?U?N$TmAj$nC+pZUgr(g=>*$lzQuK! z(1}rLV!8@?piCZd^Im=>e=VPJMAyN%m~N9m7L!+)mv-_Q zF9rBkeh+)~T-&8Po%Ga~aoN$~;f6(1(wxsWK6KBewh?!)tmD^aS zu%ArHIbGlGVLhkoe2cfSMOsddM00X5ej7An7<;(Hz9`-qJp=dGaX&sSG0>aP+b7}qCEO?Cel$U~rQ8_R3$C#EOki6ysEOVFM-(}{UzRvu_fRebH>kM2dFlzpYkvDVD!3InD+0bI| z9$HsmF1Ma`*(ILwZTB&%GDI~oOD9p^A93=Gx@~k~mkYhbx(k;X_~#2;ex@Xir}`kr zi$ei z>3Hrq_gpw=!gCj%4X964GUybEGFueOPeq*25`Q0=>x+SA@}L{MaRF$`h56RBqVIm8 z^Eshes?|fb9$UAsQctqgM@A>6W=$$^6qjF6xv=U7-sM-VUU$>R&4C@HMq>S$yk5OG zVe4Tfy*hw_?t-D>rOZKS6lrd>)QTfG}^2*FcZW8<$KomG^vRra z&H~TUD}Q`FS%TSalX7{p`US>w{&>ymur|V4>9-m_?I@%B-nh(aKAuCN-%8s7CB-={ zv*2Iktv+vLX0@F@VXnW!MlvsnKl2!sw0?&hvs#AHv!U@ZnZYy1v0+yKYa|1lT(beF z&%{{u#2~9)1=tyGhPPMGie+BHu|7Rl>J8{Z;7zga=}Qf~)8A2TmPxr$CQiLv7+%U{ ztA!&pH(M_E>5EBWq4ybGzCg-Lj1rijbx zc8F8FnQMNu#xiyHn#o?v)X172VCAQXdhIP^KcNeX*-P$S^T#z+T7HVS19w}uF?>5( zqN5=s&`%T&>zI7QxHmMeT`kq!bluvuH(ys**Enk}SQ`0;xVJEPufoQYN!&t^xbrEW zRVTmXHd|1B*mXabT zU%rWRZEtwJAzKZD%egBJK0I&OzH$4e@{I?5zMj8CZQZH-=iZi3TcA2r6Ci%p$MV+7 z?LJoBHJTVW1Kw-}1$|tj%*o^{=dt_*K3Hi{)tH@EgcNoAh(+Ciy|@wU5!?ve{28pf zShq#>#!oN(L#=h84qTSoLY!MD6%;nT`sbE`S+9fqIY zAkJ%T?GGGlwl@Y_>w>+l9YKcc@J-+J`sLiEN72gFk=KQKKG4dldSJpR*YlF!;&Dgv3A6=@OGD&Yp)>46 zZq_iXev6!Z`5@jV1};t1YwbQExGSq}<|^8@FlA|xCu$bmzNhuoUB|a@K88EGiQ8&} z12jf<7l0cLHEqq>Vx^FArahd0sn2imyklm0r$gby%i$#lTwX?a17rit7H=>=ugieEz+HJ8P&dy3==N@i;I6$)1i-#yoR_+qC zY;stp(U#j|zuLs0w5|JMf!T^ViI6P}T4wA76zaja8QBc}I>vRGBCGml%-~53L=y%N ztEMIx-tJ*xg^YDi1-+*OS4-j)R}xYykkW&@m|?-CeeCCQG&sHjZ~9`SquOw4s*oLC z1?+z|NcOVoj|VGwdS5^I;o(v(@Ip*=sL1Pic!Z*lEm+83X4!V3gr$uIfA66|LT~|wy7=o_0*z{IZDHfiw%^YF`#W7 zXgk53@D`)|0+g@p;Tndc#D483zV6p+jl6pSNBK(Rm_R@?diiDVtAMv;(CKH@D-%wC zirO?xIIe*~oAd1bJ`UW^*Zn;93%d4b&F8e52Kk8atT(4JTeS>6yUZTyY7JHEBNnxP zNQV*XI44?=8Y=Cd`J8CsPR_UKmqNdvb5(5&`1DLJN;$ld2!`Hy5P^lpfRgdN_^ zXyr(3`%>ZwngY!1SZT*(Ex!+d<&9l zBMyjUA)tY@J> zN;uc9#si^4I~aS#rUQPal*q&$Y@92&U2af2gPD0YQPS`cJX#g!U@=E#X|QPX4?mbe zo+&uJPgG{9!=NaO`m51#igKN!DEqnE`ba@?B-4Z`-ZWR1s-PCMEsVqhdImr7yPbx< z93k5~0dFG-C)VKO=!fz;qNFD0>%wzwThFy^j+oCucAo~BNzi%s0vXKAWDr_?Gh0oPbpiWOFBkW;w0x0lIM zTQzuIJU7M*&cX35Xp{37Po-;^Y6{mW?6tdJ?5}-SdRd0<3hsF?0d|H)Em*y_={lz)@`5lg6u?TE8tL*1 zkddr+ij{$8>hlViQ{PVIQk8(2ecQybw?A_pz1==KYZKv=4bwM5#@P_-(ZTm@>we^) zU^YOW*yp_xV?3tKL^|Z54D9L&t^=#O*TV(x7kZ~M{%~V36b`yW3M3}6f%8#$?CyVR zOE2&8{tV-PXq2^gOwE8cGd}hi$+7#o@6;q{IxmnHwV5@@TZJa?Q9uwFy+g3UQ|ziF z>d0_2(%~Eq>2HT`7hIJYYWeVOUYo-;T^=$EaS9vomW?N1lZ?hOIg!(x@OUf5bdiWjF2{~RzX@*tCd))4MBRU|M?Mwq>|3*l0R5iTnV|+$< z;BDPs{x|yjyZ7&)zt!<9_3Cqc#hRo&8?=Uphbb=33Lkq{VO&C-RXszjIz47p-Bee_cMSI)>@4&n0*LSoe!#9FTW|Kj<|6 zV33ar&wC$6z0XHrJ4#C81Kc4E-j7Bo{Zo#P*(-T=8I@>Q^@UNrvp#v>Ao~@T?kJE% z#_k5Z`Q@n2xlmq@H(0CA8)PT;s&$b^1f4zAm9FV4COO02)oRgYsrL*Y3KHdoAmh;6 ze<7IFS)=z0kSm9~TFvU?kf#ihdxW2Re+>v98tG~!c2<2@+d0~Vkhcf9yGKgzlOt9%I#bj2U~4rG5o)}P(fWiD zv1v@gD2;R^Q$>*uXjjk~P@c*@dgqjgxY=#ak=KM6E}(Cz)}6M8f{1e9no<=GwG1d{ zL^-`|P`I+JQ>jWvX~roAaxB+mpxR%EbL#r)LX=<46lQpTjGq5E%!Pd0xF*-_6at;r zTdLx$A$FtUs1fJ1YweEdYs(Si!*H`3q=uZN+~n)d{cpRdUY_X9#Tt7GTE?z;s$GXU z$Oa$W*7{(zGos^r=VaeWW*8!Yt?7U?10%CH=oKSpyPd9U%B^Q%PMjenFwU_Fp*(@g z6pO$EC{Lhr1?3NY2w2c@RAvhP3pnoZ-T^p%3OGDTIGU4iOpBQK-iznlNy@$thef#+ zd&+@)%F})|Xy9DuV4C?on2tns+*jBu8Gi~^{`8TByLMIX+O=vI{w`UBpA}cqHQ2jX7*{yffWd0Fvl?f&V=BJKXOk@?zv)yTytb;-yD_{|z| zX?gN+Ii3y;mugR&hl{oQRl|1eo;EyHyPp}#)$T`!CTjOvhBCE#@lcv}|6AJ8@l&T^>V=eld#BvN@|#*On%BzcZDAK`uVUiH$UHyn~(TCVxI_3 zkvozJ?Omv3Zm+t%7uKCu2Prk%5Q)?W8r?B8@=5B(tF9mXg!QHh-$q^C*}O?PnZqsk z_|A9oF1za5f-{H7jBg{Zo^d*P5_Can#Dl%VYo>as2peUVx?N)As81n9b1s8Tb1X+dYTSxR)GM?nYOBsg=^OAwOK+j~q;-*~d+{_@_w{qB zA*3i)7!DDI+@)T(i4_+iif)nDDkTc1=pOWJ%gXau#Y%5r9t#_yty{+%xJs`w#4TTdC*Z7&JrFb!jV z5`$CUH$A)(H9i_F6#7YO4%bBai9LJ;^4=X3o5Ik}dJhNTp%S4HO$Ky<3Ra|ZHi^cH z83GwpBcB+qNBLueS<7;3^~Ie37zyR-nwTc_f-0GVmc$a^OEH&mtVPD{Q!R?R6XKZ@8uIrkm<-xnaz< zumEe@*8RoTw!rJ=k24yd|ASEF_vTmm+}PI;BdOX4NjZtEd7i@g`&tF^h&93#pT)lW zaUw&_)2N4V8S3XTf>^ub!u1V55C_2}Xp3){KSztN){3a5kGvYb2P3<3Q1rVCL?6wg z?SB&^Gim!i(D4hxF=#CYXlqps$It`3P8xk1_zd-Itjl}C&$@}s(3nHy$1r4R6KT7>H%4zd}iioS}Bbx~h#4 z7vQ2fLvoSAZ~^lh;?F=8E5y5N9;n-~MCZ5$_Te@`UvI2G<2hqGGx^$lTggI?v2NQ^ z*oa@bRU)&8Wimq_G1uD)AMu#${6dRZFVbBp6@Ay%&&nJIWgeV>^=3DAC*Wk1G%L~%uuJq{1St` z_ztmBVy3UIWtOo?3&8E9;TGqqN)7J4gpt|cZ@-7kHW^^CJTvapV* zQjCt4ucMGo1f-K=q&;2Tm>~N|DWqKceRt>{Wn9HG*REy}h0g)*#!xoZ8<5 zH}bYnRY4|fSc4H36gEM~E!ibbroIR9xR|a!n&>ezMQO0!8s#kXy?t$Y-4P#AE(BDo zM_FO9nC5jgh1Mnp{*X9Wml)_vu(WR7O?A}2=f+widg2~mi)(MXb?th(3>myaY$5e` z!nc2?4gO?An1Z_-yvNrv9Agih0jI3GVCggRV@q5jl5u|HEtK1*uhH3z^-d{mYtM{!1Yp`#&jCasP3AUH-?1 z+45N5U%h%RP~q04s!`CCUj8ur3YV!aPZT(G_NZW09~n6-6hMx(xl+{Zp$`SK<3jsJ zmsS1S@CQPz-HHC<@%Ozq@*68yzP6HCm#ElWQMHb-XEy5Fb?Q?wU1zGwj?k8W8}38P zg^Aw_I!BScv(l=*HGC53a{FqeUmrf{P2tkj`5F|xVFhK=5_-sEbC|^Tfg0 zU+-XG*`V#c5RRhE@TikFs$Ot9z5HDGGvs_Vy2E~g^az=1SNuiq;TpnauTIUO-1sAK z<5*uO=3Ed%zT>_-!8MO8GxEM0@9RqC-OxC?ZtV3C14&JhT{rfcdoy5JyfIUKB;Iu+ z*Fdad!vtl9<_WSKkl>B!(sZN*cYin?czAvkws=^+t?&h9LXXjGnX=f_YiB*E*+rwU z_fl;|y1y%ppNsz3xx~pvL_{SUBOUnFMHKvI%A8bz7S_c@sbXrTD#kmcd3atOSCF4t zk*WSDUi>{cZc4(jAv~AP|0oL>T&NKlIUm}qlcnmzi%{x1tyCpSy*$FzLpslAA)f;p zMBf7%`~n*MX31QADN0R^i}j^|CO6(uPobL_SCCJkvBf7s$D9Fcw83XNU{#Bg{ahYi zjecgJAIr1W15VUw9T_i^oh-wL*P=`=%FLTeA@+})hBOI{2)y;R5gOf)uD*i14)+&v z*W>;I?greS!`+Dcvzo`Ns@B$cg++ zca^WChOzI~bkSneqZafE0h}0n>xsjRFQt@3jJ_bAg1&UMCjNwGq0WP3ErL@~uTD<* zJ@nBNzh3l#h9)etFQw-n8YFlMOU<(Ah!1=VpPh^y(kFfyb%GObk~0NL=i-nkj`2-% zcnEFm$1Gdb=fE#35Z^%5OB14hnsOo5zviF3b;HK%*52B9J@}BYf*}UT{Hc%^3SES3 zw-WA%jc~WD}rRZ}uxeJ^PCCY$MCzUDR;@7H9 zACdr5x%`z-3z#M)VcNxg0UbFLo)rqy&46hVVA6x4L_cG;Xe|cNqJ$Qu270n#Tl7P; zN85-G-Vrq@e@;GqJLu~fzzGln9h+EE`9-`5>+`htG*+b}?rf$Q$Nnb2E%bTqz(P)3 zx0jTg0*qV|_-O#VuSZv6nNG^n<<8cQK<8#w(U(lXGi;6ZirCr4wKz9(jUPvKdrg5T zMIIaQkt(0J47!*my|D;Dgm{A3e9S12N^F<_FjS>8xgC8@w*}3PH4+DEU%oyb34zIw9|M`XJnx-H>o?n3caoZq{gI!XPLI zW#J)kDv|ZtNUk0_6FqKv_iYhpOtvT90p<<-4ZV)gOZvbBvBg`zL{9|D? ztPq)M*@&;_TG)V&`F^V5i)(x$7~VkF4XtM&49>$$8~rKPC@g`Er4mzjAQWsdZ6M|J z&8$&h&oWpRnN#%S5v*IlxNq^28bp%-lT6X$2EL}Fn(4#Yq`uu+DY`2zhYnM{#MZqp zS!UsqFy8OO^Q-1<4+K>$0yXPX*+FPBfwd`6#Ti#o3L`{7kwIYw# zPE*%wHK^~B?)AmOeO=pevctwr=%V}agLuoxncP4$gJTb{8|wL#POG{Xd)wb5@S`_ zI)oEV{orJTbY((f0^?YuBZTq~$_wZ}$a93s7q;%An)|wTSEu#S(_D@vz!t`3>btC< zpuFhxZj2E4!3Z9XGS0jR>nBCM*a7Lj%3#k6`4~mwxBKRuxBt1cz1rrz8@uk@VU7<( z&D_?g4yRP6l?|R|)cGT~M_J6&*t{G}zR}^$wvi`L_OU31i^53Z4w_G-V+Tq`zy;WH z1VIFHdg~2v50q(XA|1!+n?MGYifCNhCyCb&8(?`)4D=^@4{wL|We?{8mM^j17<*xj zptp&IONb*+bkwZCWy6&zPEG2UjD3n$Vk+L{LNmw|^Pr8=wkLU6NV^6(J^Vwo_7+;3 zh*ML<(Rx{UzaqjuC%nGm15Oo%kC;FHO-+vFb&GL<)p5vbfR9gp)_L;YY?2UF~Go>warMaXy9PJ#p9Q)`=Rh%z(^Im6;$IS_D5Zu#8fN`7$m&^N96C(8*ru#Qhs;MQp6BWzY5x%2{K-ak0=iNtsR-d>N`9(OPZ&sP&|*^-M`!txFYW)~@xumN!#aty|?OTjEah zcs|Nwiq7bZ3{!HaOv?6IC0hH1qXUbnIS=IfL3TF;>zy}GfM5Yt7rA-x0X7UEt`;FY@vY5E*M z+jxH&$_cbAy`ZOA77{XdCn2|{G9(>m!&1F%)z(PP;uNGUOCH3Y#&oBtuf+8){hS{^ zk82XlUSo}E{0uI6`8T6)<-^7XQyWL)x#?x=j@91RWtUh;Iv2~6IcTmv(ut^;3Z2WQ z8WU81u)yY)2`j!`>aA#PGL>?&xwJrLOY>zzX`XB;&4GV-lAHqHEA_%rKKya`AE5P? zm|Z%`xmTGS`7TR^P5tvICo#$4eVyw;#@Bq;r+0}tC8Zo9@6bw;SASx+S{Mt>CNyY*D5@j zoIjGy&Z}hBc?HU^z?<*D z267$=&vRL{9QdMPw_r8-d|!AW@cengDfJ@i&IjH2{&2PHo9G_z35P{mx%!l8PX@G{ zinhC25Tzcv6Fd)61(jwpsf=O|Ev@sF(s^m7Q9OF=$p&~q6Wq4&dbE2i0XvKZcAIyd zQs52|yo*X`oJ*(ByUWG-{tnx$KD5QVrS`6Bo&4amN2?1?RfpP;zJJ;i)j6l`t)6sx zTj-9WkI7@znWuZQl2I6$hp;@HoI1~y>|)8RIiO$tEZHexm7|6mU7)$sm-XbSg4GJz53 zVCB69t%ph3KO)pp?CUOGO6*SQgr~z5+(wGF-)`qkTpB#BRQpSVj!(72H1%Md#yoBt zr8E9|gQ1a8*Fb`Ibx*3jzsn)@&e_vsC`*-%Wmef)cq5~VlK8@&MCF~8KL=CV|UWxTidD9JbzHt=|794zA0cS&9 z-MhLB1a>>S8L<5%KCqO*7;fa5MuR=mr-#olO}%2MRB}5)n**jmy3G^XAi-jEA0)c8 zNU3CLBk;5nVD~P~H$Yo?V8o1B*K=k-O8_nQ-(nNu;>UZL5&v^7V+Sv2G}$d^zi^0? zf}2}St?9uHiGkTgc0>llQs;So81>3om&sSSjVB zRF_XfWd9f@-W?JBM{1lN(Pxuv#SGtDv7~v1XG!B)>0$qZnM-9I|8S^d&M$6XD+OF< zT2lgRr73Mo@Oy3BU4i?z)k!VuPc&uTRwo74vlSCvCWlSEZp4IH*%g087%n6dZSm)g zx~+L`-KL|CtX20m?`QXudmH%{q1kP6rwffvUZ?hI9_;&sd%Z<~@lSD@CqtGs$kZ=e zf;<^{dUX<{c$3^Fw0cWji~1>jT@jyxm4*}k($7P5tR`m`c$N)Z2OI)+VGHnUg>;gF zdPcOjS!niNg!Ve)qMwes5*Vs#F7;G32F~%Y6!;~LPQ(cgw2ry}NwfC*^BC1yQ{rz% z69adQ>d^PZ_!rSJ4FBJH{RuR$tI_Mt(BlJ5I@JJs*`souztmHQxjY_tC`w20{{lbt z%ie^Rgt$SO+aK<4SK5_{%Gg*$=~#%4hY8e4mewl#dRv2mvDJ8Xn7(6+59d~Kv4bG>5l>@R%3T$zk=D#E2RCuZ@G4L7Y zqS>F6p3sPpfrhodi49 z)L#L@>BF{8<3^YCE7!#K37skGZwCMI3FQU7RfJ5}dukgPelJw zJEbF+WLedUSnbvfrgTLlxW!^x_BONCYsSebJ5J=-!MPg0v;A4rYc>1m2i^~`rq{p< zS0Ry~g<8@bwocu~Gs02F#P*e|*g4g8R$iP_E$(U3`KCw{{JQ{)7J`M~$IWh9*0NmVBg-{D z@(}FW28};70FK3|8gJPlZ1>)Vyo1Qot6#yA_6s>6-08jDl@}dbJ%2h&5E~o{ z+@Xz87kVq83t5AR{0{~~p`dT^KsTt!pNj9RFqW3Cg*;QbQEsH3$o5{BuJl%IKeCqI zB;V-0SxEb^L9+T+PNST8-AIPz@fD9hK6}-w#gF6f`dc3-ZT%O(41+QR1*xq62Gs!SD+?DZiKupFEwhyN1mRg)8EJz10{e*(IsK#SR%> zIY&*)mr|>LY>nHSr^^&#dta%sp;zKL`<2a;k{k1 z*c@(Pnpwvbg=zd;nNX572HW08r&4W$;U`v*I~euhp)Sx6w}pY9W6;jJxs7oR6HK$t zk?HA=PA;iLz5C=jh;+26AH%QL(ZDt9QJQNUM)@y+E9=&k=2IDahz)sEx1qfJM{-AV z+ZH!_%IqemGHjl>!{+X2ylcy_V?V}jbMGfP9{M~moj$wVXYl+*VGhbD%{F)2mQ$v& z7L~@fEiN~GI)(O?#!y>FkmGHR8!FPVLNAR)yd8I1KoxDEij^qQal3V^n_Zdgwc~ac zv4%^Ja~Cds-L>FS>@E)8HD_K0quPgF!#F7>aB7BaCBep5lH(o*hOdv#*{mzek;g`# zDKpK(m=&gxDVr?o%N(+ytWYM(OvP9>O+M^B48HupAfvKF^OEZ=Cb!-d4!|yhm>~KK zD<4+bTNbbB6w{jSC00*$<0nxaaA{I}o2lLraCI~oq3sh+X?PcU{&4hRVZS#OW2_%c zS1O>%q(sKnvQ73Dgt1f8bsGn)RgDH%-;J8}{rUjDzyle_u-6zEgjKQ)dMu~y$cW=a zOqCfslo7kP9&!!?IcIKUikv6)L% z|B!&)6MI{(CSwPh0tI@k1M`s8WXfib$ zyE7?XTT4%Z=pa*=olbd;AbOizypkAr0@6-uWOU%0AqT9*#>UZs)L}Y;Dvchi8ht&Z z1JR)@yrcGJyY!M{jamwR(6V{os*sp(Ygk^ zPECX4{)&8t`xx9hL;X7O>u9LS=zRWNC#)Mf&<7jQD?)R?Ve<%$LNlY?=}x^`>x0Vh z9q+P;I5lww#o~PM-4y5E(-v-Y;Kzyk(2@zbHbA1cBqjQj!du>jt_<~+MEdW3E9mQ9 zg-!KQ(9-C@-v_s7<#RxflTbbl^pYa?3NL$?qx_SJu~lS3TV}MCf*#5d*UzXqF%dL9 z5bYL@c-OfejwZVA?PB0f)!VoGPUxocOaNZPLE@BS^8GRq$jEa*Vq*A7`mLvDx!XlWuy2hiRCwFSz4B zcTBT0JK0Wad-mS6c37p_t!n9D`cswzOec2pgc-dR50cqBxssm@zHraw5f<1-*_}nQ16*sNvOqh5Zbxr*=*@C~RgXja zHbvM2t&qMELkcNf58Hs+Qzsp&9_srwS~-Ak+ug`#{mdHpD!N=yqpY+9TqsM14-cM` zPopM#y86U$RlXTky-vsS^I zA=%8OnwM+)+R=f1@d8c>ip}?6j$JOX(FHAgLWR9uR_kD{Gc`|_b_FIjQf3bE<$V-7FT#}$2xe7$2bmRboJn| zW7eQC8;}XnE2;1?0#on{YzLdhi?-_(n%0+n6mf#DFpZ)s*ie^`6*OYh-Y{ikXVocv_k$vLRGa&#o#<}(@9qO$#=MYILA6ev^W@0WN>ZO@ zo+7_+@_GA42NdYbY9#Gx-Ba3k_0+Z)V7j-u25KW-RN;JY6V}Uis3TsRXcsG^Z$qbz0 zm|>8m<~K~wWY91Ev0TL*;=PcFwx67osU>41#W^5FxX9S;5|Whs=QMaj;eRPwO_bWw)KC7Rc-+48G!*-NzK}H|zt} zZA0w*cBA}WRFBn6`~kB~HVE#5YtB;n z;M}@Lv>1EA&8Ty1gLxz6;%6Zbycn^b^Ha0<{v&Z7j?6zVrw=&?B4j4` z!c4PVt7Iv4SlwRG=-i>xQ8L>jlj(E$LWPmKh-H-p>zw-D4dBGzeq7Jr~~M9xskdA)R?mro*_^1nT-NKDhA>OY<)({JSwKQ0|2RjX`{qv$U& zc*%J+cA>`a#%pXoRQ=iMDcW0{C_-!%Q7(oLo>e!Z)Ndker@Lv2b7o`)q@MZ_qrqS@ z843t?Eah;LkLvMe^@ydwR8U|oU{lizh>kNU7S5m;Ih|sKgiWQ8&xV+psWPQei%cBb zNG5NCtbQFVM)dosTR+CvML+g+@9at?Cf-o~rsDfR7WBW|Iy!D|fTo ztizfzA>NIY8?ZZ%4&c166H)0%T{=wHqYfUPyM@oAb}}WxVtk<%@Y$z(L&m4Tl@ZBH zoF9NA1==8$0fKk2y9YzT;IYuLAk)gURJB&M=n>z>sM5%9qf`Pg!Q*A)-hh0aiql?H z-XH6QfyKnvW9RXW*nuI$`4D`WbAs#su3RT`DrCkfX}-W^zzIej=5-=uU_|P`qB9n^ zQ72SDBd&t9r1J%Vd$aoM#NVP!cT1O!&Pd>DLH9I)ML!UN#S@W=^}Hpd!&z2DsNwvy z4%CquScx@3<$}tdrCvR_{M{%^h1LTpe83BkDnqruUu!Es`gw#-7Z)}!9EWXqx8tn*qn_Lbv_ z#;O>gnUx4Bu+ZwCqV@GOy4U$N)>vyRi#R7e_j#1IXAji#-cTKWTSH;|o(S~^6nvRC zozL-32F8C*p+-!}B;f(&RPMr=8rbe9p zdR}N4&r4u0`UJg`cGjq$1@-+082h^lLb2!)qLm^C)M+`y}MBNIO=8uIq3qL z16tClRTLkszpj1}V;RM~r1Aq^I>VTkzPpoiV-L}}qPf%}r)o2`6xg6%fkWE7+5?q6 zshBAj>VM|l)pd80@7;~appU$FYq+Fdnf|5JXJ~C+i8H2cP1GKjp+1DK7Mrj(4TR(aD1jJg6;xrzO zYoT8PIVzYTBOFEcN|QJPeu zkNQuUR%XDbcKRc~d4{FWHp6_{ffEphK3kdYv?EjiZ=RVuiI|_joCnqqlziRz!1}_b z3pPBkenaym?kD}Pm=YNYa*1aH%@2JYd|>^P{^yz#X6mm=WL)BTu5q}8mV03RE9OMT zD=7I~$yJ*mQPd{zK9wfpGQrOzv7$ApG7T> zXw>RB8zr2sJ=8>XHtJip;z|Mj4Dfm)egHG%jZt6z3!p!`Vy=LcZ*agX(oF4j&~+OL z=LKiFW?34n?mN4BD=f_ucnf3?mb>Zf=)m)_ab9(WuA%DEPO#C3D5kqF4$-(JejaQ5pK>|U-x~W zhICMaAAOHe!-WEkPp;7TIDzerLidfvTg}{;kpAX?`%u34*C?4aRi3F)WV!Sb$6PD% zRq&x4%4a&$)qSJf)?sJ~hqjzBdtq_qHg#=D*xhW$ZDLzX1+1+tW@VOE*C{~{x{KDO zUKca`T%}UHkglCPx3%#o>`tkG&v_0vsRF)w^*y{8lX!uqgpv+eUTi(kE4VS+DwQ)d z-2!7Z;JyCbNY`PcpGDVdJ7lnldi9O)?pJDfs}0};af8q>2GcR@1)oAs{{$59F(9HX z#RvYJ7@w~d!n;v?ApxtEwnIHSDd*b3se*IuJUsFST6itWCwFBNP6Sb{hWff$oZzCe zn!5usPP@>A{lsEhor5UyRr%@amvL6J%V@K!&Fc0MYOA3Uhw*_OgVgSjev);i_r?bv z9NY>jn+ZD&BXNjK%aqHZOOEkns#%sLHA_SgIc~>^)z{z;X6ylK$8F@K10km6*k-0Q zH4@kyKx6~tW>EHjVK>mr`QE8Qy1JOgGHV*l?ijUXK|hhQp!?>@*~wkb*TYFi?U0t5 znNoa(gulI_6z2ri!tOENk6p4koYL(T>FRdP8{HY8ZPIz7d|t0hFyrzel@0aqr6sz9 zUCiEezSlpQw_Th*cgz~+hLnGY{8e}Wa1D=AYvsvSD<^u=T{(e@LhD{qrVo5A3la&n zqX#))3tBec7i^vOyTf^kE7TxW1_ZwqXRmFZSm3z7O-oeVyw|70x_iFTff{ z)NF%4z+P;f%i&AVj~}LT3C?G8$9=Cyzw2>Mvd7=h9*b$8?*t|W+0E{0IH}ftU$9zf zkmiI~|4?9l(`)9H>`HPbBhM2r%yVzkZ1{PeVWd4s?2f@k!TJ1&e6rUHTNqunJ-&tC8^a3` zX73xmwNZBS$<{!@j>Ar#b%`DuaCc#HB==w>_}>A}Veh`6ZLUJz3HIiu0)LeOvez$` z@eLB$n~w7#__EB!>|A#)ta3>#{VlQ{RxBfCEeJb|^*{6^UCl|PJZ7GJLDl6q-}CUp z4?jk@&69an(@qTX4&l!5m7vLqqlSIy92; zl!T53#O8#Ham4~kYh{pdM}u?E)$<8AhJS{7e~pi|Ifwf&O54<-&3a*N_yFF$pL}-# z_qO(q_P0h@9ey3}ejhjNwb_}#g<5}*kN;(VvEZk^mp`HH8Zj0V>aP@P!~LlLEb7C? z9JolU|F?fpUuiuGm@8Wjga(6WwEoSgUo9*M$58*CBy1ORJEPU+m=Io! zSf?BzD_o0K=c84tEcyw~9Nf!sK8|1ICZkl(@jk<)t8a{Sw$}5& zlPd%oWrL*LAxjbinK&9K2_9$-V?NWAW8`p?CD*#~aOkaI3t5@l*Se%7tIeI?))F`z z#`n+ue)^A!u9LJgPmi5JAnM8CFaIgWIP$5Y`c2@j3GSHJ;hLa)zn?>){@`b=_Ljf2 zme!NKGqkewT*~v_1(=bBkxv0<7NERHgHnkcLkUV_o5G6!yBy=1XYb9R(r*Uxn zQ?2Q)(t6PGP(T@LEpWKf5eir_>ZX4x?QFI|chuR#8@_`nUEMRZ6I${=qUVn_F)%5< z8L+Ux>0S5&O1e5_WCHfyP++bG$IbuL@(nE|EwG_(ScEzjz#kB{dUF6j8F9ANLzf$` zx8htqgS`Z&3+P->SW4UKS~$L}ZGx-5es5H#R4VyO5!#|s+|9yz?*(YgScJ99)0A(}#W zO3~JFCPyvsZech&8T~TT*=^Jkr>7EC19(*nqB(eDyWxNnw(%*D|I#2Oo{dr)Is^Zq zIe5ZTg)!~ifG;HmQj|f9{!nH}CF<9zC~yujd!f_59fPdftSdH%8A0jZqz)pL3X)Y!3#;v0zfa z!VXUH|McKb{#%c`(c_tj0X;5nu1A2{wFP;NS(1*-6%?=i}qajtIz`lf!A z4p6QMmd7kmzqxT|@QvUT0ZPf>D#>{_sZHn;-wajf44#c@nlH*hA3JZJX)oF6{hdfO z**DG+k#w2n8_r?-Z-eL0^DDr1Pc$IB7&X&<0c}pU8}2_J(+iVh{Wf;szxDPWY+?U_ z-X4m6-94Gx4Vi`@qRWnNUZkrBhfFh!#yms*jEP)t!H4)xERDE-4FBJYL2kkKMN+x! zB-Rb3M!5sN+f3M>P2AVfOu&0EhDcMH^IJ-A<_3DX8NS9MNVgYZ<$f5wQcz&~GB?zP zm|%aXD%c@muWzSxe#fBMS=v`C1oD3$P1V--cV+bL>B^_z7n!g^r=5EjM*V)QwhqbA zuAffZxE2`tOJ64Ut7y7b%D$Ot{8C#7%(ih3U{Vjknm{S=#@K`BaR8hE1@!d)MY<1F@O8~|Nps?b9v8uf1mexpXd8L4?M4MyFhhV=~Is{qKAi+?Lb4*Uc;^&y#i|p zl5bG9Stwt1Y8Kj%4cSRP=0=uW4<*Lt@)~%iYET~k=&~9pAfF-8tWhaK<6>2h_D-d_z`yZSpq!9%tW&MM@S z#%J%xfdm`&&O!M=56FA?)eZ&rtsU|Hpc)pgnU*Tw6-G4>9E`63yVt);r@NrSo-XCv z)vzY4&DZ7sHTY-$PqsbOlGC-mP~Y)5_>lv)PtQhWuRqf;KGRIf-U8p%CKh{C9zD;L z(cE~M%a(k{f}H;tT6A~EMeN`@=vgR+Gao0wT(fRO2 zkRxf^Gw@8$>l|780=Fz1a2)MxNR#Qu|#4tapjA+xB^wqU9sJ z|Im!8>Nfooj>10;&bAxi&w`X*;Ad2kwtk=~lrq{y3xvig=(@opolA1(`}%;NelyAT zLINGuESf1Yy`0ZdM0aWd{vki~DSA0zh}6+jkP+y`H+lBJjH;Tpj-ms%-qc8dPx&){ z3Z5xOV2PX&J&0Iee*}eo5b^_3iruzxhW!Cx*nw>U%_*eoXYMf#J*nlE&phX{-@n=E zJ+hfK`a56mRD$k#TEG0WCke9OK1rTJ!f3Bc{g|;vjH^^ z%aPpj{IJumE}sEAW@<&Pj}|53nZFaOSzIZVm>Lt zmskGzD^QiX!BeEB^uf#Y59%pN3+kDj?2EM*%iGPO;CS8S} zLUOPhTFx3+BOhO@HIJR5&#AxN_mVqN`y0`#hQsG0p5>WC45a`bzr*jNb)1adoyh!_ z9Wj+yCAp@)JJGX~3G-GKdcGugU*A^Tf0g*Q74b(w&s>9DZ`m_Q=BG`qjegAH_k8fC z4E{DFdc));E8_T2jf=IPYkQ(i#~N#H-#UA1DSLaMx9G~6k~w|wC^)N)omUW6F31;E z3(7<_eys~~PN|E)u|dOt7<36O=0Y}3KrBaXTqFK6rywJA1gtLtKYZul6+~G?<*=im zX>qX}9(N~WmIQs9jQtb8hM{Zgx(>})X7Vx>WnvC+IuAE*@IGF6s##l{+mRNyrDH|l z;g0UWsg99Ab|*7H_N5oAOd8CLF65XNCZ;IxKeYFELQe?eb1${mCY&CU{%q|0@Tp%% z=FV8Awm(xeOA^|QZSa8=zMrFTu#D(;5?q`04oYJn=?w2IOb#;AWbE@vJjL4L8euOB zIttHe_RX`uhBV}zaFspf=fo<@uA#Y(m7o{k`GbRW1*k6#&q|I$ZMouPE$LW?SsK>D zp2oVd@Gu20Y3G78O7Dhfp~b3|we!0ftYRwp zWy6$@(e73}&t9QFNMq5FM>Nr=vDZ=mqIuB4!o!zi0;~3ESQb#cisC^sZ&ajZ3NEFI z1Q?8AKXUq1R5>EtM?eXaQUi1xf(PrkEHPQdRKY(Cq~u8xv)EtI zW6OpNoq^_@uBZfNauRxDe1rX*h4xbceGol)XW@?w>CHx@R$$J|Pv{G|l9GZFv#F%4 z0A9uMJPr7#bm-$Vz|&*_f0Zp|qqjT2-R#1dWH{{t158od)d0Xl*l&cdG(e`@@t z;|~}=NK{YE8N1eBGTZ*A!R&dn;KPktrK&}pg!$tsl9HU#g7|%$!s55(iC3UL?@wmW z$jzORJA?ioSMoK%m{<8}M2K_ArHQ4`Q=XlURpB{2%|me+1U^XJ zk(2Z-#!<@VSjh;feI=JlOZ8GJax;9WCu1i-;Z0#KpfCp605n`WAb@olkfrX#+Ds1{gCWQ@3}>CL@2?7i+tP@Qvw;aXTM3-LZoJ$F4{63Ed2fU6YX;FZ0 zf^CX-SQ82=u-kxkk13?o8~b1Y{-a=l9LdhPp~_2hl% ze{wyOCB;^y_h;~pbtj?sSGjmPhk0_^&ZhMVdz9)rAsjHhMDiH9hur1gU0}kpgy1|ew}RGoP5qwg_-Y>nP$Is65<;|!7~ zf~N+p$N^^y4+dk*0K;jb+Y_Xu4Ble4NYE}52D~ffkr@pnH%|BRSA0AAHtsK>o%nbkBPZpKPY1Pl? zB5f7Y4kE2yPOBamo~@`H9;_(RMF(UJyMlWPHTLhY?a)FBf6=d=uR=<)tsjWg;h-6E zwEYn(e^4WjeXxvrW3nqkC7IO!0Soyg<gWoy41G~YN`>xy zhlbM@hK+7Y4Y_uo#(bKgmOqVb6EWGEOx+#+r@A^il>1Vr4N`nb=FyH*jRIwUIZ4kY zTszf7bInxx0WS{S9ApiYR-YVG+0&%)*wKky(8A~-%g9?Y`;Y0C*~86jmsg55oyzE6{0^ynh{B0Ik+xX~!^GQT#uY<+1P_T(;n2Mogr>|_PH1sPFn`QZkI~9N-8hfJCbMFJ8Z6E0&E#$;?P@f zPBL>pfhJNJ?&NpKTpv5u&cpf(9zch)>;zw<4P@cWu#EQ&Q@=Lwpae>K1NixL)Zoo< z2KOUC=`*4qj2??L@tb5`@m+Y%gH#_LNE6=0{Y!E^8k;!|vrGpjM&efFtO~1$_A&=203SUIhqrXb-l-ylpAA^;{ivI|Xq?urk zg7Pc(4$7k&^y75+Ly?{gQ+0U~Wn_mh)k4XIkhg@q8L3WEN!%{Cn>@z$0y!viWOU@% zGsv%ukx*Ck(Nb{cs~6GyW}s%FMj&?DwUtTe53Z32`FM&)yvNzn(tMeI-~?!(xxEjZ zvw#(a7|MxaX&^{~0h=a#>s&SR&6wi&XG*us)#4sfSNU{I`yoTp!*`HD`VPj5%#VY& z3Bl505=ixoXgCfX;$_~5o{o%SUPDh>#rUiJ)joft-^aF(7E@gwEKQpkr@w<*Do5+~ z9O9PIeNym+8bjEzDFuIG+)xHf=>ysTYtMm|%b}Va#!#b$+*K2O6qd%H!NV4%ZSV5$ zKpveD-5;maN_ply|CVD3?z`e0pab-TQ8O;1szB|};LL^Ev@@`h9OH~;bV#N z%aDNp!KH=FY6iG_9qu@n*%=D-cTnF)lnSMz1q>vvO7V5>CCIolqD$cM4ktc%OoF-L2gd=nQl`#b@@AturB8NyV0+_QOih z2dylx{3-A?Kl}!7_89Odx1H*B?6rMIezpgg#2@o}Y^zQ|KL?I;ALQh3{h&iD+%b3=(Kv#nYIT_LR7!IZbLxvMI>VG_}9^l;Y4~y&Hhv{fg%HYG99D7o? z;w>L|q5DKuqQ4DvpX&CjXP%*Vf(xe+(3=*N1fM|?MP+($eF+z-lyRyQG1D7S4G1Vh zhcfoV%Nmt}VIS?Hd>K=ILzw2aOw!UkomruR;G=5Ru!qa_Nk3eF3Jn zOJwAxQY2nto-G!d3s2r$>nzM!j5tO65zS^?VI&;oBGDggb)L(fv5(nJCGEA4YTs0w zH86cK>`0?(?01xNT~6hmJ8y6d7akpKfE2?}nOqDlRZnuU!p`nf^e7hV2b9>8pGNw* z;Va<-o$O8Pxq`nUSY=u4X6!jj*?r_;X1}7xFrW`K2hqPSP4t0LhHMX)^Zy8BTY#g} zA3@|A@@QpMLmSy!Y1cijiH_lv#A3faJ*tjm_WHIB>&)nxj035Ak>af?NcuVs#?8^j($d1 zCD-DeF*?pEZvWCa`8!ZT7mwW;zu*%BEf;w0LCC>6E;yL|!9tdMrxtxJw{m}>N-pbc zoFN-f&ah@7dQZJ8B$uI)%Xk50_`4OHkM-98KhNqg7yO;{nU$l+F@GnW6~`RfgTX?k z;}~s85o>(CmQ3~J{z8ph#GPh?SQX{?5AT@ZK9)flB7nf1!cg>sy7+?^JL-! zg)y_2EMl58;1;TU7lU4(x$9-0t1Au~`{@VKA*O_${Ha`)TKdciE5XgGjJsM!SQb}5 zaqMbgItV;ke0wD@yVVC(169D%-Y-kkG~6%VH*hb#A6)secj0yB=BmIVJ9mS3H*7t& z6RzB@exB^ltYjWeE|yn<9cyB0H55+G-qv`}`_!@}{-DJ-A2_Sv`&28Ygv>zOzuVIa z8y9AmI=U?hAC}lnBv5)_vSdbc$|UeFFJf^EPeZWRsv zO8-rML=zQZ6}N7;G9zrYU%Hq#aj#gw*2t4eySC;c4f-v7ESbC zdhQBkLOl?(&AxHN=M`6IWG_2-VRULVd=7Y0s zn3fV4w%r;Os@uVoV+(s*04Xip-_BJhC7|EIJUNwSaU^X}?qlsynW$#* z?WC9#9UX+ew{>_D*B}EtY#!#o z9dUJZX(FYQXK+%ZQtYL$rcy^2Lqbe~RKr2-_0prOCMdE_m%JW(`8XnRTDArcW!e9= zJL@nLln1eMBGs2k75O^+IbV#uz=XZP@XcP}w(Gk#1d+<6j_yI-STPZMHz5IIuMj`v z!FL9$eDE*dWVZh$0yzj#*|k8SyHTHyu`-oNeJoK0t!33=H>9PBm>W;yh+OBk9|bRE zM!GM6%f238f_pefzk}CJ`MVbq*WjIFNs(e|A*kYuiXJyjHc~Z~m z{+o!E;kn$)hv_@P^OW~fj4cRqDWF2HhD;}Avrf&CKq0m<&?LC++g2P8uAdz)c+6HLs@`tn4F&mFdpgJv8Ax@LOPQsLu%c8g zWt9DjWiS`#qV(6Wj=`azo{8AsC!de73&vmx@LYuMBDo?)Z-Pn~8ti=mF0lW>zhjns zj)<}9=>JZT1^K97pUd~4)(5%1cNjf=2j3M@N6$@U$}8L#On;um97ew;=r>_}gBXDJ z5h@LNh^{aN*A$_>1kPp~jRBMiT&p`WtQiL-OT^w9gGZfHH-T#WFrqDG;f0(nl@YX? zjo82ZozTVa$v#LW0~rHqwC6r>K6L&@CYMLDNM0`r@RVWJ%TOfSif)KZMe`C4?AY4Uibp*pqyr9H*|s zmIuo-M%-nac8VebmV;~6gJNfe8LUG(yVIuDdt@R(*HZv%<+K4f{9-$mx>G58BW8PY zX!jwsmSn-YL~)QEQ1z;#|3vT6wSRo##0Lg$|zZtI4VT70R@7DggG-7YZ#{#o6dCCL?{wfLn_>^mL+3{)a)6c^J4cWC`!X^ z@1By8C1TdmZuAAU>7%oq!1E0||K?NA&HnYEhu251PL$^xmL6~KZqH`(YXUY~__v^0 z45x;Vm#q@}WL1FCY(7I4REq=o>V3z(-QKH;ve{n^=GO%C`)u>hQhKI7umVv>XR&ED zkJ(J&VRi8tHT-o_S)ID~`TQeZpI6VS53n^nQW3;jqO{`Z7~V#IGe&xe`TDTB_lUQ{ zt7XCebQ@3$7Km?(Rk`%sP~*$rGq_M1R?kN(H3u1c_N~@J-=G0{Om*~;F||wwNU<+y zFhS3bb%mLUJyad-LJ65tT0gaC2?X`sn&)ZhopR~hw=lavlXhnwEXEk6fhMVnKLKU(VTaIAZU9=B5!PBzh+Pdx3cIfj>lM#^ zf$2sEo~z7R(9iqe4<;K=nP54zoZ14akxFTQXl$V@V2NiqX7Fi<|3|nt!P88uMbrtO zqOCysBPq%InTtHK$zBpD1zPq4wd%|{qDADk;qKKwwRERaeP&UZes6SIGSAS_G1N_Uy!Zbue-URO-&x7l&dsn68=>yCJx^=a_LMp(&dI9v+(Q5pW` z;;)+M&6=~iBDKUCRZ;;g+gBSIDOfZz*jBqw@S?6fX34z{`mbkbV_m3;MCXi$whn8o zVl!-hd>X~+d-}YXv$rNfTN!oH86Re63t!*oL$B518Byn+;k*rqmNo;t9F4uWzHgYM zMVBQu@g8T$ZE+^KdIw{nV;F+{(6lqKVuLp}R=SfXb3TbU`J4L+(CQN8W!1piQ}$D) z#r|PNFGAC6wAV4E&X$zMG!HAPK)jW=_1#pJCXwjK*jgU8_H!uCjQZEl=C19tGHHlB z;W@0r_c!6sk2Cc?czh($!7(adQHF2g7Rz<~XwvBpHCXd(j$^`7-sZ4c7{nY(udEid z)2?*T8qY;9zuru}45!mQ+f!L5xQ5lQXBo<#6_!BqJ7Hm*i&rqFS#t`UsL!ka{vRyR zylZC{cpxhP4hM1wH>vnoWSpQUURno_7i1an_{xc-fcqhGsc1&@hcNa)C%buw`T>v6AV;x*mKR z$$`&YAAI0aU%0tQ^B#11IIxxy1tBwtbqi>R(vb3zTjwX%m|W6{$kz_7=NL3rUxAW# zgW@X0FCAZEKGew=o+zI7LbCjsgBOM(AH#crW$CBzt9?vZCj=X`d7t1pK?DH9;SV5} ze#2;~IwC|U)f0RTA3EN!(6|4@TZa3)!^#GPx6yvf(qqEA`0l~TS@|wdABg+~5^sRn z8WNU(;E((j&jZ5t$Y0@U+W?PnjPMt%{D8A1az^gIu>2hIZ($>7eKPjH$v5Pjv@O(| zO)~az@+i_>jyV~w7RZ=a>o_;%&xrAt zh@nZaCr~Rtt1%XN&&6QJBqn`L>KSJmjW}Ht83C{1HG{Qu2i8aiV?2`UV&<{ozvEw| zFHWmTz0nqrMzX=fv*8P=uS^9sPr{2e&0lGXM;h@I>5*6J8EYJk2=D=2E|StG_>3CH zrBmxNS<&f+`~m46xY=;S(q`f!YJ#UB)EZAYZ*w>A!>LLEwC1&Asb?=kH*i5PI-P>k z+2?E&%y#&xED@I7BO3)@(8n;1W=5#o{M0%9}8 zZiVfLuo9zvovUR7Z*w)&6IXwIIqd0m;Q{=s7H?m%9-hn6tZwgt8rYv3D?Jy0A27i7 zcE%)Q>~GLYS9`vS^nv$hfhg^R=7`$$&YWCza~rk2ucUO{f|CdK@2zbvop(eRfHaB$ z1%*BswkRa}oA?d<8)bAY&cI$(0ormMG~(;ThY_iq(y+J2XjtjU(Y-wEoV?3n3fcN)~zY}SZ(<NFbr%Qtlzjfwc?CwPBi{E3b~?{{ z@NcddKpPF{@60fdtJS!|Ea18{&=OQ=-l|1^FeVfAw*cf;ndi7hCmz(OP6y$igwFJS zoG6pA;>l;RugmSBZ9$t1XwQvkBc+`#{4J#VJ5RN|+pA?HEyKlPFC@&M5atzH&wmMT z3q|0B;=m=+H%}%^GM8a=)CoohDO)8djNHl~J0Ng3Q)?$?zCxVcXXVmxj<{Z+l64p8 zdX+$>>(pyn4$okAXF~3rTN`Be2?j^43nxaPa;C$xxD7F>fRhC6iNzYg2WaHfzz4x+ zJnfluYAHJCSx&hWLYx>s@)g?kS*mU1^OR3?x*u%VaId@{kS~e#s;M>_jQ-2o$)b!Z z_=H;ISX8U^ygz%I^HJeD*e?-X4{zor%H?*J({BYDAHeJwp2maoFbtXGn6dC&#}zw< zLA7Cv5l0)aQW#F~%t0L)$>}iwkzkZtqC!gyL(}E9fHKm!W0)@tu$@*feUmA_!RSWy zc%u+A3ndm?*h_-o{5MYZ$fPv2Bk5hv^2Y6=t!a3lm}Z;8VAfU1Udu?SRlWH?33OD>5&%A z#uL{2YVnAs!0O1<*RU8D;FKa8#jUFBM+za6MUMLDXYey_h1X)v zQ|@&Dn>E5{Ye3Xw$xbGC);Sf5bK$-L)EW-HWSI*6>Mw{O^kNZh!vK6gYk`iSU#Nih z$h7ZL|148IUvcuazE|+o9iu;+^ZwwR`Q+T3l5)EVzM(9z9Qsu@NAU^q@{e1{?kVr@dWYDOu2Zw@te1}m*3XoN%dxElQw&nUqTXjmLI_r zW($y!JCDlPBG2;bEl7hW{++g+TA+=PrWI-M6|>{$_S6%9t7o}yyJtCPVcSO3Yjtax z5jtLo9tr-tZCE{w*+t*Mi)5yQj@i^3D@M&Qq%zGx4GX@hA@1cGX5)!vsJgIohu)sg zp4xunj{Vzb0b86~bI;0-?GM1yyWuRU$P~5kqJX#qC%b`}yHv}8BJ5*l!M^|}i9e&> zZoAb{Xeu8+Pv?26MyX#q-%XhBSkc~Y&3^5E@;K~^S&z+2+hOxCz;(0OX%*mClH5&w zPh+kMn3;?bJ|ux*`~Uad)qRKY-Hn%hM=0`8p2_2>8J=}%E?a@jp)))tKi7TpoJ>9c zRDLe^u)HGB8l`GM9O&lr71h-FZo?Tw6&N{Vzhe1I-py_m8zOMcxa~9^IvQGzo_T8kAKU}CZ zA)=Z@2<5L^H~r9aXKRX_ZcT@dhb72w5#kShJBN@XgdBdCbmosB2fAhok?IIEn@kgC z)z+hJsaaLsgqepY{;jsHQ!@`wm}aDDKRWd!r4L1#Hrv!!4CWST!@OHZV1p#I5_bQmNO!&m}rvNs&H! z6udp9WlWI@v`ioUHSYg!jW5;4Fr<~gdhVOAwDMO^;vRb6X6SuUSGHa6v9|LVRhm8% ztKuO!JzdqfmsiCeJfUlR2HyIG*QPWnZStU#`Ow zTH8xKdTBgpUtZR`-;BtZhnmjFk#EuB->cuxoHbv0?p^pA_hF_znlRb_QAlUgSF$udwYq1) zGbP;tDY_ARvPmEPaKdmn@FXEMn4ff>CWf+5I%FJn&Qc2RoWfPsE14d}BAh4|EfASS z^TZXBj7aiHut*a8p$=)c)ZuCgwMZ?Y&C=#jv((JB2rbOxy)8`fyq5kBbEkIm#m++> zS7(3o#b$1cu!T7gKxBGti>1labf{@@%b}M3&IBkEP0K7=D@xtKu|L4}3=?vIwwX#u zFLsav`KIcc{SaN9rEvM!Z1O@9;!_C)?W_@x#Y834Rt~fQIvR zeG-xBz>>S$VaK-6C6+F{`z$HHQ@ozD-tkmBUt`ECHR=(&U2E@awrNJRYqOTEaOZKA zkKL|o>#Dg2C}(}NW5Q8*e2{QziSkk9dBCo=ttmJ@Sf0lhufP3a+cl@SN?qGX%?Zu< znI{X@&dyQiWG)fAFS}bLuDI-Oo|tyo-CXem;@DpLu2}58>~4;@;9Fqw>k1>>;WNm3rw1GFwFtw)ZmSRbU=h73=J zWRh*F6sPF#$pWQR?=8l!q4==^y(bwvCTolDYQp+Fd{i!1nJO3O&(wG)3g}6NT7}Tq^BHz0{7lafo#_4CFezIo zmspPy5pBn7_B<=!Hvuzz!E4Pkdp@LX1Re1l-t1rm)8F`O7~7)J=NkXn_;ZYB9CYL& zPi0Lw#g|!VOr5g7uY}C(x}UfFv*o_lpSLb-HQVoN=Bn(?7q`=On22?Q*75O=ThH;k z8WFi@3ul2OJN_4*$M1vjwn3Bz~w( zXjYp(E0Vwu{yOezXV4!+{AbIrcx#mv@);s7Y`qq|$@;08uImIY)>3M(~Kec8h9_x)!N_s1n(@Q z?{1Di1_?jCx+neb~Yk>DbC(el1UdZYy}X&7p$BPMRydo4mU3%o=Q(v`ucS!yvrRz#vVj&H)Q!7Y=f z#_}0>2Ch$j(0b3RD?PZH2*H~xmF#L^PqAeTGsy^)NwjI~2Ut4{q<|Wc+eyryhgF=g z<(VyWw_yHY?u?7yb*N2HRwYQ8)@7tbU-QyM=;-(9zo zN;{jw*C59b&D8xuEIp@nlaiJutUOnlTZ#k zWCJm*wb!?=wIpJXCO>T9(1%(v4>OOk+uC!M2Jrm1$+A`f&(jdk-Hn-oe3DtX;&F9l z^6u7WTQA;AC2jD|>Lo>qSpHbQe2VJZ=jPOz?}y-B(kaFTS_!(FQBR`J0#gEw0NSwuEjv1zj8!LNbpq?xKPEf4p>Z<|6C zS`Z+_vo}JF#uh4pOvLgKU7b>*%^ z631h|!^$)qJ`AZKJ;gyYhjT80z33~eEZ$e@xFrlM)MR9pd5QQd$N!-1*TgL-MJIk8 zYa6q8fkq2+lyV{h!ym`(&;e{r)I<)h>~B{f7kJ4ZqjZlVAAX1Ss>grE_n-$(j?o@a zPWFE@N1Sax;;7_80m+3LJ&=rDl{_9ni>00DjVDG~&f+oo5MDIp@ zXNnJk`=Q9Vhxi8^^RRwsl-6Wy8jajXR~@uFN-@CihQ)<0dJb}$WNaqnm!A!F97@D) z9Mxd#4@}A$n6j7qxITUK6b!;2`h0qxj7)+Dzh0t^?hYUX>5(-GRzbyy9ziC5Ps!-7n;So4~&z`M{NwQ_&7 z!-gA}#L;!U0@7>Rt2d%ojpNnQcTw6AuUK`oZ67St8M|1iZ&Pf2%r-Mz+g5|$+;CT0 zCw{ZS$J<`RZ(3NtRnZP!F|6}i+o>#3<~Bf`iILWXK}}%WU9JsNeA&Nh1ms-!TDfJ9 z%UG^{^ff%5qbGlqSR%`FAq$uNe-JN4hAu`Vi;5~;)RIgbo`3TKhZnZZPgX8LuXV#u zz17%bA&_Vu&GNeRx0Zs&JzQChciSgTNU1PAU0H>@&69KZYmu^JJ55#S=&982II%qk zwv-+BckNiQgI*o&)bBj8gW`smUAainwR6QzdRM*6;82-fsw_c1YbP@tJ6(q=wQWb$ zRX7`;%p^S>TXby>-H|OJ^mo2Yd%qi&aGj1F9hzN2>4E|DVcUy@L=*&oe&BmSn+X?! zPknC74bnfh&*MpX323^p>6M_R1T5_?>`0+QnVJimL6;h*V+8(FPG3y?-<%lOC}qI5hx5SGQ5+~%@KL}9 zMr)H*@`_)Fb-WUPk7ErdVtS-_3-Y?_r|6ykTk)00YJK0tSB}fqm&aEo@Wew;MPGp1 zeF_qJcu|55G|5H#u0r2h6VC`=$2#IHhgBa3ms6n(C%J$0U5|H*VT~2STOj%Iwh3?F z!|4n}4S$>{hf;Zsbj7K*6H$wwa|JSLsn(%4)9XP4*Nm)lhcjGksksZ5s z^x5E1$esu5qi3O&PR1nEv}))WwDye4f!SChW8c*9PeXO^e{c|12j6Xii**gV*1Fc@ zX`;`KA`YJLTX>XTQb|k!8_<>A)R(`l2`jA$Hljt$PG|xV)nvPI*fl~l(Y^8)L%i1c z_XyMNC}cWWV|7ymehv?=V(jTxc^a0uRIc5JP=_8%gQBM)py~A$_y*Y?E$D$#oNKRw z7fBv|^R9-M$vfe34!)loWn5?ZcF1SffYNOhU*dZEh6#-fOTVgWYl5ayfr!ezye_(D z^4bfQ2ILj~F~7I339D@T0D6#Rf67NEZsXA`r@9Mh)U(K7mjkB)b z2pxIZxsnY9sJFp|V=*JTmyXzc( zck?yFD3Lkvgk9flbU*D{Td<<0&;9+p4fb1VM$jK?@2FX^uBIz*O(qGO>DmvH0`$|+s!u5$1-7tjXw0ACZTr==_9(wSap>@n60__Dq^DE-9= zW$%JorW<}_@-CnbR&uFTm$!*Te?JL7Fk)YWqBqt5#d80XQxhMum?NVf(slu#hmoHF zEJ+!1_DwLoeGR9ow0WWWKLQcmKgrlVZcX%0$-b#EoGs_^x04Jk-)X+OOYJ00ZwEt97{Rf#JJX33X86$7y zmI$qtJFk(^(b=FH1E69T9K>AfTGOC&X~Z1YNcX!dPP)He6D-h0-^ckTK6LKpD@|Tk zbwfJV`r6xRd=JOo`T*o6Ve3|mQuwsvG}cOVTpgW_KJmJ&sJAT%d+lVK>#jhWYhm8H zy@NLP{My2Gdsz4uGUwg4N9(!@UZF{aDs0MSKpI8@MKaz*|wZ+NUXBb!LPhrdQ z6903@HK2_@8*g)IUADc?7t9(Y^Dexl#YuuhGvN6JUZY&qdmV+Dxu zW2XM-j$BX#?}YN!TNU|?>yqFc4kR5tq#2yl;7&`7Eup39ToJO zY|g+Y;cgD6mmf`llN8(eZ4S&jiGByVJ4$E!W`2v~PneTejeiyM0+H2(=;?1%eT}ia zuQrXWb?Kr76Tq)z%}HOdKwGhZBx4VOUX$n@kmOCqeh02g+(CVMh&vScm*F-5Ba|V* zQc~v1av>+A@4uGce=Xkb_yNY3jDLn%pNkyU^WSr1p=V>59bdp(@R~Zdx71F`n7Qd! zD$s9lkL%Qx%a&Ev)GS+8LmW7{(kP-2Pp}6V*qFVTyokKb;gCz|vNot)>gapppLN@6 z*VMe{4i=nRnlvq5e4)Mv9^P%dHV^ZlpxR;0lj^Pfg$BQkoYmT;dT^(9n%DhuUToNm zQPH#}4m0+<1p2%^dA9(RJGa2`JnH%MSOT+HZJ)~n5nZyxQhIY5Y8gZ=(+!6788Zw9 zh)Gb(CG^}2j6Ss-SeL~75a`u+lG}hYNOA>^cahh2oG7D1)4&lpvGXX(_HI7DLt|F} zWiYaXl;0rUAZc;BREBfljq6RMziSNksyksF*oeIg81e_l*`6f#l||9R$bOgHup>}M zCz8`7N+o)@M&d)#&Cp?&ez@Zb^zvWElogy}7Iz*z#x9#ee9Lhj`Mia*#5RG>1xlsbTtJly ze7#r5k+!31a;k@GK;D!WqpGyf+?I(l+=l-kfqI}X{xVF@iziX;3RjvT!C@6q_- z*B~dOvurpy3?3$lQ|#{`=f1sC+dAyvJ--3=kaz0s=EbX>fz3Ue8B_XFy(b`0)CJWr z(9+7sUmr}vZ|V5(;BIg`H2Uchtg&6-_>!>#yv@V!jH$Ol?m1|XbkWvPCG5VFF+JYr zY);uF(+x1pKloJ@CX^d2DlFGp&V)Iy?rclJ?rd#yqrqb-h+F2+7zJ zNzdUPoP9jYA9iS$QfbH+K*~Pg=sZNnMr$`)g7BlyhL7%`xR#L})Ju>`3i3`tEgix9 zW5jfhLT0>Y1XJZY96DU1~~~YJ(gqeT_Cs=;0MWE z2DV7ewTc4;i`Ueo=pBP|5G*{S8(<+xyp7=Ow9&IkW*=;g#+U<*dFtq|C!8+Df@6YF zYyhuDa{@mHPE9k#)BO!=K+~zAJT!NYaOgvIR6kaUS^r=7?wIfce4}+~JUSPH^Y6Qn z_59lrDotCpD*dX@&?aTL(r&J#tBbad%Ar2nyu5D3&9^Vn-ms;9i9kxLgwocfZJec+ ztaJ?T>{s4bUHC zdzc2|I@$osm9u2~?zwv8F=}jJ7^!YC+q%}j4hgQ2dstFd6bvV-U9^C-U{q3xmy1oT(@+p)_O*&Qsq5{Rn_;-24h5G5mcEo`doqvD_37@}4e5XXfw9C5{GN zTP=Ch(Y=n{OSV5^zX4p@S`u7GcUPvk9@MZJeF-}k{ITXVafJIl@O)bMOvPMtv3q}A zkONlE+?Sg@U~FyddP;=S+<#k1}(1=o||b)?veQKswj zE9{GB#E|1@UK@QLQQl@db6htRKPvotN(J|i$Ze*a^##sv=Ru==pBhCCjXAFD*0Zo7 z*jq=8As2QGmkk(WM!d;0N20PF_}K^LRz=TK>qc)tUJt7ip>Iw)u<9IV>><|?K}BhP zQ|er^el+A#b*iv(+T=FhH(7;w#@Ji2U-w|Yw#C&M)0Nu%^g_l+qWy6V&Zw(#&U~7p zKTx+HAdV;2YAlL-#EvmCt#m(s4tLkl-J8+k{7-3_6Y&91L*Oo1vr+sZqLTl?qK%qB zSCX+GPv!AuJmm6$f->S9aEx?adJc!+N1t)6^dw_n#1%M0ZkSL-JCe@`^t-lX$d!ym zfJCD;cnQ8FzmDB9;W=z~1YO5>u)y5wUAbO(Uk$GobgttKhP-3-^yGMbEh*pc!U`(a z;IyR?m+@7O2x@a4{D*Zmk*sqJ^@hVsu!5-6o9YaxwgmeU(q4gad>UoG|}WR^J*y(yDmZZg;IXDgA{3_&!HR>Kg*G3iGwpj z&Y+f59`|xW0Z;05<~fg`5>fx_@!S_iJ)p z=LE(sRjvqh-k`+ zNG14t=s;rA#?+8>b&QR!gr!&8=+t<@X3$)QljlO5_rHQg#1+!#d>*7y>#*LajZT*I zPx=0LGXE#I1q%W1trq_wKP`al%GEeaVqq)yzWgM6Y?}0*eDw^z$b_We-M*JCTIp}{ zvqh95;@Mk$!x)d;M4vlm(s~V6t><9dN$5=tHRC3F_Yv;a;!f+?*!HQ3Mp|R$!LJ(r z(j{i0`YZwBK_l&)eSHl)yo&~_0hS;{qF+*cZ?@=y{47&^mA|zL(K6zP9fJGTrC!TZ z?ny+7MeoFzaiye%KgI{*ld;+3AvXcaN_|?Af7#PiN(8Jm{-qj1#8~GhV&8{nPtL=@ zBVzpULG1a3=%Y_ZpF=OQ7+b-klqgd2DU>KV`*O<`6zgWf?KT?A96yhK98(Tz}lpo&m7Dz z&rqOFfV7K)msu^&Dxef^5fdx1-7A78^U~~W=kOH;@^0PHy)w8qzoV1tyA|Sf&`JC* zzEUuVJm1F>V_d0H|Bx+RQ9@vU_`kJvKuAi*n%#u)v_!;nt zceMLEg|ByJ1P3#mSEDBVApHykz3iC3c&yi&SL6 z8b9mQI(}G|L0*r3)uJxmxZw8TGyvKm1#Dm842#`bUhgkVQX0?-3StE4E01>tyVev0X9our<>ZvY$OhNs zrAeuGU0sR_27#3ok}WXOwI-WSq|MxxA_G&sEy!QxkLQLKx%e6AB~! zyH5ue9Xj``OR*_u8`=A3QU03L;tD-{%vq2ee>H1^_#; z&3925z((xLUM(Te&*6In8J9RW>+R0prJjy&OuY7qf!fM7_ zg_Y@+%XdvGB3;B#^>!u3Uu9kr7AkpAmvXE+zJ=w=B!lUrO6+#gpC+AdgXvhMvY$kM zlBB!fFXB$O_TZ-DS@sk6c(3ld2X@#3-0KM%J9qV_Kfue#hMEnKp;l@)pL6gnD$KSF zteknshj7D{+ASH7l*EU^7_-UP>o^VA#5e0Wlzlz**Hb!dAv;dMY9mejMLXREKL>qR zg@4gbqf~#4Yc*QL%pJB^cdDUbNS6fn?ZynW?M)A?SFt(T65x-hltj z#@}@}aQL@;KE1!;hDA3J!QFsy9?`Jku;nIb1=CT+UlX*y{acsT_?uv3!KvVz^*z)w zF1EJNv%(*!AK9o8XT@Y}J^n?VjXsNCz~0|-bqn=3{3|(!-OwQFXjG%)tU57~!0Cj>3Jm`C%iF9Ock0NR{1zqumcfcW^wQeqazj0`x&Uelx^C?Vh0J zn(z7__MZrx^6P@x9gKZp6&Y`dbyPnbLQ+(r0U$Oo5J0 z|K@ZPyICovt~w;riNfYC_-Vhx_Rmc}W=^fj7r9 z>+7}k3$MLdUq7v$TYFPI%NeCmJN1COmS5?(0;~1J*t5;?!=ZK>`)ei7I~L&CkueuW zVvpyuNT{7gl2{I_vNAj$lAmju(%{RQenUN6KQCLEVE>e&+B;>f|Xp0Ql+ZK^xNIJ!a05g7~A6nY|y57u?$Oy(9Ivn(23g}E^owiowd z=iCfwfPwn=m0SBXWKYWQY@RV8@>dPh1g~t(bT=ue!z@L9wL3`#{HX3!gK`-W6+64e z*p$kBI`+KD*qs?D4n77W(#=yhT>VbpVuf5d3?ndtHstyC3y+n-%dH8Rg;r-6nCJ(DiaX%8@ptf z+iI!dnlNWdf56?eww|-!daRO`{??e&ExGrBn!S%JrAcewSNRIsetZ0XVY9{T(9Wf& zBW62f`QhcQyIa+mF;2G%@eHdw-*ZUrX-g+#p)m

A312TeSIad?q5-({=C`@Bjmt zC+f*_*ufR317ifzGYf{>(85iz%5@ZRPOau zLC3ps@=6Klx#VJLK<@R2k=vzyrj$4flxmMh&jI(+PUG8g7+tPuQ41Xtds8}gY)B)L zxp>bLWHP3Jmup)3b$&#N30e!Q;2nKfBe<1f6XIrDExS7ulGWnx0%y=cc|kR-@r23% zEZ)>-t%U)(pM1Dep1aP!-A{XFcgrhsPrrk+GaG)nU2R^08BW&$R5YG^$mzB=XT3`71V6Tmw%Y#=e68=t0g^9|^vqe*F@WHh~%6~CNRtgq4 z3WI})oN!KSS741Wu+U!F;&j&r40&2V5IN(5JI6E~(k@N(#RNtdn(hnOZS%LkU`M!g=x%A3|xx zP6fe!haPUBt1tl$mYA1`lPg)X0lfj#2EH6~jN?mHyn)W4#XYXD%UbyT>afrwkg~fQ zsb*XmE^F*>10J!azfppAe+DAc^tVw9ycUJyt6_ZY;jPRFVP}p_z(Q+ z@V%&sKAudi3wC4m#{cM2^z<7J2lrbO;q{;N_a8`ZD~S=X;WQ z$5X4OT~EwccIJf+LmhYJO|G!yPUqpu0G%WO%z{8Wn!CgUZyfFNO+ew zrEGpZ+E(pmt}*~ArDy2AI$+_wkd|PVeVE$_`lE?PfC4IWN=>Ep9OMe`U?wZYd-yvY z4vfLM1RZaojz%(J!}Q;jbdP~gUcs4TO0T>P^{$v?=31|OspUH>&4J0-mDmyHiuCG# zab=RPLbxiDuYQfIJW#UlQmR)r93bXWk(c?(19&qBoFe5WY4pSanV0;!#M?c^K(g;CKc18e`_I1MMn$ zHYuMTe#dAF=+>oVgPG^ilO_qMj4xshNyfw)1@}bkY0Ug#i+#(_LA|Skx__eyOTj;U zhV#f|?521K?W{mgaNvEYZ00^c!;QzD0WVu+nTXwiv*HrVcq3%?~Vf(#$eZY zG(L`q3KOxtahm!~lx4kdBGw0-Rt3JWT87)lV|OI)Zv3$E*~YS_XPfSBDr;nM&YXzd z4+#wAq+&9Hh|UCxk)|hZ%B?&*F;kj|HN*)}pR`T{Rd zs_`jzuJ?S+;~Gu)HCdW<#1m?xsJ>96;s3}bWIx96>J$RyR0AP24r)hta9U@&6V^@O zJQjmLlIUx3ihNRwU!eDCJ^vrd-UYs?^85pT&&fT#r57Mg({hpmO-hjf>I(CcCK8gC zyXa7=O9AHzR83lxv_(nEWhsbDL1zlOHD0zBx5+wjZa;N}xe3f|36k%;T)JILC}1tp?lIrKBj+&*&E63klbNS&XV1za9jg?P|i2KJ6B|4F$b zM*JUQhwjY*WygQeutX5>1XPn(WpQeoVG;TJbZU{1N_M6MPj?dm{yi;^D7WPKF>qVV zmfI(IP!FOw(>0}%`RIcMzZ3Z0V7?Gf-qpgwUyN(c7wG)r4l&z>;Dfi~S=y(pm>(7z zD-b+SX3Na-)4lS`^V&JeU|!cvT%Ob6iOX}k0$wkgqj!T((edByyvy}ljQ?4jh^3Od zMB5%P+mj0??sQ3Ux~_Sp*0sRs@~m8QN410tH->N$raAgOJP~k-?bJ6wj%RkOC@&*p zFnCu!)?-?d$cJyrrg24<_)nHas0@ExA&vFgp(n(ZTQ$%fk!u?C&lsupm<#QZ>H+lR z95|)Io4So!?z;E3zqV$b{(R2?+gE+`ssx#@Gfn!wYnLjqR$~?kve=|GT&dwPe0v(- zByo#tK4^H+SXvT)Y~Cvv3$YW?2XSg4M_kIgSzB7G?{iQe!Tp(p_F9ccgLKD^{J>MIf;-Z$nOd`?6QJ z_ozmc+hJ!&W&D@iK9)R$zNMx0RPtZwvj);SysaUpr}Yymf6P}CLgf*9#yPQ_5UODa z^Tv|CF&QM=4{;s|Y_p-trIpLvO;(_VgU4ZnpF^9JfNCg}aSh0OGC~r0;4ZyGkllf{ z1zw6L^W>OZ{3n&mQ5W^|J_hUWO!)h|fRVyL!_JKxU2QEHDEq@PWtI$&F*{3>WrbF? z-k@I7YY99AJ3DN9i~*?q1}i9{3eQw?v;cLe6vbj4x_EB&qb;SVmr$IMg^JrO!&^$m7-Um1XglMsE;8j_R-%s*xE)k(fS~l{-Cu`t-uWDbuD; zpI$Vbl$#3PSyV}{<&H^ma#gu#k-SoZ{2x-hXW^BDmlCgByd-#0jOj0uf5(&4!IScf zB;64j_|ij((B61_&hd z{qW@b!+2*c>DW*HzQ!%z=Qnt$Ei7^L@gvlxDowNwlbI9C*|Pfs_iwp+Tb_{M`w7l? zLIfvqy8^%s_Ac`>Jlh@sidrZ@a1t|=yn38w!F>-tFavR#t?|>Ev+lwzxkd3v#7~ZW8T373Ht&t-_HECZJ5^6fY&&VM%TNZn} zrV!|43|E9&$)U5=Kw%2#o&@F{_9c_o=+{L^nN?5u!TM3nrK~B2@7!|7riITxx9c~b z{`-?l8K!^7q{!RO8qD5k2pJ31RbB~qK#*SX9r@w#`!TPK`yo8_zbSY5cQ{2M#TK&R_CXpndkuc2nTcz@ zTlELLfgbnbFZ$*MUKAd2QF*2jh?veTCwN1X(s+_A)^>+X@ElWCMtMczh9Q=EKOjS9 zmCwXW!rc@nF9;p7Ybd#F43UEYautbL0%5`I55P`hMl`;4^1V&f#^lZWW~MHLF6wEW z1w%rp7cq_|f0f*NrdQP9%vm6quz*1?Wy~#HC(IZ0!fgVu)gHRYpMw8p`8LF4ou)JiG?}s$!c~H2 zn@jK6qU&Iwo(2O1b9a-l)ENyO3(Um`Xpg5}(c{Z=Y;5C;`+0fdw<)g8TI?7wi6{tK ziwS-vbD(?;t2z<0$HXU&IzDa@APoU2SOj)oZb1ejk%_3X93*H7E86vO|O$d>e#q0F@dwvs;mVbPj zly8k60dnG&Gi-SSdaX3H_JF=|mUAqy!7uT3>Zf&N3l6`+e=U21Jv*>lzubMFp_djR!J1P<6fJ@?kYeZm96UBW8C0Zf|$K`juWQwYeNXH?=G{Wvf+f|NRfRes|c zwUNpay8}}X9uLR`BER-bhFE55BphJdJwmT+4tld4y~+HR-sE4=n?L)1DE4c4KwkW9 z{rd3SBY1ANpJB?^#>G6FXmz2m8d(BXo{^O=@5?SlmM{Ev0?3sNeAAJcC$M@t8*~>- z!ZQV{^m^R+UEl>$#Ia&QBE9C#8h^Gpn=_U#2ujN5^cBr5i{+Ny>sa7rW=*g8N@B6E zMdtd9$=ZT}(;lEGb`0;IJ(XI1EA#z{$4fOqIShLQurCdbVm zXt>P|t@r$ZVrCMUxAc6A7*E?3uE&p52auyGE)nNX)kJyKQ1Y+C(}0jj2we-QqishB z$Anc8P1(fK5@5j6{Oy8=N!$r7K^6Os_f^3ZQW+}knm~SpEn~b>g?`wTLOz+{g6AZ* z$$n3$q2H5mDuewvaS1h=LLBx#Qy|xnACaOw?wT3Ecr1Q-SdI9O_n|RM!wf~9W4N*hv4r z^q!X&At7r~Z&7Pcit8;3!|RB3P`pq?Z5aMoDC}brw~ko6^o+K*X9uD)gnitO8w43@ zlE%1t(xf(3^j$0P$jNZ5@MI70>w)*3-@zPo`N4Nl?sNV-TVVe&MOFKqg_TB>`q zTFMw!XSPYycJkw6K!Qac2|FpJh+xN3QUXNx4ri0Pi2xCXF`kydufPZNP#@DR?SkzX zCE}nj^5e_=7bvc!d)f+d_fx4>WUHcCsu7)za!&&(R1T}xH}zSi*38Sb(Ngz8e!UcH zt$zLbKL0ngZs`ei{at$z~5 z7S8a8$YX1p3Y%E=tRJX!>`(n`{R{2WfpL4NxYCZyylC-qA1(MS06~?+fnN*c0w$K@ zl-)(JFC$AAdXtuSrQjLrG35#}<9f%ofc2XC#$Pm=T7Fj#kE+US?Gae8vLJhUU@QIv zya1MEqV!sLCQPN?;pFc}UI<)w*DqQ>X{9pnL``I)7XAlJqb^WcdA9Da1H-V=xkA8V z0*)FG2Xf#A4)2UpGT=bseGlHLw}uPvlp}l!#7Y+|SC{4E)X|?Gkpjwgs-q}uM7+@l z&Si32$he<{O`Pl}a|+Jyk?+qg0g{gK;A+|GY)yQAXj*wzA33-m{sF4^`DMm~hapFw zQpsbqWFB-E2{#)(?Q^!)LuP528K&dZXs3sr^2|3$#M(k*5lKg=ae9X-qI6G>><{S2#B5!%L z3)-?v4p{ZTn@T)3K7D*VcU(6f9v>SY9UmDV#{1Ct_;_;sEBqZF|8ks2Dq7+a$hFgq zo4mw$*ehI+ReTwzD}z$`&ucV?3wPx1Iu44?V_Ey{I|$-O+HEao3Gn@c4NTBg!t5-G z5M;KHp_VRvahT;u*w8_L3xF0Ru_c1GTj@<)c+?4z4E8JJRO5J9lPSs?mGz9_eNKy| zG>pjC?$QXGK&N1VZLe2hbjg6dw%e zNtoXIk8!SB%j+Y3}Aa`v|lL}Zk8FmTe_F$t1tF!=p z&WW#sb?vyP-6u2t(Q}$T7{KR-P(z&{G_~9_X?8 z7hdge?msJJU4X12d{-#B@S<>RAL1rN-RnQgr=QNRVN+mZav`{{Z(v@i7_k&mQ}0`} zbrQd4z%<#uB-XlbmTQkq77u=1n+kcqXrEev6hu0xj}&;Bm-gmZzXBNTQ!4zRp!BRx zt+{eeCH6cgG23@Au@2-$Vz|K%fYW9OHb4gn1{-C-K%WsQ>Of}YVm9%YF=F~XxQN`< zYp1gYACSk0U;A7DsB8Me#2^!S1H~z({2>JdL&Q-!HQi*da@Rxsl8Tq(RwHr)?WVM> zWRouRbBCr|xr^&Yj*-x2J+)gyLrOe0L8*b5Eb$CH4bWX^fgr1RG9EC17Iwpe4H<}K z2b@5;+VK~E8z`gD{$7p7QMgm{oNm{JYKl^!;2!?qapA_&e^wvD)!dzi!({(_w6VHm ze-BA)oNPf7+hO{3oGqK%pCz^wfOo5@pXZ-}pVXJMBi8I37qQBHKz%IguL9}? zed?MnW*5fqx5-VBUP|%h>)#UP^#=NDuj;0llFCsH$hWThA!ObkwwfaHa7l#I1@Y}z zus9+OBW5d6H>?QDBQraC3zcD4iL#6Fv0avq;bh(rI5pKu8_3)upyX)dB%={m0``$*yjcnfK}AdQPX-2p!UiEuzraL9*TMn_?lXPp4Z{9xO z_{5sDqRG-2V-}R_NMYR)9 z6;ShyGdfO7a_xJ1(z|leA;!M0*o`&&<*4}F#ga5z7p0XQRIY(E)*)MKHD)LKAJ^{e47EvTPzes*b1wkgf}9p6<&KLcU+yG(+=!R zhcPd>8+m_`Wuppb#=%B9_d~!ey*&3c9}^uPJ69P4FQ^YR(N<|6IiW^a;=(i8@g0HU z;s?bUnJ4HDGh(fpu`~rs;)S3q25c6#PFU4}yDqk2q-_A1NsDJx`M$B^YNtw(dxk;o zgbZ=?y`c~|8QqhuLrM;7WcMFFpj4c%C0pyEWI9 zSFNU&CgR zjwnz6T7+L2$m$r&!yoH=OImv%mw;b92)@)G|8>X%&f1OLITX@#_v)29=k)uUK;b@% zc(%)${vQ88IOp76Y7G@JtV3(nJg40qFj-^rw>7W~bC@qHGFWf|&5eAUm?3!+{-!F~ z%7Ezl91u>st=COHgh0o~^7a`tf^YB*T4>j}KaKvU?5my_F z_7ig>IH3@y*m*9omX0PfSA7%zj+h29g_CEhe=}b2yHQ+yHj}FIloP^ zm)dZoGX{jIXp@Dmpo)LS6P!e`cj+SYksDQakZ`e9VkW{|Aus+?XdyhWPY=^Na0ZR< zvmM&Q3wZ(*7eu||oJd+RHTDuD#T-bim#N)|74;mV;;HPYY^dZVVZyy6=8u$Bw20*- zu+BXzXfdZaOON@S^V*ml*nRFgH*l|$bubTU=QFTY-!1l?nEp1oqCl5BPYmcpN$u8{ zr5VUoYe_M4Kyy2|u~`=v9Hi1PN?^?2Ng{wELYaR$iHKwW~VRYOkK;5we)YSyj)% z`j~@x19gGxOoRE7f7vpzh1{pSjPt1TbWQgdC!-~GD8weho?KOAuG587f<(E zkLM-Eymx30t3tUujUA+YA+J4bI0Ro0WR9T`6yH1}wu?Tuztg(#w9vxCT!euYm;K;M zdw~@80`@=b1uu@J?FCdv&>UU3RN^N_Lp?CD;Wcqne3p=bvrN$3Z1@oRjP(-u2^#8m zgw#!^$^PQKs}1$^lM+kkct{;E)JxjvclG?et8H!2pphvxbDj;QlsKVN`Zz(o#aJH< zwWH+m5Nvk!Oj~ZySYOq)Drl(hMKn)cJy$=JtOtju=LFD_VF_k|azOdD=9L|I(er{J z&ihqy61p<`7xp>$7Rd0zNlR!aa!trka@q{NR}-+6xb$oFvV?J*-i=%g;#l`$WVx|c zKgC$c2$9(t*iBW%^jBqUFMb`0OG25Ur)^)LX0(YH&fs9dW6W7V$wyF(jKSXkvQR0o zQ|Tx9p+@W})r2ItgT?F1ktkWv{QFWO65e-2)sA3dQDD6<^_ z5bjl0z+0u zPT3BnE>PIz&b(%B$gdc9lOVh6#4DdTGm*`Yw5>ukcL4Zb-lO@Bf$GKDM?=5BT$EDfuu=qnJyPqVk9+475j8HDoc*YsP z*)(t_khzQcKvJwL4)TZ!7~oiyjj~olsH$~$>+7wVkg8z0kt)uRvKt)COy+UK0*F=+ z&L5>dNEq317Za8t{yz)I99F6N3=`?XGvY%1{(vlyLx7Ko+3EWgq+bQsKkyQ)9BjA? z-?F&3XdWr7c;uVLYP<<27jd8!b^%R;=4V$SvnJcoCTq)4p$-5)M+7fyHtwopJ^arr~NwZ<1R@=hFDv~ z<+b$}?Q~=UPYe!&J$te9kWwP#JG9#8@O_7kJ-d?=Z3&UKWmbx|7%&8~I>4)AnQlo( z)O*2;9Pv-KDSs(zBfrcs+a)vSu-*2@WWUUr!od5DWr|AVYhl;_+$ ztRTwR50-5#xfo)?KkG5^S0nSy6g-a!oI#Tgw_SDn9(e|^yZ2;K{ZUz43k^V)7#cOT zS#_r1M*TD3(4Dr6XFtXKRKhEq>Z;ZfCBD(fP`VbEyV%fQ=-ESGD=0hz^R~)Hi# zhX0W4P!2^yt#UuyByD^+bW`w;!8UkzF?DQ!4bnBi7#L*f6?0}IN>Ul%`5Z^k&pU!% zo@eNp4^HrcKGU9xP^XRbNgWlfR|}>+&<9#A#UAW@S*6S?(|erf%{eQ@-`Ov5@qoZ`6Ik6(KkZ9x#-BL zU8-kDPW}|%SW?m2iaFaBIMVcz??~vSfF)EJw1Ap}Sx5Ygy(!2>UJ4%JE9-DRA!g4i zKn6@$D3Li>M!pl1IbW3pnqSPKT!a{CX0TJ}jZC;n2fGdAF{+;#A!k|TnPgMmL-k-Rhv5Y9cWjIzPb{40KJnTVhg~( zW?;9tdXfVH*j1l`@1fC=Ev^JMkVe1g;)8`sP<9BG-1l&zF6M&*a*$|M3Yj4fz`6t- zzYQ%i_7cpR1U6D?kMM$@A^HRF-lJ1#7OBMaAt}j<%?Zs6q^_D8>r!ByW0mKEe_=MS zlH)vt-j$k{nkSjp))V!1fq>{LrE8Sdqi~%HwPFlZtH?B}fMt@*}U;KY_?XNjP)u_zE&7JI2mwL|(QAtnWaHgvb(y$5cDEZ{NP7Y5Ud&I1p4w z;$K8JbF#!QM=zJ?Km`1qcivfe?VT&v+(}^H24#O7eE?++jlRVD_&~kHC`$|vi#sqh z-)rK38?g8@QR+f8h*F_Zfu|C^JSLXjtU>7u!zSS+USlAeWr>9&FY&=mWV71u;|FnP z7VhkeK8iaxkBSna*T-MB9{!H6-n7b}Ct8!7R(f)+bSQ-r(dSWm4WxJ4&W|9OeVLSu z?j0z@dE>F@3-DThiHARS{X|kZ6!j3HpMQy`-p|wokjY*Wdp>#zrAkLB*Fv))(D4$Pc$ncPPNntsd`1dCtfAryp7cU`ZYes6;ifd&KO_$8O*vll2 z0r832!FES2*sr<>nEJJeA_yQ9sJ>LM^>$$*On_I#{|tOoB$i(lXzR22iGPvZad2 zmR3i1;8*_tXvyWY7N=V(K}#K|#Sz_y@+(IU40Q9vydZ{Fd}dg^=Hsl9wsJ%C=eTYi zS>%Mp*3u0g_LCtmRCjpf%5-AdHRIH6X_=;jlP9n-x$skUIssSfuv)m8Yj~&NUL-q@=SnSetxX@ z{Hiv4+=2RDeV6#`5RFf0{o}3+sOjg!W<-vU3e%{(+yEa)Z@}NGG&SufkWzA3JMU=q zj&iKk1RtZ`oB&Dx@=>TYP+gB)ZHe$?Z$EM+QCnbGW`MQme#~n#^F#D}mbE@7EWhy0 z=&nV1N$j7le>r6d&*a#Q6LL`B4(^;QfK_qldQH|o8 zXPwKvjJRNAt3wWfd7GedzzbPsV60NeD|db{3VJbl%W=vk=Bf9#D)eW@jT+EUj(B!E zjnnv?^^}STvck&JHPiDyM3GV7!bRv^a)_c=q>{#QZnEanaau3u#o0A@!%v(6zw!ao z2j9%lv)Fy4vB#Z{xz^zRe;^K7eEtZNmB#bAu-M->hQgC`v2&cx#a`zg*X=0XJ9K$2 z6qt)2qKuXIx_SN!_Ys6k0P7KZlr$D_KIFO!rMrjbZK9Iwn`0N>|EB%B#P+v3?{_t$ z%;RE>x#4s#mWjPs#odd2N0w-t?3+#O!zN_hX~i864dq69$qg%e3(cM?w+j8>(T6S` zPo(WgaD&rQr?Fgq9&?8%AE|ZT?h511I^1cx|Ec$HuO{5X^EI&e(=%aazp07Z$u!=G zu-Yjp&9qqg(K3m5hks@DA>|?RUF!~SO*1JgQk>7RdmoU18J3$Pu(Qh$XFNNW zQ$slE!LxU-M9e|Vt#xd(unx`qmF`e8jZO|VP}=+n*2^{EZCA&LOCkJX6t*wO6O?zX z1P{53>m^cnPR)I zjTrA61Ca6*C(ksx8lBR_L#fvW$Sj%_85q`xUB1_OkBhTN6AdX?gde1Kima|Ll7^JU zLC@sqDPQK-5>1_RuK)YX8UNZFTKVsS!dycchj%JweRt{Rrlub~ahS}eyt^^8ThcY2 zydKsyY3zH>TU=GB-JZI|l@*Z!@nwaRaj$TC_)H7qKFr(POuJI#_zw$vV5j_-k;b#q z_~^yh0jl_@+lmp*9Vr6|NFk%igA5zF;r#Ic?&kv=pX09%^=Le)>NyGy?m9AGXl5Uz=8&Z`J0!W1e9v648TL;HaDZj{bQ~;&bL1uDS&-Be~sI7gL9M*2s*RF}Il;Ff(E}q&;9kU$VwONk&O`u}K zkB*RXAS;v`5QROPMq$Ux{jzcJC?B^QvX2TrY6|naaTfQ`^ULEvH0IqB=;CI-%>0jdXPd^PKBuV+^mGQJyrxv8 zm2_=_4RX!I961;(G72q#GDCDsRGnbYc89>xY2*)ROn*EX(}?~%pjFCrG5lC zl+HyKW@8@aV&4&(6OA!fLRyl=X^+{s3ZqDSW*8pi9jD;!%r=G;$KdnKY+;O&ZW-G9 z_qep1G0L8I7L&xlxWf37z8@`L0Ie&GjK$y~iMPjT4^-%Zrc`z~imT_x>AcFQMFdaU zfO(Ud{}PuQC0+d}|Jt~;OO7=ISv~RUxYQs=D?MTz3b78!VPGdAu01`^R8mWi>D7sD zj7j0xbp*PWxMFT_taozP&Tk4fnNHlJqg+l{f=scz{6`gHeGFI`qVQc z{ci6VU(t6i>jsr+%Q1)tvo{1fkb zeif*Cs*76~bQ`dWj=4`3Gj+^^H#fVKE^;0_Ciu+#tl)ij&AU7M`}iGoOax{YX7hMpY7k&zog&P|CaEo@Vs!p za1!ku_?Gs53h(E9OH~sc^$kLmP$V!yt#AqR-X1@-RB5_i>_P8jj~l+FhKI&gnCFuh zl;(%yuewyG8F5L(<`3~qJ!q-JS}!-Yq3v77h%gO4%9Qr69PjtXf9<60j~l1M%l6I- z7T;%hhQ0CUTxt`%NoMX4LUhLJ(=#^zTiU;2yi=@!?gQ_@OKua^6>EMde#pg`M&q0K zYWEbs68XGq<8rF8cqv^g47onGgPoD-J>_2wjFMB{nkFi@)cE#_?|Xfx6-<1Oui7Vb zsGF?*R(PFl^6m!3=35AI3KFiuYw^)@$W(G-tmc9lzG8ohOHB90mBxp#!;-{1qm&0p zxzGCPwcp0Ku8^2sh$C{|sKl;_NPcMfphdn4IvX-Q!H1d{%swmMr|c&Oh!xUCh?857soVR-RX^Cg*7;s{8*U(!0)DGfD6C zH0={wbpdh5NJn}5Xu5axuqa!6zZLI2 z5SN+S<5#;j@!UcUM|pWhZ9(nR^t6(b&b0XU3=q@j@F%9d#b~@{mkZ;lLY}*zTeI*} z#7wG9ug3qoRa%m^3hW+a%1yUAZ%pUZ7_9zHyh?Yn2PnY_^(ZWd;R4XhG5<-Ru+ykm zHg3f%%iytW@fGz`o_Yyq>XZ|uYsnt_KAuLlX=hxHCmVFPd8~e=SH*RIa6-Yv)Lcr) z;hz5B1lG9*YknKnyvd(~bI~r?`%F!hjTzj?2PQ-neHkBH>fz}MCY$j5M>53`DvZDL zu->QmKHl!m+tliQ2;<8#{VP5wmSsy>5By#dua0DirGX*hjq-c&{8XMFpk$`$RD3`z zx!!L@txt`({ZGNdq|&Y4lpb;W$TxJ8OEpZmi~eN4hW$W|M%={A3Nyqs;>+gb-r1HQfC|K39lQ z=a^P}JrB7U!OPAd??kLI)mkJoP6>Vwc0BJ%Jlz-ZbdS1J#Zrqen`nf%by3$WB=x%Yf6}Q1-Khv~0zEymF8e=bddpvyt zDsss5YEp|&+^Rn*j=X2G?bk+54tPMtlyWt(V~}<4a#Grm!*@M>;;rWDT%h0?S|LNo z7p8Hm-@n5}shqAurT4OJj6MlzEIposBV@)J*z_20+UHSobahQ?Ms34dcVUArK#WpR zF3Vst7aWIFHWb%DL#bXabNHI66qPdjVoX^>b0eS2)M_*5-B#O1RMR)E-Gn%k49E)j?85QC_0hvzadyXd*v-SKRJ%1koIJ6VQa%=P?XSXsNM z>~zhrIQ4zJ^p;*45K)$-HLG9R!}MDP$UG zY@q(dkZ+i*s|)T(RSd^fD1Gyq&tcL3C2+#s%?5|WQO)NH45M^pS~RsvQM%qu9x43s zZ8%{AhllQg=<}?3D{E7xkK;cDg^*@Oa3RkQ?XL0`eijv8) zni2rj)5Dh-doQirl`8(tPOt zbRWLi%No_*K!{T84jg{uIuHYw_;j3;4@cdQ}h!}xAFDihX~obP#~_DpTP^|du*b~0{xv#d8E? znQs4{OF0i(DEf4z?(xwO<1mBQ$V{{1RD10N_55&%=X+a-Tz;myx)Zt)JSWh<*U`Ty zFW~xC*pbrLZPmip*MFO$`d25|-pnjwsH^+ET2s3%W}xxigh%FySQ3pAxkck)tgXC7gXj{g_ROgIl0) zVvGcqV5UM7V=HFHOOPw3(02@+5m^Lzr@PP@(1+Xs{R#9bQ^@pZR^-FqK<7Ko%kXSn zKtK-gVYdcjd~%3&$ONSy$R+VCtQlg|;K|~I9XTR1kez)UDTSXqd~kt{dAjFq6)FE5 z90!XD>xix=FOW^8BoAj5nwWtxAvz{Jt}(80(N9;6uZBmYvXTkh6j8>rN*dF&xKiN#(EM>a4HRnpt_frabR9)es}i+#difS01c;~C z-;7I!{K(m~XRs)CQJYvydM+0TuV!L#9fr zSxDD|B(Z-CWf0>*)b2(N>Y^=tf+=rw0bP~O;}Rb-+|zf)a9_2zhT5wctk8R%-X-lD z;A046f%t|(df$>w@E!opFX+L$L~7(~ejx5Xx4V^yYS!45bxJ|$p|)dX-9dLPJPdm0 zg~Xa`kz;~-a;K3CxD~99ZtE-o)Cg z;p^yKQiIR%&k;X6U9L^(-Y-T@dDebPyw`@$t&^W`be;61OJJo#hi-V0aV!Er4}8@T zs|gM@Cle=#$QaM9f6?;F)837K0uS8-82posPl|u%G`v{6)J^lfAve6+D~WT_H{eCcBMT+s z{*i-?&hj+WW}O$>K<1G6`WGqvd~B_r_lvu5V zSjX^er5qtdMyy1F*Ly@D{Y0QxbB*_H_`dhPt#>sb!1llMQ2g$SJQTnEuRIhlxSa6s z#a_?{w0*%~T%}VYucLR#uUw_`zWqv<%kh6)=@e0!89rsqW81};57<=QPhd2t%Nz2R zE~I~PH~v2EWD}{8AA?fZ#OTOp$=8QTVhZAgIZ(q3*zH71>MY=orXF^6+6wyA4sH=a zY)LxuHzOAEYidp2kpCXNRo~ka@*05Ewb%RU05gju28U=~Fj~{0D{A_2stIHI|6A8z z(se<~qI8NK5UcwkBuAtE4(VQ|k`JUdU`{%1Q~p2qlFT5&+NA{O#A!}NM{6)k&!xDV zqe~FOTQ#=SY2`JQ)}B;SoBDGPMbRrr_4e$xDNd)j>gY0*nLEY^pTQT>AfC$5oIJ@G zMOm>fS2#+q{k7lgH$e7w4_)IZz2>`1sjq6(?-qZ%b%>(abo+Vn+X{Ts#byfgU0(l5 zea;#$Xd4uO87+!q%wDZ9+vWCi3v<>`s_*S_<4QKJxV;&|Oc(E;H7{okFJ9qsh5B{z z-pj2UPeub&<6BPbv*ag31)v3HgfX}z;Lfr9=rOE|-q9TVnhnG?%Clv$ zFk~C*rA40tI3%8g0@pvFl2`n*Eh9f0W6zP( z9QPf^eUjL$XfayaJ6bAI;Y;FghNuC*1%V(jc+|M;KAxGSNBN#%9cEC1e2Z?->mP@U ztBbM1SGvg`zW!gD;jVF$Lz~^2D}Gf%pJ(Gv{2h+bzwaU1NE*A(O=}4aD+Kz!6YciJ zS+w%_FvUeVKEN=OXQ5crcWqctyG_XZSnmQ}{lsda+$8vh;yucXs&ipe&2kjmr__-O z%58MZXx>|f>$FzzQeX(4kgMOM+@}|(o((VNdOGa6b?~7=Ny{tTAFO}i{_xR2woB=+ z7M~&F^s*Q$C>=DTb8Vuz{)#UO+6>4G~djt1(vy0 z|C2j@2HeEV`3Kh`9|N+jQdIZP&SIfrMf`2W4Spt}n}Do#l`nQRGt=ScmDgBrBZ=L^ ztSR#xa#-BPB*w>?gc4=wH{|BQm33!^Bxa>S$d{%7LO^dWc1KsB`;e`?Kt~eNS?}u!uzz;HnLdKdwEf z+pku^xBu80wP3$(wd9~SkIhrtRuQ9Z4Xy8csi&NoS6A`JF?Q8$0g|_tM8ZpGw$T(& zb_oOYZHsa(lXwO_ex9Nx``1G*NY7j``n|i4;#uhtKbq}OI8w7EeLsr6396nt@~|^y zc-_6&Ep3o*0Y@_;JGn!O`CAPx+P$W?r_(lsd%Z_nfh=>EpWC*}Cg}@A2XODuu)uc{ z$4bfr++Gv-YYMp_iXEvLOyZvL2Uf@(O@4U)B5G($^h=Z%hJDaHB+cMrf|_~Mv0C3+ zn<}3fV}AO3NN(#Lne%_RmOc2mtt3V@lfAZ2&Za7~kPNH!%%L4?G8~x;*n`JcN)CO0 z1$2km*|Ch`<16W$K53hJ?l9(58B+?G4q+fA`sig8|7qo=0iEM!$)Un*M-i*Mwn%+g zw__EZXSxS7GdJT(F*`?{fe6h%t!&fV)?Dwn!B0>2Iwws2Benv}t7mdvhsKzMWZX>c zP@v+~Ymr+UXOCW-@G_?5|_s0jx+~8I*|g(&4Oi8hI6EAnuoh?8Db17 ziB;?2pV6!Cux3ym*2XHebOnl%9w_v4%w&$3;o<=5D32MJU*m7!&5lewo1Nf&GaaSO zo3*Kmp}1a1Rp?^RBK}gzXlgCqlxYh3O`kjiBorpm1y5WH?!8P6Q_*KR`urd;u&FN_ z1DSE5*wRl^M#jgdO4sN!ZrM{in>mG5Wz`XuF%b1hSqL6xl+zLt0WZDGL$`SD5#@^n zq<(!hW6;+qC2QPTcTtVrU9^;Q7dfS#_w4V6&}s3-`W**VLl)W^RPfwYwR9()J+V9z%~W%k>t9m4-?&OPrx~c?zZ58 zeU|fiXF_1YIrAByH(|+Z<#y0$>`{@ zX7f|wVb}0t27kbw;a>luD=jC#LiONvde!Xr`*Nb!QvN^m`b$#6jht%trl@vd?9^1TWIUncL8 zEZEI1e^$d;?DA)Yv)AKAI?z3y(-QfaHV^#v(i!D&kN9LD69VCLDc91E6Bb>JnKibI zlnKp-+5%4Pu-R7@O18;>qbHwT6jRJL#q8Ud*$ZM{M89%MfTEMWYal-KihPUEtcC_6 z098t8aOqF<9A3*BGC?iLf%G-ye_WFo!b|=&00i~PtN(eY(r^jak^@V=rB;QZU%ci$ z`oGKM9N+N2PBP=BtHQ{))axo4!Ri@I-U|=$!Q|#~hU@YrlDo!VcP5gLj{kWn=lwH2{b=0n z9ZV7+hiZ-vCd`A51df)1?!GN%_RnPMKSVt53OlB}#W9`A8}P?SguaAh%y!@KZa|&%8u<7X3bt zeoGv?T{5n~XtS@@a*OhSD2u&K)E2&gorC_q3O?Z0MSbfTBezh!6*LC@4tPC~l_0H9 zS}~8tG%qwGzwHL^gUAsU_Chy;B}QS^oz5UFHx)IV*Z%aTDKbS?PHsNw^GbvwjtGmm z7-AvZUd_wiC2P5%fvtGnKL*y%QSP$=&C9f2&CyLxtA8;0^mw30^Ga0-od?a)b=5n8 zbtN^kXSwZEURoRFF^6wWaNDWx-7S}Ku2It%B)zev7bqMb$I0A`7}rAW2OQ#0 zqyjO10vf$Epys$n*+FoCEpEr`rBYMQ*#fT0UWyDwIG4o86o?|HxO9q`CPF>w6|v%| z1!KEwBK_SLmqoNSWE%^~dJ5L4+O!2N^ka=t)P$2@9))=^ z;Be^}$X8}JuEFyQXF)7c^Y|8MW=)z1&YoJf2vWnx0|ag5!*c|uB-))0O~l5#kpX*} zcEHIVwEB@(>f8mKg-c_V_*EuIjUNplNLhzyP|NyedAUBezPX_EcKbUur?sp3c1Qu| zYZM34b8r^f-mCdGet%J0Q68&;gr-u5ZHvwxv{jz%uw8rBqU|lBy`sH#-}JZYlRW+Q zsKcg%oFY@~hY$T}jRROJI+gfY5y=)52RAs@FP5CU4O+HUFBen?*Dscz)9S4FX0;L1 z_urNXFS%X@C0WN!d~acT)PyrN@Vv52X}LTL*5%Spz`1i_ zLuMn33^}^_92=ru91hd?_1@wf-7TP!Y+zl~eT1_t;F!YDI=myl@I(CPXX<596X;D*OlNMyPX*{}(ATH&dxLoK(J0HdV4a)v}fIKei zfOT%mvSse(mk{$J>mZTP7OZA*tOh|6kx=*Ex||DbVZ`StS~DFtB5xPxXe;WhlAOLadL8bl7`qPk6_@zSyyznQQaZM< z+FJ-;Z{5RHOy75qO--~4;M}&r;ItcEi?uwElJl=vwQQzZDVGxN2f_=SMrh=+h51~j zpyt$q9LQfOt|&@ZYI4-mf{0%8&2)7_o+UG^T13^bo?D5Un5)kZCZ8OcRxNjAmRPEy%q)35+5X#e3;6qpPwAaCt z{)N~3c%`=QEcp`ego`S^qVIv7B_z<&KZ-WGMn|g?UyphiqaJ!iYB)SFm|Q)QX+R&1 zR_zxqmF}sk&rVxyG^?B3vE#^~lL;?wW*@tn_wuAj!G7wzQB8_SSUzV?tbj8+s_Y*D z-(3mLQpFEA_se!Wlt8r6^li``ux0hJ4zHsDtC;|G!Kz0*&*JQJRXSy1dM#(Z<%Tc& zu5C=D7xKiJm;{u6)^!$rT|LT1cG+gd=<`74)l#dL4F~wYyAH`7b}&V|9UW-Fs5^)j zHaO~N{T;rWT;LXk;2m?$sl*nlY>4H2hmHKYInWYBG|d)=9GS8I;40u2+j*^x&jZiO zQ~%zUak{5@2l5h=zMcH#zWgpOpYu`N!gtzUhzTN(x!Ub@)BYWC9YO!t(X;SSdfp{< zIFa?PSJs=Qk5O9`_{>`@^2I0@?N{z6tF$LQ0Yz{2F{@G@$WaMF<r<<6!V1p1OhX<2uXwF*f`8WZJSoKVp0P)AF zP4iYJd_v^uBgrv2EWx}I^&W7&kgeb>J)b%^K{_Oq zuf|S@vpJa54tKg44!Ef1-OzWA#L}2FUk!YI^hZZ(otch|Fk&2rZm-ViSh@TbEqDEG zD=0GSS|{}?mBhXmy&X^C#u18o`e5w){r>H0aCrarh1;q8Ac?Pt-i+&W#p}{orceoq zZU>l*d!To=t z4gI&!h9q7bEk$2X4PWjPF$nx7hpaufQF2(;O@y<;U~=2gCPyZxLBHm|!*KJ2-w0Q( zeaaK4%tLtyuR_>OP##AxK}S}7b%HyMo`k+AyCpoR9BEh;1`GaQo2o$h`x=tLJHy_1#ysq zI7mSpq#%w;K{R%OO}JqB17(}-pzA8FydAqe;u4h|z_3CVV5=@OjEE_!;UMp#$*qiV zqC9lb?L})dW8P-^L_Yz~v+^WN`%dKqCd@Ze8m1H)8V4%MK~j_l>ds>?)DU%^I=LAU(`>B#>JXqufSE$wt`8QF8vS21=E3P?J^f z-$SPt zq~>XmiKfJE=J)eOI*qOfEBgso5!SYHwi=fFy_lUaW{0jj=qR{5FGZ!7^!H?(e#ZGH zmq==X^NM&Ye9FhC!J`y$XL>BW)QzVjiHD+(V8m;O2((5<)EXtw8UrgJLt{-QXl9!T zmEb5wgT%Bgb`()hz2qjL6`J9t>N;;X)NG9G?GHEiv4FfxmfN8XoqJ1 zWDyxGG0i~6`fForArUc&VPr|+a6fG3pu)(+``&djbr~63eYz!IUm+K?Yu9m5%oFgqRB=U7HWJAqz8VD-s;b4Sp}rlve4|<9T8Hatk-2 zh1uWQ!Zo<_Kiidwqd{KB$tO@2U4St>p1QIWSG{_z6y>N_%#I^+$jOQ1|Bja~CE>be zlamR{%^dt7sMa^tsnV)IEkNlObt9~lZ4y%pb`Nq;0^Q`0E+EoQ)+FuRE7Hzp(2nP9 zo;cf(%A*D7!L2Ern)oPHlnMnEjL5Gjf4Y(%m4N?H9yMc9m%9b;RA-}lTpd0?f!FhR znehE%yer~v?5@(-g!7oc%8N*QFRgzHo^OF+q}pi@ptn*}R@~jpVq^?gP>Nj7TIH6y zX8KOGyv~NfW&C#Y_Q4e)+k#kPxk=m~0)=E-?;VWEv|SNHE#fy8=xH|z%mvDA0)8 zOJk;O$L?UvrdaPCEYKkqq0~3EOJaYI#xZZdpZKP}P=k5<<$BX)TMJFwX@3|<=o870 zQ?w5!;(r?GZe|cq#~O~^0{!X!ELakb-J%w{&}&KTchQ$o?<258bTydKL)sU4%)G6q zn$~d=&&hN@8a9MoR!(en5V@RhUX`BlIyO}NuG^9huZF*Ft@M~UerqFO=>0d zSv(l)#42fl?9^RMDyXK#FA9j1(Pb~8w>nSoh&Z2a-*GVJ) zt&r4(Hg-y<-e^Ec%NqHj#|rmq*43 z>}Bv-Gdkg?pqkV$5gTkU_{=Tfm*;Fc<$OkH7ox(`z-S<`{d&5?;S_K79kE9pb=9PU z>}L*6<5%ke(9`ld z-c8H}@U1d!B{)65A-)t;#`!wE@V79}jF~*v$&$Pqv4dN$5+IKa1mRy%?pdV;UBbHH zaZ`JnlzV4@<<1WfU}h|UPQ@fz$4#DeD` zEa$Wb3p0^bg230CwCDP;Cqjx(B!i=y98yv0V<7dx4hVb$s&!%|;>mTp>2CJTzSlWI z`{O<0NrjH+Q|QCKG3ud4 z?Ze10jy;sc6KEE5Left+ik}k6Q+Q7teHi&+E@G_M1><|72XObjV;d`$_3f`F2Bjmf zC{(qiFYK(^P9SmE;*W^3{0(s)a}iwOw6`w*Q=x@t4wFJUy1Y>jMu$-B(&JkT5-a3Y(GXk3*{?csd){@tH3b^mP-1fy<6P4!TTe-F3^U4@o?_{=H(d*3E zhU$XS8v7w_(YD{uWOwVv(-NJA9d!%s`ah4Hq@DeI$6}YN31g^ z#PAMG<|Jii@bjO>H*F*3Pv9hho_WG6iH z8eMmv;hpL()RsYQ9}DnGO^+(*8m4QPu1mU(sXc^JCudZl^^Rfc8+2l;625nGNVv{A znNwcPz;X$`ic=`>62v!g)IUg%_Fw(|#3^~T#=8pV`BJAI88EASHZOy3>Hi$cSl}l} zIM$IRJW)Fn`H$3d*gi^AmRHm>dAp^O)2@a;-yYkgJ`3h33!ZCA*l-z~vkurk5p!U0m6;9+ zVG{o{xUrtq z-anoC`-h3o`~HC>GVr*3XXt+g`rbcuT73U<=x+k&hpi&9f8^xkrz0b;;Zq$?fBoag ztCPR>jr?x%(?3UEz$Zf!z5e0Iuf8suKiVbG=!9p*noCEcxB@+A^htb2PTTSSr?qPj zZ=<^McV;AOEWc#g1luw8$gzXtIK+WG9G;4_$dcv65FRb?QO0&)$0^&$B(%=56q%UD z!J#B{$tHx4wM*${zx{Y+u}djVMN{}}x?yFD^vgQiFe%w8Z4=_G8%DMz&;HJ}oYM5) zb)vav?rUc5+xwWH&rXZb)|VvpbSc z@~}0zo#%QY`8W@sOm^__spQ}BFq~}X;nT^7dDxw7;o&pM2X)zZ-l(6sPrqQileibh z(}}x~cER|4q8TBqkS2mWd^*v%%EYh5qIGec16nWfM?B>E!3?vBH(FLkX_F>P;2kR2(m9)<~VjICetJo>jV6IXDzF#3M zl0x()Y8@mmO0@SRC~hg#5Rd;kKREY%9;8DC%<6%Gg!O2Aze5eH0+GXhPTc^ihf{L3 z5UT?Y@+iB`UsNQtcv>hYaGkNGenKzSV1GLT>;H2#P<$1SuT00UXog65ObTu?fM=5`x5PZA8mN>D97LoGtIb#SMC z-YA|vZ@f9((u6siYmxRV_eooMRPs?+G#Wh2mfFV4Y^(F+TLoyaYDyQO>N+T{;UW#W{PR8w(7vou#7vkBK=i}DOKgMmy zolzNW7a*4gj=?5-qb&?J3^MiBK|HTCJ5;-VrT=W}d81+aP-_jm>&WW$0qldQ=Z#yZ zVOwP)3$6A>f=%Qkf%cvj_MbPBurkp)2x}xpGmLk@W)g4|giK%)OVCENi$8}3bfvMj zhCldy%`%Uw6=D4!aqowjqvagr+N=qyW}Ff%6B-khm$y3LX#qHY2NZELTwWxXH>|qvr7X)eJr4 zcMNSo@5YfoGf6+FJ>EsBtf=-ErK~6gWH0)18%nhW!mu(zJ&@zUQRWq1<{RjHzsK)D!aFY-(?!DI#G{Wt*GBLZsiEk(9mL(`}t(^^RB>R|FBBbERaLx(ByEz z0w_FPk18P=ZHYwbhVbeYT9>y)CHyMBzkH<5q0b8f_BsD$n6)_@{TdL4guqANpl4UA zt>X;VHLzRjmLaF2))nZ7nYV;7O!)|Df_{|lHxNB2xH{u~3HTHXo3W5%52 zp6o5sVbO>C3w@mo+^eg7WR_BNzqKq0y8K68=9_aE*vwwh?u;ooI^nJZKc zxa&8pQt8KP^T(@f%ktz~-jG+VA7tMyzSRCBTRgYa_rCizZy}CV-b*bx`j6%1Jav_J zW$G%G_|&l&tu3x?f(|;g-8P#vZX;&3?+fDy?27+-I%PaPWg1S<#}i)|9&nD$+&fuG z6Xo2<^B*!z;6T2BCBeCIUVt7??<7*r+>!sp82%r@9eEz~XUt7=M#6KqZTZ$C?SDH5 zBZ^!=nu*`fnS0jEONPM*E@Pm8d0mNj8Uij0GdXBlfs@sgLBj>|5B#K>vQbGVYhR*L zpu;XZeKAbi0;?@ED<^LO6I`+`x-xXhWr5sR)UCi>WVlkauYvxfV0~l*?`7<5LOO-I zX#O|=Imn`Ks&58MHCCI9vPzqtt7WKV8oLf>@KLg<^dCK!@I}+qBH&(=KqiL<`q6?d zz?w_ZAND_rxA;kl?&SU1%;t=$s%HH8ni=g;NYR)2Lr6cuwZ!`ngS{H8_GG;evx`q) ziKC+ZG&D2G3l*d)p_EZMYf%7I9!eRX0>P;wWh!9>E|Tin+24)2_NR6=l6TA(JsBt5 z3y0P30nqK;zIFA!WQe zyQN80X>Ue~hG4e~Z#%U$fL&nVDeWE4sS@f6HGZrrSfkGx8MuODpsk7O6=7qMS~MS{ zQ}d?`$1Jwp5JNr$=e{8lQZU=E6tgy21eY4@gXf{W?jj9yryIYn&GSYFR&=?(z0B%s zE-v)lR?haqI>QVs{)v!Nl)nw!fxu@@7(G$4AiW#Xm`tp3)(4*R6vy85TpfGHV;$QG z3vkuGI(V^zMH-}j-;)(13$?_*hD=%^l7+5!LBXE^(r@!)_ZeR%YqY|*f@98;vw8TE z?Lm$UqcwiP^^y9FYH8_$KH>_eVD3E>FqF;-~2u`|NuvG&NLEn77VwYtX{)3An$ z&Iqj6D=^HB+)NeN{Cdi9H)Dq1>gs~Fu@G7p`XJP$5+9xfj}~ie(T{;u8CHk2ef6{O zO5qrK7Uw-`kM?C;>V$u?Mxdx+?Zy!;)TQlYsa05-H|kAO_R$^Mrki>_8DkNkW+@## z19=#@_k5nj=uw{MPh-%`@?1PYoSk^LxOmnWnqe4gWS8y;dS!W1xc1n3Rx6X0OdwMU z872ZtA>m8EydwvCk;Bz;Y}R-IEo_O>n0XnE9SeZsztPY zbqQ5c4u$?Da2Dg^+f&2wAK~qi)e>lyE-8k7mC(_m1t2TD3VQbIK=0D_t$;NXZAAM( zjcEIu3RkLX%J?j)s9UgefSTfx3pUkVXCcS?2%cG<2cJ0&K0~&__Vky)0>FWpYTvWX z^mQv-BQdOjU@g$O=Kg_zack?k_`$@JwRpFXO-4UxD~-umjK+ zs_LLNb&Q&ZXzJ))&8DtC8R*&kWTWV=XnCS>%nOS}&}O;=EqV9Ul{I~{|8~^W4BLgY z3k@orqa50sHF{==>i<9$d^%buo&bsgyy(dEYoRM^xxfDr)Kbf9`ETeQNtk=3jJtsV zuE#oUJ9zi$liRf} Bg<5tx1^7M~+9po>QbVzohbk2;Z^lLp0rtzCubFtMIS?vJ_ zoXg?q-;Eqe>?5C#Qykf@yQP0G;{F%5>nO$^RrwRlx7@1!eMtQr`_ioX2crs?&}HDt z4^3BfMBKPbE4a@hi2wqJvKnsF*c<@eQ{#pru0XD9Ps-$bvWCyip7M%E-fx5oh_UoUvw7xyq(Sr^24#CGt#-x0*@PBk_WR4 z8U8IryBul^iP_JF#N3am-U=zR*RwSy*?T=-k4ag*o||J*cCW`3bLx^W%lp))timhz zdbY(V-$Oj#-|&3ZJYP=CtN`NiJt`x{oX$+~;V9Ko9D_$H`%zFr>{n8xWaGLWobKhc zm(xK`Q*I%a#p$EC3*;Aheopst+RN!6r|C|SpVP<2j^eIRLf|Dh-OFh&r-PiPJ4Xpl zAH}mEKjZm1-OFiuMj;mDH1?Fo1mDJW4oI9H)IZK+(SS#Cu$bF(mz!0*?4$aY@s@DL zk`?ee`5xULB8a_{5<(IWFX`6Zb&_u5Ms=k%+NSU|X06OJty&neb?aP|~e9=7a*J z50p*8zEc*cjb$^V{hr@pj$Vg3k+5i?RuC*w3xdV?m0(U&&{z;GP#^PIZ=8tdH|7Nw zYA<co|JnWpe(;}_(e^0*}bBg>kl`~{a8Z}csu=o z88S(xQVZTCgB^jUKQ2R|IUi<;v=8q-iFEAWSI7e_BlW_Ahsg-N-qr(LXP zosR0llS;MYD`GWGi*`T%CID_OK1sEwDI<0rYVRP8J2*;_uO;OuaE5dKKqj}&GxZPEXb~BWvq}1 z409|Tul(D2Wdsu?3os11d5oR7Q($-p3cUhLK4WKbUWD^asOH=Tfn{$L0JvvLb}1r} zE(XL3S#x->vTR_GVVt%-f3JCf9a|zU6;=zl__;O8%*ulgg|~&7LktOLmNg6i2d>3J A-2eap literal 0 HcmV?d00001 diff --git a/workspace_tools/build_api.py b/workspace_tools/build_api.py index 2bfaff0d81..c2e85e9c0f 100644 --- a/workspace_tools/build_api.py +++ b/workspace_tools/build_api.py @@ -217,6 +217,7 @@ def build_mbed_libs(target, toolchain_name, options=None, verbose=False, clean=F toolchain.copy_files(resources.headers, BUILD_TARGET) toolchain.copy_files(resources.linker_script, BUILD_TOOLCHAIN) + toolchain.copy_files(resources.bin_files, BUILD_TOOLCHAIN) objects = toolchain.compile_sources(resources, TMP_PATH) toolchain.copy_files(objects, BUILD_TOOLCHAIN) diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 1f513e4cdb..c6c55cbf91 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -72,7 +72,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('ARCH_MAX', ('ARM', 'GCC_ARM')), - ('NRF51822', ('ARM', 'GCC_ARM')), + ('NRF51822', ('ARM', 'GCC_ARM', 'IAR')), ('NRF51_DK', ('ARM', 'GCC_ARM')), ('NRF51_DONGLE', ('ARM', 'GCC_ARM')), ('HRM1017', ('ARM', 'GCC_ARM')), diff --git a/workspace_tools/export/exporters.py b/workspace_tools/export/exporters.py index 097e7abaf4..60bfc7d3e6 100644 --- a/workspace_tools/export/exporters.py +++ b/workspace_tools/export/exporters.py @@ -36,7 +36,7 @@ class Exporter(): for r_type in ['headers', 's_sources', 'c_sources', 'cpp_sources', 'objects', 'libraries', 'linker_script', - 'lib_builds', 'lib_refs', 'repo_files', 'hex_files']: + 'lib_builds', 'lib_refs', 'repo_files', 'hex_files', 'bin_files']: r = getattr(resources, r_type) if r: self.toolchain.copy_files(r, trg_path, rel_path=src_path) diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py index 9c937faeb4..a3fe1a7be3 100644 --- a/workspace_tools/export/iar.py +++ b/workspace_tools/export/iar.py @@ -56,6 +56,7 @@ class IAREmbeddedWorkbench(Exporter): 'MTS_MDOT_F405RG', 'MTS_MDOT_F411RE', 'MTS_DRAGONFLY_F411RE', + 'NRF51822', ] def generate(self): diff --git a/workspace_tools/export/iar_nrf51822.ewp.tmpl b/workspace_tools/export/iar_nrf51822.ewp.tmpl new file mode 100644 index 0000000000..223ea68d2c --- /dev/null +++ b/workspace_tools/export/iar_nrf51822.ewp.tmpl @@ -0,0 +1,958 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 30 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + {% for files in source_files %} + + $PROJ_DIR$\{{files}} + + {% endfor %} + + + diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index a1d9c44163..e01da5275c 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -715,7 +715,7 @@ class NRF51822(Target): Target.__init__(self) self.core = "Cortex-M0" self.extra_labels = ["NORDIC", "NRF51822_MKIT", "MCU_NRF51822", "MCU_NORDIC_16K"] - self.supported_toolchains = ["ARM", "GCC_ARM"] + self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"] self.is_disk_virtual = True self.detect_code = ["1070"] @@ -723,7 +723,7 @@ class NRF51822(Target): return 6 def init_hooks(self, hook, toolchain_name): - if toolchain_name in ['ARM_STD', 'ARM_MICRO', 'GCC_ARM']: + if toolchain_name in ['ARM_STD', 'ARM_MICRO', 'GCC_ARM', 'IAR']: hook.hook_add_binary("post", self.binary_hook) @staticmethod diff --git a/workspace_tools/toolchains/__init__.py b/workspace_tools/toolchains/__init__.py index dd1a02a72d..76ac0f25a9 100644 --- a/workspace_tools/toolchains/__init__.py +++ b/workspace_tools/toolchains/__init__.py @@ -110,6 +110,7 @@ class Resources: # Other files self.hex_files = [] + self.bin_files = [] def add(self, resources): self.inc_dirs += resources.inc_dirs @@ -133,6 +134,7 @@ class Resources: self.linker_script = resources.linker_script self.hex_files += resources.hex_files + self.bin_files += resources.bin_files def relative_to(self, base, dot=False): for field in ['inc_dirs', 'headers', 's_sources', 'c_sources', @@ -168,6 +170,7 @@ class Resources: ('Libraries', self.libraries), ('Hex files', self.hex_files), + ('Hex files', self.bin_files), ): if resources: s.append('%s:\n ' % label + '\n '.join(resources)) @@ -387,6 +390,9 @@ class mbedToolchain: elif ext == '.hex': resources.hex_files.append(file_path) + + elif ext == '.bin': + resources.bin_files.append(file_path) return resources From aab9677cda51816dc804420ed57c33d5774226b3 Mon Sep 17 00:00:00 2001 From: GustavWi Date: Wed, 4 Feb 2015 13:58:40 +0100 Subject: [PATCH 23/25] trivial correction --- workspace_tools/toolchains/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/workspace_tools/toolchains/__init__.py b/workspace_tools/toolchains/__init__.py index 76ac0f25a9..8e4b1896af 100644 --- a/workspace_tools/toolchains/__init__.py +++ b/workspace_tools/toolchains/__init__.py @@ -170,7 +170,7 @@ class Resources: ('Libraries', self.libraries), ('Hex files', self.hex_files), - ('Hex files', self.bin_files), + ('Bin files', self.bin_files), ): if resources: s.append('%s:\n ' % label + '\n '.join(resources)) From 11d836f6dee6c46312829710419f63474728c72f Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Thu, 5 Feb 2015 13:43:12 +0900 Subject: [PATCH 24/25] Fix a bug that Ether Driver there is a case where the transmission can not be performed correctly. Fix a bug as below. - If Ether driver have been set multiple transmit data without waiting for the received data, Ether driver can not send data correctly . --- libraries/net/eth/lwip-eth/arch/TARGET_RZ_A1H/rza1_emac.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/libraries/net/eth/lwip-eth/arch/TARGET_RZ_A1H/rza1_emac.c b/libraries/net/eth/lwip-eth/arch/TARGET_RZ_A1H/rza1_emac.c index 13165da925..761679e3b7 100644 --- a/libraries/net/eth/lwip-eth/arch/TARGET_RZ_A1H/rza1_emac.c +++ b/libraries/net/eth/lwip-eth/arch/TARGET_RZ_A1H/rza1_emac.c @@ -63,7 +63,7 @@ static void rza1_phy_task(void *arg) { struct netif *netif = (struct netif*)arg; s32_t connect_sts = 0; /* 0: disconnect, 1:connect */ s32_t link_sts; - s32_t link_mode_new; + s32_t link_mode_new = NEGO_FAIL; s32_t link_mode_old = NEGO_FAIL; while (1) { @@ -125,7 +125,6 @@ static err_t rza1_low_level_output(struct netif *netif, struct pbuf *p) { } } } - pbuf_free(p); return err; } From 9b4470823b2f18d8731c8799bf63fac95883b375 Mon Sep 17 00:00:00 2001 From: Takafumi Naka Date: Fri, 6 Feb 2015 02:44:01 +0900 Subject: [PATCH 25/25] Update system_nrf51822.c Fixed support for mbed HRM1017. It had been broken Feb.27th. --- .../cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c index 74271f3a51..53430791fc 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c @@ -71,7 +71,7 @@ void SystemInit(void) // Start the external 32khz crystal oscillator. -#ifdef TARGET_DELTA_DFCM_NNN40 || TARGET_HRM1017 +#if defined(TARGET_DELTA_DFCM_NNN40) || defined(TARGET_HRM1017) NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_RC << CLOCK_LFCLKSRC_SRC_Pos); #else NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos);