From 3046e5b7fea6394a6f439feebad855ff9de50331 Mon Sep 17 00:00:00 2001 From: Michel JAOUEN Date: Fri, 1 Jul 2016 17:08:00 +0200 Subject: [PATCH] [STM32F3]: Hal update release cube V1.6.0 HAL V1.3.0 --- .../TARGET_STM32F3/stm32_hal_legacy.h | 15 +- .../TARGET_STM/TARGET_STM32F3/stm32f3xx_hal.c | 10 +- .../TARGET_STM/TARGET_STM32F3/stm32f3xx_hal.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_adc.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_adc.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_adc_ex.c | 77 ++-- .../TARGET_STM32F3/stm32f3xx_hal_adc_ex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_can.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_can.h | 8 +- .../TARGET_STM32F3/stm32f3xx_hal_cec.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_cec.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_comp.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_comp.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_comp_ex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_conf.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_cortex.c | 53 +-- .../TARGET_STM32F3/stm32f3xx_hal_cortex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_crc.c | 9 +- .../TARGET_STM32F3/stm32f3xx_hal_crc.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_crc_ex.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_crc_ex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_dac.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_dac.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_dac_ex.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_dac_ex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_def.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_dma.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_dma.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_dma_ex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_flash.c | 6 +- .../TARGET_STM32F3/stm32f3xx_hal_flash.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_flash_ex.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_flash_ex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_gpio.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_gpio.h | 7 +- .../TARGET_STM32F3/stm32f3xx_hal_gpio_ex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_hrtim.c | 84 +++- .../TARGET_STM32F3/stm32f3xx_hal_hrtim.h | 8 +- .../TARGET_STM32F3/stm32f3xx_hal_i2c.c | 64 +-- .../TARGET_STM32F3/stm32f3xx_hal_i2c.h | 6 +- .../TARGET_STM32F3/stm32f3xx_hal_i2c_ex.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_i2c_ex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_i2s.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_i2s.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_i2s_ex.c | 40 +- .../TARGET_STM32F3/stm32f3xx_hal_i2s_ex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_irda.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_irda.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_irda_ex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_iwdg.c | 350 +++++------------ .../TARGET_STM32F3/stm32f3xx_hal_iwdg.h | 122 ++---- .../TARGET_STM32F3/stm32f3xx_hal_nand.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_nand.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_nor.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_nor.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_opamp.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_opamp.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_opamp_ex.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_opamp_ex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_pccard.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_pccard.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_pcd.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_pcd.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_pcd_ex.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_pcd_ex.h | 2 +- .../TARGET_STM32F3/stm32f3xx_hal_pwr.c | 24 +- .../TARGET_STM32F3/stm32f3xx_hal_pwr.h | 43 +-- .../TARGET_STM32F3/stm32f3xx_hal_pwr_ex.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_pwr_ex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_rcc.c | 16 +- .../TARGET_STM32F3/stm32f3xx_hal_rcc.h | 22 +- .../TARGET_STM32F3/stm32f3xx_hal_rcc_ex.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_rcc_ex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_rtc.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_rtc.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_rtc_ex.c | 8 +- .../TARGET_STM32F3/stm32f3xx_hal_rtc_ex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_sdadc.c | 6 +- .../TARGET_STM32F3/stm32f3xx_hal_sdadc.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_smartcard.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_smartcard.h | 4 +- .../stm32f3xx_hal_smartcard_ex.c | 4 +- .../stm32f3xx_hal_smartcard_ex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_smbus.c | 16 +- .../TARGET_STM32F3/stm32f3xx_hal_smbus.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_spi.c | 12 +- .../TARGET_STM32F3/stm32f3xx_hal_spi.h | 28 +- .../TARGET_STM32F3/stm32f3xx_hal_spi_ex.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_spi_ex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_sram.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_sram.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_tim.c | 6 +- .../TARGET_STM32F3/stm32f3xx_hal_tim.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_tim_ex.c | 365 +++++++++--------- .../TARGET_STM32F3/stm32f3xx_hal_tim_ex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_tsc.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_tsc.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_uart.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_uart.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_uart_ex.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_uart_ex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_usart.c | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_usart.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_usart_ex.h | 4 +- .../TARGET_STM32F3/stm32f3xx_hal_wwdg.c | 330 +++++----------- .../TARGET_STM32F3/stm32f3xx_hal_wwdg.h | 152 +++----- 106 files changed, 971 insertions(+), 1226 deletions(-) diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32_hal_legacy.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32_hal_legacy.h index d01656d14e..fe303a459b 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32_hal_legacy.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32_hal_legacy.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** @@ -150,6 +150,9 @@ #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT @@ -160,8 +163,16 @@ #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal.c index 8cea52cb08..536c99a6b2 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -70,11 +70,11 @@ * @{ */ /** - * @brief STM32F3xx HAL Driver version number V1.2.1 + * @brief STM32F3xx HAL Driver version number V1.3.0 */ #define __STM32F3xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F3xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32F3xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F3xx_HAL_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32F3xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F3xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24)\ |(__STM32F3xx_HAL_VERSION_SUB1 << 16)\ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal.h index 53ec02f065..08e3baca72 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc.c index 048b8f4659..cec4304ffb 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_adc.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc.h index 1aaa090f0e..7e079daec4 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_adc.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file containing functions prototypes of ADC HAL library. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc_ex.c index 969757dece..9b8df1c9ac 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: @@ -6941,8 +6941,11 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_ADC_MODE(multimode->Mode)); - assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode)); - assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); + if(multimode->Mode != ADC_MODE_INDEPENDENT) + { + assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode)); + assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); + } /* Process locked */ __HAL_LOCK(hadc); @@ -6964,31 +6967,22 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); - /* Configuration of ADC common group ADC1&ADC2, ADC3&ADC4 if available */ - /* (ADC2, ADC3, ADC4 availability depends on STM32 product) */ - /* - DMA access mode */ - MODIFY_REG(tmpADC_Common->CCR , - ADC_CCR_MDMA | - ADC_CCR_DMACFG , - multimode->DMAAccessMode | - ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests) ); - - /* Parameters that can be updated only when ADC is disabled: */ - /* - Multimode mode selection */ - /* - Multimode delay */ - /* Note: If ADC is not in the appropriate state to modify these */ - /* parameters, their setting is bypassed without error reporting */ - /* (as it can be the expected behaviour in case of intended action */ - /* to update parameter above (which fulfills the ADC state */ - /* condition: no conversion on going on group regular) */ - /* on the fly). */ - if ((ADC_IS_ENABLE(hadc) == RESET) && - (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) + /* If multimode is selected, configure all multimode paramaters. */ + /* Otherwise, reset multimode parameters (can be used in case of */ + /* transition from multimode to independent mode). */ + if(multimode->Mode != ADC_MODE_INDEPENDENT) { /* Configuration of ADC common group ADC1&ADC2, ADC3&ADC4 if available */ /* (ADC2, ADC3, ADC4 availability depends on STM32 product) */ - /* - set the selected multimode */ /* - DMA access mode */ + MODIFY_REG(tmpADC_Common->CCR , + ADC_CCR_MDMA | + ADC_CCR_DMACFG , + multimode->DMAAccessMode | + ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests) ); + + /* Parameters that can be updated only when ADC is disabled: */ + /* - Multimode mode selection */ /* - Set delay between two sampling phases */ /* Note: Delay range depends on selected resolution: */ /* from 1 to 12 clock cycles for 12 bits */ @@ -6997,11 +6991,34 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /* from 1 to 6 clock cycles for 6 bits */ /* If a higher delay is selected, it will be clamped to maximum delay */ /* range */ - MODIFY_REG(tmpADC_Common->CCR , - ADC_CCR_MULTI | - ADC_CCR_DELAY , - multimode->Mode | - multimode->TwoSamplingDelay ); + /* Note: If ADC is not in the appropriate state to modify these */ + /* parameters, their setting is bypassed without error reporting */ + /* (as it can be the expected behaviour in case of intended action */ + /* to update parameter above (which fulfills the ADC state */ + /* condition: no conversion on going on group regular) */ + /* on the fly). */ + if ((ADC_IS_ENABLE(hadc) == RESET) && + (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) + { + MODIFY_REG(tmpADC_Common->CCR , + ADC_CCR_MULTI | + ADC_CCR_DELAY , + multimode->Mode | + multimode->TwoSamplingDelay ); + } + } + else /* ADC_MODE_INDEPENDENT */ + { + CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG); + + /* Parameters that can be updated only when ADC is disabled: */ + /* - Multimode mode selection */ + /* - Multimode delay */ + if ((ADC_IS_ENABLE(hadc) == RESET) && + (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) + { + CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI | ADC_CCR_DELAY); + } } } /* If one of the ADC sharing the same common group is enabled, no update */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc_ex.h index 328340bf27..ee14413ffe 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_adc_ex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file containing functions prototypes of ADC HAL library. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_can.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_can.c index bf6212709e..32755a68a1 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_can.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_can.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_can.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief CAN HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Controller Area Network (CAN) peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_can.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_can.h index dd6f07f344..f5650a4b20 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_can.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_can.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_can.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of CAN HAL module. ****************************************************************************** * @attention @@ -239,7 +239,7 @@ typedef struct __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ __IO uint32_t ErrorCode; /*!< CAN Error code - This parameter can be a value of @ref HAL_CAN_Error_Code */ + This parameter can be a value of @ref CAN_Error_Code */ }CAN_HandleTypeDef; /** @@ -252,7 +252,7 @@ typedef struct * @{ */ -/** @defgroup HAL_CAN_Error_Code CAN Error Code +/** @defgroup CAN_Error_Code CAN Error Code * @{ */ #define HAL_CAN_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cec.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cec.c index df6acb4257..d66898c9b0 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cec.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cec.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_cec.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief CEC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the High Definition Multimedia Interface diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cec.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cec.h index f9569fe8c8..24892a5f12 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cec.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cec.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_cec.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of CEC HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_comp.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_comp.c index 2f80df57f8..f5a7cbc2f1 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_comp.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_comp.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_comp.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief COMP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the COMP peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_comp.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_comp.h index 61eff111fd..5041ce9733 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_comp.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_comp.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_comp.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of COMP HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_comp_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_comp_ex.h index 8bb83cc6cd..b621a5ece1 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_comp_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_comp_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_comp_ex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of COMP HAL Extended module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_conf.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_conf.h index 7e3f231249..310db53d91 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_conf.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_conf.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_conf.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief HAL configuration file. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cortex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cortex.c index bf07e4be43..2f86ddfdf2 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cortex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cortex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_cortex.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: @@ -22,30 +22,8 @@ This section provides functions allowing to configure the NVIC interrupts (IRQ). The Cortex-M4 exceptions are managed by CMSIS functions. - (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() - function according to the following table. + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function - @brief CORTEX_NVIC_Priority_Table - The table below gives the allowed values of the pre-emption priority and subpriority according - to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function - ========================================================================================================================== - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - ========================================================================================================================== - NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority - | | | 4 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - | | | 3 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - | | | 2 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - | | | 1 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bits for subpriority - ========================================================================================================================== (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() @@ -120,6 +98,31 @@ ****************************************************************************** */ +/* + Additional Tables: CORTEX_NVIC_Priority_Table + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function + ========================================================================================================================== + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ========================================================================================================================== + NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority + | | | 4 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + | | | 3 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bits for subpriority + ========================================================================================================================== + +*/ + /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cortex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cortex.h index b00b6c9bb9..da687cb9c9 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cortex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cortex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_cortex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc.c index e076117ca3..55572a924a 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_crc.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cyclic Redundancy Check (CRC) peripheral: @@ -214,9 +214,12 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; - + /* Reset CRC calculation unit */ __HAL_CRC_DR_RESET(hcrc); + + /* Reset IDR register content */ + CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ; /* DeInit the low level hardware */ HAL_CRC_MspDeInit(hcrc); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc.h index 9203e11d98..db70dee6fd 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_crc.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc_ex.c index b3f2ffc10f..d45b34d289 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_crc_ex.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Extended CRC HAL module driver. * This file provides firmware functions to manage the extended * functionalities of the CRC peripheral. diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc_ex.h index a37e35df6c..5cc4f5bf08 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_crc_ex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of CRC HAL extension module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac.c index a65bfc4763..8b1858a133 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_dac.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac.h index f4c9174e0c..de1a7bc2c2 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_dac.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac_ex.c index 8f896c3e9b..6b0de964a5 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief DACEx HAL module driver. * This file provides firmware functions to manage the extended * functionalities of the DAC peripheral. diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac_ex.h index f7c56ab643..05bd228bc8 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_dac_ex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of DAC HAL Extended module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_def.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_def.h index 7dae63f6f1..760b04dd45 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_def.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_def.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_def.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dma.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dma.c index 8507b695d6..e8199fb813 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dma.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dma.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_dma.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief DMA HAL module driver. * * This file provides firmware functions to manage the following diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dma.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dma.h index e67e2a86db..2f4e4a46a7 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dma.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dma.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_dma.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dma_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dma_ex.h index 2af71cc9b0..f8e1ddb3c6 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dma_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dma_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash.c index 70e70b1205..ee98bd9e6c 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_flash.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: @@ -578,7 +578,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) * @verbatim =============================================================================== - ##### Peripheral errors functions ##### + ##### Peripheral Errors functions ##### =============================================================================== [..] This subsection permit to get in run-time errors of the FLASH peripheral. diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash.h index 4dd8a41a41..8ac517a197 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_flash.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of Flash HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash_ex.c index e331f081ec..2b6718f530 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Extended FLASH HAL module driver. * * This file provides firmware functions to manage the following diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash_ex.h index e4017da8e4..c596850cf7 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of Flash HAL Extended module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_gpio.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_gpio.c index 8ad4def37a..4701849bbe 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_gpio.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_gpio.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_gpio.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_gpio.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_gpio.h index 9bb5f44479..744ba6eca6 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_gpio.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_gpio.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_gpio.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention @@ -229,7 +229,8 @@ typedef enum */ #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) -#define IS_GPIO_PIN(__PIN__) (((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) +#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\ + (((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00)) #define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_gpio_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_gpio_ex.h index 41eb5d71cb..94becc8e59 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_gpio_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_gpio_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of GPIO HAL Extended module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_hrtim.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_hrtim.c index ebc0d78bbe..f4f063f4dd 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_hrtim.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_hrtim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_hrtim.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the High Resolution Timer (HRTIM) peripheral: @@ -1258,6 +1258,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, CompareUnit = HRTIM_COMPAREUNIT_2; } break; + default: + break; } CompareCfg.CompareValue = pSimpleOCChannelCfg->Pulse; @@ -1318,6 +1320,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; } break; + default: + break; } HRTIM_OutputConfig(hhrtim, @@ -1822,6 +1826,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, CompareUnit = HRTIM_COMPAREUNIT_2; } break; + default: + break; } CompareCfg.CompareValue = pSimplePWMChannelCfg->Pulse; @@ -2030,6 +2036,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); } break; + default: + break; } /* Enable the timer counter */ @@ -2104,6 +2112,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); } break; + default: + break; } /* Disable the timer counter */ @@ -2213,6 +2223,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2); } break; + default: + break; } /* Enable the timer counter */ @@ -2295,6 +2307,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2); } break; + default: + break; } /* Disable the timer counter */ @@ -2452,6 +2466,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2; } break; + default: + break; } /* Enable the timer counter */ @@ -2507,6 +2523,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE; } break; + default: + break; } /* Disable the timer counter */ @@ -2573,6 +2591,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2); } break; + default: + break; } /* Enable the timer counter */ @@ -2635,6 +2655,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2); } break; + default: + break; } /* Disable the timer counter */ @@ -2722,7 +2744,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2); } break; - } + default: + break; + } /* Enable the timer counter */ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]); @@ -2793,6 +2817,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2); } break; + default: + break; } /* Disable the timer counter */ @@ -2924,6 +2950,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh CompareUnit = HRTIM_COMPAREUNIT_2; } break; + default: + break; } CompareCfg.CompareValue = pSimpleOnePulseChannelCfg->Pulse; @@ -3143,6 +3171,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); } break; + default: + break; } /* Enable the timer counter */ @@ -3217,6 +3247,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); } break; + default: + break; } /* Disable the timer counter */ @@ -3709,6 +3741,8 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger; } break; + default: + break; } /* Update the HRTIM registers */ @@ -3995,6 +4029,8 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr; } break; + default: + break; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4218,6 +4254,8 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate; } break; + default: + break; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4298,6 +4336,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue; } break; + default: + break; } } else @@ -4372,6 +4412,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, } } break; + default: + break; } } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4431,6 +4473,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = pCaptureCfg->Trigger; } break; + default: + break; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4594,6 +4638,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, } } break; + default: + break; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5175,6 +5221,8 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR |= HRTIM_CPT2CR_SWCPT; } break; + default: + break; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5492,6 +5540,8 @@ uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim, captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR; } break; + default: + break; } return captured_value; @@ -5567,6 +5617,8 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim, } } break; + default: + break; } return output_level; @@ -5659,6 +5711,8 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim, output_bit = HRTIM_OENR_TE2OEN; } break; + default: + break; } if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != RESET) @@ -5756,6 +5810,8 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim, } } break; + default: + break; } return delayed_protection_status; @@ -6702,6 +6758,8 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, hrtim_bmcr |= ( pTimerCfg->BurstMode << 5); } break; + default: + break; } /* Update the HRTIM registers */ @@ -6750,6 +6808,8 @@ static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim, hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue; } break; + default: + break; } } else @@ -6777,6 +6837,8 @@ static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim, hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue; } break; + default: + break; } } } @@ -6848,6 +6910,8 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10; } break; + default: + break; } switch (CaptureUnit) @@ -6862,6 +6926,8 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger; } break; + default: + break; } } @@ -6914,6 +6980,8 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, shift = 16; } break; + default: + break; } /* Clear output config */ @@ -7176,6 +7244,8 @@ static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10; } break; + default: + break; } } @@ -7268,6 +7338,8 @@ static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim, } } break; + default: + break; } return interrupt; @@ -7362,6 +7434,8 @@ static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim, } } break; + default: + break; } return dma_request; @@ -7404,6 +7478,8 @@ static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hdma = hhrtim->hdmaTimerE; } break; + default: + break; } return hdma; @@ -7483,6 +7559,8 @@ static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU; } break; + default: + break; } } diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_hrtim.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_hrtim.h index ed9f58c85d..cb5eedce3f 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_hrtim.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_hrtim.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_hrtim.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of HRTIM HAL module. ****************************************************************************** * @attention @@ -2116,8 +2116,8 @@ typedef struct { ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \ || \ (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))) + (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))) #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000) diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c.c index 2c2b2330b2..9855ff27e9 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_i2c.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief I2C HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: @@ -88,7 +88,7 @@ *** Interrupt mode IO sequential operation *** - =================================== + ============================================== [..] (@) These interfaces allow to manage a sequential transfer with a repeated start condition when a direction change during transfer @@ -115,8 +115,6 @@ (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (+++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit - (+++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). @@ -613,7 +611,8 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) * @brief Transmits in master mode an amount of data in blocking mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration @@ -736,7 +735,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA * @brief Receives in master mode an amount of data in blocking mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration @@ -1131,7 +1131,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1199,7 +1200,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1365,7 +1367,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa * @brief Transmit in master mode an amount of data in non-blocking mode with DMA * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1472,7 +1475,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t * @brief Receive in master mode an amount of data in non-blocking mode with DMA * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1709,7 +1713,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD * @brief Write an amount of data in blocking mode to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -1860,7 +1865,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress * @brief Read an amount of data in blocking mode from a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2003,7 +2009,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2101,7 +2108,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2198,7 +2206,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2313,7 +2322,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2428,7 +2438,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @note This function is used with Memory devices * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param Trials Number of trials * @param Timeout Timeout duration * @retval HAL status @@ -2545,7 +2556,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS @@ -2618,7 +2630,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS @@ -2876,7 +2889,8 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) * @brief Abort a master I2C IT or DMA process communication with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) @@ -3054,7 +3068,7 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) * @brief Slave Address Match callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFEROPTIONS + * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION * @param AddrMatchCode: Address Match Code * @retval None */ @@ -3593,7 +3607,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin * @brief Master sends target device address followed by internal memory address for write request. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param Timeout Timeout duration @@ -3659,7 +3674,8 @@ return HAL_OK; * @brief Master sends target device address followed by internal memory address for read request. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param Timeout Timeout duration diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c.h index c62fbc1569..53607046f9 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_i2c.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention @@ -314,7 +314,7 @@ typedef struct __I2C_HandleTypeDef * @} */ -/** @defgroup I2C_XferDirection I2C Transfer Direction +/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View * @{ */ #define I2C_DIRECTION_TRANSMIT (0x00000000U) diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c_ex.c index b09352190f..1e89a9fefc 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_i2c_ex.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief I2C Extended HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2C Extended peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c_ex.h index 98504d3c61..409f71a0eb 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of I2C HAL Extended module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s.c index 01cd2e0f04..95efe4e06e 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_i2s.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s.h index 491773e31f..30e636f4fc 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_i2s.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s_ex.c index 4cddbc6f5e..b6b5a3d16c 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_i2s_ex.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief I2S Extended HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2S Extended peripheral: @@ -19,21 +19,7 @@ called I2Sxext ie. I2S2ext for SPI2 and I2S3ext for SPI3). (#) The Extended block is not a full SPI IP, it is used only as I2S slave to implement full duplex mode. The Extended block uses the same clock sources - as its master (refer to the following Figure). - - +-----------------------+ - I2Sx_SCK | | - ----------+-->| I2Sx |------------------->I2Sx_SD(in/out) - +--|-->| | - | | +-----------------------+ - | | - I2S_WS | | - ------>| | - | | +-----------------------+ - | +-->| | - | | I2Sx_ext |------------------->I2Sx_extSD(in/out) - +----->| | - +-----------------------+ + as its master. (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers. @@ -115,6 +101,26 @@ ****************************************************************************** */ +/* + Additional Figure: The Extended block uses the same clock sources as its master. + (refer to the following Figure). + + +-----------------------+ + I2Sx_SCK | | + ----------+-->| I2Sx |------------------->I2Sx_SD(in/out) + +--|-->| | + | | +-----------------------+ + | | + I2S_WS | | + ------>| | + | | +-----------------------+ + | +-->| | + | | I2Sx_ext |------------------->I2Sx_extSD(in/out) + +----->| | + +-----------------------+ + +*/ + /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s_ex.h index e8d6ec919c..d5de540a20 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_i2s_ex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of I2S HAL Extended module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_irda.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_irda.c index 3a1a0d91e9..2abf5312b0 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_irda.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_irda.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_irda.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief IRDA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the IrDA (Infrared Data Association) Peripheral diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_irda.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_irda.h index 3e80be0a91..8f3a47bd64 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_irda.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_irda.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_irda.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief This file contains all the functions prototypes for the IRDA * firmware library. ****************************************************************************** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_irda_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_irda_ex.h index f818f227a6..b9ff375d7c 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_irda_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_irda_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_irda_ex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of IRDA HAL Extension module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_iwdg.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_iwdg.c index 690e99b790..c70273a7b7 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_iwdg.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_iwdg.c @@ -2,37 +2,43 @@ ****************************************************************************** * @file stm32f3xx_hal_iwdg.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 - * @brief IWDG HAL module driver. + * @version V1.3.0 + * @date 01-July-2016 + * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: - * + Initialization and de-initialization functions + * + Initialization and Start functions * + IO operation functions - * + Peripheral State functions - * + * @verbatim ============================================================================== ##### IWDG Generic features ##### ============================================================================== - [..] + [..] (+) The IWDG can be started by either software or hardware (configurable - through option byte). + through option byte). - (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and - thus stays active even if the main clock fails. - Once the IWDG is started, the LSI is forced ON and cannot be disabled - (LSI cannot be disabled too), and the counter starts counting down from - the reset value of 0xFFF. When it reaches the end of count value (0x000) - a system reset is generated. + (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even + if the main clock fails. - (+) The IWDG counter should be refreshed at regular intervals, otherwise the - watchdog generates an MCU reset when the counter reaches 0. + (+) Once the IWDG is started, the LSI is forced ON and both can not be + disabled. The counter starts counting down from the reset value (0xFFF). + When it reaches the end of count value (0x000) a reset signal is + generated (IWDG reset). + + (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, + the IWDG_RLR value is reloaded in the counter and the watchdog reset is + prevented. (+) The IWDG is implemented in the VDD voltage domain that is still functional - in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). - IWDGRST flag in RCC_CSR register can be used to inform when an IWDG - reset occurs. + in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). + IWDGRST flag in RCC_CSR register can be used to inform when an IWDG + reset occurs. + + (+) Debug mode : When the microcontroller enters debug mode (core halted), + the IWDG counter either continues to work normally or stops, depending + on DBG_IWDG_STOP configuration bit in DBG module, accessible through + __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros [..] Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s The IWDG timeout may vary due to LSI frequency dispersion. STM32L4xx @@ -40,44 +46,37 @@ connected internally to TIM16 CH1 input capture). The measured value can be used to have an IWDG timeout with an acceptable accuracy. - ##### How to use this driver ##### ============================================================================== - [..] - If Window option is disabled - - (+) Use IWDG using HAL_IWDG_Init() function to : - (++) Enable write access to IWDG_PR, IWDG_RLR. - (++) Configure the IWDG prescaler, counter reload value. - This reload value will be loaded in the IWDG counter each time the counter - is reloaded, then the IWDG will start counting down from this value. - (+) Use IWDG using HAL_IWDG_Start() function to : - (++) Reload IWDG counter with value defined in the IWDG_RLR register. - (++) Start the IWDG, when the IWDG is used in software mode (no need - to enable the LSI, it will be enabled by hardware). - (+) Then the application program must refresh the IWDG counter at regular - intervals during normal operation to prevent an MCU reset, using - HAL_IWDG_Refresh() function. - [..] - if Window option is enabled: - - (+) Use IWDG using HAL_IWDG_Start() function to enable IWDG downcounter - (+) Use IWDG using HAL_IWDG_Init() function to : - (++) Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. - (++) Configure the IWDG prescaler, reload value and window value. - (+) Then the application program must refresh the IWDG counter at regular - intervals during normal operation to prevent an MCU reset, using - HAL_IWDG_Refresh() function. + [..] + (#) Use IWDG using HAL_IWDG_Init() function to : + (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI + clock is forced ON and IWDG counter starts downcounting. + (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR & + IWDG_WINR. + (++) Configure the IWDG prescaler and counter reload value. This reload + value will be loaded in the IWDG counter each time the watchdog is + reloaded, then the IWDG will start counting down from this value. + (++) wait for status flags to be reset" + (++) Depending on window parameter: + (+++) If Window Init parameter is same as Window register value, + nothing more is done but reload counter value in order to exit + function withy exact time base. + (+++) Else modify Window register. This will automatically reload + watchdog counter. + + (#) Then the application program must refresh the IWDG counter at regular + intervals during normal operation to prevent an MCU reset, using + HAL_IWDG_Refresh() function. *** IWDG HAL driver macros list *** ==================================== [..] - Below the list of most used macros in IWDG HAL driver. - + Below the list of most used macros in IWDG HAL driver: (+) __HAL_IWDG_START: Enable the IWDG peripheral - (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register - (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status - + (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in + the reload register + @endverbatim ****************************************************************************** * @attention @@ -116,63 +115,63 @@ * @{ */ -/** @defgroup IWDG IWDG +#ifdef HAL_IWDG_MODULE_ENABLED +/** @addtogroup IWDG * @brief IWDG HAL module driver. * @{ */ -#ifdef HAL_IWDG_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup IWDG_Private_Defines IWDG Private Defines * @{ */ - -#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000 -/* Local define used to check the SR status register */ -#define IWDG_SR_FLAGS (IWDG_FLAG_PVU | IWDG_FLAG_RVU | IWDG_FLAG_WVU) - +/* Status register need 5 RC LSI divided by prescaler clock to be updated. With + higher prescaler (256), and according to HSI variation, we need to wait at + least 6 cycles so 48 ms. */ +#define HAL_IWDG_DEFAULT_TIMEOUT 48u /** * @} */ + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup IWDG_Exported_Functions IWDG Exported Functions +/** @addtogroup IWDG_Exported_Functions * @{ */ -/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. +/** @addtogroup IWDG_Exported_Functions_Group1 + * @brief Initialization and Start functions. * @verbatim =============================================================================== - ##### Initialization and de-initialization functions ##### + ##### Initialization and Start functions ##### =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the IWDG according to the specified parameters - in the IWDG_InitTypeDef and create the associated handle - (+) Manage Window option - (+) Initialize the IWDG MSP - (+) DeInitialize the IWDG MSP + [..] This section provides functions allowing to: + (+) Initialize the IWDG according to the specified parameters in the + IWDG_InitTypeDef of associated handle. + (+) Manage Window option. + (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog + is reloaded in order to exit function with correct time base. @endverbatim * @{ */ /** - * @brief Initialize the IWDG according to the specified - * parameters in the IWDG_InitTypeDef and initialize the associated handle. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * @brief Initialize the IWDG according to the specified parameters in the + * IWDG_InitTypeDef and start watchdog. Before exiting function, + * watchdog is refreshed in order to have correct time base. + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Check the IWDG handle allocation */ if(hiwdg == NULL) @@ -181,227 +180,88 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) } /* Check the parameters */ + assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance)); assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); - /* Check pending flag, if previous update not done, return error */ - if(((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0) - { - return HAL_ERROR; - } + /* Enable IWDG. LSI is turned on automaticaly */ + __HAL_IWDG_START(hiwdg); - if(hiwdg->State == HAL_IWDG_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hiwdg->Lock = HAL_UNLOCKED; - - /* Init the low level hardware */ - HAL_IWDG_MspInit(hiwdg); - } - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_BUSY; - - /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers */ - /* by writing 0x5555 in KR */ + /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing + 0x5555 in KR */ IWDG_ENABLE_WRITE_ACCESS(hiwdg); - /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */ - MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler); - MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload); + /* Write to IWDG registers the Prescaler & Reload values to work with */ + hiwdg->Instance->PR = hiwdg->Init.Prescaler; + hiwdg->Instance->RLR = hiwdg->Init.Reload; - /* check if window option is enabled */ - if (((hiwdg->Init.Window) != IWDG_WINDOW_DISABLE) || ((hiwdg->Instance->WINR) != IWDG_WINDOW_DISABLE)) + /* Check pending flag, if previous update not done, return timeout */ + tickstart = HAL_GetTick(); + + /* Wait for register to be updated */ + while(hiwdg->Instance->SR != RESET) { - tickstart = HAL_GetTick(); - - /* Wait for register to be updated */ - while(((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0) + if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT) { - if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT) - { - /* Set IWDG state */ - hiwdg->State = HAL_IWDG_STATE_TIMEOUT; - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } - - /* Write to IWDG WINR the IWDG_Window value to compare with */ - MODIFY_REG(hiwdg->Instance->WINR, IWDG_WINR_WIN, hiwdg->Init.Window); } - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_READY; + /* If window parameter is different than current value, modify window + register */ + if(hiwdg->Instance->WINR != hiwdg->Init.Window) + { + /* Write to IWDG WINR the IWDG_Window value to compare with. In any case, + even if window feature is disabled, Watchdog will be reloaded by writing + windows register */ + hiwdg->Instance->WINR = hiwdg->Init.Window; + } + else + { + /* Reload IWDG counter with value defined in the reload register */ + __HAL_IWDG_RELOAD_COUNTER(hiwdg); + } /* Return function status */ return HAL_OK; } -/** - * @brief Initialize the IWDG MSP. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. - * @retval None - */ -__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hiwdg); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IWDG_MspInit could be implemented in the user file - */ -} - /** * @} */ -/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions + +/** @addtogroup IWDG_Exported_Functions_Group2 + * @brief IO operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] This section provides functions allowing to: - (+) Start the IWDG. + [..] This section provides functions allowing to: (+) Refresh the IWDG. @endverbatim * @{ */ -/** - * @brief Start the IWDG. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg) -{ - uint32_t tickstart = 0; - - /* Process locked */ - __HAL_LOCK(hiwdg); - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_BUSY; - - /* Reload IWDG counter with value defined in the RLR register */ - if ((hiwdg->Init.Window) == IWDG_WINDOW_DISABLE) - { - __HAL_IWDG_RELOAD_COUNTER(hiwdg); - } - - /* Start the IWDG peripheral */ - __HAL_IWDG_START(hiwdg); - - tickstart = HAL_GetTick(); - - /* Wait until PVU, RVU, WVU flag are RESET */ - while(((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0) - { - - if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT) - { - /* Set IWDG state */ - hiwdg->State = HAL_IWDG_STATE_TIMEOUT; - - /* Process unlocked */ - __HAL_UNLOCK(hiwdg); - - return HAL_TIMEOUT; - } - } - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hiwdg); - - /* Return function status */ - return HAL_OK; -} /** * @brief Refresh the IWDG. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) { - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hiwdg); - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_BUSY; - - tickstart = HAL_GetTick(); - - /* Wait until RVU flag is RESET */ - while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET) - { - if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT) - { - /* Set IWDG state */ - hiwdg->State = HAL_IWDG_STATE_TIMEOUT; - - /* Process unlocked */ - __HAL_UNLOCK(hiwdg); - - return HAL_TIMEOUT; - } - } - /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hiwdg); - /* Return function status */ return HAL_OK; } -/** - * @} - */ - -/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Return the IWDG handle state. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. - * @retval HAL state - */ -HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg) -{ - /* Return IWDG handle state */ - return hiwdg->State; -} - /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_iwdg.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_iwdg.h index 2ee43eb24e..a493d1cf85 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_iwdg.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_iwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_iwdg.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention @@ -50,7 +50,7 @@ * @{ */ -/** @addtogroup IWDG +/** @defgroup IWDG IWDG * @{ */ @@ -59,19 +59,6 @@ * @{ */ -/** - * @brief IWDG HAL State Structure definition - */ -typedef enum -{ - HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */ - HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */ - HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */ - HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */ - HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */ - -}HAL_IWDG_StateTypeDef; - /** * @brief IWDG Init structure definition */ @@ -97,10 +84,6 @@ typedef struct IWDG_InitTypeDef Init; /*!< IWDG required parameters */ - HAL_LockTypeDef Lock; /*!< IWDG Locking object */ - - __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */ - }IWDG_HandleTypeDef; /** @@ -115,21 +98,21 @@ typedef struct /** @defgroup IWDG_Prescaler IWDG Prescaler * @{ */ -#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */ -#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */ -#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */ -#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */ -#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */ -#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */ -#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */ +#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */ +#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */ +#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */ +#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */ +#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ +#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ +#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ /** * @} */ -/** @defgroup IWDG_Window IWDG Window +/** @defgroup IWDG_Window_option IWDG Window option * @{ */ -#define IWDG_WINDOW_DISABLE ((uint32_t)0x00000FFF) +#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN /** * @} */ @@ -143,124 +126,89 @@ typedef struct * @{ */ -/** @brief Reset IWDG handle state. - * @param __HANDLE__: IWDG handle. - * @retval None - */ -#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET) - /** * @brief Enable the IWDG peripheral. - * @param __HANDLE__: IWDG handle + * @param __HANDLE__ IWDG handle * @retval None */ #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE) /** - * @brief Reload IWDG counter with value defined in the reload register. - * @param __HANDLE__: IWDG handle + * @brief Reload IWDG counter with value defined in the reload register + * (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled). + * @param __HANDLE__ IWDG handle * @retval None */ #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD) -/** - * @brief Get the selected IWDG flag status. - * @param __HANDLE__: IWDG handle - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag - * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag - * @arg IWDG_FLAG_WVU: Watchdog counter window value flag - * @retval The new state of __FLAG__ (TRUE or FALSE) . - */ -#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) - /** * @} */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup IWDG_Exported_Functions +/** @defgroup IWDG_Exported_Functions IWDG Exported Functions * @{ */ -/** @addtogroup IWDG_Exported_Functions_Group1 +/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions * @{ */ -/* Initialization/de-initialization functions ********************************/ +/* Initialization/Start functions ********************************************/ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); -void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg); /** * @} */ -/** @addtogroup IWDG_Exported_Functions_Group2 +/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions * @{ */ /* I/O operation functions ****************************************************/ -HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg); HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); /** * @} */ -/** @addtogroup IWDG_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State functions ************************************************/ -HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg); -/** - * @} - */ - /** * @} */ /* Private constants ---------------------------------------------------------*/ -/** @addtogroup IWDG_Private_Defines +/** @defgroup IWDG_Private_Constants IWDG Private Constants * @{ */ /** * @brief IWDG Key Register BitMask */ -#define IWDG_KEY_RELOAD ((uint32_t)0x0000AAAA) /*!< IWDG Reload Counter Enable */ -#define IWDG_KEY_ENABLE ((uint32_t)0x0000CCCC) /*!< IWDG Peripheral Enable */ -#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x00005555) /*!< IWDG KR Write Access Enable */ -#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x00000000) /*!< IWDG KR Write Access Disable */ - -/** - * @brief IWDG Flag definition - */ -#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update flag */ -#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update flag */ -#define IWDG_FLAG_WVU ((uint32_t)IWDG_SR_WVU) /*!< Watchdog counter window value update flag */ +#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */ +#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */ +#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */ +#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */ /** * @} */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup IWDG_Private_Macro IWDG Private Macros +/** @defgroup IWDG_Private_Macros IWDG Private Macros * @{ */ /** - * @brief Enables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. - * @param __HANDLE__: IWDG handle + * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. + * @param __HANDLE__ IWDG handle * @retval None */ #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) /** - * @brief Disables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. - * @param __HANDLE__: IWDG handle + * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. + * @param __HANDLE__ IWDG handle * @retval None */ #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE) /** * @brief Check IWDG prescaler value. - * @param __PRESCALER__: IWDG prescaler value + * @param __PRESCALER__ IWDG prescaler value * @retval None */ #define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ @@ -273,17 +221,17 @@ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg); /** * @brief Check IWDG reload value. - * @param __RELOAD__: IWDG reload value + * @param __RELOAD__ IWDG reload value * @retval None */ -#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF) +#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL) /** * @brief Check IWDG window value. - * @param __WINDOW__: IWDG window value + * @param __WINDOW__ IWDG window value * @retval None */ -#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0xFFF) +#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN) /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nand.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nand.c index 9757ac4a21..5835f44f6f 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nand.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nand.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_nand.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief NAND HAL module driver. * This file provides a generic firmware to drive NAND memories mounted * as external device. diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nand.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nand.h index b172a1b197..4b19b04518 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nand.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nand.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_nand.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of NAND HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nor.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nor.c index f2f5695565..fd59e32dc3 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nor.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nor.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_nor.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief NOR HAL module driver. * This file provides a generic firmware to drive NOR memories mounted * as external device. diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nor.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nor.h index e15f65cf61..6da375c017 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nor.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nor.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_nor.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of NOR HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp.c index c7032a8362..8a31442da8 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_opamp.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief OPAMP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the operational amplifiers (OPAMP1,...OPAMP4) diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp.h index 67b6c05d1f..2ef1c065de 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_opamp.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of OPAMP HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp_ex.c index 1ea97f757f..4de9132387 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_opamp_ex.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Extended OPAMP HAL module driver. * * This file provides firmware functions to manage the following diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp_ex.h index adb6060d7e..68274e9d1c 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_opamp_ex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of OPAMP HAL Extended module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pccard.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pccard.c index 4cadbe0474..a8dc5e6d88 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pccard.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pccard.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_pccard.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief PCCARD HAL module driver. * This file provides a generic firmware to drive PCCARD memories mounted * as external device. diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pccard.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pccard.h index 51f2f96b50..608c833eda 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pccard.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pccard.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_pccard.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of PCCARD HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd.c index 81af8b62a0..d0ed066a82 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_pcd.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd.h index 7e09aeea13..131be217ad 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_pcd.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd_ex.c index 23317292e3..4127cda932 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Extended PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd_ex.h index 837db2ec57..4b75cc91ac 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd_ex.h @@ -3,7 +3,7 @@ * @file stm32f3xx_hal_pcd_ex.h * @author MCD Application Team * @version V1.3.0 - * @date 26-June-2015 + * @date 01-July-2016 * @brief Header file of PCD HAL Extension module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr.c index 90eebd4acb..b6e8abb283 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_pwr.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -254,35 +254,31 @@ void HAL_PWR_DisableBkUpAccess(void) /** * @brief Enables the WakeUp PINx functionality. * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. - * This parameter can be one of the following values: - * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3 + * This parameter can be value of : + * @ref PWREx_WakeUp_Pins * @retval None */ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) { - __IO uint32_t tmp = 0; - /* Check the parameters */ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - tmp = CSR_EWUP1_BB + (WakeUpPinx << 2); - *(__IO uint32_t *) (tmp) = (uint32_t)ENABLE; + /* Enable the EWUPx pin */ + SET_BIT(PWR->CSR, WakeUpPinx); } /** * @brief Disables the WakeUp PINx functionality. * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. - * This parameter can be one of the following values: - * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3 + * This parameter can be values of : + * @ref PWREx_WakeUp_Pins * @retval None */ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) { - __IO uint32_t tmp = 0; - /* Check the parameters */ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - tmp = CSR_EWUP1_BB + (WakeUpPinx << 2); - *(__IO uint32_t *) (tmp) = (uint32_t)DISABLE; + /* Disable the EWUPx pin */ + CLEAR_BIT(PWR->CSR, WakeUpPinx); } /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr.h index 81c897f288..a5945ec0c1 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_pwr.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention @@ -56,39 +56,6 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ -/** @defgroup PWR_Alias_Exported_Constants PWR Alias Exported Constants - * @{ - */ -/* ------------- PWR registers bit address in the alias region ---------------*/ -#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ -#define CR_OFFSET (PWR_OFFSET + 0x00) -/* Alias word address of DBP bit */ -#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP) -#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BIT_NUMBER * 4)) - -/* Alias word address of PVDE bit */ -#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE) -#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BIT_NUMBER * 4)) - -/* --- CSR Register ---*/ -#define CSR_OFFSET (PWR_OFFSET + 0x04) -/* Alias word address of EWUP1 bit */ -#define EWUP1_BitNumber POSITION_VAL(PWR_CSR_EWUP1) -#define CSR_EWUP1_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP1_BitNumber * 4)) - -/* Alias word address of EWUP2 bit */ -#define EWUP2_BitNumber POSITION_VAL(PWR_CSR_EWUP2) -#define CSR_EWUP2_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP2_BitNumber * 4)) - -/* Alias word address of EWUP3 bit */ -#define EWUP3_BitNumber POSITION_VAL(PWR_CSR_EWUP3) -#define CSR_EWUP3_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP3_BitNumber * 4)) -/** - * @} - */ - /** @defgroup PWR_Exported_Constants PWR Exported Constants * @{ */ @@ -97,9 +64,9 @@ * @{ */ -#define PWR_WAKEUP_PIN1 ((uint32_t)0x00) /*!< Wakeup pin 1 */ -#define PWR_WAKEUP_PIN2 ((uint32_t)0x01) /*!< Wakeup pin 2 */ -#define PWR_WAKEUP_PIN3 ((uint32_t)0x02) /*!< Wakeup pin 3 */ +#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) /*!< Wakeup pin 1 */ +#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) /*!< Wakeup pin 2 */ +#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) /*!< Wakeup pin 3 */ /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr_ex.c index cb811a244b..beaac486a9 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr_ex.h index 09e49c50c2..b4a4bda75b 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of PWR HAL Extended module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc.c index f879a52713..e9d3e71a25 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_rcc.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: @@ -76,7 +76,7 @@ * ****************************************************************************** */ - + /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" @@ -244,7 +244,7 @@ void HAL_RCC_DeInit(void) /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); - + /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); @@ -277,18 +277,18 @@ void HAL_RCC_DeInit(void) */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(RCC_OscInitStruct != NULL); assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - + /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) @@ -627,7 +627,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(RCC_ClkInitStruct != NULL); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc.h index aba70a7155..c4097e803c 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_rcc.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention @@ -63,14 +63,14 @@ */ /* Disable Backup domain write protection state change timeout */ -#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */ /* LSE state change timeout */ #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT -#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ +#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */ -#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */ -#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */ +#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ /** * @} */ @@ -1004,7 +1004,7 @@ typedef struct #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) #define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) -#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) +#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U) #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) @@ -1029,7 +1029,7 @@ typedef struct #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) #define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST)) -#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U) #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) @@ -1053,7 +1053,7 @@ typedef struct #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) -#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U) #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) @@ -1520,7 +1520,7 @@ typedef struct * access is denied to this domain after reset, you have to enable write * access using the Power Backup Access macro before to configure * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the + * @note Once the RTC clock is configured it cannot be changed unless the * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by * a Power On Reset (POR). * diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc_ex.c index eb10d63546..21fc725c7e 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Extended RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc_ex.h index 454248542f..82c925ca15 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc.c index da92c6e760..45f707f4ed 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_rtc.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real-Time Clock (RTC) peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc.h index 75a191dfc1..8c29564118 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_rtc.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc_ex.c index 9b1f420eab..fa50fdf198 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Extended RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) Extended peripheral: @@ -895,8 +895,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t } } + /* Disable the Wake-Up timer */ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + /* Clear flag Wake-Up */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + tickstart = HAL_GetTick(); /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc_ex.h index d65246cf9b..a7a71cc748 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of RTC HAL Extended module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sdadc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sdadc.c index 5eff01bb6c..151c58db3f 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sdadc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sdadc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_sdadc.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Sigma-Delta Analog to Digital Converter * (SDADC) peripherals: @@ -535,7 +535,7 @@ HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc, channelnum = (uint32_t)(Channel>>16); /* Set the channel configuration */ - hsdadc->Instance->CONFCHR1 &= (uint32_t) ~(SDADC_CONFCHR1_CONFCH0 << (channelnum << 2)); + hsdadc->Instance->CONFCHR1 &= (uint32_t) ~((uint32_t)SDADC_CONFCHR1_CONFCH0 << (channelnum << 2)); hsdadc->Instance->CONFCHR1 |= (uint32_t) (ConfIndex << (channelnum << 2)); } else diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sdadc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sdadc.h index 78ca0d0224..c2af156cd4 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sdadc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sdadc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_sdadc.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief This file contains all the functions prototypes for the SDADC * firmware library. ****************************************************************************** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard.c index 342260ad9a..4e109a1ed6 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_smartcard.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief SMARTCARD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the SMARTCARD peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard.h index c115154827..2e0415e671 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_smartcard.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard_ex.c index 0c09e2ee03..06ebbcc601 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_smartcard_ex.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief SMARTCARD HAL module driver. * * This file provides extended firmware functions to manage the following diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard_ex.h index 21b93d8359..f6333d3f84 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_smartcard_ex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of SMARTCARD HAL Extended module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smbus.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smbus.c index f750926be9..046bf4dde2 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smbus.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smbus.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_smbus.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief SMBUS HAL module driver. * This file provides firmware functions to manage the following * functionalities of the System Management Bus (SMBus) peripheral, @@ -438,7 +438,8 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) * @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition @@ -526,7 +527,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint * @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition @@ -608,7 +610,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 * @note This abort can be called only if state is ready * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress) @@ -911,7 +914,8 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) * @brief Check if target device is ready for communication. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param Trials Number of trials * @param Timeout Timeout duration * @retval HAL status diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smbus.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smbus.h index 65dd2bf6e8..59618955c6 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smbus.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smbus.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_smbus.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of SMBUS HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_spi.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_spi.c index 24d4052de3..edf3a6215e 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_spi.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_spi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_spi.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief SPI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Peripheral Interface (SPI) peripheral: @@ -2295,7 +2295,9 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; } /* Disable TXE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); @@ -2375,7 +2377,9 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; } /* Disable TXE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_spi.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_spi.h index 52bca96521..3866d91d7d 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_spi.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_spi.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_spi.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention @@ -140,13 +140,13 @@ typedef struct __SPI_HandleTypeDef uint16_t TxXferSize; /*!< SPI Tx Transfer size */ - uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ + __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ uint16_t RxXferSize; /*!< SPI Rx Transfer size */ - uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ + __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ @@ -470,10 +470,10 @@ typedef struct __SPI_HandleTypeDef */ #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ do{ \ - __IO uint32_t tmpreg; \ - tmpreg = (__HANDLE__)->Instance->SR; \ + __IO uint32_t tmpreg_modf; \ + tmpreg_modf = (__HANDLE__)->Instance->SR; \ (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \ - UNUSED(tmpreg); \ + UNUSED(tmpreg_modf); \ } while(0) /** @brief Clear the SPI OVR pending flag. @@ -484,10 +484,10 @@ typedef struct __SPI_HandleTypeDef */ #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ do{ \ - __IO uint32_t tmpreg; \ - tmpreg = (__HANDLE__)->Instance->DR; \ - tmpreg = (__HANDLE__)->Instance->SR; \ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg_ovr; \ + tmpreg_ovr = (__HANDLE__)->Instance->DR; \ + tmpreg_ovr = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_ovr); \ } while(0) /** @brief Clear the SPI FRE pending flag. @@ -498,9 +498,9 @@ typedef struct __SPI_HandleTypeDef */ #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ do{ \ - __IO uint32_t tmpreg; \ - tmpreg = (__HANDLE__)->Instance->SR; \ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg_fre; \ + tmpreg_fre = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_fre); \ } while(0) /** @brief Enable the SPI peripheral. diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_spi_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_spi_ex.c index 450ed8809b..944b996406 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_spi_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_spi_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_spi_ex.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Extended SPI HAL module driver. * This file provides firmware functions to manage the following * SPI peripheral extended functionalities : diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_spi_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_spi_ex.h index d9e03006fd..bea8657169 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_spi_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_spi_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_spi_ex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of SPI HAL Extended module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sram.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sram.c index 17d472f4d2..814e63a4c3 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sram.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sram.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_sram.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief SRAM HAL module driver. * This file provides a generic firmware to drive SRAM memories * mounted as external device. diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sram.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sram.h index e01c442f5e..1fa98ad550 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sram.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sram.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_sram.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of SRAM HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim.c index 3d0997746d..0e266e80ed 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_tim.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -1143,7 +1143,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode. * @param htim: TIM handle - * @param Channel: TIM Channel to be disabled + * @param Channel: TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim.h index 2801de98b1..5f1ba43a44 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_tim.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim_ex.c index a5c56be6cc..e79b337a8c 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer Extended peripheral: @@ -1883,179 +1883,6 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, return HAL_OK; } -/** - * @brief Configures the OCRef clear feature - * @param htim: TIM handle - * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that - * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @arg TIM_Channel_5: TIM Channel 5 - * @arg TIM_Channel_6: TIM Channel 6 - * @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx, - * STM32F398xx and STM32F303x8 up to 6 OC channels can be configured - * @retval None - */ -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - TIM_ClearInputConfigTypeDef *sClearInputConfig, - uint32_t Channel) -{ - uint32_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); - - /* Check input state */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (sClearInputConfig->ClearInputSource) - { - case TIM_CLEARINPUTSOURCE_NONE: - { - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Clear the OCREF clear selection bit */ - tmpsmcr &= ~TIM_SMCR_OCCS; - - /* Clear the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set TIMx_SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - break; - - case TIM_CLEARINPUTSOURCE_OCREFCLR: - { - /* Clear the OCREF clear selection bit */ - htim->Instance->SMCR &= ~TIM_SMCR_OCCS; - } - break; - - case TIM_CLEARINPUTSOURCE_ETR: - { - /* Check the parameters */ - assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); - assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); - assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); - - TIM_ETR_SetConfig(htim->Instance, - sClearInputConfig->ClearInputPrescaler, - sClearInputConfig->ClearInputPolarity, - sClearInputConfig->ClearInputFilter); - - /* Set the OCREF clear selection bit */ - htim->Instance->SMCR |= TIM_SMCR_OCCS; - } - break; - default: - break; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; - } - else - { - /* Disable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; - } - } - break; - case TIM_CHANNEL_2: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; - } - else - { - /* Disable the Ocref clear feature for Channel 2 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; - } - } - break; - case TIM_CHANNEL_3: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; - } - else - { - /* Disable the Ocref clear feature for Channel 3 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; - } - } - break; - case TIM_CHANNEL_4: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; - } - else - { - /* Disable the Ocref clear feature for Channel 4 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; - } - } - break; - case TIM_CHANNEL_5: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE; - } - else - { - /* Disable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE; - } - } - break; - case TIM_CHANNEL_6: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE; - } - else - { - /* Disable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE; - } - } - break; - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} /** * @brief Configures the TIM in master mode. @@ -2507,6 +2334,194 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan * @} */ +/** @addtogroup TIM_Exported_Functions_Group8 + * @{ + */ +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ + defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ + defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ + defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) +/** + * @brief Configures the OCRef clear feature + * @param htim: TIM handle + * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_Channel_5: TIM Channel 5 + * @arg TIM_Channel_6: TIM Channel 6 + * @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx, + * STM32F398xx and STM32F303x8 up to 6 OC channels can be configured + * @retval None + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + uint32_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Check input state */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Clear the OCREF clear selection bit */ + tmpsmcr &= ~TIM_SMCR_OCCS; + + /* Clear the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set TIMx_SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + break; + + case TIM_CLEARINPUTSOURCE_OCREFCLR: + { + /* Clear the OCREF clear selection bit */ + htim->Instance->SMCR &= ~TIM_SMCR_OCCS; + } + break; + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + + /* Set the OCREF clear selection bit */ + htim->Instance->SMCR |= TIM_SMCR_OCCS; + } + break; + default: + break; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; + } + else + { + /* Disable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; + } + } + break; + case TIM_CHANNEL_2: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; + } + else + { + /* Disable the Ocref clear feature for Channel 2 */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; + } + } + break; + case TIM_CHANNEL_3: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; + } + else + { + /* Disable the Ocref clear feature for Channel 3 */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; + } + } + break; + case TIM_CHANNEL_4: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; + } + else + { + /* Disable the Ocref clear feature for Channel 4 */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; + } + } + break; + case TIM_CHANNEL_5: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE; + } + else + { + /* Disable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE; + } + } + break; + case TIM_CHANNEL_6: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE; + } + else + { + /* Disable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE; + } + } + break; + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx || */ + /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + /* STM32F301x8 || STM32F302x8 || STM32F318xx */ +/** + * @} + */ + /** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions * @brief Extension Callbacks functions * diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim_ex.h index 9439fc95af..9312d4cbd7 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of TIM HAL Extended module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tsc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tsc.c index ddd264c61d..3ccbbed234 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tsc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tsc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_tsc.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Touch Sensing Controller (TSC) peripheral: * + Initialization and De-initialization diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tsc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tsc.h index 63f25c9fec..59a43ee1a9 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tsc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tsc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_tsc.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of TSC HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart.c index 396d54c350..c539592d8a 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_uart.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief UART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart.h index 9654641129..97c38c6e31 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_uart.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of UART HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart_ex.c index 2801fbb49a..433ee44138 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_uart_ex.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Extended UART HAL module driver. * This file provides firmware functions to manage the following extended * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart_ex.h index 32a4956301..06db7373c1 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_uart_ex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of UART HAL Extension module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_usart.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_usart.c index 9551147a26..855bf0a892 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_usart.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_usart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_usart.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief USART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_usart.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_usart.h index f036bfbd7f..6f73def3e7 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_usart.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_usart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_usart.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of USART HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_usart_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_usart_ex.h index 55f291511a..85023c978a 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_usart_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_usart_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_usart_ex.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of USART HAL Extension module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_wwdg.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_wwdg.c index 72903488b5..78165f57bc 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_wwdg.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_wwdg.c @@ -2,19 +2,18 @@ ****************************************************************************** * @file stm32f3xx_hal_wwdg.c * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: - * + Initialization and de-initialization functions + * + Initialization and Configuration function * + IO operation functions - * + Peripheral State functions @verbatim ============================================================================== ##### WWDG specific features ##### ============================================================================== - [..] + [..] Once enabled the WWDG generates a system reset on expiry of a programmed time period, unless the program refreshes the counter (T[6;0] downcounter) before reaching 0x3F value (i.e. a reset is generated when the counter @@ -23,49 +22,75 @@ (+) An MCU reset is also generated if the counter value is refreshed before the counter has reached the refresh window value. This implies that the counter must be refreshed in a limited window. + (+) Once enabled the WWDG cannot be disabled except by a system reset. + (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has - occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)). - (+) The WWDG counter input clock is derived from the APB clock divided + occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)). + + (+) The WWDG downcounter input clock is derived from the APB clock divided by a programmable prescaler. - (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler) - (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock - where T[5;0] are the lowest 6 bits of Counter. + + (+) WWDG downcounter clock (Hz) = PCLK1 / (4096 * Prescaler) + + (+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock) + where T[5;0] are the lowest 6 bits of downcounter. + (+) WWDG Counter refresh is allowed between the following limits : - (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock - (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock + (++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock) + (++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock) + (+) Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms + (+) The Early Wakeup Interrupt (EWI) can be used if specific safety + operations or data logging must be performed before the actual reset is + generated. When the downcounter reaches the value 0x40, an EWI interrupt + is generated and the corresponding interrupt service routine (ISR) can + be used to trigger specific actions (such as communications or data + logging), before resetting the device. + In some applications, the EWI interrupt can be used to manage a software + system check and/or system recovery/graceful degradation, without + generating a WWDG reset. In this case, the corresponding interrupt + service routine (ISR) should reload the WWDG counter to avoid the WWDG + reset, then trigger the required actions. + Note:When the EWI interrupt cannot be served, e.g. due to a system lock + in a higher priority task, the WWDG reset will eventually be generated. + + (+) Debug mode : When the microcontroller enters debug mode (core halted), + the WWDG counter either continues to work normally or stops, depending + on DBG_WWDG_STOP configuration bit in DBG module, accessible through + __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros ##### How to use this driver ##### ============================================================================== [..] (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). - (+) Set the WWDG prescaler, refresh window and counter value - using HAL_WWDG_Init() function. - (+) Start the WWDG using HAL_WWDG_Start() function. - When the WWDG is enabled the counter value should be configured to - a value greater than 0x40 to prevent generating an immediate reset. - (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is - generated when the counter reaches 0x40, and then start the WWDG using - HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback() is executed and user can - add his own code by customization of function pointer HAL_WWDG_WakeupCallback(). - Once enabled, EWI interrupt cannot be disabled except by a system reset. + + (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup + Interrupt mode using using HAL_WWDG_Init() function. + This enables WWDG peripheral and the downcounter starts downcounting + from given counter value. + Init function can be called again to modify all watchdog parameters, + however if EWI mode has been set once, it can't be clear until next + reset. + (+) The application program must refresh the WWDG counter at regular intervals during normal operation to prevent an MCU reset using HAL_WWDG_Refresh() function. This operation must occur only when - the counter is lower than the refresh window value already programmed. + the counter is lower than the window value already programmed. + + (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when + the counter reaches 0x40. User can add his own code in weak function + HAL_WWDG_EarlyWakeupCallback(). *** WWDG HAL driver macros list *** ================================== [..] Below the list of most used macros in WWDG HAL driver. - - (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral - (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt - (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source - (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status - (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags + + (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source. + (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status. + (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags. @endverbatim ****************************************************************************** @@ -105,13 +130,12 @@ * @{ */ +#ifdef HAL_WWDG_MODULE_ENABLED /** @defgroup WWDG WWDG * @brief WWDG HAL module driver. * @{ */ -#ifdef HAL_WWDG_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -123,30 +147,28 @@ * @{ */ -/** @defgroup WWDG_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. +/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions. * @verbatim ============================================================================== - ##### Initialization and de-initialization functions ##### + ##### Initialization and Configuration functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize the WWDG according to the specified parameters - in the WWDG_InitTypeDef and initialize the associated handle. - (+) DeInitialize the WWDG peripheral. + (+) Initialize and start the WWDG according to the specified parameters + in the WWDG_InitTypeDef of associated handle. (+) Initialize the WWDG MSP. - (+) DeInitialize the WWDG MSP. @endverbatim * @{ */ /** - * @brief Initialize the WWDG according to the specified - * parameters in the WWDG_InitTypeDef and initialize the associated handle. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. + * @brief Initialize the WWDG according to the specified. + * parameters in the WWDG_InitTypeDef of associated handle. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) @@ -162,78 +184,29 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler)); assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window)); assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); - - if(hwwdg->State == HAL_WWDG_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hwwdg->Lock = HAL_UNLOCKED; + assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode)); - /* Init the low level hardware */ - HAL_WWDG_MspInit(hwwdg); - } + /* Init the low level hardware */ + HAL_WWDG_MspInit(hwwdg); - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; + /* Set WWDG Counter */ + WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter)); /* Set WWDG Prescaler and Window */ - MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window)); - - /* Set WWDG Counter */ - MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_READY; + WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window)); /* Return function status */ return HAL_OK; } -/** - * @brief DeInitialize the WWDG peripheral. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg) -{ - /* Check the WWDG handle allocation */ - if(hwwdg == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance)); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; - - /* DeInit the low level hardware */ - HAL_WWDG_MspDeInit(hwwdg); - - /* Reset WWDG Control register */ - hwwdg->Instance->CR = (uint32_t)0x0000007F; - - /* Reset WWDG Configuration register */ - hwwdg->Instance->CFR = (uint32_t)0x0000007F; - - /* Reset WWDG Status register */ - hwwdg->Instance->SR = 0; - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hwwdg); - - /* Return function status */ - return HAL_OK; -} /** * @brief Initialize the WWDG MSP. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @note When rewriting this function in user file, mechanism may be added + * to avoid multiple initialize when HAL_WWDG_Init function is called + * again to change parameters. * @retval None */ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) @@ -246,22 +219,6 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) */ } -/** - * @brief DeInitialize the WWDG MSP. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval None - */ -__weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hwwdg); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_WWDG_MspDeInit could be implemented in the user file - */ -} - /** * @} */ @@ -273,93 +230,25 @@ __weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg) ============================================================================== ##### IO operation functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to: - (+) Start the WWDG. (+) Refresh the WWDG. (+) Handle WWDG interrupt request and associated function callback. -@endverbatim +@endverbatim * @{ */ -/** - * @brief Start the WWDG. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg) -{ - /* Process Locked */ - __HAL_LOCK(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; - - /* Enable the peripheral */ - __HAL_WWDG_ENABLE(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hwwdg); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Start the WWDG with interrupt enabled. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg) -{ - /* Process Locked */ - __HAL_LOCK(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; - - /* Enable the Early Wakeup Interrupt */ - __HAL_WWDG_ENABLE_IT(hwwdg, WWDG_IT_EWI); - - /* Enable the peripheral */ - __HAL_WWDG_ENABLE(hwwdg); - - /* Return function status */ - return HAL_OK; -} - /** * @brief Refresh the WWDG. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @param Counter: value of counter to put in WWDG counter + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval HAL status */ -HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter) +HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg) { - /* Process Locked */ - __HAL_LOCK(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - /* Write to WWDG CR the WWDG Counter value to refresh with */ - MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, Counter); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hwwdg); + WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter)); /* Return function status */ return HAL_OK; @@ -369,13 +258,14 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter) * @brief Handle WWDG interrupt request. * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations * or data logging must be performed before the actual reset is generated. - * The EWI interrupt is enabled when calling HAL_WWDG_Start_IT function. + * The EWI interrupt is enabled by calling HAL_WWDG_Init function with + * EWIMode set to WWDG_EWI_ENABLE. * When the downcounter reaches the value 0x40, and EWI interrupt is * generated and the corresponding Interrupt Service Routine (ISR) can * be used to trigger specific actions (such as communications or data * logging), before resetting the device. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval None */ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) @@ -386,67 +276,31 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) /* Check if WWDG Early Wakeup Interrupt occurred */ if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) { - /* Early Wakeup callback */ - HAL_WWDG_WakeupCallback(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_READY; - /* Clear the WWDG Early Wakeup flag */ __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF); - /* Process Unlocked */ - __HAL_UNLOCK(hwwdg); + /* Early Wakeup callback */ + HAL_WWDG_EarlyWakeupCallback(hwwdg); } } } /** - * @brief Early Wakeup WWDG callback. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. + * @brief WWDG Early Wakeup callback. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval None */ -__weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg) +__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg) { /* Prevent unused argument(s) compilation warning */ UNUSED(hwwdg); /* NOTE: This function should not be modified, when the callback is needed, - the HAL_WWDG_WakeupCallback could be implemented in the user file + the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file */ } -/** - * @} - */ - -/** @defgroup WWDG_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the WWDG handle state. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval HAL state - */ -HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg) -{ - return hwwdg->State; -} - /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_wwdg.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_wwdg.h index 75b07f4422..e17d681676 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_wwdg.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_wwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_wwdg.h * @author MCD Application Team - * @version V1.2.1 - * @date 29-April-2015 + * @version V1.3.0 + * @date 01-July-2016 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention @@ -60,31 +60,22 @@ * @{ */ -/** - * @brief WWDG HAL State Structure definition - */ -typedef enum -{ - HAL_WWDG_STATE_RESET = 0x00, /*!< WWDG not yet initialized or disabled */ - HAL_WWDG_STATE_READY = 0x01, /*!< WWDG initialized and ready for use */ - HAL_WWDG_STATE_BUSY = 0x02, /*!< WWDG internal process is ongoing */ - HAL_WWDG_STATE_TIMEOUT = 0x03, /*!< WWDG timeout state */ - HAL_WWDG_STATE_ERROR = 0x04 /*!< WWDG error state */ -}HAL_WWDG_StateTypeDef; - /** * @brief WWDG Init structure definition */ typedef struct { - uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG. - This parameter can be a value of @ref WWDG_Prescaler */ + uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG. + This parameter can be a value of @ref WWDG_Prescaler */ - uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter. - This parameter must be a number lower than Max_Data = 0x80 */ + uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter. + This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */ - uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. - This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ + uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. + This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ + + uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not. + This parameter can be a value of @ref WWDG_EWI_Mode */ }WWDG_InitTypeDef; @@ -97,10 +88,6 @@ typedef struct WWDG_InitTypeDef Init; /*!< WWDG required parameters */ - HAL_LockTypeDef Lock; /*!< WWDG locking object */ - - __IO HAL_WWDG_StateTypeDef State; /*!< WWDG communication state */ - }WWDG_HandleTypeDef; /** * @} @@ -115,7 +102,7 @@ typedef struct /** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition * @{ */ -#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */ +#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */ /** * @} */ @@ -124,19 +111,27 @@ typedef struct * @brief WWDG Flag definition * @{ */ -#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */ +#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */ /** * @} */ /** @defgroup WWDG_Prescaler WWDG Prescaler * @{ - */ -#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */ -#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ -#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ -#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */ + */ +#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ +#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ +#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */ +/** + * @} + */ +/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode + * @{ + */ +#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */ +#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */ /** * @} */ @@ -150,14 +145,17 @@ typedef struct /** @defgroup WWDG_Private_Macros WWDG Private Macros * @{ */ -#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ - ((__PRESCALER__) == WWDG_PRESCALER_2) || \ - ((__PRESCALER__) == WWDG_PRESCALER_4) || \ - ((__PRESCALER__) == WWDG_PRESCALER_8)) +#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ + ((__PRESCALER__) == WWDG_PRESCALER_2) || \ + ((__PRESCALER__) == WWDG_PRESCALER_4) || \ + ((__PRESCALER__) == WWDG_PRESCALER_8)) -#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F) +#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W)) -#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F)) +#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T)) + +#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \ + ((__MODE__) == WWDG_EWI_DISABLE)) /** * @} */ @@ -169,93 +167,66 @@ typedef struct * @{ */ -/** @brief Reset WWDG handle state. - * @param __HANDLE__: WWDG handle - * @retval None - */ -#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET) - /** * @brief Enable the WWDG peripheral. - * @param __HANDLE__: WWDG handle + * @param __HANDLE__ WWDG handle * @retval None */ -#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) - -/** - * @brief Disable the WWDG peripheral. - * @param __HANDLE__: WWDG handle - * @note WARNING: This is a dummy macro for HAL code alignment. - * Once enable, WWDG Peripheral cannot be disabled except by a system reset. - * @retval None - */ -#define __HAL_WWDG_DISABLE(__HANDLE__) /* dummy macro */ +#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) /** * @brief Enable the WWDG early wakeup interrupt. * @param __HANDLE__: WWDG handle - * @param __INTERRUPT__: specifies the interrupt to enable. + * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt * @note Once enabled this interrupt cannot be disabled except by a system reset. * @retval None */ -#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__)) - -/** - * @brief Disable the WWDG early wakeup interrupt. - * @param __HANDLE__: WWDG handle - * @param __INTERRUPT__: specifies the interrupt to disable. - * This parameter can be one of the following values: - * @arg WWDG_IT_EWI: Early wakeup interrupt - * @note WARNING: This is a dummy macro for HAL code alignment. - * Once enabled this interrupt cannot be disabled except by a system reset. - * @retval None - */ -#define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__) /* dummy macro */ +#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__)) /** * @brief Check whether the selected WWDG interrupt has occurred or not. - * @param __HANDLE__: WWDG handle - * @param __INTERRUPT__: specifies the it to check. + * @param __HANDLE__ WWDG handle + * @param __INTERRUPT__ specifies the it to check. * This parameter can be one of the following values: * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT * @retval The new state of WWDG_FLAG (SET or RESET). */ -#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__)) +#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__)) /** @brief Clear the WWDG interrupt pending bits. * bits to clear the selected interrupt pending bits. - * @param __HANDLE__: WWDG handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ WWDG handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one of the following values: * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag */ -#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__)) +#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__)) /** * @brief Check whether the specified WWDG flag is set or not. - * @param __HANDLE__: WWDG handle - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ WWDG handle + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag * @retval The new state of WWDG_FLAG (SET or RESET). */ -#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) +#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) /** * @brief Clear the WWDG's pending flags. - * @param __HANDLE__: WWDG handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ WWDG handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag * @retval None */ -#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) +#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) /** @brief Check whether the specified WWDG interrupt source is enabled or not. - * @param __HANDLE__: WWDG Handle. - * @param __INTERRUPT__: specifies the WWDG interrupt source to check. + * @param __HANDLE__ WWDG Handle. + * @param __INTERRUPT__ specifies the WWDG interrupt source to check. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early Wakeup Interrupt * @retval state of __INTERRUPT__ (TRUE or FALSE). @@ -277,9 +248,7 @@ typedef struct */ /* Initialization/de-initialization functions **********************************/ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); -HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg); void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); -void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg); /** * @} */ @@ -288,20 +257,9 @@ void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg); * @{ */ /* I/O operation functions ******************************************************/ -HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg); -HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg); -HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter); +HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg); void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg); -void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg); -/** - * @} - */ - -/** @addtogroup WWDG_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State functions **************************************************/ -HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg); +void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg); /** * @} */