mirror of https://github.com/ARMmbed/mbed-os.git
Merge branch 'master' into release
Conflicts: tools/export/uvision4.py tools/export/uvision5.pypull/2175/head
0xc0170
commit
edf015ad92
|
|
@ -0,0 +1,49 @@
|
|||
# Ignoring files from mbed build
|
||||
|
||||
The `.mbedignore` file allows you to ignore files and directories from being processed by `mbed build` command.
|
||||
|
||||
## Usage
|
||||
You can place the `.mbedignore` file in any directory where `mbed build` command is going to search for source files.
|
||||
|
||||
The most convenient place is the root directory of the library or application. However, this is not a requirement.
|
||||
|
||||
Avoid defining rules that would cross the library boundaries as those would lead to side effects or build problems that are hard to find.
|
||||
|
||||
## Syntax
|
||||
|
||||
Each line in the `.mbedignore` file is a file pattern used for matching files. Each matched file or directory is ignored from build.
|
||||
|
||||
The following wildcards are accepted:
|
||||
|
||||
|Pattern | Meaning|
|
||||
|--------|--------|
|
||||
| `*` | Matches everything. |
|
||||
| `?` | Matches any single character. |
|
||||
| `[seq]` | Matches any character in seq. |
|
||||
| `[!seq]` | Matches any character not in seq. |
|
||||
|
||||
File is parsed with Python's [fnmatch](https://docs.python.org/2/library/fnmatch.html) functionality so the syntax follows basic shell patterns with the following exceptions:
|
||||
|
||||
1. Each line is internally prefixed with the path of the `.mbedignore` file.
|
||||
2. Line cannot start with `.` or `/` (because of rule 1)
|
||||
|
||||
Globbing functionality is not used, so you cannot recursively match specific file pattern. You need to define rule per directory in that case.
|
||||
|
||||
Relative paths can be used, so you can match files deeper in the build tree. However, avoid crossing library boundaries.
|
||||
|
||||
### Example
|
||||
A file located in `source/obsolete/.mbedignore` with following content:
|
||||
|
||||
```
|
||||
*.c
|
||||
*.h
|
||||
second_level/*.c
|
||||
```
|
||||
|
||||
After applying the rule 1, actual patterns used internally for matching the source files are:
|
||||
|
||||
```
|
||||
source/obsolete/*.c
|
||||
source/obsolete/*.h
|
||||
source/obsolete/second_level/*.c
|
||||
```
|
||||
|
|
@ -19,6 +19,8 @@
|
|||
#define __MBED_UTIL_CRITICAL_H__
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
|
@ -47,7 +49,7 @@ bool core_util_are_interrupts_enabled(void);
|
|||
* section) will be preserved on exit from the section.
|
||||
* 4) This implementation will currently only work on code running in privileged mode.
|
||||
*/
|
||||
void core_util_critical_section_enter();
|
||||
void core_util_critical_section_enter(void);
|
||||
|
||||
/** Mark the end of a critical section
|
||||
*
|
||||
|
|
@ -60,7 +62,7 @@ void core_util_critical_section_enter();
|
|||
* section) will be preserved on exit from the section.
|
||||
* 4) This implementation will currently only work on code running in privileged mode.
|
||||
*/
|
||||
void core_util_critical_section_exit();
|
||||
void core_util_critical_section_exit(void);
|
||||
|
||||
/**
|
||||
* Atomic compare and set. It compares the contents of a memory location to a
|
||||
|
|
@ -106,7 +108,7 @@ void core_util_critical_section_exit();
|
|||
*
|
||||
* function incr(p : pointer to int, a : int) returns int {
|
||||
* done = false
|
||||
* *value = *p // This fetch operation need not be atomic.
|
||||
* value = *p // This fetch operation need not be atomic.
|
||||
* while not done {
|
||||
* done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
|
||||
* }
|
||||
|
|
@ -159,7 +161,7 @@ bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_
|
|||
*
|
||||
* function incr(p : pointer to int, a : int) returns int {
|
||||
* done = false
|
||||
* *value = *p // This fetch operation need not be atomic.
|
||||
* value = *p // This fetch operation need not be atomic.
|
||||
* while not done {
|
||||
* done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
|
||||
* }
|
||||
|
|
@ -212,7 +214,7 @@ bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uin
|
|||
*
|
||||
* function incr(p : pointer to int, a : int) returns int {
|
||||
* done = false
|
||||
* *value = *p // This fetch operation need not be atomic.
|
||||
* value = *p // This fetch operation need not be atomic.
|
||||
* while not done {
|
||||
* done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
|
||||
* }
|
||||
|
|
@ -222,12 +224,57 @@ bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uin
|
|||
bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue);
|
||||
|
||||
/**
|
||||
* Atomic increment.
|
||||
* @param valuePtr Target memory location being incremented.
|
||||
* @param delta The amount being incremented.
|
||||
* @return The new incremented value.
|
||||
* Atomic compare and set. It compares the contents of a memory location to a
|
||||
* given value and, only if they are the same, modifies the contents of that
|
||||
* memory location to a given new value. This is done as a single atomic
|
||||
* operation. The atomicity guarantees that the new value is calculated based on
|
||||
* up-to-date information; if the value had been updated by another thread in
|
||||
* the meantime, the write would fail due to a mismatched expectedCurrentValue.
|
||||
*
|
||||
* Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
|
||||
* you to the article on compare-and swap].
|
||||
*
|
||||
* @param ptr The target memory location.
|
||||
* @param[in,out] expectedCurrentValue A pointer to some location holding the
|
||||
* expected current value of the data being set atomically.
|
||||
* The computed 'desiredValue' should be a function of this current value.
|
||||
* @Note: This is an in-out parameter. In the
|
||||
* failure case of atomic_cas (where the
|
||||
* destination isn't set), the pointee of expectedCurrentValue is
|
||||
* updated with the current value.
|
||||
* @param[in] desiredValue The new value computed based on '*expectedCurrentValue'.
|
||||
*
|
||||
* @return true if the memory location was atomically
|
||||
* updated with the desired value (after verifying
|
||||
* that it contained the expectedCurrentValue),
|
||||
* false otherwise. In the failure case,
|
||||
* exepctedCurrentValue is updated with the new
|
||||
* value of the target memory location.
|
||||
*
|
||||
* pseudocode:
|
||||
* function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
|
||||
* if *p != *old {
|
||||
* *old = *p
|
||||
* return false
|
||||
* }
|
||||
* *p = new
|
||||
* return true
|
||||
* }
|
||||
*
|
||||
* @Note: In the failure case (where the destination isn't set), the value
|
||||
* pointed to by expectedCurrentValue is still updated with the current value.
|
||||
* This property helps writing concise code for the following incr:
|
||||
*
|
||||
* function incr(p : pointer to int, a : int) returns int {
|
||||
* done = false
|
||||
* value = *p // This fetch operation need not be atomic.
|
||||
* while not done {
|
||||
* done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
|
||||
* }
|
||||
* return value + a
|
||||
* }
|
||||
*/
|
||||
uint8_t core_util_atomic_incr_u8(uint8_t * valuePtr, uint8_t delta);
|
||||
bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *desiredValue);
|
||||
|
||||
/**
|
||||
* Atomic increment.
|
||||
|
|
@ -235,7 +282,7 @@ uint8_t core_util_atomic_incr_u8(uint8_t * valuePtr, uint8_t delta);
|
|||
* @param delta The amount being incremented.
|
||||
* @return The new incremented value.
|
||||
*/
|
||||
uint16_t core_util_atomic_incr_u16(uint16_t * valuePtr, uint16_t delta);
|
||||
uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta);
|
||||
|
||||
/**
|
||||
* Atomic increment.
|
||||
|
|
@ -243,7 +290,26 @@ uint16_t core_util_atomic_incr_u16(uint16_t * valuePtr, uint16_t delta);
|
|||
* @param delta The amount being incremented.
|
||||
* @return The new incremented value.
|
||||
*/
|
||||
uint32_t core_util_atomic_incr_u32(uint32_t * valuePtr, uint32_t delta);
|
||||
uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta);
|
||||
|
||||
/**
|
||||
* Atomic increment.
|
||||
* @param valuePtr Target memory location being incremented.
|
||||
* @param delta The amount being incremented.
|
||||
* @return The new incremented value.
|
||||
*/
|
||||
uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta);
|
||||
|
||||
/**
|
||||
* Atomic increment.
|
||||
* @param valuePtr Target memory location being incremented.
|
||||
* @param delta The amount being incremented in bytes.
|
||||
* @return The new incremented value.
|
||||
*
|
||||
* @note The type of the pointer argument is not taken into account
|
||||
* and the pointer is incremented by bytes.
|
||||
*/
|
||||
void *core_util_atomic_incr_ptr(void **valuePtr, ptrdiff_t delta);
|
||||
|
||||
/**
|
||||
* Atomic decrement.
|
||||
|
|
@ -251,7 +317,7 @@ uint32_t core_util_atomic_incr_u32(uint32_t * valuePtr, uint32_t delta);
|
|||
* @param delta The amount being decremented.
|
||||
* @return The new decremented value.
|
||||
*/
|
||||
uint8_t core_util_atomic_decr_u8(uint8_t * valuePtr, uint8_t delta);
|
||||
uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta);
|
||||
|
||||
/**
|
||||
* Atomic decrement.
|
||||
|
|
@ -259,7 +325,7 @@ uint8_t core_util_atomic_decr_u8(uint8_t * valuePtr, uint8_t delta);
|
|||
* @param delta The amount being decremented.
|
||||
* @return The new decremented value.
|
||||
*/
|
||||
uint16_t core_util_atomic_decr_u16(uint16_t * valuePtr, uint16_t delta);
|
||||
uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta);
|
||||
|
||||
/**
|
||||
* Atomic decrement.
|
||||
|
|
@ -267,7 +333,18 @@ uint16_t core_util_atomic_decr_u16(uint16_t * valuePtr, uint16_t delta);
|
|||
* @param delta The amount being decremented.
|
||||
* @return The new decremented value.
|
||||
*/
|
||||
uint32_t core_util_atomic_decr_u32(uint32_t * valuePtr, uint32_t delta);
|
||||
uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta);
|
||||
|
||||
/**
|
||||
* Atomic decrement.
|
||||
* @param valuePtr Target memory location being decremented.
|
||||
* @param delta The amount being decremented in bytes.
|
||||
* @return The new decremented value.
|
||||
*
|
||||
* @note The type of the pointer argument is not taken into account
|
||||
* and the pointer is decremented by bytes
|
||||
*/
|
||||
void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta);
|
||||
|
||||
#ifdef __cplusplus
|
||||
} // extern "C"
|
||||
|
|
|
|||
|
|
@ -15,15 +15,11 @@
|
|||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#define __STDC_LIMIT_MACROS
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include "critical.h"
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "mbed_assert.h"
|
||||
|
||||
// Module include
|
||||
#include "critical.h"
|
||||
|
||||
#define EXCLUSIVE_ACCESS (!defined (__CORTEX_M0) && !defined (__CORTEX_M0PLUS))
|
||||
|
||||
static volatile uint32_t interrupt_enable_counter = 0;
|
||||
|
|
@ -38,7 +34,7 @@ bool core_util_are_interrupts_enabled(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
void core_util_critical_section_enter()
|
||||
void core_util_critical_section_enter(void)
|
||||
{
|
||||
bool interrupts_disabled = !core_util_are_interrupts_enabled();
|
||||
__disable_irq();
|
||||
|
|
@ -63,7 +59,7 @@ void core_util_critical_section_enter()
|
|||
interrupt_enable_counter++;
|
||||
}
|
||||
|
||||
void core_util_critical_section_exit()
|
||||
void core_util_critical_section_exit(void)
|
||||
{
|
||||
/* If critical_section_enter has not previously been called, do nothing */
|
||||
if (interrupt_enable_counter) {
|
||||
|
|
@ -127,7 +123,7 @@ bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uin
|
|||
return !__STREXW(desiredValue, (volatile uint32_t*)ptr);
|
||||
}
|
||||
|
||||
uint8_t core_util_atomic_incr_u8(uint8_t * valuePtr, uint8_t delta)
|
||||
uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta)
|
||||
{
|
||||
uint8_t newValue;
|
||||
do {
|
||||
|
|
@ -136,7 +132,7 @@ uint8_t core_util_atomic_incr_u8(uint8_t * valuePtr, uint8_t delta)
|
|||
return newValue;
|
||||
}
|
||||
|
||||
uint16_t core_util_atomic_incr_u16(uint16_t * valuePtr, uint16_t delta)
|
||||
uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta)
|
||||
{
|
||||
uint16_t newValue;
|
||||
do {
|
||||
|
|
@ -145,7 +141,7 @@ uint16_t core_util_atomic_incr_u16(uint16_t * valuePtr, uint16_t delta)
|
|||
return newValue;
|
||||
}
|
||||
|
||||
uint32_t core_util_atomic_incr_u32(uint32_t * valuePtr, uint32_t delta)
|
||||
uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta)
|
||||
{
|
||||
uint32_t newValue;
|
||||
do {
|
||||
|
|
@ -155,7 +151,7 @@ uint32_t core_util_atomic_incr_u32(uint32_t * valuePtr, uint32_t delta)
|
|||
}
|
||||
|
||||
|
||||
uint8_t core_util_atomic_decr_u8(uint8_t * valuePtr, uint8_t delta)
|
||||
uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta)
|
||||
{
|
||||
uint8_t newValue;
|
||||
do {
|
||||
|
|
@ -164,7 +160,7 @@ uint8_t core_util_atomic_decr_u8(uint8_t * valuePtr, uint8_t delta)
|
|||
return newValue;
|
||||
}
|
||||
|
||||
uint16_t core_util_atomic_decr_u16(uint16_t * valuePtr, uint16_t delta)
|
||||
uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta)
|
||||
{
|
||||
uint16_t newValue;
|
||||
do {
|
||||
|
|
@ -173,7 +169,7 @@ uint16_t core_util_atomic_decr_u16(uint16_t * valuePtr, uint16_t delta)
|
|||
return newValue;
|
||||
}
|
||||
|
||||
uint32_t core_util_atomic_decr_u32(uint32_t * valuePtr, uint32_t delta)
|
||||
uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta)
|
||||
{
|
||||
uint32_t newValue;
|
||||
do {
|
||||
|
|
@ -236,7 +232,8 @@ bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uin
|
|||
return success;
|
||||
}
|
||||
|
||||
uint8_t core_util_atomic_incr_u8(uint8_t * valuePtr, uint8_t delta)
|
||||
|
||||
uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta)
|
||||
{
|
||||
uint8_t newValue;
|
||||
core_util_critical_section_enter();
|
||||
|
|
@ -246,7 +243,7 @@ uint8_t core_util_atomic_incr_u8(uint8_t * valuePtr, uint8_t delta)
|
|||
return newValue;
|
||||
}
|
||||
|
||||
uint16_t core_util_atomic_incr_u16(uint16_t * valuePtr, uint16_t delta)
|
||||
uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta)
|
||||
{
|
||||
uint16_t newValue;
|
||||
core_util_critical_section_enter();
|
||||
|
|
@ -256,7 +253,7 @@ uint16_t core_util_atomic_incr_u16(uint16_t * valuePtr, uint16_t delta)
|
|||
return newValue;
|
||||
}
|
||||
|
||||
uint32_t core_util_atomic_incr_u32(uint32_t * valuePtr, uint32_t delta)
|
||||
uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta)
|
||||
{
|
||||
uint32_t newValue;
|
||||
core_util_critical_section_enter();
|
||||
|
|
@ -267,7 +264,7 @@ uint32_t core_util_atomic_incr_u32(uint32_t * valuePtr, uint32_t delta)
|
|||
}
|
||||
|
||||
|
||||
uint8_t core_util_atomic_decr_u8(uint8_t * valuePtr, uint8_t delta)
|
||||
uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta)
|
||||
{
|
||||
uint8_t newValue;
|
||||
core_util_critical_section_enter();
|
||||
|
|
@ -277,7 +274,7 @@ uint8_t core_util_atomic_decr_u8(uint8_t * valuePtr, uint8_t delta)
|
|||
return newValue;
|
||||
}
|
||||
|
||||
uint16_t core_util_atomic_decr_u16(uint16_t * valuePtr, uint16_t delta)
|
||||
uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta)
|
||||
{
|
||||
uint16_t newValue;
|
||||
core_util_critical_section_enter();
|
||||
|
|
@ -287,7 +284,7 @@ uint16_t core_util_atomic_decr_u16(uint16_t * valuePtr, uint16_t delta)
|
|||
return newValue;
|
||||
}
|
||||
|
||||
uint32_t core_util_atomic_decr_u32(uint32_t * valuePtr, uint32_t delta)
|
||||
uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta)
|
||||
{
|
||||
uint32_t newValue;
|
||||
core_util_critical_section_enter();
|
||||
|
|
@ -299,3 +296,19 @@ uint32_t core_util_atomic_decr_u32(uint32_t * valuePtr, uint32_t delta)
|
|||
|
||||
#endif
|
||||
|
||||
|
||||
bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *desiredValue) {
|
||||
return core_util_atomic_cas_u32(
|
||||
(uint32_t *)ptr,
|
||||
(uint32_t *)expectedCurrentValue,
|
||||
(uint32_t)desiredValue);
|
||||
}
|
||||
|
||||
void *core_util_atomic_incr_ptr(void **valuePtr, ptrdiff_t delta) {
|
||||
return (void *)core_util_atomic_incr_u32((uint32_t *)valuePtr, (uint32_t)delta);
|
||||
}
|
||||
|
||||
void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta) {
|
||||
return (void *)core_util_atomic_decr_u32((uint32_t *)valuePtr, (uint32_t)delta);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -98,6 +98,9 @@ static void init_serial() {
|
|||
#if DEVICE_SERIAL
|
||||
if (stdio_uart_inited) return;
|
||||
serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX);
|
||||
#if MBED_CONF_CORE_STDIO_BAUD_RATE
|
||||
serial_baud(&stdio_uart, MBED_CONF_CORE_STDIO_BAUD_RATE);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -545,7 +548,6 @@ extern "C" int __wrap_main(void) {
|
|||
// code will call a function to setup argc and argv (__iar_argc_argv) if it is defined.
|
||||
// Since mbed doesn't use argc/argv, we use this function to call our mbed_main.
|
||||
extern "C" void __iar_argc_argv() {
|
||||
mbed_sdk_init();
|
||||
mbed_main();
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -571,7 +571,7 @@
|
|||
"inherits": ["Target"],
|
||||
"progen": {"target": "frdm-k64f"},
|
||||
"detect_code": ["0240"],
|
||||
"device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "STORAGE"],
|
||||
"device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "STORAGE"],
|
||||
"features": ["IPV4"],
|
||||
"release": true
|
||||
},
|
||||
|
|
@ -583,7 +583,7 @@
|
|||
"is_disk_virtual": true,
|
||||
"macros": ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"],
|
||||
"progen": {"target": "mts-gambit"},
|
||||
"device_has": ["I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"]
|
||||
"device_has": ["I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"]
|
||||
},
|
||||
"HEXIWEAR": {
|
||||
"inherits": ["Target"],
|
||||
|
|
@ -595,7 +595,7 @@
|
|||
"default_toolchain": "ARM",
|
||||
"detect_code": ["0214"],
|
||||
"progen": {"target": "hexiwear-k64f"},
|
||||
"device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
|
||||
"device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
|
||||
"default_build": "standard"
|
||||
},
|
||||
"NUCLEO_F030R8": {
|
||||
|
|
@ -985,7 +985,7 @@
|
|||
"extra_labels": ["STM", "STM32F4", "STM32F407", "STM32F407VG"],
|
||||
"macros": ["LSI_VALUE=32000"],
|
||||
"inherits": ["Target"],
|
||||
"progen": {"target": "lpc1768"},
|
||||
"progen": {"target": "arch-max"},
|
||||
"device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
|
||||
"release": true
|
||||
},
|
||||
|
|
|
|||
|
|
@ -1,56 +0,0 @@
|
|||
/* mbed Microcontroller Library - stackheap
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
/* mbed Microcontroller Library - stackheap
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
/* mbed Microcontroller Library - stackheap
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
/* mbed Microcontroller Library - stackheap
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
/* mbed Microcontroller Library - stackheap
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
/* mbed Microcontroller Library - stackheap
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
/* mbed Microcontroller Library - stackheap
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
/* mbed Microcontroller Library - stackheap
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
/* mbed Microcontroller Library - stackheap
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
/* mbed Microcontroller Library - stackheap
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
/* mbed Microcontroller Library - stackheap
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32_hal_legacy.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief This file contains aliases definition for the STM32Cube HAL constants
|
||||
* macros and functions maintained for legacy purpose.
|
||||
******************************************************************************
|
||||
|
|
@ -150,6 +150,9 @@
|
|||
#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
|
||||
#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
|
||||
#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
|
||||
#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
|
||||
#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
|
||||
#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
|
||||
|
||||
#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
|
||||
#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
|
||||
|
|
@ -160,8 +163,16 @@
|
|||
#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
|
||||
#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
|
||||
#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
|
||||
#if defined(STM32L0)
|
||||
/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
|
||||
/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
|
||||
/* to the second dedicated IO (only for COMP2). */
|
||||
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
|
||||
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
|
||||
#else
|
||||
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
|
||||
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
|
||||
#endif
|
||||
#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
|
||||
#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief HAL module driver.
|
||||
* This is the common part of the HAL initialization
|
||||
*
|
||||
|
|
@ -70,11 +70,11 @@
|
|||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief STM32F3xx HAL Driver version number V1.2.1
|
||||
* @brief STM32F3xx HAL Driver version number V1.3.0
|
||||
*/
|
||||
#define __STM32F3xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32F3xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __STM32F3xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
|
||||
#define __STM32F3xx_HAL_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
|
||||
#define __STM32F3xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32F3xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24)\
|
||||
|(__STM32F3xx_HAL_VERSION_SUB1 << 16)\
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief This file contains all the functions prototypes for the HAL
|
||||
* module driver.
|
||||
******************************************************************************
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_adc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Analog to Digital Convertor (ADC)
|
||||
* peripheral:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file containing functions prototypes of ADC HAL library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_adc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Analog to Digital Convertor (ADC)
|
||||
* peripheral:
|
||||
|
|
@ -6941,8 +6941,11 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
|
|||
/* Check the parameters */
|
||||
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
|
||||
assert_param(IS_ADC_MODE(multimode->Mode));
|
||||
assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
|
||||
assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
|
||||
if(multimode->Mode != ADC_MODE_INDEPENDENT)
|
||||
{
|
||||
assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
|
||||
assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
|
||||
}
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hadc);
|
||||
|
|
@ -6964,31 +6967,22 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
|
|||
/* control registers) */
|
||||
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
|
||||
|
||||
/* Configuration of ADC common group ADC1&ADC2, ADC3&ADC4 if available */
|
||||
/* (ADC2, ADC3, ADC4 availability depends on STM32 product) */
|
||||
/* - DMA access mode */
|
||||
MODIFY_REG(tmpADC_Common->CCR ,
|
||||
ADC_CCR_MDMA |
|
||||
ADC_CCR_DMACFG ,
|
||||
multimode->DMAAccessMode |
|
||||
ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
|
||||
|
||||
/* Parameters that can be updated only when ADC is disabled: */
|
||||
/* - Multimode mode selection */
|
||||
/* - Multimode delay */
|
||||
/* Note: If ADC is not in the appropriate state to modify these */
|
||||
/* parameters, their setting is bypassed without error reporting */
|
||||
/* (as it can be the expected behaviour in case of intended action */
|
||||
/* to update parameter above (which fulfills the ADC state */
|
||||
/* condition: no conversion on going on group regular) */
|
||||
/* on the fly). */
|
||||
if ((ADC_IS_ENABLE(hadc) == RESET) &&
|
||||
(ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) )
|
||||
/* If multimode is selected, configure all multimode paramaters. */
|
||||
/* Otherwise, reset multimode parameters (can be used in case of */
|
||||
/* transition from multimode to independent mode). */
|
||||
if(multimode->Mode != ADC_MODE_INDEPENDENT)
|
||||
{
|
||||
/* Configuration of ADC common group ADC1&ADC2, ADC3&ADC4 if available */
|
||||
/* (ADC2, ADC3, ADC4 availability depends on STM32 product) */
|
||||
/* - set the selected multimode */
|
||||
/* - DMA access mode */
|
||||
MODIFY_REG(tmpADC_Common->CCR ,
|
||||
ADC_CCR_MDMA |
|
||||
ADC_CCR_DMACFG ,
|
||||
multimode->DMAAccessMode |
|
||||
ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
|
||||
|
||||
/* Parameters that can be updated only when ADC is disabled: */
|
||||
/* - Multimode mode selection */
|
||||
/* - Set delay between two sampling phases */
|
||||
/* Note: Delay range depends on selected resolution: */
|
||||
/* from 1 to 12 clock cycles for 12 bits */
|
||||
|
|
@ -6997,11 +6991,34 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
|
|||
/* from 1 to 6 clock cycles for 6 bits */
|
||||
/* If a higher delay is selected, it will be clamped to maximum delay */
|
||||
/* range */
|
||||
MODIFY_REG(tmpADC_Common->CCR ,
|
||||
ADC_CCR_MULTI |
|
||||
ADC_CCR_DELAY ,
|
||||
multimode->Mode |
|
||||
multimode->TwoSamplingDelay );
|
||||
/* Note: If ADC is not in the appropriate state to modify these */
|
||||
/* parameters, their setting is bypassed without error reporting */
|
||||
/* (as it can be the expected behaviour in case of intended action */
|
||||
/* to update parameter above (which fulfills the ADC state */
|
||||
/* condition: no conversion on going on group regular) */
|
||||
/* on the fly). */
|
||||
if ((ADC_IS_ENABLE(hadc) == RESET) &&
|
||||
(ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) )
|
||||
{
|
||||
MODIFY_REG(tmpADC_Common->CCR ,
|
||||
ADC_CCR_MULTI |
|
||||
ADC_CCR_DELAY ,
|
||||
multimode->Mode |
|
||||
multimode->TwoSamplingDelay );
|
||||
}
|
||||
}
|
||||
else /* ADC_MODE_INDEPENDENT */
|
||||
{
|
||||
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
|
||||
|
||||
/* Parameters that can be updated only when ADC is disabled: */
|
||||
/* - Multimode mode selection */
|
||||
/* - Multimode delay */
|
||||
if ((ADC_IS_ENABLE(hadc) == RESET) &&
|
||||
(ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) )
|
||||
{
|
||||
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI | ADC_CCR_DELAY);
|
||||
}
|
||||
}
|
||||
}
|
||||
/* If one of the ADC sharing the same common group is enabled, no update */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_adc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file containing functions prototypes of ADC HAL library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_can.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief CAN HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Controller Area Network (CAN) peripheral:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_can.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of CAN HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -239,7 +239,7 @@ typedef struct
|
|||
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< CAN Error code
|
||||
This parameter can be a value of @ref HAL_CAN_Error_Code */
|
||||
This parameter can be a value of @ref CAN_Error_Code */
|
||||
|
||||
}CAN_HandleTypeDef;
|
||||
/**
|
||||
|
|
@ -252,7 +252,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_CAN_Error_Code CAN Error Code
|
||||
/** @defgroup CAN_Error_Code CAN Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CAN_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_cec.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief CEC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the High Definition Multimedia Interface
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_cec.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of CEC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_comp.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief COMP HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the COMP peripheral:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_comp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of COMP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_comp_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of COMP HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief HAL configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_cortex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief CORTEX HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the CORTEX:
|
||||
|
|
@ -22,30 +22,8 @@
|
|||
This section provides functions allowing to configure the NVIC interrupts (IRQ).
|
||||
The Cortex-M4 exceptions are managed by CMSIS functions.
|
||||
|
||||
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
|
||||
function according to the following table.
|
||||
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function
|
||||
|
||||
@brief CORTEX_NVIC_Priority_Table
|
||||
The table below gives the allowed values of the pre-emption priority and subpriority according
|
||||
to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function
|
||||
==========================================================================================================================
|
||||
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
||||
==========================================================================================================================
|
||||
NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
|
||||
| | | 4 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
|
||||
| | | 3 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
|
||||
| | | 2 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
|
||||
| | | 1 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
|
||||
| | | 0 bits for subpriority
|
||||
==========================================================================================================================
|
||||
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
|
||||
|
||||
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
|
||||
|
|
@ -120,6 +98,31 @@
|
|||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
Additional Tables: CORTEX_NVIC_Priority_Table
|
||||
The table below gives the allowed values of the pre-emption priority and subpriority according
|
||||
to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function
|
||||
==========================================================================================================================
|
||||
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
||||
==========================================================================================================================
|
||||
NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
|
||||
| | | 4 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
|
||||
| | | 3 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
|
||||
| | | 2 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
|
||||
| | | 1 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
|
||||
| | | 0 bits for subpriority
|
||||
==========================================================================================================================
|
||||
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of CORTEX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_crc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief CRC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
|
||||
|
|
@ -218,6 +218,9 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
|
|||
/* Reset CRC calculation unit */
|
||||
__HAL_CRC_DR_RESET(hcrc);
|
||||
|
||||
/* Reset IDR register content */
|
||||
CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ;
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
HAL_CRC_MspDeInit(hcrc);
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_crc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of CRC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_crc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Extended CRC HAL module driver.
|
||||
* This file provides firmware functions to manage the extended
|
||||
* functionalities of the CRC peripheral.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_crc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of CRC HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dac.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief DAC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Digital to Analog Converter (DAC) peripheral:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of DAC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dac_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief DACEx HAL module driver.
|
||||
* This file provides firmware functions to manage the extended
|
||||
* functionalities of the DAC peripheral.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dac_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of DAC HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_def.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
******************************************************************************
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dma.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief DMA HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dma.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of DMA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dma_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of DMA HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_flash.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief FLASH HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the internal FLASH memory:
|
||||
|
|
@ -578,7 +578,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
|
|||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral errors functions #####
|
||||
##### Peripheral Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permit to get in run-time errors of the FLASH peripheral.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_flash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of Flash HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_flash_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Extended FLASH HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_flash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of Flash HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief GPIO HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of GPIO HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -229,7 +229,8 @@ typedef enum
|
|||
*/
|
||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
||||
|
||||
#define IS_GPIO_PIN(__PIN__) (((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00)
|
||||
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\
|
||||
(((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00))
|
||||
|
||||
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
|
||||
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_gpio_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of GPIO HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_hrtim.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief TIM HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the High Resolution Timer (HRTIM) peripheral:
|
||||
|
|
@ -1258,6 +1258,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
|
|||
CompareUnit = HRTIM_COMPAREUNIT_2;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
CompareCfg.CompareValue = pSimpleOCChannelCfg->Pulse;
|
||||
|
|
@ -1318,6 +1320,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
|
|||
OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
HRTIM_OutputConfig(hhrtim,
|
||||
|
|
@ -1822,6 +1826,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
|
|||
CompareUnit = HRTIM_COMPAREUNIT_2;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
CompareCfg.CompareValue = pSimplePWMChannelCfg->Pulse;
|
||||
|
|
@ -2030,6 +2036,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,
|
|||
__HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Enable the timer counter */
|
||||
|
|
@ -2104,6 +2112,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
|
|||
__HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Disable the timer counter */
|
||||
|
|
@ -2213,6 +2223,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
|
|||
__HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Enable the timer counter */
|
||||
|
|
@ -2295,6 +2307,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
|
|||
__HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Disable the timer counter */
|
||||
|
|
@ -2452,6 +2466,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,
|
|||
hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Enable the timer counter */
|
||||
|
|
@ -2507,6 +2523,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,
|
|||
hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Disable the timer counter */
|
||||
|
|
@ -2573,6 +2591,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,
|
|||
__HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Enable the timer counter */
|
||||
|
|
@ -2635,6 +2655,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,
|
|||
__HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Disable the timer counter */
|
||||
|
|
@ -2722,7 +2744,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
|
|||
__HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
|
||||
}
|
||||
break;
|
||||
}
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Enable the timer counter */
|
||||
__HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
|
||||
|
|
@ -2793,6 +2817,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
|
|||
__HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Disable the timer counter */
|
||||
|
|
@ -2924,6 +2950,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh
|
|||
CompareUnit = HRTIM_COMPAREUNIT_2;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
CompareCfg.CompareValue = pSimpleOnePulseChannelCfg->Pulse;
|
||||
|
|
@ -3143,6 +3171,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,
|
|||
__HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Enable the timer counter */
|
||||
|
|
@ -3217,6 +3247,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
|
|||
__HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Disable the timer counter */
|
||||
|
|
@ -3709,6 +3741,8 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
|
|||
hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Update the HRTIM registers */
|
||||
|
|
@ -3995,6 +4029,8 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt
|
|||
hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
hhrtim->State = HAL_HRTIM_STATE_READY;
|
||||
|
|
@ -4218,6 +4254,8 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
|
|||
hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
hhrtim->State = HAL_HRTIM_STATE_READY;
|
||||
|
|
@ -4298,6 +4336,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
|
|||
hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
@ -4372,6 +4412,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
|
|||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
hhrtim->State = HAL_HRTIM_STATE_READY;
|
||||
|
|
@ -4431,6 +4473,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
|
|||
hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = pCaptureCfg->Trigger;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
hhrtim->State = HAL_HRTIM_STATE_READY;
|
||||
|
|
@ -4594,6 +4638,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
|
|||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
hhrtim->State = HAL_HRTIM_STATE_READY;
|
||||
|
|
@ -5175,6 +5221,8 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,
|
|||
hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR |= HRTIM_CPT2CR_SWCPT;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
hhrtim->State = HAL_HRTIM_STATE_READY;
|
||||
|
|
@ -5492,6 +5540,8 @@ uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
|
|||
captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return captured_value;
|
||||
|
|
@ -5567,6 +5617,8 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
|
|||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return output_level;
|
||||
|
|
@ -5659,6 +5711,8 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
|
|||
output_bit = HRTIM_OENR_TE2OEN;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != RESET)
|
||||
|
|
@ -5756,6 +5810,8 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim,
|
|||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return delayed_protection_status;
|
||||
|
|
@ -6702,6 +6758,8 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
|
|||
hrtim_bmcr |= ( pTimerCfg->BurstMode << 5);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Update the HRTIM registers */
|
||||
|
|
@ -6750,6 +6808,8 @@ static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
|
|||
hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
@ -6777,6 +6837,8 @@ static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
|
|||
hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -6848,6 +6910,8 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
|
|||
CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
switch (CaptureUnit)
|
||||
|
|
@ -6862,6 +6926,8 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
|
|||
hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -6914,6 +6980,8 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
|
|||
shift = 16;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Clear output config */
|
||||
|
|
@ -7176,6 +7244,8 @@ static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
|
|||
hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -7268,6 +7338,8 @@ static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
|
|||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return interrupt;
|
||||
|
|
@ -7362,6 +7434,8 @@ static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
|
|||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return dma_request;
|
||||
|
|
@ -7404,6 +7478,8 @@ static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef *
|
|||
hdma = hhrtim->hdmaTimerE;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return hdma;
|
||||
|
|
@ -7483,6 +7559,8 @@ static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
|
|||
hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_hrtim.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of HRTIM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -2116,8 +2116,8 @@ typedef struct {
|
|||
((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \
|
||||
|| \
|
||||
(((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
|
||||
((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \
|
||||
((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))
|
||||
(((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \
|
||||
((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))))
|
||||
|
||||
#define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000)
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_i2c.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief I2C HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
|
||||
|
|
@ -88,7 +88,7 @@
|
|||
|
||||
|
||||
*** Interrupt mode IO sequential operation ***
|
||||
===================================
|
||||
==============================================
|
||||
[..]
|
||||
(@) These interfaces allow to manage a sequential transfer with a repeated start condition
|
||||
when a direction change during transfer
|
||||
|
|
@ -115,8 +115,6 @@
|
|||
(++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
|
||||
(+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
|
||||
add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
|
||||
(+++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit
|
||||
(+++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive
|
||||
(++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
|
||||
(+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
|
||||
add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
|
||||
|
|
@ -613,7 +611,8 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
|
|||
* @brief Transmits in master mode an amount of data in blocking mode.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param pData Pointer to data buffer
|
||||
* @param Size Amount of data to be sent
|
||||
* @param Timeout Timeout duration
|
||||
|
|
@ -736,7 +735,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
|
|||
* @brief Receives in master mode an amount of data in blocking mode.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param pData Pointer to data buffer
|
||||
* @param Size Amount of data to be sent
|
||||
* @param Timeout Timeout duration
|
||||
|
|
@ -1131,7 +1131,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
|
|||
* @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param pData Pointer to data buffer
|
||||
* @param Size Amount of data to be sent
|
||||
* @retval HAL status
|
||||
|
|
@ -1199,7 +1200,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
|
|||
* @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param pData Pointer to data buffer
|
||||
* @param Size Amount of data to be sent
|
||||
* @retval HAL status
|
||||
|
|
@ -1365,7 +1367,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
|
|||
* @brief Transmit in master mode an amount of data in non-blocking mode with DMA
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param pData Pointer to data buffer
|
||||
* @param Size Amount of data to be sent
|
||||
* @retval HAL status
|
||||
|
|
@ -1472,7 +1475,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
|
|||
* @brief Receive in master mode an amount of data in non-blocking mode with DMA
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param pData Pointer to data buffer
|
||||
* @param Size Amount of data to be sent
|
||||
* @retval HAL status
|
||||
|
|
@ -1709,7 +1713,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
|
|||
* @brief Write an amount of data in blocking mode to a specific memory address
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param MemAddress Internal memory address
|
||||
* @param MemAddSize Size of internal memory address
|
||||
* @param pData Pointer to data buffer
|
||||
|
|
@ -1860,7 +1865,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
|
|||
* @brief Read an amount of data in blocking mode from a specific memory address
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param MemAddress Internal memory address
|
||||
* @param MemAddSize Size of internal memory address
|
||||
* @param pData Pointer to data buffer
|
||||
|
|
@ -2003,7 +2009,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
|
|||
* @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param MemAddress Internal memory address
|
||||
* @param MemAddSize Size of internal memory address
|
||||
* @param pData Pointer to data buffer
|
||||
|
|
@ -2101,7 +2108,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
|
|||
* @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param MemAddress Internal memory address
|
||||
* @param MemAddSize Size of internal memory address
|
||||
* @param pData Pointer to data buffer
|
||||
|
|
@ -2198,7 +2206,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
|
|||
* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param MemAddress Internal memory address
|
||||
* @param MemAddSize Size of internal memory address
|
||||
* @param pData Pointer to data buffer
|
||||
|
|
@ -2313,7 +2322,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
|
|||
* @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param MemAddress Internal memory address
|
||||
* @param MemAddSize Size of internal memory address
|
||||
* @param pData Pointer to data buffer
|
||||
|
|
@ -2428,7 +2438,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
|
|||
* @note This function is used with Memory devices
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param Trials Number of trials
|
||||
* @param Timeout Timeout duration
|
||||
* @retval HAL status
|
||||
|
|
@ -2545,7 +2556,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
|
|||
* @note This interface allow to manage repeated start condition when a direction change during transfer
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param pData Pointer to data buffer
|
||||
* @param Size Amount of data to be sent
|
||||
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
|
||||
|
|
@ -2618,7 +2630,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
|
|||
* @note This interface allow to manage repeated start condition when a direction change during transfer
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param pData Pointer to data buffer
|
||||
* @param Size Amount of data to be sent
|
||||
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
|
||||
|
|
@ -2876,7 +2889,8 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
|
|||
* @brief Abort a master I2C IT or DMA process communication with Interrupt.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
|
||||
|
|
@ -3054,7 +3068,7 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
|
|||
* @brief Slave Address Match callback.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFEROPTIONS
|
||||
* @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
|
||||
* @param AddrMatchCode: Address Match Code
|
||||
* @retval None
|
||||
*/
|
||||
|
|
@ -3593,7 +3607,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
|
|||
* @brief Master sends target device address followed by internal memory address for write request.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param MemAddress Internal memory address
|
||||
* @param MemAddSize Size of internal memory address
|
||||
* @param Timeout Timeout duration
|
||||
|
|
@ -3659,7 +3674,8 @@ return HAL_OK;
|
|||
* @brief Master sends target device address followed by internal memory address for read request.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param MemAddress Internal memory address
|
||||
* @param MemAddSize Size of internal memory address
|
||||
* @param Timeout Timeout duration
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of I2C HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -314,7 +314,7 @@ typedef struct __I2C_HandleTypeDef
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XferDirection I2C Transfer Direction
|
||||
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_i2c_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief I2C Extended HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of I2C Extended peripheral:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_i2c_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of I2C HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_i2s.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief I2S HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_i2s.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of I2S HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_i2s_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief I2S Extended HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of I2S Extended peripheral:
|
||||
|
|
@ -19,21 +19,7 @@
|
|||
called I2Sxext ie. I2S2ext for SPI2 and I2S3ext for SPI3).
|
||||
(#) The Extended block is not a full SPI IP, it is used only as I2S slave to
|
||||
implement full duplex mode. The Extended block uses the same clock sources
|
||||
as its master (refer to the following Figure).
|
||||
|
||||
+-----------------------+
|
||||
I2Sx_SCK | |
|
||||
----------+-->| I2Sx |------------------->I2Sx_SD(in/out)
|
||||
+--|-->| |
|
||||
| | +-----------------------+
|
||||
| |
|
||||
I2S_WS | |
|
||||
------>| |
|
||||
| | +-----------------------+
|
||||
| +-->| |
|
||||
| | I2Sx_ext |------------------->I2Sx_extSD(in/out)
|
||||
+----->| |
|
||||
+-----------------------+
|
||||
as its master.
|
||||
|
||||
(#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
|
||||
|
||||
|
|
@ -115,6 +101,26 @@
|
|||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
Additional Figure: The Extended block uses the same clock sources as its master.
|
||||
(refer to the following Figure).
|
||||
|
||||
+-----------------------+
|
||||
I2Sx_SCK | |
|
||||
----------+-->| I2Sx |------------------->I2Sx_SD(in/out)
|
||||
+--|-->| |
|
||||
| | +-----------------------+
|
||||
| |
|
||||
I2S_WS | |
|
||||
------>| |
|
||||
| | +-----------------------+
|
||||
| +-->| |
|
||||
| | I2Sx_ext |------------------->I2Sx_extSD(in/out)
|
||||
+----->| |
|
||||
+-----------------------+
|
||||
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_i2s_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of I2S HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_irda.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief IRDA HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the IrDA (Infrared Data Association) Peripheral
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_irda.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief This file contains all the functions prototypes for the IRDA
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_irda_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of IRDA HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,37 +2,43 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_iwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief IWDG HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Independent Watchdog (IWDG) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Initialization and Start functions
|
||||
* + IO operation functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### IWDG Generic features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
[..]
|
||||
(+) The IWDG can be started by either software or hardware (configurable
|
||||
through option byte).
|
||||
through option byte).
|
||||
|
||||
(+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and
|
||||
thus stays active even if the main clock fails.
|
||||
Once the IWDG is started, the LSI is forced ON and cannot be disabled
|
||||
(LSI cannot be disabled too), and the counter starts counting down from
|
||||
the reset value of 0xFFF. When it reaches the end of count value (0x000)
|
||||
a system reset is generated.
|
||||
(+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
|
||||
if the main clock fails.
|
||||
|
||||
(+) The IWDG counter should be refreshed at regular intervals, otherwise the
|
||||
watchdog generates an MCU reset when the counter reaches 0.
|
||||
(+) Once the IWDG is started, the LSI is forced ON and both can not be
|
||||
disabled. The counter starts counting down from the reset value (0xFFF).
|
||||
When it reaches the end of count value (0x000) a reset signal is
|
||||
generated (IWDG reset).
|
||||
|
||||
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
|
||||
the IWDG_RLR value is reloaded in the counter and the watchdog reset is
|
||||
prevented.
|
||||
|
||||
(+) The IWDG is implemented in the VDD voltage domain that is still functional
|
||||
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
|
||||
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
|
||||
reset occurs.
|
||||
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
|
||||
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
|
||||
reset occurs.
|
||||
|
||||
(+) Debug mode : When the microcontroller enters debug mode (core halted),
|
||||
the IWDG counter either continues to work normally or stops, depending
|
||||
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
|
||||
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
|
||||
|
||||
[..] Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s
|
||||
The IWDG timeout may vary due to LSI frequency dispersion. STM32L4xx
|
||||
|
|
@ -40,43 +46,36 @@
|
|||
connected internally to TIM16 CH1 input capture). The measured value
|
||||
can be used to have an IWDG timeout with an acceptable accuracy.
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
If Window option is disabled
|
||||
[..]
|
||||
(#) Use IWDG using HAL_IWDG_Init() function to :
|
||||
(++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
|
||||
clock is forced ON and IWDG counter starts downcounting.
|
||||
(++) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
|
||||
IWDG_WINR.
|
||||
(++) Configure the IWDG prescaler and counter reload value. This reload
|
||||
value will be loaded in the IWDG counter each time the watchdog is
|
||||
reloaded, then the IWDG will start counting down from this value.
|
||||
(++) wait for status flags to be reset"
|
||||
(++) Depending on window parameter:
|
||||
(+++) If Window Init parameter is same as Window register value,
|
||||
nothing more is done but reload counter value in order to exit
|
||||
function withy exact time base.
|
||||
(+++) Else modify Window register. This will automatically reload
|
||||
watchdog counter.
|
||||
|
||||
(+) Use IWDG using HAL_IWDG_Init() function to :
|
||||
(++) Enable write access to IWDG_PR, IWDG_RLR.
|
||||
(++) Configure the IWDG prescaler, counter reload value.
|
||||
This reload value will be loaded in the IWDG counter each time the counter
|
||||
is reloaded, then the IWDG will start counting down from this value.
|
||||
(+) Use IWDG using HAL_IWDG_Start() function to :
|
||||
(++) Reload IWDG counter with value defined in the IWDG_RLR register.
|
||||
(++) Start the IWDG, when the IWDG is used in software mode (no need
|
||||
to enable the LSI, it will be enabled by hardware).
|
||||
(+) Then the application program must refresh the IWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
HAL_IWDG_Refresh() function.
|
||||
[..]
|
||||
if Window option is enabled:
|
||||
|
||||
(+) Use IWDG using HAL_IWDG_Start() function to enable IWDG downcounter
|
||||
(+) Use IWDG using HAL_IWDG_Init() function to :
|
||||
(++) Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
||||
(++) Configure the IWDG prescaler, reload value and window value.
|
||||
(+) Then the application program must refresh the IWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
HAL_IWDG_Refresh() function.
|
||||
(#) Then the application program must refresh the IWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
HAL_IWDG_Refresh() function.
|
||||
|
||||
*** IWDG HAL driver macros list ***
|
||||
====================================
|
||||
[..]
|
||||
Below the list of most used macros in IWDG HAL driver.
|
||||
|
||||
Below the list of most used macros in IWDG HAL driver:
|
||||
(+) __HAL_IWDG_START: Enable the IWDG peripheral
|
||||
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register
|
||||
(+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
|
||||
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
|
||||
the reload register
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
|
|
@ -116,63 +115,63 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG IWDG
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
/** @addtogroup IWDG
|
||||
* @brief IWDG HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Defines IWDG Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000
|
||||
/* Local define used to check the SR status register */
|
||||
#define IWDG_SR_FLAGS (IWDG_FLAG_PVU | IWDG_FLAG_RVU | IWDG_FLAG_WVU)
|
||||
|
||||
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
|
||||
higher prescaler (256), and according to HSI variation, we need to wait at
|
||||
least 6 cycles so 48 ms. */
|
||||
#define HAL_IWDG_DEFAULT_TIMEOUT 48u
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
|
||||
/** @addtogroup IWDG_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions.
|
||||
/** @addtogroup IWDG_Exported_Functions_Group1
|
||||
* @brief Initialization and Start functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
##### Initialization and Start functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the IWDG according to the specified parameters
|
||||
in the IWDG_InitTypeDef and create the associated handle
|
||||
(+) Manage Window option
|
||||
(+) Initialize the IWDG MSP
|
||||
(+) DeInitialize the IWDG MSP
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the IWDG according to the specified parameters in the
|
||||
IWDG_InitTypeDef of associated handle.
|
||||
(+) Manage Window option.
|
||||
(+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
|
||||
is reloaded in order to exit function with correct time base.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the IWDG according to the specified
|
||||
* parameters in the IWDG_InitTypeDef and initialize the associated handle.
|
||||
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* @brief Initialize the IWDG according to the specified parameters in the
|
||||
* IWDG_InitTypeDef and start watchdog. Before exiting function,
|
||||
* watchdog is refreshed in order to have correct time base.
|
||||
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified IWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
uint32_t tickstart;
|
||||
|
||||
/* Check the IWDG handle allocation */
|
||||
if(hiwdg == NULL)
|
||||
|
|
@ -181,227 +180,88 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
|||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
|
||||
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
|
||||
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
|
||||
assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
|
||||
|
||||
/* Check pending flag, if previous update not done, return error */
|
||||
if(((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Enable IWDG. LSI is turned on automaticaly */
|
||||
__HAL_IWDG_START(hiwdg);
|
||||
|
||||
if(hiwdg->State == HAL_IWDG_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hiwdg->Lock = HAL_UNLOCKED;
|
||||
|
||||
/* Init the low level hardware */
|
||||
HAL_IWDG_MspInit(hiwdg);
|
||||
}
|
||||
|
||||
/* Change IWDG peripheral state */
|
||||
hiwdg->State = HAL_IWDG_STATE_BUSY;
|
||||
|
||||
/* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers */
|
||||
/* by writing 0x5555 in KR */
|
||||
/* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
|
||||
0x5555 in KR */
|
||||
IWDG_ENABLE_WRITE_ACCESS(hiwdg);
|
||||
|
||||
/* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
|
||||
MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler);
|
||||
MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload);
|
||||
/* Write to IWDG registers the Prescaler & Reload values to work with */
|
||||
hiwdg->Instance->PR = hiwdg->Init.Prescaler;
|
||||
hiwdg->Instance->RLR = hiwdg->Init.Reload;
|
||||
|
||||
/* check if window option is enabled */
|
||||
if (((hiwdg->Init.Window) != IWDG_WINDOW_DISABLE) || ((hiwdg->Instance->WINR) != IWDG_WINDOW_DISABLE))
|
||||
/* Check pending flag, if previous update not done, return timeout */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for register to be updated */
|
||||
while(hiwdg->Instance->SR != RESET)
|
||||
{
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for register to be updated */
|
||||
while(((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0)
|
||||
if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
|
||||
{
|
||||
/* Set IWDG state */
|
||||
hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
||||
/* Write to IWDG WINR the IWDG_Window value to compare with */
|
||||
MODIFY_REG(hiwdg->Instance->WINR, IWDG_WINR_WIN, hiwdg->Init.Window);
|
||||
}
|
||||
|
||||
/* Change IWDG peripheral state */
|
||||
hiwdg->State = HAL_IWDG_STATE_READY;
|
||||
/* If window parameter is different than current value, modify window
|
||||
register */
|
||||
if(hiwdg->Instance->WINR != hiwdg->Init.Window)
|
||||
{
|
||||
/* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
|
||||
even if window feature is disabled, Watchdog will be reloaded by writing
|
||||
windows register */
|
||||
hiwdg->Instance->WINR = hiwdg->Init.Window;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Reload IWDG counter with value defined in the reload register */
|
||||
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the IWDG MSP.
|
||||
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified IWDG module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hiwdg);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_IWDG_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions_Group2
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Start the IWDG.
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Refresh the IWDG.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start the IWDG.
|
||||
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified IWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hiwdg);
|
||||
|
||||
/* Change IWDG peripheral state */
|
||||
hiwdg->State = HAL_IWDG_STATE_BUSY;
|
||||
|
||||
/* Reload IWDG counter with value defined in the RLR register */
|
||||
if ((hiwdg->Init.Window) == IWDG_WINDOW_DISABLE)
|
||||
{
|
||||
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
|
||||
}
|
||||
|
||||
/* Start the IWDG peripheral */
|
||||
__HAL_IWDG_START(hiwdg);
|
||||
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait until PVU, RVU, WVU flag are RESET */
|
||||
while(((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0)
|
||||
{
|
||||
|
||||
if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
|
||||
{
|
||||
/* Set IWDG state */
|
||||
hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hiwdg);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Change IWDG peripheral state */
|
||||
hiwdg->State = HAL_IWDG_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hiwdg);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Refresh the IWDG.
|
||||
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified IWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hiwdg);
|
||||
|
||||
/* Change IWDG peripheral state */
|
||||
hiwdg->State = HAL_IWDG_STATE_BUSY;
|
||||
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait until RVU flag is RESET */
|
||||
while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
|
||||
{
|
||||
/* Set IWDG state */
|
||||
hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hiwdg);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Reload IWDG counter with value defined in the reload register */
|
||||
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
|
||||
|
||||
/* Change IWDG peripheral state */
|
||||
hiwdg->State = HAL_IWDG_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hiwdg);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the peripheral.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the IWDG handle state.
|
||||
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified IWDG module.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
/* Return IWDG handle state */
|
||||
return hiwdg->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of IWDG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -50,7 +50,7 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG
|
||||
/** @defgroup IWDG IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
@ -59,19 +59,6 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IWDG HAL State Structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */
|
||||
HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */
|
||||
HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
|
||||
HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */
|
||||
HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */
|
||||
|
||||
}HAL_IWDG_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IWDG Init structure definition
|
||||
*/
|
||||
|
|
@ -97,10 +84,6 @@ typedef struct
|
|||
|
||||
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< IWDG Locking object */
|
||||
|
||||
__IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
|
||||
|
||||
}IWDG_HandleTypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -115,21 +98,21 @@ typedef struct
|
|||
/** @defgroup IWDG_Prescaler IWDG Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */
|
||||
#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */
|
||||
#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */
|
||||
#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */
|
||||
#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */
|
||||
#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */
|
||||
#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */
|
||||
#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
|
||||
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
|
||||
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
|
||||
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
|
||||
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
|
||||
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
|
||||
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Window IWDG Window
|
||||
/** @defgroup IWDG_Window_option IWDG Window option
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_WINDOW_DISABLE ((uint32_t)0x00000FFF)
|
||||
#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -143,124 +126,89 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset IWDG handle state.
|
||||
* @param __HANDLE__: IWDG handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the IWDG peripheral.
|
||||
* @param __HANDLE__: IWDG handle
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Reload IWDG counter with value defined in the reload register.
|
||||
* @param __HANDLE__: IWDG handle
|
||||
* @brief Reload IWDG counter with value defined in the reload register
|
||||
* (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
|
||||
|
||||
/**
|
||||
* @brief Get the selected IWDG flag status.
|
||||
* @param __HANDLE__: IWDG handle
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
|
||||
* @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
|
||||
* @arg IWDG_FLAG_WVU: Watchdog counter window value flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE) .
|
||||
*/
|
||||
#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup IWDG_Exported_Functions
|
||||
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions_Group1
|
||||
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
/* Initialization/Start functions ********************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
||||
void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions_Group2
|
||||
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @addtogroup IWDG_Private_Defines
|
||||
/** @defgroup IWDG_Private_Constants IWDG Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief IWDG Key Register BitMask
|
||||
*/
|
||||
#define IWDG_KEY_RELOAD ((uint32_t)0x0000AAAA) /*!< IWDG Reload Counter Enable */
|
||||
#define IWDG_KEY_ENABLE ((uint32_t)0x0000CCCC) /*!< IWDG Peripheral Enable */
|
||||
#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x00005555) /*!< IWDG KR Write Access Enable */
|
||||
#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x00000000) /*!< IWDG KR Write Access Disable */
|
||||
|
||||
/**
|
||||
* @brief IWDG Flag definition
|
||||
*/
|
||||
#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update flag */
|
||||
#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update flag */
|
||||
#define IWDG_FLAG_WVU ((uint32_t)IWDG_SR_WVU) /*!< Watchdog counter window value update flag */
|
||||
#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
|
||||
#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
|
||||
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
|
||||
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Macro IWDG Private Macros
|
||||
/** @defgroup IWDG_Private_Macros IWDG Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
||||
* @param __HANDLE__: IWDG handle
|
||||
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Disables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
||||
* @param __HANDLE__: IWDG handle
|
||||
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
|
||||
|
||||
/**
|
||||
* @brief Check IWDG prescaler value.
|
||||
* @param __PRESCALER__: IWDG prescaler value
|
||||
* @param __PRESCALER__ IWDG prescaler value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
|
||||
|
|
@ -273,17 +221,17 @@ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
|
|||
|
||||
/**
|
||||
* @brief Check IWDG reload value.
|
||||
* @param __RELOAD__: IWDG reload value
|
||||
* @param __RELOAD__ IWDG reload value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
|
||||
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
|
||||
|
||||
/**
|
||||
* @brief Check IWDG window value.
|
||||
* @param __WINDOW__: IWDG window value
|
||||
* @param __WINDOW__ IWDG window value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0xFFF)
|
||||
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_nand.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief NAND HAL module driver.
|
||||
* This file provides a generic firmware to drive NAND memories mounted
|
||||
* as external device.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_nand.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of NAND HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_nor.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief NOR HAL module driver.
|
||||
* This file provides a generic firmware to drive NOR memories mounted
|
||||
* as external device.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_nor.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of NOR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_opamp.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief OPAMP HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the operational amplifiers (OPAMP1,...OPAMP4)
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_opamp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of OPAMP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_opamp_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Extended OPAMP HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_opamp_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of OPAMP HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_pccard.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief PCCARD HAL module driver.
|
||||
* This file provides a generic firmware to drive PCCARD memories mounted
|
||||
* as external device.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_pccard.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of PCCARD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_pcd.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief PCD HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the USB Peripheral Controller:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_pcd.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of PCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_pcd_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Extended PCD HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the USB Peripheral Controller:
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @file stm32f3xx_hal_pcd_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.0
|
||||
* @date 26-June-2015
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of PCD HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief PWR HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
|
|
@ -254,35 +254,31 @@ void HAL_PWR_DisableBkUpAccess(void)
|
|||
/**
|
||||
* @brief Enables the WakeUp PINx functionality.
|
||||
* @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3
|
||||
* This parameter can be value of :
|
||||
* @ref PWREx_WakeUp_Pins
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||||
tmp = CSR_EWUP1_BB + (WakeUpPinx << 2);
|
||||
*(__IO uint32_t *) (tmp) = (uint32_t)ENABLE;
|
||||
/* Enable the EWUPx pin */
|
||||
SET_BIT(PWR->CSR, WakeUpPinx);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the WakeUp PINx functionality.
|
||||
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3
|
||||
* This parameter can be values of :
|
||||
* @ref PWREx_WakeUp_Pins
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||||
tmp = CSR_EWUP1_BB + (WakeUpPinx << 2);
|
||||
*(__IO uint32_t *) (tmp) = (uint32_t)DISABLE;
|
||||
/* Disable the EWUPx pin */
|
||||
CLEAR_BIT(PWR->CSR, WakeUpPinx);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of PWR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -56,39 +56,6 @@
|
|||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PWR_Alias_Exported_Constants PWR Alias Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/* ------------- PWR registers bit address in the alias region ---------------*/
|
||||
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CR Register ---*/
|
||||
#define CR_OFFSET (PWR_OFFSET + 0x00)
|
||||
/* Alias word address of DBP bit */
|
||||
#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
|
||||
#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BIT_NUMBER * 4))
|
||||
|
||||
/* Alias word address of PVDE bit */
|
||||
#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
|
||||
#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BIT_NUMBER * 4))
|
||||
|
||||
/* --- CSR Register ---*/
|
||||
#define CSR_OFFSET (PWR_OFFSET + 0x04)
|
||||
/* Alias word address of EWUP1 bit */
|
||||
#define EWUP1_BitNumber POSITION_VAL(PWR_CSR_EWUP1)
|
||||
#define CSR_EWUP1_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP1_BitNumber * 4))
|
||||
|
||||
/* Alias word address of EWUP2 bit */
|
||||
#define EWUP2_BitNumber POSITION_VAL(PWR_CSR_EWUP2)
|
||||
#define CSR_EWUP2_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP2_BitNumber * 4))
|
||||
|
||||
/* Alias word address of EWUP3 bit */
|
||||
#define EWUP3_BitNumber POSITION_VAL(PWR_CSR_EWUP3)
|
||||
#define CSR_EWUP3_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP3_BitNumber * 4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Constants PWR Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -97,9 +64,9 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_WAKEUP_PIN1 ((uint32_t)0x00) /*!< Wakeup pin 1 */
|
||||
#define PWR_WAKEUP_PIN2 ((uint32_t)0x01) /*!< Wakeup pin 2 */
|
||||
#define PWR_WAKEUP_PIN3 ((uint32_t)0x02) /*!< Wakeup pin 3 */
|
||||
#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) /*!< Wakeup pin 1 */
|
||||
#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) /*!< Wakeup pin 2 */
|
||||
#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) /*!< Wakeup pin 3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_pwr_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Extended PWR HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_pwr_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of PWR HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_rcc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief RCC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Reset and Clock Control (RCC) peripheral:
|
||||
|
|
@ -277,7 +277,7 @@ void HAL_RCC_DeInit(void)
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
uint32_t tickstart = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(RCC_OscInitStruct != NULL);
|
||||
|
|
@ -627,7 +627,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
uint32_t tickstart = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(RCC_ClkInitStruct != NULL);
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_rcc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of RCC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -63,14 +63,14 @@
|
|||
*/
|
||||
|
||||
/* Disable Backup domain write protection state change timeout */
|
||||
#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
|
||||
#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
|
||||
/* LSE state change timeout */
|
||||
#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
|
||||
#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
|
||||
#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
|
||||
#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
|
||||
#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
|
||||
#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
|
||||
#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
|
||||
#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
|
||||
#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
|
||||
#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1004,7 +1004,7 @@ typedef struct
|
|||
#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
|
||||
#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
|
||||
|
||||
#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
|
||||
#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
|
||||
#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
|
||||
#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
|
||||
#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
|
||||
|
|
@ -1029,7 +1029,7 @@ typedef struct
|
|||
#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
|
||||
#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST))
|
||||
|
||||
#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
|
||||
#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
|
||||
#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
|
||||
#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
|
||||
#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
|
||||
|
|
@ -1053,7 +1053,7 @@ typedef struct
|
|||
#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
|
||||
#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
|
||||
|
||||
#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
|
||||
#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
|
||||
#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
|
||||
#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
|
||||
#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
|
||||
|
|
@ -1520,7 +1520,7 @@ typedef struct
|
|||
* access is denied to this domain after reset, you have to enable write
|
||||
* access using the Power Backup Access macro before to configure
|
||||
* the RTC clock source (to be done once after reset).
|
||||
* @note Once the RTC clock is configured it can't be changed unless the
|
||||
* @note Once the RTC clock is configured it cannot be changed unless the
|
||||
* Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
|
||||
* a Power On Reset (POR).
|
||||
*
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_rcc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Extended RCC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities RCC extension peripheral:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_rcc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of RCC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_rtc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief RTC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Real-Time Clock (RTC) peripheral:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of RTC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_rtc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Extended RTC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Real Time Clock (RTC) Extended peripheral:
|
||||
|
|
@ -895,8 +895,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
|
|||
}
|
||||
}
|
||||
|
||||
/* Disable the Wake-Up timer */
|
||||
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
|
||||
|
||||
/* Clear flag Wake-Up */
|
||||
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
|
||||
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_rtc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of RTC HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_sdadc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Sigma-Delta Analog to Digital Converter
|
||||
* (SDADC) peripherals:
|
||||
|
|
@ -535,7 +535,7 @@ HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc,
|
|||
channelnum = (uint32_t)(Channel>>16);
|
||||
|
||||
/* Set the channel configuration */
|
||||
hsdadc->Instance->CONFCHR1 &= (uint32_t) ~(SDADC_CONFCHR1_CONFCH0 << (channelnum << 2));
|
||||
hsdadc->Instance->CONFCHR1 &= (uint32_t) ~((uint32_t)SDADC_CONFCHR1_CONFCH0 << (channelnum << 2));
|
||||
hsdadc->Instance->CONFCHR1 |= (uint32_t) (ConfIndex << (channelnum << 2));
|
||||
}
|
||||
else
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_sdadc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief This file contains all the functions prototypes for the SDADC
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_smartcard.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief SMARTCARD HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the SMARTCARD peripheral:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_smartcard.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of SMARTCARD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_smartcard_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief SMARTCARD HAL module driver.
|
||||
*
|
||||
* This file provides extended firmware functions to manage the following
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_smartcard_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of SMARTCARD HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx_hal_smbus.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 29-April-2015
|
||||
* @version V1.3.0
|
||||
* @date 01-July-2016
|
||||
* @brief SMBUS HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the System Management Bus (SMBus) peripheral,
|
||||
|
|
@ -438,7 +438,8 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
|
|||
* @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
|
||||
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified SMBUS.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param pData Pointer to data buffer
|
||||
* @param Size Amount of data to be sent
|
||||
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
|
||||
|
|
@ -526,7 +527,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
|
|||
* @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
|
||||
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified SMBUS.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param pData Pointer to data buffer
|
||||
* @param Size Amount of data to be sent
|
||||
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
|
||||
|
|
@ -608,7 +610,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1
|
|||
* @note This abort can be called only if state is ready
|
||||
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified SMBUS.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
|
||||
|
|
@ -911,7 +914,8 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
|
|||
* @brief Check if target device is ready for communication.
|
||||
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified SMBUS.
|
||||
* @param DevAddress Target device address
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
* in datasheet must be shift at right before call interface
|
||||
* @param Trials Number of trials
|
||||
* @param Timeout Timeout duration
|
||||
* @retval HAL status
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue