mirror of https://github.com/ARMmbed/mbed-os.git
Fix LPC17XX and LPC40XX USB race condition
If a SETUP packet arrives shortly after an IN then the packets will be processed in the wrong order - SETUP first then IN. This causes the subsequent control transfer to fail. Fix this problem by processing IN packets before processing SETUP packets.pull/5878/head
parent
635a82495c
commit
eda332cbf8
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@ -590,6 +590,25 @@ void USBHAL::usbisr(void) {
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if (LPC_USB->USBDevIntSt & EP_SLOW) {
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if (LPC_USB->USBDevIntSt & EP_SLOW) {
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// (Slow) Endpoint Interrupt
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// (Slow) Endpoint Interrupt
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// Process IN packets before SETUP packets
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// Note - order of OUT and SETUP does not matter as OUT packets
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// are clobbered by SETUP packets and thus ignored.
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//
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// A SETUP packet can arrive at any time where as an IN packet is
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// only sent after calling EP0write and an OUT packet after EP0read.
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// The functions EP0write and EP0read are called only in response to
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// a setup packet or IN/OUT packets sent in response to that
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// setup packet. Therefore, if an IN or OUT packet is pending
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// at the same time as a SETUP packet, the IN or OUT packet belongs
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// to the previous control transfer and should either be processed
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// before the SETUP packet (in the case of IN) or dropped (in the
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// case of OUT as SETUP clobbers the OUT data).
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if (LPC_USB->USBEpIntSt & EP(EP0IN)) {
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selectEndpointClearInterrupt(EP0IN);
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LPC_USB->USBDevIntClr = EP_SLOW;
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EP0in();
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}
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// Process each endpoint interrupt
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// Process each endpoint interrupt
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if (LPC_USB->USBEpIntSt & EP(EP0OUT)) {
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if (LPC_USB->USBEpIntSt & EP(EP0OUT)) {
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if (selectEndpointClearInterrupt(EP0OUT) & SIE_SE_STP) {
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if (selectEndpointClearInterrupt(EP0OUT) & SIE_SE_STP) {
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@ -601,12 +620,6 @@ void USBHAL::usbisr(void) {
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LPC_USB->USBDevIntClr = EP_SLOW;
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LPC_USB->USBDevIntClr = EP_SLOW;
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}
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}
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if (LPC_USB->USBEpIntSt & EP(EP0IN)) {
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selectEndpointClearInterrupt(EP0IN);
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LPC_USB->USBDevIntClr = EP_SLOW;
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EP0in();
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}
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for (uint8_t num = 2; num < 16*2; num++) {
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for (uint8_t num = 2; num < 16*2; num++) {
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if (LPC_USB->USBEpIntSt & EP(num)) {
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if (LPC_USB->USBEpIntSt & EP(num)) {
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selectEndpointClearInterrupt(num);
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selectEndpointClearInterrupt(num);
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@ -595,6 +595,25 @@ void USBHAL::usbisr(void) {
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if (LPC_USB->DevIntSt & EP_SLOW) {
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if (LPC_USB->DevIntSt & EP_SLOW) {
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// (Slow) Endpoint Interrupt
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// (Slow) Endpoint Interrupt
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// Process IN packets before SETUP packets
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// Note - order of OUT and SETUP does not matter as OUT packets
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// are clobbered by SETUP packets and thus ignored.
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//
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// A SETUP packet can arrive at any time where as an IN packet is
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// only sent after calling EP0write and an OUT packet after EP0read.
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// The functions EP0write and EP0read are called only in response to
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// a setup packet or IN/OUT packets sent in response to that
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// setup packet. Therefore, if an IN or OUT packet is pending
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// at the same time as a SETUP packet, the IN or OUT packet belongs
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// to the previous control transfer and should either be processed
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// before the SETUP packet (in the case of IN) or dropped (in the
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// case of OUT as SETUP clobbers the OUT data).
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if (LPC_USB->EpIntSt & EP(EP0IN)) {
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selectEndpointClearInterrupt(EP0IN);
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LPC_USB->DevIntClr = EP_SLOW;
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EP0in();
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}
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// Process each endpoint interrupt
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// Process each endpoint interrupt
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if (LPC_USB->EpIntSt & EP(EP0OUT)) {
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if (LPC_USB->EpIntSt & EP(EP0OUT)) {
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if (selectEndpointClearInterrupt(EP0OUT) & SIE_SE_STP) {
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if (selectEndpointClearInterrupt(EP0OUT) & SIE_SE_STP) {
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@ -606,12 +625,6 @@ void USBHAL::usbisr(void) {
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LPC_USB->DevIntClr = EP_SLOW;
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LPC_USB->DevIntClr = EP_SLOW;
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}
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}
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if (LPC_USB->EpIntSt & EP(EP0IN)) {
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selectEndpointClearInterrupt(EP0IN);
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LPC_USB->DevIntClr = EP_SLOW;
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EP0in();
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}
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for (uint8_t num = 2; num < 16*2; num++) {
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for (uint8_t num = 2; num < 16*2; num++) {
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if (LPC_USB->EpIntSt & EP(num)) {
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if (LPC_USB->EpIntSt & EP(num)) {
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selectEndpointClearInterrupt(num);
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selectEndpointClearInterrupt(num);
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