diff --git a/libraries/mbed/targets/cmsis/Freescale/TARGET_KL05Z/TOOLCHAIN_ARM_STD/startup_MKL05Z4.s b/libraries/mbed/targets/cmsis/Freescale/TARGET_KL05Z/TOOLCHAIN_ARM_STD/startup_MKL05Z4.s index 3b9d260435..2fbfad0338 100644 --- a/libraries/mbed/targets/cmsis/Freescale/TARGET_KL05Z/TOOLCHAIN_ARM_STD/startup_MKL05Z4.s +++ b/libraries/mbed/targets/cmsis/Freescale/TARGET_KL05Z/TOOLCHAIN_ARM_STD/startup_MKL05Z4.s @@ -74,7 +74,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD LPTimer_IRQHandler ; LPTimer interrupt DCD Reserved_45_IRQHandler ; Reserved interrupt 45 DCD PORTA_IRQHandler ; Port A interrupt - DCD PORTD_IRQHandler ; Port D interrupt + DCD PORTB_IRQHandler ; Port B interrupt __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors @@ -286,7 +286,7 @@ Default_Handler PROC EXPORT LPTimer_IRQHandler [WEAK] EXPORT Reserved_45_IRQHandler [WEAK] EXPORT PORTA_IRQHandler [WEAK] - EXPORT PORTD_IRQHandler [WEAK] + EXPORT PORTB_IRQHandler [WEAK] EXPORT DefaultISR [WEAK] DMA0_IRQHandler @@ -320,7 +320,7 @@ MCG_IRQHandler LPTimer_IRQHandler Reserved_45_IRQHandler PORTA_IRQHandler -PORTD_IRQHandler +PORTB_IRQHandler DefaultISR B . diff --git a/libraries/mbed/targets/cmsis/Freescale/TARGET_KL05Z/system_MKL05Z4.c b/libraries/mbed/targets/cmsis/Freescale/TARGET_KL05Z/system_MKL05Z4.c index 68f90445bf..87d52b1e0c 100644 --- a/libraries/mbed/targets/cmsis/Freescale/TARGET_KL05Z/system_MKL05Z4.c +++ b/libraries/mbed/targets/cmsis/Freescale/TARGET_KL05Z/system_MKL05Z4.c @@ -90,5 +90,67 @@ extern int stdio_retargeting_module; ---------------------------------------------------------------------------- */ void SystemCoreClockUpdate(void) { -/* TODO */ + uint32_t MCGOUTClock; + uint8_t Divider; + + if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) { + /* FLL is selected */ + if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) { + /* External reference clock is selected */ + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ + if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) { + MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */ + } + } else { + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ + } + + /* Select correct multiplier to calculate the MCG output clock */ + switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { + case 0x0u: + MCGOUTClock *= 640u; + break; + case 0x20u: + MCGOUTClock *= 1280u; + break; + case 0x40u: + MCGOUTClock *= 1920u; + break; + case 0x60u: + MCGOUTClock *= 2560u; + break; + case 0x80u: + MCGOUTClock *= 732u; + break; + case 0xA0u: + MCGOUTClock *= 1464u; + break; + case 0xC0u: + MCGOUTClock *= 2197u; + break; + case 0xE0u: + MCGOUTClock *= 2929u; + break; + default: + break; + } + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) { + /* Internal reference clock is selected */ + if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) { + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ + } else { + MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */ + } + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) { + /* External reference clock is selected */ + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + } else { + /* Reserved value */ + return; + } + + SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); + } diff --git a/libraries/mbed/targets/hal/Freescale/TARGET_KL05Z/rtc_api.c b/libraries/mbed/targets/hal/Freescale/TARGET_KL05Z/rtc_api.c index e9b185764c..3727bc26e5 100644 --- a/libraries/mbed/targets/hal/Freescale/TARGET_KL05Z/rtc_api.c +++ b/libraries/mbed/targets/hal/Freescale/TARGET_KL05Z/rtc_api.c @@ -16,26 +16,26 @@ #include "rtc_api.h" static void init(void) { - /* - * configure PTA5 with alternate function 1: RTC_CLKIN - * As the kl05z board does not have a 32kHz osc, - * we use an external clock generated by the - * interface chip - */ - PORTA->PCR[5] &= ~PORT_PCR_MUX_MASK; - PORTA->PCR[5] = PORT_PCR_MUX(1); + // enable RTC clock + SIM->SCGC6 |= SIM_SCGC6_RTC_MASK; - // select RTC_CLKIN as RTC clock source + // select OSC32 as RTC clock source SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK; - SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(2); + } void rtc_init(void) { + uint32_t i; init(); //Configure the TSR. default value: 1 RTC->TSR = 1; + RTC->CR |= RTC_CR_OSCE_MASK; + + //delay for OSCE stabilization + for(i=0; i<0x100000; i++); + // enable counter RTC->SR |= RTC_SR_TCE_MASK; } @@ -54,8 +54,9 @@ int rtc_isenabled(void) { // if RTC not enabled return 0 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; SIM->SCGC6 |= SIM_SCGC6_RTC_MASK; - if ((RTC->SR & RTC_SR_TCE_MASK) == 0) + if ((RTC->SR & RTC_SR_TCE_MASK) == 0) { return 0; + } init(); return 1; @@ -71,8 +72,9 @@ void rtc_write(time_t t) { // we do not write 0 into TSR // to avoid invalid time - if (t == 0) + if (t == 0) { t = 1; + } // write seconds RTC->TSR = t; diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index e8af9513f7..2799511683 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -66,7 +66,6 @@ class KL05Z(Target): Target.__init__(self) self.core = "Cortex-M0+" - self.vendor = "Freescale" self.supported_toolchains = ["ARM"]