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TARGET_STM32L1 astyle

pull/7351/head
jeromecoutant 2018-06-27 14:44:37 +02:00
parent baf97d78aa
commit ecffec8336
19 changed files with 235 additions and 192 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/PeripheralNames.h
View File

@ -50,9 +50,9 @@ typedef enum {
UART_3 = (int)USART3_BASE
} UARTName;
#define STDIO_UART_TX PA_2
#define STDIO_UART_RX PA_3
#define STDIO_UART UART_2
#define STDIO_UART_TX PA_2
#define STDIO_UART_RX PA_3
#define STDIO_UART UART_2
typedef enum {
SPI_1 = (int)SPI1_BASE,

2
targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/PinNames.h
View File

@ -234,7 +234,7 @@ typedef enum {
I2C_SCL = I2C0_SCL,
I2C_SDA = I2C0_SDA,
} PinName;
#ifdef __cplusplus

32
targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_eeprom.c
View File

@ -34,13 +34,13 @@
#define XDOT_EEPROM_SIZE 0x00002000
typedef union {
uint32_t* w;
uint8_t* b;
uint32_t *w;
uint8_t *b;
} b2w;
typedef union {
uint16_t* hw;
uint8_t* b;
uint16_t *hw;
uint8_t *b;
} b2hw;
enum {
@ -49,7 +49,8 @@ enum {
word_write
};
static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data) {
static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data)
{
if (addr > XDOT_EEPROM_SIZE - 1) {
return -1;
}
@ -61,7 +62,8 @@ static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data) {
}
}
static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data) {
static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data)
{
if (addr > XDOT_EEPROM_SIZE - 2) {
return -1;
}
@ -73,7 +75,8 @@ static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data) {
}
}
static int xdot_eeprom_write_word(uint32_t addr, uint32_t data) {
static int xdot_eeprom_write_word(uint32_t addr, uint32_t data)
{
if (addr > XDOT_EEPROM_SIZE - 4) {
return -1;
}
@ -85,18 +88,20 @@ static int xdot_eeprom_write_word(uint32_t addr, uint32_t data) {
}
}
static int xdot_eeprom_read_byte(uint32_t addr, uint8_t* data) {
static int xdot_eeprom_read_byte(uint32_t addr, uint8_t *data)
{
if (addr > XDOT_EEPROM_SIZE - 1) {
return -1;
}
*data = (*((uint8_t*)(XDOT_EEPROM_START + addr)));
*data = (*((uint8_t *)(XDOT_EEPROM_START + addr)));
return 0;
}
int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) {
int xdot_eeprom_write_buf(uint32_t addr, uint8_t *buf, uint32_t size)
{
uint32_t bytes_written = 0;
if (addr + size > XDOT_EEPROM_SIZE) {
@ -133,7 +138,7 @@ int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) {
}
//printf("%smatch\r\n", mismatch[i] ? "mis" : "");
}
if (! (mismatch[0] || mismatch[1] || mismatch[2] || mismatch[3])) {
if (!(mismatch[0] || mismatch[1] || mismatch[2] || mismatch[3])) {
//printf("all match - no write necessary\r\n");
bytes_written += 4;
continue;
@ -180,7 +185,7 @@ int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) {
}
//printf("%smatch\r\n", mismatch[i] ? "mis" : "");
}
if (! (mismatch[0] || mismatch[1])) {
if (!(mismatch[0] || mismatch[1])) {
//printf("all match - no write necessary\r\n");
bytes_written += 2;
continue;
@ -261,7 +266,8 @@ int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) {
return 0;
}
int xdot_eeprom_read_buf(uint32_t addr, uint8_t* buf, uint32_t size) {
int xdot_eeprom_read_buf(uint32_t addr, uint8_t *buf, uint32_t size)
{
if (addr + size > XDOT_EEPROM_SIZE) {
return -1;
}

4
targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_eeprom.h
View File

@ -46,7 +46,7 @@ extern "C" {
* valid addresses are 0x0000 - 0x1FFF
* returns 0 if all data was successfully written otherwise -1
*/
int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size);
int xdot_eeprom_write_buf(uint32_t addr, uint8_t *buf, uint32_t size);
/* xdot_eeprom_read_buf
* attempts to read size bytes into buf starting at addr
@ -54,7 +54,7 @@ int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size);
* valid addresses are 0x0000 - 0x1FFF
* returns 0 if all data was successfully read otherwise -1
*/
int xdot_eeprom_read_buf(uint32_t addr, uint8_t* buf, uint32_t size);
int xdot_eeprom_read_buf(uint32_t addr, uint8_t *buf, uint32_t size);
#ifdef __cplusplus
}

41
targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_low_power.c
View File

@ -37,15 +37,18 @@ static uint32_t portB[6];
static uint32_t portC[6];
static uint32_t portH[6];
void xdot_disable_systick_int() {
void xdot_disable_systick_int()
{
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
void xdot_enable_systick_int() {
void xdot_enable_systick_int()
{
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
}
void xdot_save_gpio_state() {
void xdot_save_gpio_state()
{
portA[0] = GPIOA->MODER;
portA[1] = GPIOA->OTYPER;
portA[2] = GPIOA->OSPEEDR;
@ -75,7 +78,8 @@ void xdot_save_gpio_state() {
portH[5] = GPIOH->AFR[1];
}
void xdot_restore_gpio_state() {
void xdot_restore_gpio_state()
{
GPIOA->MODER = portA[0];
GPIOA->OTYPER = portA[1];
GPIOA->OSPEEDR = portA[2];
@ -105,7 +109,8 @@ void xdot_restore_gpio_state() {
GPIOH->AFR[1] = portH[5];
}
void xdot_enter_stop_mode() {
void xdot_enter_stop_mode()
{
GPIO_InitTypeDef GPIO_InitStruct;
// disable ADC and DAC - they can consume power in stop mode
@ -224,8 +229,8 @@ void xdot_enter_stop_mode() {
HSERCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
HSERCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 24 MHz xtal on OSC_IN/OSC_OUT */
HSERCC_OscInitStruct.HSIState = RCC_HSI_OFF;
// SYSCLK = 32 MHz ((24 MHz * 4) / 3)
// USBCLK = 48 MHz ((24 MHz * 4) / 2) --> USB OK
// SYSCLK = 32 MHz ((24 MHz * 4) / 3)
// USBCLK = 48 MHz ((24 MHz * 4) / 2) --> USB OK
HSERCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
HSERCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
HSERCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
@ -249,12 +254,12 @@ void xdot_enter_stop_mode() {
/* Enable the HSI for ADC peripherals */
RCC_OscInitTypeDef HSIRCC_OscInitStruct;
HAL_RCC_GetOscConfig(&HSIRCC_OscInitStruct);
if ( HSIRCC_OscInitStruct.HSIState != RCC_HSI_ON ) {
if (HSIRCC_OscInitStruct.HSIState != RCC_HSI_ON) {
HSIRCC_OscInitStruct.HSIState = RCC_HSI_ON;
HSIRCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
HSIRCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
HAL_StatusTypeDef ret = HAL_RCC_OscConfig(&HSIRCC_OscInitStruct);
if ( ret != HAL_OK ) {
if (ret != HAL_OK) {
debug("HSI initialization failed - ADC will not function properly\r\n");
}
}
@ -271,18 +276,22 @@ void xdot_enter_stop_mode() {
DAC->CR |= DAC_CR_EN2;
}
void xdot_enter_standby_mode() {
void xdot_enter_standby_mode()
{
// enable ULP and enable fast wakeup
HAL_PWREx_EnableUltraLowPower();
HAL_PWREx_EnableFastWakeUp();
// disable HSI, MSI, and LSI if they are running
if (RCC->CR & RCC_CR_HSION)
if (RCC->CR & RCC_CR_HSION) {
RCC->CR &= ~RCC_CR_HSION;
if (RCC->CR & RCC_CR_MSION)
}
if (RCC->CR & RCC_CR_MSION) {
RCC->CR &= ~RCC_CR_MSION;
if (RCC->CSR & RCC_CSR_LSION)
}
if (RCC->CSR & RCC_CSR_LSION) {
RCC->CSR &= ~RCC_CSR_LSION;
}
// make sure wakeup and standby flags are cleared
@ -293,10 +302,12 @@ void xdot_enter_standby_mode() {
HAL_PWR_EnterSTANDBYMode();
}
void xdot_enable_standby_wake_pin() {
void xdot_enable_standby_wake_pin()
{
HAL_PWR_EnableWakeUpPin(PWR_WAKEUP_PIN1);
}
void xdot_disable_standby_wake_pin() {
void xdot_disable_standby_wake_pin()
{
HAL_PWR_DisableWakeUpPin(PWR_WAKEUP_PIN1);
}

2
targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/PinNames.h
View File

@ -94,7 +94,7 @@ typedef enum {
SPI_RF_MISO = PA_6,
SPI_RF_SCK = PA_5,
SPI_RF_CS = PB_0,
SPI_RF_RESET= PB_13,
SPI_RF_RESET = PB_13,
DIO0 = PA_11,
DIO1 = PB_1,

44
targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h
View File

@ -48,19 +48,19 @@ typedef enum {
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
PA_1_ALT0 = PA_1|ALT0,
PA_1_ALT1 = PA_1|ALT1,
PA_1_ALT0 = PA_1 | ALT0,
PA_1_ALT1 = PA_1 | ALT1,
PA_2 = 0x02,
PA_3 = 0x03,
PA_4 = 0x04,
PA_4_ALT0 = PA_4|ALT0,
PA_4_ALT0 = PA_4 | ALT0,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
@ -69,27 +69,27 @@ typedef enum {
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PA_15_ALT0 = PA_15|ALT0,
PA_15_ALT0 = PA_15 | ALT0,
PB_0 = 0x10,
PB_1 = 0x11,
PB_2 = 0x12,
PB_3 = 0x13,
PB_3_ALT0 = PB_3|ALT0,
PB_3_ALT0 = PB_3 | ALT0,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT1 = PB_4|ALT1,
PB_4_ALT0 = PB_4 | ALT0,
PB_4_ALT1 = PB_4 | ALT1,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT1 = PB_5|ALT1,
PB_5_ALT0 = PB_5 | ALT0,
PB_5_ALT1 = PB_5 | ALT1,
PB_6 = 0x16,
PB_7 = 0x17,
PB_8 = 0x18,
PB_8_ALT0 = PB_8|ALT0,
PB_8_ALT1 = PB_8|ALT1,
PB_8_ALT0 = PB_8 | ALT0,
PB_8_ALT1 = PB_8 | ALT1,
PB_9 = 0x19,
PB_9_ALT0 = PB_9|ALT0,
PB_9_ALT1 = PB_9|ALT1,
PB_9_ALT0 = PB_9 | ALT0,
PB_9_ALT1 = PB_9 | ALT1,
PB_10 = 0x1A,
PB_11 = 0x1B,
PB_12 = 0x1C,
@ -108,9 +108,9 @@ typedef enum {
PC_8 = 0x28,
PC_9 = 0x29,
PC_10 = 0x2A,
PC_10_ALT0 = PC_10|ALT0,
PC_10_ALT0 = PC_10 | ALT0,
PC_11 = 0x2B,
PC_11_ALT0 = PC_11|ALT0,
PC_11_ALT0 = PC_11 | ALT0,
PC_12 = 0x2C,
PC_13 = 0x2D,
PC_14 = 0x2E,
@ -181,17 +181,17 @@ typedef enum {
SPI_CS = PB_6,
PWM_OUT = PB_3,
/**** USB pins ****/
/**** USB pins ****/
USB_DM = PA_11,
USB_DP = PA_12,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PH_0,
RCC_OSC_OUT = PH_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_TRACESWO = PB_3,

24
targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PeripheralNames.h
View File

@ -51,20 +51,20 @@ typedef enum {
} UARTName;
#if (MX_DEFAULT_SERIAL_PINS == 0)
//Use B10/B11 as default serial port
#define STDIO_UART_TX PB_10
#define STDIO_UART_RX PB_11
#define STDIO_UART UART_3
//Use B10/B11 as default serial port
#define STDIO_UART_TX PB_10
#define STDIO_UART_RX PB_11
#define STDIO_UART UART_3
#elif (MX_DEFAULT_SERIAL_PINS == 1)
//Use A2/A3 as default serial port
#define STDIO_UART_TX PA_2
#define STDIO_UART_RX PA_3
#define STDIO_UART UART_2
//Use A2/A3 as default serial port
#define STDIO_UART_TX PA_2
#define STDIO_UART_RX PA_3
#define STDIO_UART UART_2
#else
//Use A2/A3 as default serial port
#define STDIO_UART_TX PA_2
#define STDIO_UART_RX PA_3
#define STDIO_UART UART_2
//Use A2/A3 as default serial port
#define STDIO_UART_TX PA_2
#define STDIO_UART_RX PA_3
#define STDIO_UART UART_2
#endif
typedef enum {

6
targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PeripheralNames.h
View File

@ -50,9 +50,9 @@ typedef enum {
UART_3 = (int)USART3_BASE
} UARTName;
#define STDIO_UART_TX PA_2
#define STDIO_UART_RX PA_3
#define STDIO_UART UART_2
#define STDIO_UART_TX PA_2
#define STDIO_UART_RX PA_3
#define STDIO_UART UART_2
typedef enum {
SPI_1 = (int)SPI1_BASE,

2
targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PinNames.h
View File

@ -151,7 +151,7 @@ typedef enum {
I2C_SCL = I2C1_SCL,
I2C_SDA = I2C1_SDA,
// LoRa
LORA_RESET = PA_1,
LORA_MOSI = PB_5,

32
targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_eeprom.c
View File

@ -34,13 +34,13 @@
#define XDOT_EEPROM_SIZE 0x00002000
typedef union {
uint32_t* w;
uint8_t* b;
uint32_t *w;
uint8_t *b;
} b2w;
typedef union {
uint16_t* hw;
uint8_t* b;
uint16_t *hw;
uint8_t *b;
} b2hw;
enum {
@ -49,7 +49,8 @@ enum {
word_write
};
static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data) {
static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data)
{
if (addr > XDOT_EEPROM_SIZE - 1) {
return -1;
}
@ -61,7 +62,8 @@ static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data) {
}
}
static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data) {
static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data)
{
if (addr > XDOT_EEPROM_SIZE - 2) {
return -1;
}
@ -73,7 +75,8 @@ static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data) {
}
}
static int xdot_eeprom_write_word(uint32_t addr, uint32_t data) {
static int xdot_eeprom_write_word(uint32_t addr, uint32_t data)
{
if (addr > XDOT_EEPROM_SIZE - 4) {
return -1;
}
@ -85,18 +88,20 @@ static int xdot_eeprom_write_word(uint32_t addr, uint32_t data) {
}
}
static int xdot_eeprom_read_byte(uint32_t addr, uint8_t* data) {
static int xdot_eeprom_read_byte(uint32_t addr, uint8_t *data)
{
if (addr > XDOT_EEPROM_SIZE - 1) {
return -1;
}
*data = (*((uint8_t*)(XDOT_EEPROM_START + addr)));
*data = (*((uint8_t *)(XDOT_EEPROM_START + addr)));
return 0;
}
int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) {
int xdot_eeprom_write_buf(uint32_t addr, uint8_t *buf, uint32_t size)
{
uint32_t bytes_written = 0;
if (addr + size > XDOT_EEPROM_SIZE) {
@ -133,7 +138,7 @@ int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) {
}
//printf("%smatch\r\n", mismatch[i] ? "mis" : "");
}
if (! (mismatch[0] || mismatch[1] || mismatch[2] || mismatch[3])) {
if (!(mismatch[0] || mismatch[1] || mismatch[2] || mismatch[3])) {
//printf("all match - no write necessary\r\n");
bytes_written += 4;
continue;
@ -180,7 +185,7 @@ int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) {
}
//printf("%smatch\r\n", mismatch[i] ? "mis" : "");
}
if (! (mismatch[0] || mismatch[1])) {
if (!(mismatch[0] || mismatch[1])) {
//printf("all match - no write necessary\r\n");
bytes_written += 2;
continue;
@ -261,7 +266,8 @@ int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) {
return 0;
}
int xdot_eeprom_read_buf(uint32_t addr, uint8_t* buf, uint32_t size) {
int xdot_eeprom_read_buf(uint32_t addr, uint8_t *buf, uint32_t size)
{
if (addr + size > XDOT_EEPROM_SIZE) {
return -1;
}

4
targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_eeprom.h
View File

@ -46,7 +46,7 @@ extern "C" {
* valid addresses are 0x0000 - 0x1FFF
* returns 0 if all data was successfully written otherwise -1
*/
int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size);
int xdot_eeprom_write_buf(uint32_t addr, uint8_t *buf, uint32_t size);
/* xdot_eeprom_read_buf
* attempts to read size bytes into buf starting at addr
@ -54,7 +54,7 @@ int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size);
* valid addresses are 0x0000 - 0x1FFF
* returns 0 if all data was successfully read otherwise -1
*/
int xdot_eeprom_read_buf(uint32_t addr, uint8_t* buf, uint32_t size);
int xdot_eeprom_read_buf(uint32_t addr, uint8_t *buf, uint32_t size);
#ifdef __cplusplus
}

41
targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_low_power.c
View File

@ -37,15 +37,18 @@ static uint32_t portB[6];
static uint32_t portC[6];
static uint32_t portH[6];
void xdot_disable_systick_int() {
void xdot_disable_systick_int()
{
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
void xdot_enable_systick_int() {
void xdot_enable_systick_int()
{
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
}
void xdot_save_gpio_state() {
void xdot_save_gpio_state()
{
portA[0] = GPIOA->MODER;
portA[1] = GPIOA->OTYPER;
portA[2] = GPIOA->OSPEEDR;
@ -75,7 +78,8 @@ void xdot_save_gpio_state() {
portH[5] = GPIOH->AFR[1];
}
void xdot_restore_gpio_state() {
void xdot_restore_gpio_state()
{
GPIOA->MODER = portA[0];
GPIOA->OTYPER = portA[1];
GPIOA->OSPEEDR = portA[2];
@ -105,7 +109,8 @@ void xdot_restore_gpio_state() {
GPIOH->AFR[1] = portH[5];
}
void xdot_enter_stop_mode() {
void xdot_enter_stop_mode()
{
GPIO_InitTypeDef GPIO_InitStruct;
// disable ADC and DAC - they can consume power in stop mode
@ -224,8 +229,8 @@ void xdot_enter_stop_mode() {
HSERCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
HSERCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 24 MHz xtal on OSC_IN/OSC_OUT */
HSERCC_OscInitStruct.HSIState = RCC_HSI_OFF;
// SYSCLK = 32 MHz ((24 MHz * 4) / 3)
// USBCLK = 48 MHz ((24 MHz * 4) / 2) --> USB OK
// SYSCLK = 32 MHz ((24 MHz * 4) / 3)
// USBCLK = 48 MHz ((24 MHz * 4) / 2) --> USB OK
HSERCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
HSERCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
HSERCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
@ -249,12 +254,12 @@ void xdot_enter_stop_mode() {
/* Enable the HSI for ADC peripherals */
RCC_OscInitTypeDef HSIRCC_OscInitStruct;
HAL_RCC_GetOscConfig(&HSIRCC_OscInitStruct);
if ( HSIRCC_OscInitStruct.HSIState != RCC_HSI_ON ) {
if (HSIRCC_OscInitStruct.HSIState != RCC_HSI_ON) {
HSIRCC_OscInitStruct.HSIState = RCC_HSI_ON;
HSIRCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
HSIRCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
HAL_StatusTypeDef ret = HAL_RCC_OscConfig(&HSIRCC_OscInitStruct);
if ( ret != HAL_OK ) {
if (ret != HAL_OK) {
debug("HSI initialization failed - ADC will not function properly\r\n");
}
}
@ -271,18 +276,22 @@ void xdot_enter_stop_mode() {
DAC->CR |= DAC_CR_EN2;
}
void xdot_enter_standby_mode() {
void xdot_enter_standby_mode()
{
// enable ULP and enable fast wakeup
HAL_PWREx_EnableUltraLowPower();
HAL_PWREx_EnableFastWakeUp();
// disable HSI, MSI, and LSI if they are running
if (RCC->CR & RCC_CR_HSION)
if (RCC->CR & RCC_CR_HSION) {
RCC->CR &= ~RCC_CR_HSION;
if (RCC->CR & RCC_CR_MSION)
}
if (RCC->CR & RCC_CR_MSION) {
RCC->CR &= ~RCC_CR_MSION;
if (RCC->CSR & RCC_CSR_LSION)
}
if (RCC->CSR & RCC_CSR_LSION) {
RCC->CSR &= ~RCC_CSR_LSION;
}
// make sure wakeup and standby flags are cleared
@ -293,11 +302,13 @@ void xdot_enter_standby_mode() {
HAL_PWR_EnterSTANDBYMode();
}
void xdot_enable_standby_wake_pin() {
void xdot_enable_standby_wake_pin()
{
HAL_PWR_EnableWakeUpPin(PWR_WAKEUP_PIN1);
}
void xdot_disable_standby_wake_pin() {
void xdot_disable_standby_wake_pin()
{
HAL_PWR_DisableWakeUpPin(PWR_WAKEUP_PIN1);
}

16
targets/TARGET_STM/TARGET_STM32L1/analogout_device.c
View File

@ -39,7 +39,8 @@
static int pa4_used = 0;
static int pa5_used = 0;
void analogout_init(dac_t *obj, PinName pin) {
void analogout_init(dac_t *obj, PinName pin)
{
DAC_ChannelConfTypeDef sConfig = {0};
// Get the peripheral name (DAC_1, ...) from the pin and assign it to the object
@ -70,7 +71,7 @@ void analogout_init(dac_t *obj, PinName pin) {
obj->handle.Instance = DAC;
obj->handle.State = HAL_DAC_STATE_RESET;
if (HAL_DAC_Init(&obj->handle) != HAL_OK ) {
if (HAL_DAC_Init(&obj->handle) != HAL_OK) {
error("HAL_DAC_Init failed");
}
@ -94,10 +95,15 @@ void analogout_init(dac_t *obj, PinName pin) {
analogout_write_u16(obj, 0);
}
void analogout_free(dac_t *obj) {
void analogout_free(dac_t *obj)
{
// Reset DAC and disable clock
if (obj->pin == PA_4) pa4_used = 0;
if (obj->pin == PA_5) pa5_used = 0;
if (obj->pin == PA_4) {
pa4_used = 0;
}
if (obj->pin == PA_5) {
pa5_used = 0;
}
if ((pa4_used == 0) && (pa5_used == 0)) {
__DAC_FORCE_RESET();
__DAC_RELEASE_RESET();

12
targets/TARGET_STM/TARGET_STM32L1/flash_api.c
View File

@ -93,7 +93,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
}
int32_t flash_program_page(flash_t *obj, uint32_t address,
const uint8_t *data, uint32_t size)
const uint8_t *data, uint32_t size)
{
uint32_t StartAddress = 0;
int32_t status = 0;
@ -119,7 +119,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address,
if ((uint32_t) data % 4 != 0) {
volatile uint32_t data32;
while (address < (StartAddress + size) && (status == 0)) {
for (uint8_t i =0; i < 4; i++) {
for (uint8_t i = 0; i < 4; i++) {
*(((uint8_t *) &data32) + i) = *(data + i);
}
@ -132,7 +132,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address,
}
} else { /* case where data is aligned, so let's avoid any copy */
while ((address < (StartAddress + size)) && (status == 0)) {
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) {
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t *) data)) == HAL_OK) {
address = address + 4;
data = data + 4;
} else {
@ -146,7 +146,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address,
return status;
}
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
{
if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
return MBED_FLASH_INVALID_SIZE;
@ -161,12 +161,12 @@ uint32_t flash_get_page_size(const flash_t *obj)
return 4;
}
uint32_t flash_get_start_address(const flash_t *obj)
uint32_t flash_get_start_address(const flash_t *obj)
{
return FLASH_BASE;
}
uint32_t flash_get_size(const flash_t *obj)
uint32_t flash_get_size(const flash_t *obj)
{
return FLASH_SIZE;
}

7
targets/TARGET_STM/TARGET_STM32L1/pin_device.h
View File

@ -56,14 +56,15 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3
}
}
static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
{
uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
if (STM_PIN(pin) > 7)
if (STM_PIN(pin) > 7) {
LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
else
} else {
LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
}
}
#endif

3
targets/TARGET_STM/TARGET_STM32L1/pwmout_device.c
View File

@ -33,8 +33,7 @@
#ifdef DEVICE_PWMOUT
const pwm_apb_map_t pwm_apb_map_table[] =
{
const pwm_apb_map_t pwm_apb_map_table[] = {
#if defined(TIM2_BASE)
{PWM_2, PWMOUT_ON_APB1},
#endif

120
targets/TARGET_STM/TARGET_STM32L1/serial_device.c
View File

@ -51,7 +51,7 @@ static void uart_irq(UARTName uart_name)
int8_t id = get_uart_index(uart_name);
if (id >= 0) {
UART_HandleTypeDef * huart = &uart_handlers[id];
UART_HandleTypeDef *huart = &uart_handlers[id];
if (serial_irq_ids[id] != 0) {
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET) {
@ -111,7 +111,7 @@ static void uart5_irq(void)
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
struct serial_s *obj_s = SERIAL_S(obj);
irq_handler = handler;
serial_irq_ids[obj_s->index] = id;
}
@ -240,7 +240,7 @@ void serial_break_set(serial_t *obj)
* LOCAL HELPER FUNCTIONS
******************************************************************************/
/**
/**
* Configure the TX buffer for an asynchronous write serial transaction
*
* @param obj The serial object.
@ -260,7 +260,7 @@ static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t
obj->tx_buff.length = tx_length;
obj->tx_buff.pos = 0;
}
/**
* Configure the RX buffer for an asynchronous write serial transaction
*
@ -282,7 +282,7 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t
obj->rx_buff.pos = 0;
}
/**
/**
* Configure events
*
* @param obj The serial object
@ -290,9 +290,9 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t
* @param enable Set to non-zero to enable events, or zero to disable them
*/
static void serial_enable_event(serial_t *obj, int event, uint8_t enable)
{
{
struct serial_s *obj_s = SERIAL_S(obj);
// Shouldn't have to enable interrupt here, just need to keep track of the requested events.
if (enable) {
obj_s->events |= event;
@ -349,7 +349,7 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name)
* MBED API FUNCTIONS
******************************************************************************/
/**
/**
* Begin asynchronous TX transfer. The used buffer is specified in the serial
* object, tx_buff
*
@ -363,28 +363,28 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name)
* @return Returns number of data transfered, or 0 otherwise
*/
int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
{
{
// TODO: DMA usage is currently ignored
(void) hint;
// Check buffer is ok
MBED_ASSERT(tx != (void*)0);
MBED_ASSERT(tx != (void *)0);
MBED_ASSERT(tx_width == 8); // support only 8b width
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef * huart = &uart_handlers[obj_s->index];
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
if (tx_length == 0) {
return 0;
}
// Set up buffer
serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width);
// Set up events
serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events
serial_enable_event(obj, event, 1); // Set only the wanted events
// Enable interrupt
IRQn_Type irq_n = serial_get_irq_n(obj_s->uart);
NVIC_ClearPendingIRQ(irq_n);
@ -394,14 +394,14 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
NVIC_EnableIRQ(irq_n);
// the following function will enable UART_IT_TXE and error interrupts
if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) {
if (HAL_UART_Transmit_IT(huart, (uint8_t *)tx, tx_length) != HAL_OK) {
return 0;
}
return tx_length;
}
/**
/**
* Begin asynchronous RX transfer (enable interrupt for data collecting)
* The used buffer is specified in the serial object, rx_buff
*
@ -422,18 +422,18 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
/* Sanity check arguments */
MBED_ASSERT(obj);
MBED_ASSERT(rx != (void*)0);
MBED_ASSERT(rx != (void *)0);
MBED_ASSERT(rx_width == 8); // support only 8b width
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0);
serial_enable_event(obj, event, 1);
// set CharMatch
obj->char_match = char_match;
serial_rx_buffer_set(obj, rx, rx_length, rx_width);
IRQn_Type irq_n = serial_get_irq_n(obj_s->uart);
@ -443,8 +443,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
NVIC_SetVector(irq_n, (uint32_t)handler);
NVIC_EnableIRQ(irq_n);
// following HAL function will enable the RXNE interrupt + error interrupts
HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length);
// following HAL function will enable the RXNE interrupt + error interrupts
HAL_UART_Receive_IT(huart, (uint8_t *)rx, rx_length);
}
/**
@ -456,10 +456,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
uint8_t serial_tx_active(serial_t *obj)
{
MBED_ASSERT(obj);
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0);
}
@ -472,20 +472,22 @@ uint8_t serial_tx_active(serial_t *obj)
uint8_t serial_rx_active(serial_t *obj)
{
MBED_ASSERT(obj);
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
}
}
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag
} else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
@ -507,49 +509,49 @@ int serial_irq_handler_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
volatile int return_event = 0;
uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer);
uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer);
uint8_t i = 0;
// TX PART:
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
// Return event SERIAL_EVENT_TX_COMPLETE if requested
if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) {
if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE) != 0) {
return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events);
}
}
}
// Handle error events
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events);
}
}
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events);
}
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events);
}
}
HAL_UART_IRQHandler(huart);
// Abort if an error occurs
if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) ||
(return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
(return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
(return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
(return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
return return_event;
}
//RX PART
if (huart->RxXferSize != 0) {
obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount;
@ -557,7 +559,7 @@ int serial_irq_handler_asynch(serial_t *obj)
if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) {
return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events);
}
// Check if char_match is present
if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) {
if (buf != NULL) {
@ -570,12 +572,12 @@ int serial_irq_handler_asynch(serial_t *obj)
}
}
}
}
return return_event;
}
return return_event;
}
/**
/**
* Abort the ongoing TX transaction. It disables the enabled interupt for TX and
* flush TX hardware buffer if TX FIFO is used
*
@ -585,17 +587,17 @@ void serial_tx_abort_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
// clear flags
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
// reset states
huart->TxXferCount = 0;
// update handle state
if(huart->State == HAL_UART_STATE_BUSY_TX_RX) {
if (huart->State == HAL_UART_STATE_BUSY_TX_RX) {
huart->State = HAL_UART_STATE_BUSY_RX;
} else {
huart->State = HAL_UART_STATE_READY;
@ -612,20 +614,20 @@ void serial_rx_abort_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
// disable interrupts
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
// clear flags
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear errors flag
// reset states
huart->RxXferCount = 0;
// update handle state
if(huart->State == HAL_UART_STATE_BUSY_TX_RX) {
if (huart->State == HAL_UART_STATE_BUSY_TX_RX) {
huart->State = HAL_UART_STATE_BUSY_TX;
} else {
huart->State = HAL_UART_STATE_READY;
@ -655,9 +657,9 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
MBED_ASSERT(obj_s->uart != (UARTName)NC);
if(type == FlowControlNone) {
if (type == FlowControlNone) {
// Disable hardware flow control
obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
}
if (type == FlowControlRTS) {
// Enable RTS
@ -687,7 +689,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
// Enable the pin for RTS function
pinmap_pinout(rxflow, PinMap_UART_RTS);
}
init_uart(obj);
}

29
targets/TARGET_STM/TARGET_STM32L1/spi_api.c
View File

@ -39,34 +39,35 @@
#if DEVICE_SPI_ASYNCH
#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
#else
#define SPI_S(obj) (( struct spi_s *)(obj))
#define SPI_S(obj) (( struct spi_s *)(obj))
#endif
/*
* Only the frequency is managed in the family specific part
* the rest of SPI management is common to all STM32 families
*/
int spi_get_clock_freq(spi_t *obj) {
int spi_get_clock_freq(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
int spi_hz = 0;
int spi_hz = 0;
/* Get source clock depending on SPI instance */
/* Get source clock depending on SPI instance */
switch ((int)spiobj->spi) {
case SPI_1:
/* SPI_1. Source CLK is PCKL2 */
spi_hz = HAL_RCC_GetPCLK2Freq();
break;
case SPI_2:
/* SPI_1. Source CLK is PCKL2 */
spi_hz = HAL_RCC_GetPCLK2Freq();
break;
case SPI_2:
#ifdef SPI_3
case SPI_3:
#endif
/* SPI_2, SPI_3. Source CLK is PCKL1 */
spi_hz = HAL_RCC_GetPCLK1Freq();
break;
default:
error("CLK: SPI instance not set");
/* SPI_2, SPI_3. Source CLK is PCKL1 */
spi_hz = HAL_RCC_GetPCLK1Freq();
break;
default:
error("CLK: SPI instance not set");
break;
}
return spi_hz;