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Merge pull request #1058 from neilt6/patch-1 

NUCLEO-F411RE USB clock frequency fix
pull/1066/head
Martin Kojtal 2015-04-23 08:21:49 +01:00
parent b73059c798 f522ea7967
commit ecaaa712eb
1 changed files with 21 additions and 21 deletions
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42
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.c
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@ -27,15 +27,15 @@
* | 2- PLL_HSE_XTAL | * | 2- PLL_HSE_XTAL |
* | (external 8 MHz xtal) | * | (external 8 MHz xtal) |
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* SYSCLK(MHz) | 100 | 100 * SYSCLK(MHz) | 96 | 96
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* AHBCLK (MHz) | 100 | 100 * AHBCLK (MHz) | 96 | 96
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* APB1CLK (MHz) | 50 | 50 * APB1CLK (MHz) | 48 | 48
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* APB2CLK (MHz) | 100 | 100 * APB2CLK (MHz) | 96 | 96
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* USB capable (48 MHz precise clock) | NO | NO * USB capable (48 MHz precise clock) | YES | YES
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
****************************************************************************** ******************************************************************************
* @attention * @attention
@ -611,11 +611,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
//RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
//RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384)
RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4) RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200) RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4)
RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{ {
return 0; // FAIL return 0; // FAIL
@ -623,10 +623,10 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
{ {
return 0; // FAIL return 0; // FAIL
@ -665,11 +665,11 @@ uint8_t SetSysClock_PLL_HSI(void)
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
//RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
//RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384)
RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200) RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4)
RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{ {
return 0; // FAIL return 0; // FAIL
@ -677,10 +677,10 @@ uint8_t SetSysClock_PLL_HSI(void)
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
{ {
return 0; // FAIL return 0; // FAIL