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Merge remote-tracking branch 'upstream/master'

pull/185/head
tkuyucu 2014-02-19 12:45:10 +01:00
parent befaefcdb8 00078565b9
commit ec220d9996
25 changed files with 798 additions and 195 deletions
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4
README.md
View File

@ -42,6 +42,10 @@ Freescale:
* [KL46Z](https://mbed.org/platforms/FRDM-KL46Z/) (Cortex-M0+)
STMicroelectronics:
* [Nucleo-F103RB](https://mbed.org/platforms/ST-Nucleo-F103RB/) (Cortex-M3)
* [Nucleo-L152RE](https://mbed.org/platforms/ST-Nucleo-L152RE/) (Cortex-M3)
* [Nucleo-F030R8](https://mbed.org/platforms/ST-Nucleo-F030R8/) (Cortex-M0)
* [Nucleo-F401RE](https://mbed.org/platforms/ST-Nucleo-F401RE/) (Cortex-M4)
* STM32F407 (Cortex-M4)
Supported Toolchains and IDEs

9
libraries/USBDevice/USBDevice/USBDevice.cpp
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@ -703,12 +703,15 @@ bool USBDevice::configured(void)
return (device.state == CONFIGURED);
}
void USBDevice::connect(void)
void USBDevice::connect(bool blocking)
{
/* Connect device */
USBHAL::connect();
/* Block if not configured */
while (!configured());
if (blocking) {
/* Block if not configured */
while (!configured());
}
}
void USBDevice::disconnect(void)

4
libraries/USBDevice/USBDevice/USBDevice.h
View File

@ -37,8 +37,10 @@ public:
/*
* Connect a device
*
* @param blocking: block if not configured
*/
void connect(void);
void connect(bool blocking = true);
/*
* Disconnect a device

5
libraries/USBDevice/USBMSD/USBMSD.cpp
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@ -103,8 +103,7 @@ bool USBMSD::USBCallback_request(void) {
}
bool USBMSD::connect() {
bool USBMSD::connect(bool blocking) {
//disk initialization
if (disk_status() & NO_INIT) {
if (disk_initialize()) {
@ -131,7 +130,7 @@ bool USBMSD::connect() {
}
//connect the device
USBDevice::connect();
USBDevice::connect(blocking);
return true;
}

3
libraries/USBDevice/USBMSD/USBMSD.h
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@ -70,9 +70,10 @@ public:
/**
* Connect the USB MSD device. Establish disk initialization before really connect the device.
*
* @param blocking if not configured
* @returns true if successful
*/
bool connect();
bool connect(bool blocking = true);
/**
* Disconnect the USB MSD device.

41
libraries/fs/sd/SDFileSystem.cpp
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@ -120,8 +120,12 @@
#define SD_DBG 0
SDFileSystem::SDFileSystem(PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name) :
FATFileSystem(name), _spi(mosi, miso, sclk), _cs(cs) {
FATFileSystem(name), _spi(mosi, miso, sclk), _cs(cs), _is_initialized(0) {
_cs = 1;
// Set default to 100kHz for initialisation and 1MHz for data transfer
_init_sck = 100000;
_transfer_sck = 1000000;
}
#define R1_IDLE_STATE (1 << 0)
@ -143,8 +147,8 @@ SDFileSystem::SDFileSystem(PinName mosi, PinName miso, PinName sclk, PinName cs,
#define SDCARD_V2HC 3
int SDFileSystem::initialise_card() {
// Set to 100kHz for initialisation, and clock card with cs = 1
_spi.frequency(100000);
// Set to SCK for initialisation, and clock card with cs = 1
_spi.frequency(_init_sck);
_cs = 1;
for (int i = 0; i < 16; i++) {
_spi.write(0xFF);
@ -200,8 +204,12 @@ int SDFileSystem::initialise_card_v2() {
}
int SDFileSystem::disk_initialize() {
int i = initialise_card();
debug_if(SD_DBG, "init card = %d\n", i);
_is_initialized = initialise_card();
if (_is_initialized == 0) {
debug("Fail to initialize card\n");
return 1;
}
debug_if(SD_DBG, "init card = %d\n", _is_initialized);
_sectors = _sd_sectors();
// Set block length to 512 (CMD16)
@ -209,12 +217,17 @@ int SDFileSystem::disk_initialize() {
debug("Set 512-byte block timed out\n");
return 1;
}
_spi.frequency(1000000); // Set to 1MHz for data transfer
// Set SCK for data transfer
_spi.frequency(_transfer_sck);
return 0;
}
int SDFileSystem::disk_write(const uint8_t *buffer, uint64_t block_number) {
if (!_is_initialized) {
return -1;
}
// set write address for single block (CMD24)
if (_cmd(24, block_number * cdv) != 0) {
return 1;
@ -226,6 +239,10 @@ int SDFileSystem::disk_write(const uint8_t *buffer, uint64_t block_number) {
}
int SDFileSystem::disk_read(uint8_t *buffer, uint64_t block_number) {
if (!_is_initialized) {
return -1;
}
// set read address for single block (CMD17)
if (_cmd(17, block_number * cdv) != 0) {
return 1;
@ -236,7 +253,15 @@ int SDFileSystem::disk_read(uint8_t *buffer, uint64_t block_number) {
return 0;
}
int SDFileSystem::disk_status() { return 0; }
int SDFileSystem::disk_status() {
// FATFileSystem::disk_status() returns 0 when initialized
if (_is_initialized) {
return 0;
} else {
return 1;
}
}
int SDFileSystem::disk_sync() { return 0; }
uint64_t SDFileSystem::disk_sectors() { return _sectors; }

9
libraries/fs/sd/SDFileSystem.h
View File

@ -73,10 +73,17 @@ protected:
int _write(const uint8_t *buffer, uint32_t length);
uint64_t _sd_sectors();
uint64_t _sectors;
void set_init_sck(uint32_t sck) { _init_sck = sck; }
// Note: The highest SPI clock rate is 20 MHz for MMC and 25 MHz for SD
void set_transfer_sck(uint32_t sck) { _transfer_sck = sck; }
uint32_t _init_sck;
uint32_t _transfer_sck;
SPI _spi;
DigitalOut _cs;
int cdv;
int _is_initialized;
};
#endif

12
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/MKL05Z4.sct Normal file
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@ -0,0 +1,12 @@
LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
ER_IROM1 0x00000000 0x8000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
; 0x1000 - 0xC0 = 0xF40
RW_IRAM1 0x1FFFFCC0 0xF40 {
.ANY (+RW +ZI)
}
}

348
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/startup_MKL05Z4.s Normal file
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@ -0,0 +1,348 @@
;/*****************************************************************************
; * @file: startup_MKL25Z4.s
; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
; * MKL05Z4
; * @version: 1.1
; * @date: 2012-6-21
; *
; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
;*
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; *****************************************************************************/
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
EXPORT __initial_sp
Stack_Mem SPACE Stack_Size
__initial_sp EQU 0x20000C00 ; Top of RAM
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
EXPORT __heap_base
EXPORT __heap_limit
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt
DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt
DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt
DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt
DCD Reserved20_IRQHandler ; Reserved interrupt 20
DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
DCD LLW_IRQHandler ; Low Leakage Wakeup
DCD I2C0_IRQHandler ; I2C0 interrupt
DCD Reserved_25_IRQHandler ; Reserved interrupt 25
DCD SPI0_IRQHandler ; SPI0 interrupt
DCD Reserved_27_IRQHandler ; Reserved interrupt 27
DCD UART0_IRQHandler ; UART0 status and error interrupt
DCD Reserved_29_IRQHandler ; Reserved interrupt 29
DCD Reserved_30_IRQHandler ; Reserved interrupt 30
DCD ADC0_IRQHandler ; ADC0 interrupt
DCD CMP0_IRQHandler ; CMP0 interrupt
DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
DCD Reserved_35_IRQHandler ; Reserved interrupt 35
DCD RTC_IRQHandler ; RTC interrupt
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
DCD PIT_IRQHandler ; PIT timer channel 0 interrupt
DCD Reserved_39_IRQHandler ; Reserved interrupt 39
DCD Reserved_40_IRQHandler ; Reserved interrupt 40
DCD DAC0_IRQHandler ; DAC0 interrupt
DCD TSI0_IRQHandler ; TSI0 interrupt
DCD MCG_IRQHandler ; MCG interrupt
DCD LPTimer_IRQHandler ; LPTimer interrupt
DCD Reserved_45_IRQHandler ; Reserved interrupt 45
DCD PORTA_IRQHandler ; Port A interrupt
DCD PORTB_IRQHandler ; Port B interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
; <h> Flash Configuration
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
; <i> and security information that allows the MCU to restrict acces to the FTFL module.
; <h> Backdoor Comparison Key
; <o0> Backdoor Key 0 <0x0-0xFF:2>
; <o1> Backdoor Key 1 <0x0-0xFF:2>
; <o2> Backdoor Key 2 <0x0-0xFF:2>
; <o3> Backdoor Key 3 <0x0-0xFF:2>
; <o4> Backdoor Key 4 <0x0-0xFF:2>
; <o5> Backdoor Key 5 <0x0-0xFF:2>
; <o6> Backdoor Key 6 <0x0-0xFF:2>
; <o7> Backdoor Key 7 <0x0-0xFF:2>
BackDoorK0 EQU 0xFF
BackDoorK1 EQU 0xFF
BackDoorK2 EQU 0xFF
BackDoorK3 EQU 0xFF
BackDoorK4 EQU 0xFF
BackDoorK5 EQU 0xFF
BackDoorK6 EQU 0xFF
BackDoorK7 EQU 0xFF
; </h>
; <h> Program flash protection bytes (FPROT)
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
; <i> Each bit protects a 1/32 region of the program flash memory.
; <h> FPROT0
; <i> Program flash protection bytes
; <i> 1/32 - 8/32 region
; <o.0> FPROT0.0
; <o.1> FPROT0.1
; <o.2> FPROT0.2
; <o.3> FPROT0.3
; <o.4> FPROT0.4
; <o.5> FPROT0.5
; <o.6> FPROT0.6
; <o.7> FPROT0.7
nFPROT0 EQU 0x00
FPROT0 EQU nFPROT0:EOR:0xFF
; </h>
; <h> FPROT1
; <i> Program Flash Region Protect Register 1
; <i> 9/32 - 16/32 region
; <o.0> FPROT1.0
; <o.1> FPROT1.1
; <o.2> FPROT1.2
; <o.3> FPROT1.3
; <o.4> FPROT1.4
; <o.5> FPROT1.5
; <o.6> FPROT1.6
; <o.7> FPROT1.7
nFPROT1 EQU 0x00
FPROT1 EQU nFPROT1:EOR:0xFF
; </h>
; <h> FPROT2
; <i> Program Flash Region Protect Register 2
; <i> 17/32 - 24/32 region
; <o.0> FPROT2.0
; <o.1> FPROT2.1
; <o.2> FPROT2.2
; <o.3> FPROT2.3
; <o.4> FPROT2.4
; <o.5> FPROT2.5
; <o.6> FPROT2.6
; <o.7> FPROT2.7
nFPROT2 EQU 0x00
FPROT2 EQU nFPROT2:EOR:0xFF
; </h>
; <h> FPROT3
; <i> Program Flash Region Protect Register 3
; <i> 25/32 - 32/32 region
; <o.0> FPROT3.0
; <o.1> FPROT3.1
; <o.2> FPROT3.2
; <o.3> FPROT3.3
; <o.4> FPROT3.4
; <o.5> FPROT3.5
; <o.6> FPROT3.6
; <o.7> FPROT3.7
nFPROT3 EQU 0x00
FPROT3 EQU nFPROT3:EOR:0xFF
; </h>
; </h>
; </h>
; <h> Flash nonvolatile option byte (FOPT)
; <i> Allows the user to customize the operation of the MCU at boot time.
; <o.0> LPBOOT0
; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
; <o.4> LPBOOT1
; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
; <o.2> NMI_DIS
; <0=> NMI interrupts are always blocked
; <1=> NMI pin/interrupts reset default to enabled
; <o.3> RESET_PIN_CFG
; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
; <1=> RESET pin is dedicated
; <o.3> FAST_INIT
; <0=> Slower initialization
; <1=> Fast Initialization
FOPT EQU 0xFF
; </h>
; <h> Flash security byte (FSEC)
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
; <o.0..1> SEC
; <2=> MCU security status is unsecure
; <3=> MCU security status is secure
; <i> Flash Security
; <i> This bits define the security state of the MCU.
; <o.2..3> FSLACC
; <2=> Freescale factory access denied
; <3=> Freescale factory access granted
; <i> Freescale Failure Analysis Access Code
; <i> This bits define the security state of the MCU.
; <o.4..5> MEEN
; <2=> Mass erase is disabled
; <3=> Mass erase is enabled
; <i> Mass Erase Enable Bits
; <i> Enables and disables mass erase capability of the FTFL module
; <o.6..7> KEYEN
; <2=> Backdoor key access enabled
; <3=> Backdoor key access disabled
; <i> Backdoor key Security Enable
; <i> These bits enable and disable backdoor key access to the FTFL module.
FSEC EQU 0xFE
; </h>
IF :LNOT::DEF:RAM_TARGET
AREA |.ARM.__at_0x400|, CODE, READONLY
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
DCB FPROT0, FPROT1, FPROT2, FPROT3
DCB FSEC, FOPT, 0xFF, 0xFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DMA0_IRQHandler [WEAK]
EXPORT DMA1_IRQHandler [WEAK]
EXPORT DMA2_IRQHandler [WEAK]
EXPORT DMA3_IRQHandler [WEAK]
EXPORT Reserved20_IRQHandler [WEAK]
EXPORT FTFA_IRQHandler [WEAK]
EXPORT LVD_LVW_IRQHandler [WEAK]
EXPORT LLW_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT Reserved_25_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT Reserved_27_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT Reserved_29_IRQHandler [WEAK]
EXPORT Reserved_30_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT TPM0_IRQHandler [WEAK]
EXPORT TPM1_IRQHandler [WEAK]
EXPORT Reserved_35_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTC_Seconds_IRQHandler [WEAK]
EXPORT PIT_IRQHandler [WEAK]
EXPORT Reserved_39_IRQHandler [WEAK]
EXPORT Reserved_40_IRQHandler [WEAK]
EXPORT DAC0_IRQHandler [WEAK]
EXPORT TSI0_IRQHandler [WEAK]
EXPORT MCG_IRQHandler [WEAK]
EXPORT LPTimer_IRQHandler [WEAK]
EXPORT Reserved_45_IRQHandler [WEAK]
EXPORT PORTA_IRQHandler [WEAK]
EXPORT PORTB_IRQHandler [WEAK]
EXPORT DefaultISR [WEAK]
DMA0_IRQHandler
DMA1_IRQHandler
DMA2_IRQHandler
DMA3_IRQHandler
Reserved20_IRQHandler
FTFA_IRQHandler
LVD_LVW_IRQHandler
LLW_IRQHandler
I2C0_IRQHandler
Reserved_25_IRQHandler
SPI0_IRQHandler
Reserved_27_IRQHandler
UART0_IRQHandler
Reserved_29_IRQHandler
Reserved_30_IRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
TPM0_IRQHandler
TPM1_IRQHandler
Reserved_35_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT_IRQHandler
Reserved_39_IRQHandler
Reserved_40_IRQHandler
DAC0_IRQHandler
TSI0_IRQHandler
MCG_IRQHandler
LPTimer_IRQHandler
Reserved_45_IRQHandler
PORTA_IRQHandler
PORTB_IRQHandler
DefaultISR
B .
ENDP
ALIGN
END

31
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/sys.cpp Normal file
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@ -0,0 +1,31 @@
/* mbed Microcontroller Library - stackheap
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* Setup a fixed single stack/heap memory model,
* between the top of the RW/ZI region and the stackpointer
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$RW_IRAM1$$ZI$$Limit[];
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

340
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.c
View File

@ -1,122 +1,256 @@
/*
** ###################################################################
** Processors: MKL05Z32FK4
** MKL05Z32LC4
** MKL05Z32VLF4
**
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: KL05P48M48SF1RM, Rev.3, Sep 2012
** Version: rev. 1.6, 2013-04-11
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2013 Freescale, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2012-06-08)
** Initial version.
** - rev. 1.1 (2012-06-21)
** Update according to reference manual rev. 1.
** - rev. 1.2 (2012-08-01)
** Device type UARTLP changed to UART0.
** Missing PORTB_IRQn interrupt number definition added.
** - rev. 1.3 (2012-10-04)
** Update according to reference manual rev. 3.
** - rev. 1.4 (2012-11-22)
** MCG module - bit LOLS in MCG_S register renamed to LOLS0.
** NV registers - bit EZPORT_DIS in NV_FOPT register removed.
** - rev. 1.5 (2013-04-05)
** Changed start of doxygen comment.
** - rev. 1.6 (2013-04-11)
** SystemInit methods updated with predefined initialization sequence.
**
** ###################################################################
*/
/*!
* @file MKL05Z4
* @version 1.6
* @date 2013-04-11
* @brief Device specific configuration file for MKL05Z4 (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "MKL05Z4.h"
#define DISABLE_WDOG 1
#define DISABLE_WDOG 1
#define CLOCK_SETUP 1
/* Predefined clock setups
Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Reference clock source for MCG module is the slow internal clock source 32.768kHz
Core clock = 47.97MHz, BusClock = 23.48MHz
Core clock = 41.94MHz, BusClock = 20.97MHz
1 ... Multipurpose Clock Generator (MCG) in FLL Engaged External (FEE) mode
Reference clock source for MCG module is an external crystal 32.768kHz
Core clock = 47.97MHz, BusClock = 23.98MHz
2 ... Multipurpose Clock Generator (MCG) in FLL Bypassed Low Power Internal (BLPI) mode
Core clock/Bus clock derived directly from an fast internal 4MHz clock with no multiplication
Core clock = 4MHz, BusClock = 4MHz
*/
#define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */
/*----------------------------------------------------------------------------
Define clock source values
*----------------------------------------------------------------------------*/
#if (CLOCK_SETUP == 0)
#define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
#elif (CLOCK_SETUP == 1)
#define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */
#elif (CLOCK_SETUP == 2)
#define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
#endif /* (CLOCK_SETUP == 2) */
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
void SystemInit(void) {
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit (void) {
#if (DISABLE_WDOG)
/* Disable the WDOG module */
/* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
SIM->COPC = (uint32_t)0x00u;
/* Disable the WDOG module */
/* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
SIM->COPC = (uint32_t)0x00u;
#endif /* (DISABLE_WDOG) */
SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTA_MASK); /* Enable clock gate for ports to enable pin routing */
/* SIM_SCGC5: LPTMR=1 */
SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK;
/* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
/* SIM_SOPT1: OSC32KSEL=0 */
SIM->SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */
/* SIM_SOPT2: TPMSRC=2 */
SIM->SOPT2 = (uint32_t)((SIM->SOPT2 & (uint32_t)~(uint32_t)(SIM_SOPT2_TPMSRC(0x01))) |
(uint32_t)(SIM_SOPT2_TPMSRC(0x02))); /* Set the TPM clock */
/* PORTA_PCR3: ISF=0,MUX=0 */
PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* MCG_SC: FCRDIV=1 */
MCG->SC = (uint8_t)((MCG->SC & (uint8_t)~(uint8_t)(MCG_SC_FCRDIV(0x06))) |
(uint8_t)(MCG_SC_FCRDIV(0x01)));
/* Switch to FEI Mode */
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) |
MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK;
/* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=1 */
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_IRCS_MASK);
/* MCG_C4: DMX32=1,DRST_DRS=1 */
MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(MCG_C4_DRST_DRS(0x02))) |
(uint8_t)(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x01)));
/* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0->CR = OSC_CR_ERCLKEN_MASK;
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
}
#if (CLOCK_SETUP == 0)
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
/* Switch to FEI Mode */
/* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x00) |
MCG_C1_FRDIV(0x00) |
MCG_C1_IREFS_MASK |
MCG_C1_IRCLKEN_MASK;
/* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
MCG->C2 = MCG_C2_RANGE0(0x00);
/* MCG_C4: DMX32=0,DRST_DRS=1 */
MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
MCG_C4_DMX32_MASK |
MCG_C4_DRST_DRS(0x02)
)) | (uint8_t)(
MCG_C4_DRST_DRS(0x01)
));
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0->CR = OSC_CR_ERCLKEN_MASK;
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
}
#elif (CLOCK_SETUP == 1)
/* SIM->SCGC5: PORTA=1 */
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
/* PORTA->PCR[3]: ISF=0,MUX=0 */
PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* PORTA->PCR[4]: ISF=0,MUX=0 */
PORTA->PCR[4] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* Switch to FEE Mode */
/* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_EREFS0_MASK);
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0->CR = OSC_CR_ERCLKEN_MASK;
/* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
/* MCG->C4: DMX32=1,DRST_DRS=1 */
MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
MCG_C4_DRST_DRS(0x02)
)) | (uint8_t)(
MCG_C4_DMX32_MASK |
MCG_C4_DRST_DRS(0x01)
));
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
}
#elif (CLOCK_SETUP == 2)
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x00)); /* Update system prescalers */
/* MCG->SC: FCRDIV=0 */
MCG->SC &= (uint8_t)~(uint8_t)(MCG_SC_FCRDIV(0x07));
/* Switch to FBI Mode */
/* MCG->C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x01) |
MCG_C1_FRDIV(0x00) |
MCG_C1_IREFS_MASK |
MCG_C1_IRCLKEN_MASK;
/* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=1 */
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_IRCS_MASK);
/* MCG->C4: DMX32=0,DRST_DRS=0 */
MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0->CR = OSC_CR_ERCLKEN_MASK;
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
while((MCG->S & 0x0CU) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
}
/* Switch to BLPI Mode */
/* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=1,IRCS=1 */
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_LP_MASK | MCG_C2_IRCS_MASK);
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
while((MCG->S & MCG_S_IRCST_MASK) == 0x00U) { /* Check that the fast external reference clock is selected. */
}
#endif /* (CLOCK_SETUP == 2) */
}
void SystemCoreClockUpdate(void) {
uint32_t MCGOUTClock;
uint8_t Divider;
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
/* FLL is selected */
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
/* External reference clock is selected */
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
}
} else {
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
}
void SystemCoreClockUpdate (void) {
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
uint8_t Divider;
/* Select correct multiplier to calculate the MCG output clock */
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
case 0x0u:
MCGOUTClock *= 640u;
break;
case 0x20u:
MCGOUTClock *= 1280u;
break;
case 0x40u:
MCGOUTClock *= 1920u;
break;
case 0x60u:
MCGOUTClock *= 2560u;
break;
case 0x80u:
MCGOUTClock *= 732u;
break;
case 0xA0u:
MCGOUTClock *= 1464u;
break;
case 0xC0u:
MCGOUTClock *= 2197u;
break;
case 0xE0u:
MCGOUTClock *= 2929u;
break;
default:
break;
}
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
/* Internal reference clock is selected */
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
} else {
MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
}
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
/* External reference clock is selected */
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
} else {
/* Reserved value */
return;
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
/* Output of FLL is selected */
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
/* External reference clock is selected */
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
/* Select correct multiplier to calculate the MCG output clock */
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
case 0x0u:
MCGOUTClock *= 640u;
break;
case 0x20u:
MCGOUTClock *= 1280u;
break;
case 0x40u:
MCGOUTClock *= 1920u;
break;
case 0x60u:
MCGOUTClock *= 2560u;
break;
case 0x80u:
MCGOUTClock *= 732u;
break;
case 0xA0u:
MCGOUTClock *= 1464u;
break;
case 0xC0u:
MCGOUTClock *= 2197u;
break;
case 0xE0u:
MCGOUTClock *= 2929u;
break;
default:
break;
}
SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
/* Internal reference clock is selected */
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
/* External reference clock is selected */
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
/* Reserved value */
return;
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
}

31
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.h
View File

@ -1,37 +1,52 @@
/*
** ###################################################################
** Processor: MKL05Z128VLK4
** Processors: MKL05Z32FK4
** MKL05Z32LC4
** MKL05Z32VLF4
**
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: KL05RM, Rev.1, Jun 2012
** Version: rev. 1.1, 2012-06-21
** Reference manual: KL05P48M48SF1RM, Rev.3, Sep 2012
** Version: rev. 1.6, 2013-04-11
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
** Copyright: 2013 Freescale, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2012-06-13)
** - rev. 1.0 (2012-06-08)
** Initial version.
** - rev. 1.1 (2012-06-21)
** Update according to reference manual rev. 1.
** - rev. 1.2 (2012-08-01)
** Device type UARTLP changed to UART0.
** Missing PORTB_IRQn interrupt number definition added.
** - rev. 1.3 (2012-10-04)
** Update according to reference manual rev. 3.
** - rev. 1.4 (2012-11-22)
** MCG module - bit LOLS in MCG_S register renamed to LOLS0.
** NV registers - bit EZPORT_DIS in NV_FOPT register removed.
** - rev. 1.5 (2013-04-05)
** Changed start of doxygen comment.
** - rev. 1.6 (2013-04-11)
** SystemInit methods updated with predefined initialization sequence.
**
** ###################################################################
*/
/**
/*!
* @file MKL05Z4
* @version 1.1
* @date 2012-06-21
* @version 1.6
* @date 2013-04-11
* @brief Device specific configuration file for MKL05Z4 (header file)
*
* Provides a system configuration function and a global variable that contains

52
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/PeripheralPins.c
View File

@ -23,23 +23,22 @@ const PinMap PinMap_RTC[] = {
/************ADC***************/
const PinMap PinMap_ADC[] = {
/* A0-A5 pins */
{PTA0, ADC0_SE12, 0},
{PTA7, ADC0_SE7, 0},
{PTA8, ADC0_SE3, 0},
{PTA9, ADC0_SE2, 0},
{PTA12, ADC0_SE0, 0},
{PTB0, ADC0_SE6, 0},
{PTB1, ADC0_SE5, 0},
{PTB2, ADC0_SE4, 0},
{PTB5, ADC0_SE1, 0},
{PTB8, ADC0_SE11, 0},
{PTB9, ADC0_SE10, 0},
{PTB10, ADC0_SE9, 0},
{PTB11, ADC0_SE8, 0},
{PTB13, ADC0_SE13, 0},
/* Rest of pins ADC Mux */
{PTB2, ADC0_SE4, 0},
{PTB1, ADC0_SE5, 0},
{PTB5, ADC0_SE1, 0},
{PTA12, ADC0_SE0, 0},
{PTB10, ADC0_SE9, 0},
{PTB11, ADC0_SE8, 0},
{PTB7, ADC0_SE7, 0},
{PTB0, ADC0_SE6, 0},
{NC, NC, 0}
{NC, NC, 0}
};
/************DAC***************/
@ -50,44 +49,59 @@ const PinMap PinMap_DAC[] = {
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{PTA3, I2C_0, 3},
{PTA4, I2C_0, 2},
{PTB4, I2C_0, 2},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{PTA3, I2C_0, 2},
{PTA4, I2C_0, 3},
{PTB3, I2C_0, 2},
{NC , NC , 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{PTB1, UART_0, 2},
{PTB2, UART_0, 3},
{PTB3, UART_0, 3},
{NC , NC , 0}
};
const PinMap PinMap_UART_RX[] = {
{PTB1, UART_0, 3},
{PTB2, UART_0, 2},
{PTB4, UART_0, 3},
{NC , NC , 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
{PTB0, SPI_0, 3},
{NC , NC , 0}
{PTB0, SPI_0, 3},
{PTB17, SPI_0, 3},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{PTA7, SPI_0, 3},
{NC , NC , 0}
{PTA7 , SPI_0, 3},
{PTB15, SPI_0, 2},
{PTB16, SPI_0, 3},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{PTA6, SPI_0, 3},
{NC , NC , 0}
{PTA6 , SPI_0, 3},
{PTA7 , SPI_0, 2},
{PTB15, SPI_0, 3},
{PTB16, SPI_0, 2},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{PTA5, SPI_0, 3},
{NC , NC , 0}
{PTA5 , SPI_0, 3},
{PTA19, SPI_0, 3},
{NC , NC , 0}
};
/************PWM***************/

11
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/PinNames.h
View File

@ -78,10 +78,10 @@ typedef enum {
LED_BLUE = PTB10,
// mbed original LED naming
LED1 = LED_BLUE,
LED1 = LED_RED,
LED2 = LED_GREEN,
LED3 = LED_RED,
LED4 = LED_RED,
LED3 = LED_BLUE,
LED4 = LED_BLUE,
// USB Pins
USBTX = PTB1,
@ -96,7 +96,7 @@ typedef enum {
D5 = PTA12,
D6 = PTB6,
D7 = PTB7,
D8 = PTA10,
D8 = PTB10,
D9 = PTB11,
D10 = PTA5,
D11 = PTA7,
@ -111,6 +111,9 @@ typedef enum {
A3 = PTA0,
A4 = PTA9,
A5 = PTB13,
I2C_SCL = D15,
I2C_SDA = D14,
// Not connected
NC = (int)0xFFFFFFFF

3
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/PinNames.h
View File

@ -232,6 +232,9 @@ typedef enum {
A3 = PTB3,
A4 = PTC2,
A5 = PTC1,
I2C_SCL = D15,
I2C_SDA = D14,
// Not connected
NC = (int)0xFFFFFFFF

2
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/us_ticker.c
View File

@ -44,7 +44,7 @@ static void pit_init(void) {
PIT->CHANNEL[1].TCTRL |= PIT_TCTRL_TEN_MASK; // Start timer 1
// Use channel 0 as a prescaler for channel 1
PIT->CHANNEL[0].LDVAL = bus_frequency() / 1000000 - 1;
PIT->CHANNEL[0].LDVAL = (bus_frequency() + 500000) / 1000000 - 1;
PIT->CHANNEL[0].TCTRL = PIT_TCTRL_TEN_MASK; // Start timer 0, disable interrupts
}

2
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_irq_api.c
View File

@ -47,7 +47,7 @@ static inline void handle_interrupt_in(uint32_t port) {
LPC_GPIO_TypeDef *port_reg = ((LPC_GPIO_TypeDef *) (LPC_GPIO0_BASE + (port * 0x10000)));
// Get index of function table from Mask Interrupt Status register
channel = numofbits(port_reg->MIS - 1);
channel = numofbits(port_reg->MIS - 1) + (port * 12);
if (port_reg->MIS & port_reg->IBE) {
// both edge, read the level of pin

8
libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/us_ticker.c
View File

@ -36,9 +36,9 @@
#define TIM_MST_RCC RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE)
static int us_ticker_inited = 0;
static uint32_t SlaveCounter = 0;
static uint32_t oc_int_part = 0;
static uint16_t oc_rem_part = 0;
static volatile uint32_t SlaveCounter = 0;
static volatile uint32_t oc_int_part = 0;
static volatile uint16_t oc_rem_part = 0;
void set_compare(uint16_t count) {
// Set new output compare value
@ -49,9 +49,9 @@ void set_compare(uint16_t count) {
// Used to increment the slave counter
static void tim_update_irq_handler(void) {
SlaveCounter++;
if (TIM_GetITStatus(TIM_MST, TIM_IT_Update) == SET) {
TIM_ClearITPendingBit(TIM_MST, TIM_IT_Update);
SlaveCounter++;
}
}

8
libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/us_ticker.c
View File

@ -36,9 +36,9 @@
#define TIM_MST_RCC RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE)
static int us_ticker_inited = 0;
static uint32_t SlaveCounter = 0;
static uint32_t oc_int_part = 0;
static uint16_t oc_rem_part = 0;
static volatile uint32_t SlaveCounter = 0;
static volatile uint32_t oc_int_part = 0;
static volatile uint16_t oc_rem_part = 0;
void set_compare(uint16_t count) {
// Set new output compare value
@ -49,9 +49,9 @@ void set_compare(uint16_t count) {
// Used to increment the slave counter
static void tim_update_irq_handler(void) {
SlaveCounter++;
if (TIM_GetITStatus(TIM_MST, TIM_IT_Update) == SET) {
TIM_ClearITPendingBit(TIM_MST, TIM_IT_Update);
SlaveCounter++;
}
}

8
libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/us_ticker.c
View File

@ -39,9 +39,9 @@
static TIM_HandleTypeDef TimMasterHandle;
static int us_ticker_inited = 0;
static uint32_t SlaveCounter = 0;
static uint32_t oc_int_part = 0;
static uint16_t oc_rem_part = 0;
static volatile uint32_t SlaveCounter = 0;
static volatile uint32_t oc_int_part = 0;
static volatile uint16_t oc_rem_part = 0;
void set_compare(uint16_t count) {
// Set new output compare value
@ -52,10 +52,10 @@ void set_compare(uint16_t count) {
// Used to increment the slave counter
static void tim_update_irq_handler(void) {
SlaveCounter++;
if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_UPDATE) == SET) {
__HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_UPDATE);
__HAL_TIM_SetCounter(&TimMasterHandle, 0); // Reset counter !!!
SlaveCounter++;
}
}

24
libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/analogout_api.c
View File

@ -63,16 +63,17 @@ void analogout_init(dac_t *obj, PinName pin) {
// Configure and enable DAC channel
DAC_InitStructure.DAC_Trigger = DAC_Trigger_None;
DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;
DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Disable;
if (pin == PA_4) {
if (obj->channel == PA_4) {
DAC_Init(DAC_Channel_1, &DAC_InitStructure);
DAC_Cmd(DAC_Channel_1, ENABLE);
}
else { // PA_5
DAC_Init(DAC_Channel_2, &DAC_InitStructure);
DAC_Cmd(DAC_Channel_2, ENABLE);
}
//if (obj->channel == PA_5) {
// DAC_Init(DAC_Channel_2, &DAC_InitStructure);
// DAC_Cmd(DAC_Channel_2, ENABLE);
//}
analogout_write_u16(obj, 0);
}
@ -84,18 +85,19 @@ static inline void dac_write(dac_t *obj, uint16_t value) {
if (obj->channel == PA_4) {
DAC_SetChannel1Data(DAC_Align_12b_R, value);
}
else { // PA_5
DAC_SetChannel2Data(DAC_Align_12b_R, value);
}
//if (obj->channel == PA_5) {
// DAC_SetChannel2Data(DAC_Align_12b_R, value);
//}
}
static inline int dac_read(dac_t *obj) {
if (obj->channel == PA_4) {
return (int)DAC_GetDataOutputValue(DAC_Channel_1);
}
else { // PA_5
return (int)DAC_GetDataOutputValue(DAC_Channel_2);
}
//if (obj->channel == PA_5) {
// return (int)DAC_GetDataOutputValue(DAC_Channel_2);
//}
return 0;
}
void analogout_write(dac_t *obj, float value) {

29
libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/us_ticker.c
View File

@ -35,9 +35,9 @@
#define TIM_MST_RCC RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM9, ENABLE)
static int us_ticker_inited = 0;
static uint32_t SlaveCounter = 0;
static uint32_t oc_int_part = 0;
static uint16_t oc_rem_part = 0;
static volatile uint32_t SlaveCounter = 0;
static volatile uint32_t oc_int_part = 0;
static volatile uint16_t oc_rem_part = 0;
void set_compare(uint16_t count) {
// Set new output compare value
@ -58,20 +58,19 @@ static void tim_update_oc_irq_handler(void) {
// Output compare interrupt: used by interrupt system
if (TIM_GetITStatus(TIM_MST, TIM_IT_CC1) == SET) {
TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1);
}
if (oc_rem_part > 0) {
set_compare(oc_rem_part); // Finish the remaining time left
oc_rem_part = 0;
}
else {
if (oc_int_part > 0) {
set_compare(0xFFFF);
oc_rem_part = cval; // To finish the counter loop the next time
oc_int_part--;
if (oc_rem_part > 0) {
set_compare(oc_rem_part); // Finish the remaining time left
oc_rem_part = 0;
}
else {
us_ticker_irq_handler();
if (oc_int_part > 0) {
set_compare(0xFFFF);
oc_rem_part = cval; // To finish the counter loop the next time
oc_int_part--;
}
else {
us_ticker_irq_handler();
}
}
}
}

5
workspace_tools/build_release.py
View File

@ -36,8 +36,9 @@ OFFICIAL_MBED_LIBRARY_BUILD = (
('LPC1114', ('uARM',)),
('LPC11U35_401', ('ARM', 'uARM')),
('KL25Z', ('ARM', 'GCC_ARM')),
('KL46Z', ('ARM', 'GCC_ARM')),
('KL05Z', ('ARM', 'uARM', 'GCC_ARM')),
('KL25Z', ('ARM', 'GCC_ARM')),
('KL46Z', ('ARM', 'GCC_ARM')),
('NUCLEO_F103RB', ('ARM', 'uARM')),
('NUCLEO_L152RE', ('ARM', 'uARM')),

2
workspace_tools/export/uvision4.py
View File

@ -21,7 +21,7 @@ from os.path import basename
class Uvision4(Exporter):
NAME = 'uVision4'
TARGETS = ['LPC1768', 'LPC11U24', 'KL05Z', 'KL25Z', 'KL46Z', 'K20D5M', 'LPC1347', 'LPC1114', 'LPC11C24', 'LPC4088', 'LPC812', 'NUCLEO_F103RB', 'NUCLEO_L152RE', 'NUCLEO_F030R8', 'NUCLEO_F401RE', 'C027']
TARGETS = ['LPC1768', 'LPC11U24', 'KL05Z', 'KL25Z', 'KL46Z', 'K20D5M', 'LPC1347', 'LPC1114', 'LPC11C24', 'LPC4088', 'LPC812', 'NUCLEO_F103RB', 'NUCLEO_L152RE', 'NUCLEO_F030R8', 'NUCLEO_F401RE', 'UBLOX_C027']
USING_MICROLIB = ['LPC11U24', 'LPC1114', 'LPC11C24', 'LPC812', 'NUCLEO_F103RB', 'NUCLEO_L152RE', 'NUCLEO_F030R8', 'NUCLEO_F401RE']

2
workspace_tools/targets.py
View File

@ -108,7 +108,7 @@ class KL05Z(Target):
self.extra_labels = ['Freescale', 'KLXX']
self.supported_toolchains = ["ARM", "GCC_ARM"]
self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"]
self.is_disk_virtual = True