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Refactor load region definitions for ArmC6 toolchain

pull/14466/head
harmut01 2021-03-25 09:26:00 +00:00
parent 2e3bf05d23
commit ea83d07465
2 changed files with 5 additions and 5 deletions
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6
targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/gd32f307vg.sct
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@ -46,14 +46,14 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (1024K)
}
; 84 vectors (16 core + 68 peripheral) * 4 bytes = 336 bytes to reserve (0x150)
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE-Stack_Size) { ; RW data
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-RAM_FIXED_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM1_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM1_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap region growing up
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -Stack_Size { ; stack
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -Stack_Size { ; Stack region growing down
}
}

4
targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_ARM_STD/gd32f450zi.sct
View File

@ -46,11 +46,11 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (3*1024K)
}
; 107 vectors (16 core + 91 peripheral) * 4 bytes = 428 bytes to reserve (0x1B0, 8-byte aligned)
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE-Stack_Size) { ; RW data
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-RAM_FIXED_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM1_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM1_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap region growing up
}
ARM_LIB_STACK MBED_RAM_START+MBED_RAM_SIZE EMPTY -Stack_Size { ; Stack region growing down