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STM32F7 QSPI flash timeouts and 4-byte addressing (#152) 

* STM32F7: Unconditionally enable QSPI workarounds

On the STM32769NI at least this patch is required for stable QSPI use.
Enable it uncondtionally in case other boards need it too.

Further discussions:

https://github.com/ARMmbed/mbed-os/issues/10049
https://github.com/ARMmbed/mbed-os/issues/15108

https://github.com/STMicroelectronics/STM32CubeF7/issues/52
https://github.com/STMicroelectronics/STM32CubeF7/issues/82

* QSPIF: Attempt 4-byte addressing on Macronix chips

mbed-os PR 11531 introduced 4-byte addressing in the QSPIF block device:

https://github.com/ARMmbed/mbed-os/pull/11531

During testing it was found that this code broke on the NRF52840_DK and
DISCO_F769NI.

The NRF52840_DK controller seems unable to handle 4-byte addressing at
all and has been disabled entirely in another code section.

The DISCO_F769NI breakage was attributed to the flash chip but after more
research I believe this is related to the QSPI controller, not the 4-byte
addressing itself.

Now that the QSPI controller has a workaround, enable 4-byte addressing
again and hope it works fine this time.
pull/15437/head
Jookia 2023-03-22 03:19:22 +11:00 committed by GitHub
parent ed4c4f432b
commit ea044e0695
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2 changed files with 0 additions and 9 deletions
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1
storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp
View File

@ -1095,7 +1095,6 @@ int QSPIFBlockDevice::_handle_vendor_quirks()
_needs_fast_mode = true;
_num_status_registers = 3;
_read_status_reg_2_inst = QSPIF_INST_RDCR;
_attempt_4_byte_addressing = false;
break;
case 0x9d:
// ISSI devices have only one status register

8
targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_qspi.c
View File

@ -571,10 +571,8 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
__HAL_DMA_DISABLE(hqspi->hdma);
}
#if defined(QSPI1_V1_0)
/* Clear Busy bit */
HAL_QSPI_Abort_IT(hqspi);
#endif
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
@ -616,10 +614,8 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
}
#if defined(QSPI1_V1_0)
/* Workaround - Extra data written in the FIFO at the end of a read transfer */
HAL_QSPI_Abort_IT(hqspi);
#endif
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
@ -1021,10 +1017,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u
/* Clear Transfer Complete bit */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
#if defined(QSPI1_V1_0)
/* Clear Busy bit */
status = HAL_QSPI_Abort(hqspi);
#endif
}
}
@ -1112,10 +1106,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
/* Clear Transfer Complete bit */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
#if defined(QSPI1_V1_0)
/* Workaround - Extra data written in the FIFO at the end of a read transfer */
status = HAL_QSPI_Abort(hqspi);
#endif
}
}