Add XIP capability, enable QSPI. XIP can be enable by adding macro XIP_ENABLE in mbed_app.json. It's disabled by default.

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S

@@ -53,23 +53,6 @@ __StackLimit:
 __StackTop:
     .size    __StackTop, . - __StackTop
 
-    .section .heap
-    .align    3
-#ifdef __HEAP_SIZE
-    .equ    Heap_Size, __HEAP_SIZE
-#else
-    .equ    Heap_Size, 0x00000400
-#endif
-    .globl    __HeapBase
-    .globl    __HeapLimit
-__HeapBase:
-    .if    Heap_Size
-    .space    Heap_Size
-    .endif
-    .size    __HeapBase, . - __HeapBase
-__HeapLimit:
-    .size    __HeapLimit, . - __HeapLimit
-
     .section .vectors
     .align 2
     .globl    __Vectors

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h

@@ -22,6 +22,76 @@
 * limitations under the License.
 ********************************************************************************/
 
+/*******************************************************************************
+
+QSPI_CONFIG_START
+
+<CySMIFConfiguration>
+    <DevicePath>PSoC 6.xml</DevicePath>
+    <SlotConfigs>
+        <SlotConfig>
+            <SlaveSlot>0</SlaveSlot>
+            <PartNumber>S25FL512S</PartNumber>
+            <MemoryMapped>true</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18000000</StartAddress>
+            <Size>0x40000</Size>
+            <EndAddress>0x1803FFFF</EndAddress>
+            <WriteEnable>true</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
+            <MemoryConfigsPath>S25FL512S</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>1</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18010000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1801FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>2</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18020000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1802FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>3</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18030000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1803FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+    </SlotConfigs>
+</CySMIFConfiguration>
+
+QSPI_CONFIG_END
+
+*******************************************************************************/
+
 #ifndef CYCFG_QSPI_MEMSLOT_H
 #define CYCFG_QSPI_MEMSLOT_H
 #include "cy_smif_memslot.h"
@@ -41,6 +111,7 @@ extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd;
 extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL128S_SlaveSlot_0;
 
 extern const cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0;
+
 extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
 
 extern const cy_stc_smif_block_config_t smifBlockConfig;

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld

@@ -162,6 +162,21 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
 SECTIONS
 {
     /* Cortex-M4 application image */
+    /* Places the code in the Execute in Place (XIP) section. See the smif driver
+     *  documentation for details.
+     */
+    .cy_xip :
+    {
+        . = ALIGN(4);
+        __cy_xip_start__ = .;
+        KEEP(*(.cy_xip))
+        #if XIP_ENABLE == 1
+        *lwipstack*.o (.text .text* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+        *mbed-cloud-client*.o (.text .text* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+        #endif
+        __cy_xip_end__ = .;
+    } > xip
+
     .text FLASH_CM4_START :
     {
         . = ALIGN(4);
@@ -173,7 +188,11 @@ SECTIONS
         __end__ = .;
 
         . = ALIGN(4);
+        #if XIP_ENABLE == 1
+        *(EXCLUDE_FILE(*lwipstack*.o *mbed-cloud-client*.o) .text .text*)
+        #else
         *(.text*)
+        #endif
 
         KEEP(*(.init))
         KEEP(*(.fini))
@@ -193,7 +212,11 @@ SECTIONS
         *(.dtors)
 
         /* Read-only code (constants). */
+        #if XIP_ENABLE == 1
+        *(EXCLUDE_FILE(*lwipstack*.o *mbed-cloud-client*.o) .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+        #else
         *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+        #endif
 
         KEEP(*(.eh_frame*))
     } > flash
@@ -400,15 +423,6 @@ SECTIONS
     } > sflash_rtoc_2
 
 
-    /* Places the code in the Execute in Place (XIP) section. See the smif driver
-    *  documentation for details.
-    */
-    .cy_xip :
-    {
-        KEEP(*(.cy_xip))
-    } > xip
-
-
     /* eFuse */
     .cy_efuse :
     {

targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c

@@ -31,6 +31,9 @@
 void mailbox_init(void);
 #endif
 
+#if defined(XIP_ENABLE)
+extern void qspi_xip_start();
+#endif
 
 #if (defined(CY_CFG_PWR_SYS_IDLE_MODE) && (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_ACTIVE))
 /*******************************************************************************
@@ -100,6 +103,9 @@ void mbed_sdk_init(void)
     /* Enable global interrupts (disabled in CM4 startup assembly) */
     __enable_irq();
 #endif
+#if defined(XIP_ENABLE)
+    qspi_xip_start();
+#endif
 
 #if defined (CY_CFG_PWR_SYS_IDLE_MODE)
     /* Configure the lowest power state the system is allowed to enter

targets/TARGET_Cypress/TARGET_PSOC6/xip_user.c

@@ -0,0 +1,84 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2019, Arm Limited and affiliates.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifdef XIP_ENABLE
+#include "cy_smif.h"
+#include "cy_smif_memslot.h"
+#include "cycfg_qspi_memslot.h"
+#include "qspi_api.h"
+
+/********************************************************************
+* NULL terminated array of SMIF structures for use in TOC2
+********************************************************************/
+typedef struct
+{
+    const cy_stc_smif_block_config_t * smifCfg; /* Pointer to SMIF top-level configuration */
+    const uint32_t null_t; /* NULL termination */
+} stc_smif_ipblocks_arr_t;
+
+/* 
+ * PSoC 6 boot sequence is such that the TOC2 needs to verified before switching to the application code.
+ * In the mbed build system the CRC for TOC2 is not calculated. Hence CRC has to be manually placed in the TOC2
+ * SMIF config structure is placed at a fixed address so as to fix the CRC for table of contents2 (TOC2).
+*/
+__attribute__((section(".cy_sflash_user_data"))) __attribute__((used))
+const stc_smif_ipblocks_arr_t smifIpBlocksArr = {&smifBlockConfig, 0x00000000};
+
+/********************************************************************
+* Point to the SMIF block structure in the table of contents2 (TOC2).
+* 
+* This enables memory reads using Cypress Programmer, without this
+* structure, external memory access from Cypress Programmer will not 
+* work 
+********************************************************************/
+
+__attribute__((section(".cy_toc_part2"))) __attribute__((used))
+const int cyToc[128] =
+{
+    0x200-4,                 /* Offset=0x00: Object Size, bytes */          
+    0x01211220,              /* Offset=0x04: Magic Number (TOC Part 2, ID) */   
+    0,                       /* Offset=0x08: Key Storage Address */  
+    (int)&smifIpBlocksArr,   /* Offset=0x0C: This points to a null terminated array of SMIF structures. */   
+    0x10000000u,             /* Offset=0x10: App image start address */
+    [127] =  0x0B1F0000      /* Offset=0x1FC: CRC16-CCITT (the upper 2 bytes contain the CRC and the lower 2 bytes are 0) */ 
+};
+
+/* QSPI HAL object */
+qspi_t QSPI_HW;
+
+void qspi_xip_start()
+{
+    QSPI_HW.hal_qspi.base = SMIF0;
+    QSPI_HW.hal_qspi.slave_select = CY_SMIF_SLAVE_SELECT_0;
+    qspi_status_t qspi_api_result = QSPI_STATUS_OK;
+
+    /* Initialize the QSPI interface */
+    qspi_api_result = qspi_init(&QSPI_HW, QSPI_IO_0, QSPI_IO_1, QSPI_IO_2, QSPI_IO_3, QSPI_CLK, QSPI_SEL, 0, 0);
+    
+    if(qspi_api_result == QSPI_STATUS_OK)
+    {
+        /* Initialize the memory device connected to SMIF slot */
+        Cy_SMIF_Memslot_Init(QSPI_HW.hal_qspi.base, (cy_stc_smif_block_config_t*)&smifBlockConfig, &(QSPI_HW.hal_qspi.context));
+
+        /* Enable quad mode of operation */
+        Cy_SMIF_Memslot_QuadEnable(QSPI_HW.hal_qspi.base, (cy_stc_smif_mem_config_t*)smifMemConfigs[0], &(QSPI_HW.hal_qspi.context));
+
+        /* Set the operation mode to XIP */
+        Cy_SMIF_SetMode(QSPI_HW.hal_qspi.base, CY_SMIF_MEMORY);
+    }
+}
+#endif

targets/targets.json

@@ -8579,6 +8579,7 @@
             "SERIAL_FC",
             "SERIAL_ASYNCH",
             "SLEEP",
+            "QSPI",
             "SPI",
             "SPI_ASYNCH",
             "SPISLAVE",

tools/toolchains/mbed_toolchain.py

@@ -990,6 +990,12 @@ class mbedToolchain:
                 self.ld.append(define_string)
                 self.flags["ld"].append(define_string)
 
+        if "XIP_ENABLE" in self.target.macros :
+                define_string = self.make_ld_define(
+                    "XIP_ENABLE", 1)
+                self.ld.append(define_string)
+                self.flags["ld"].append(define_string)
+
     # Set the configuration data
     def set_config_data(self, config_data):
         self.config_data = config_data