From 1e2e14e11ddf01b1387962854ea94bce98086979 Mon Sep 17 00:00:00 2001 From: tomoyuki yamanaka Date: Fri, 3 Jun 2016 18:36:28 +0900 Subject: [PATCH 1/3] Implement SystemcoreClock We implemented SystemcoreClock which is defined in CMSIS. --- .../TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c | 15 +++++++++++++++ .../TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h | 2 ++ .../TARGET_VK_RZ_A1H/system_VKRZA1H.c | 15 +++++++++++++++ .../TARGET_VK_RZ_A1H/system_VKRZA1H.h | 2 ++ 4 files changed, 34 insertions(+) diff --git a/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c b/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c index a07f8c4bc8..71d93e76f6 100644 --- a/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c +++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c @@ -51,6 +51,7 @@ void FPUEnable(void); uint32_t IRQNestLevel; unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075 +uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; /*!< System Clock Frequency (Core Clock) */ /** @@ -198,6 +199,20 @@ uint32_t InterruptHandlerUnregister (IRQn_Type irq) } } +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock. + */ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; +} + + /** * Initialize the system * diff --git a/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h b/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h index 832e58bb91..bd7ba03809 100644 --- a/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h +++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h @@ -43,6 +43,8 @@ extern "C" { #endif +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + typedef void(*IRQHandler)(); uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler); uint32_t InterruptHandlerUnregister(IRQn_Type); diff --git a/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c index 04bfbd0935..d97ccae069 100644 --- a/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c +++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c @@ -51,6 +51,7 @@ void FPUEnable(void); uint32_t IRQNestLevel; unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075 +uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; /*!< System Clock Frequency (Core Clock) */ /** @@ -198,6 +199,20 @@ uint32_t InterruptHandlerUnregister (IRQn_Type irq) } } +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock. + */ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; +} + + /** * Initialize the system * diff --git a/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.h b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.h index bc7637b39d..f04b37b8a4 100644 --- a/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.h +++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.h @@ -43,6 +43,8 @@ extern "C" { #endif +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + typedef void(*IRQHandler)(); uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler); uint32_t InterruptHandlerUnregister(IRQn_Type); From 0a9e5fa3d60083146aa6b0adbf683fe3a0d72f13 Mon Sep 17 00:00:00 2001 From: tomoyuki yamanaka Date: Fri, 10 Jun 2016 16:13:35 +0900 Subject: [PATCH 2/3] Implement SystemCoreClockUpdate () function We changed to calculare the CPU Clock by the division ratio setting of from FRQCR register. --- .../TARGET_RZ_A1H/system_MBRZA1H.c | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c b/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c index 71d93e76f6..d8db0843e1 100644 --- a/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c +++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c @@ -49,6 +49,12 @@ void FPUEnable(void); #endif +#define FRQCR_IFC_MSK (0x0030) +#define FRQCR_IFC_SHFT (8) +#define FRQCR_IFC_1P1 (0) /* x1/1 */ +#define FRQCR_IFC_2P3 (1) /* x2/3 */ +#define FRQCR_IFC_1P3 (3) /* x1/3 */ + uint32_t IRQNestLevel; unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075 uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; /*!< System Clock Frequency (Core Clock) */ @@ -209,7 +215,22 @@ uint32_t InterruptHandlerUnregister (IRQn_Type irq) */ void SystemCoreClockUpdate (void) { - SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; + uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT; + + switch (frqcr_ifc) { + case FRQCR_IFC_1P1: + SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; + break; + case FRQCR_IFC_2P3: + SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3; + break; + case FRQCR_IFC_1P3: + SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK / 3; + break; + default: + /* do nothing */ + break; + } } From 8f3e72f01c17bf8a4e2e561afe0115043891bdab Mon Sep 17 00:00:00 2001 From: tomoyuki yamanaka Date: Fri, 10 Jun 2016 16:16:06 +0900 Subject: [PATCH 3/3] Implement SystemCoreClockUpdate () function --- .../TARGET_VK_RZ_A1H/system_VKRZA1H.c | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c index d97ccae069..8017e372a3 100644 --- a/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c +++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c @@ -49,6 +49,12 @@ void FPUEnable(void); #endif +#define FRQCR_IFC_MSK (0x0030) +#define FRQCR_IFC_SHFT (8) +#define FRQCR_IFC_1P1 (0) /* x1/1 */ +#define FRQCR_IFC_2P3 (1) /* x2/3 */ +#define FRQCR_IFC_1P3 (3) /* x1/3 */ + uint32_t IRQNestLevel; unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075 uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; /*!< System Clock Frequency (Core Clock) */ @@ -209,7 +215,22 @@ uint32_t InterruptHandlerUnregister (IRQn_Type irq) */ void SystemCoreClockUpdate (void) { - SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; + uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT; + + switch (frqcr_ifc) { + case FRQCR_IFC_1P1: + SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; + break; + case FRQCR_IFC_2P3: + SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3; + break; + case FRQCR_IFC_1P3: + SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK / 3; + break; + default: + /* do nothing */ + break; + } }