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QSPI: initial HAL nrf52840 version 

This commit adds QSPI HAL implementation for nrf52840 MCU targets
pull/6106/head
Martin Kojtal 2017-11-10 12:24:13 +00:00
parent 4b044c2873
commit e8c059cca7
7 changed files with 2892 additions and 1243 deletions
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127
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/sdk_config.h
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@ -2091,6 +2091,133 @@
#endif //SPI_ENABLED
// </e>
// <e> QSPI_ENABLED - nrf_drv_qspi - QSPI peripheral driver.
//==========================================================
#ifndef QSPI_ENABLED
#define QSPI_ENABLED 1
#endif
#if QSPI_ENABLED
// <o> QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns). <0-255>
#ifndef QSPI_CONFIG_SCK_DELAY
#define QSPI_CONFIG_SCK_DELAY 1
#endif
// <o> QSPI_CONFIG_READOC - Number of data lines and opcode used for reading.
// <0=> FastRead
// <1=> Read2O
// <2=> Read2IO
// <3=> Read4O
// <4=> Read4IO
#ifndef QSPI_CONFIG_READOC
#define QSPI_CONFIG_READOC 4
#endif
// <o> QSPI_CONFIG_WRITEOC - Number of data lines and opcode used for writing.
// <0=> PP
// <1=> PP2O
// <2=> PP4O
// <3=> PP4IO
#ifndef QSPI_CONFIG_WRITEOC
#define QSPI_CONFIG_WRITEOC 3
#endif
// <o> QSPI_CONFIG_ADDRMODE - Addressing mode.
// <0=> 24bit
// <1=> 32bit
#ifndef QSPI_CONFIG_ADDRMODE
#define QSPI_CONFIG_ADDRMODE 0
#endif
// <o> QSPI_CONFIG_MODE - SPI mode.
// <0=> Mode 0
// <1=> Mode 1
#ifndef QSPI_CONFIG_MODE
#define QSPI_CONFIG_MODE 0
#endif
// <o> QSPI_CONFIG_FREQUENCY - Frequency divider.
// <0=> 32MHz/1
// <1=> 32MHz/2
// <2=> 32MHz/3
// <3=> 32MHz/4
// <4=> 32MHz/5
// <5=> 32MHz/6
// <6=> 32MHz/7
// <7=> 32MHz/8
// <8=> 32MHz/9
// <9=> 32MHz/10
// <10=> 32MHz/11
// <11=> 32MHz/12
// <12=> 32MHz/13
// <13=> 32MHz/14
// <14=> 32MHz/15
// <15=> 32MHz/16
#ifndef QSPI_CONFIG_FREQUENCY
#define QSPI_CONFIG_FREQUENCY 1
#endif
// <s> QSPI_PIN_SCK - SCK pin value.
#ifndef QSPI_PIN_SCK
#define QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED
#endif
// <s> QSPI_PIN_CSN - CSN pin value.
#ifndef QSPI_PIN_CSN
#define QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED
#endif
// <s> QSPI_PIN_IO0 - IO0 pin value.
#ifndef QSPI_PIN_IO0
#define QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED
#endif
// <s> QSPI_PIN_IO1 - IO1 pin value.
#ifndef QSPI_PIN_IO1
#define QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED
#endif
// <s> QSPI_PIN_IO2 - IO2 pin value.
#ifndef QSPI_PIN_IO2
#define QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED
#endif
// <s> QSPI_PIN_IO3 - IO3 pin value.
#ifndef QSPI_PIN_IO3
#define QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED
#endif
// <o> QSPI_CONFIG_IRQ_PRIORITY - Interrupt priority
// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
// <0=> 0 (highest)
// <1=> 1
// <2=> 2
// <3=> 3
// <4=> 4
// <5=> 5
// <6=> 6
// <7=> 7
#ifndef QSPI_CONFIG_IRQ_PRIORITY
#define QSPI_CONFIG_IRQ_PRIORITY 7
#endif
#endif //QSPI_ENABLED
// </e>
// <q> SYSTICK_ENABLED - nrf_drv_systick - SysTick driver

738
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_qspi.h Normal file
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@ -0,0 +1,738 @@
/* Copyright (c) 2016 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**
* @defgroup nrf_qspi_hal QSPI HAL
* @{
* @ingroup nrf_qspi
*
* @brief Hardware access layer for accessing the QSPI peripheral.
*/
#ifndef NRF_QSPI_H__
#define NRF_QSPI_H__
#include <stddef.h>
#include <stdbool.h>
#include "boards.h"
#include "nrf.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief This value can be used as a parameter for the @ref nrf_qspi_pins_set
* function to specify that a given QSPI signal (SCK, CSN, IO0, IO1, IO2, or IO3)
* will not be connected to a physical pin.
*/
#define NRF_QSPI_PIN_NOT_CONNECTED 0xFF
/**
* @brief Macro for setting proper values to pin registers.
*/
#define NRF_QSPI_PIN_VAL(pin) (pin) == NRF_QSPI_PIN_NOT_CONNECTED ? 0xFFFFFFFF : (pin)
/**
* @brief QSPI tasks.
*/
typedef enum
{
/*lint -save -e30*/
NRF_QSPI_TASK_ACTIVATE = offsetof(NRF_QSPI_Type, TASKS_ACTIVATE), /**< Activate the QSPI interface. */
NRF_QSPI_TASK_READSTART = offsetof(NRF_QSPI_Type, TASKS_READSTART), /**< Start transfer from external flash memory to internal RAM. */
NRF_QSPI_TASK_WRITESTART = offsetof(NRF_QSPI_Type, TASKS_WRITESTART), /**< Start transfer from internal RAM to external flash memory. */
NRF_QSPI_TASK_ERASESTART = offsetof(NRF_QSPI_Type, TASKS_ERASESTART), /**< Start external flash memory erase operation. */
/*lint -restore*/
} nrf_qspi_task_t;
/**
* @brief QSPI events.
*/
typedef enum
{
/*lint -save -e30*/
NRF_QSPI_EVENT_READY = offsetof(NRF_QSPI_Type, EVENTS_READY) /**< QSPI peripheral is ready after it executes any task. */
/*lint -restore*/
} nrf_qspi_event_t;
/**
* @brief QSPI interrupts.
*/
typedef enum
{
NRF_QSPI_INT_READY_MASK = QSPI_INTENSET_READY_Msk /**< Interrupt on READY event. */
} nrf_qspi_int_mask_t;
/**
* @brief QSPI frequency divider values.
*/
typedef enum
{
NRF_QSPI_FREQ_32MDIV1, /**< 32.0 MHz. */
NRF_QSPI_FREQ_32MDIV2, /**< 16.0 MHz. */
NRF_QSPI_FREQ_32MDIV3, /**< 10.6 MHz. */
NRF_QSPI_FREQ_32MDIV4, /**< 8.00 MHz. */
NRF_QSPI_FREQ_32MDIV5, /**< 6.40 MHz. */
NRF_QSPI_FREQ_32MDIV6, /**< 5.33 MHz. */
NRF_QSPI_FREQ_32MDIV7, /**< 4.57 MHz. */
NRF_QSPI_FREQ_32MDIV8, /**< 4.00 MHz. */
NRF_QSPI_FREQ_32MDIV9, /**< 3.55 MHz. */
NRF_QSPI_FREQ_32MDIV10, /**< 3.20 MHz. */
NRF_QSPI_FREQ_32MDIV11, /**< 2.90 MHz. */
NRF_QSPI_FREQ_32MDIV12, /**< 2.66 MHz. */
NRF_QSPI_FREQ_32MDIV13, /**< 2.46 MHz. */
NRF_QSPI_FREQ_32MDIV14, /**< 2.29 MHz. */
NRF_QSPI_FREQ_32MDIV15, /**< 2.13 MHz. */
NRF_QSPI_FREQ_32MDIV16, /**< 2.00 MHz. */
} nrf_qspi_frequency_t;
/**
* @brief Interface configuration for a read operation.
*/
typedef enum
{
NRF_QSPI_READOC_FASTREAD = QSPI_IFCONFIG0_READOC_FASTREAD, /**< Single data line SPI. FAST_READ (opcode 0x0B). */
NRF_QSPI_READOC_READ2O = QSPI_IFCONFIG0_READOC_READ2O, /**< Dual data line SPI. READ2O (opcode 0x3B). */
NRF_QSPI_READOC_READ2IO = QSPI_IFCONFIG0_READOC_READ2IO, /**< Dual data line SPI. READ2IO (opcode 0xBB). */
NRF_QSPI_READOC_READ4O = QSPI_IFCONFIG0_READOC_READ4O, /**< Quad data line SPI. READ4O (opcode 0x6B). */
NRF_QSPI_READOC_READ4IO = QSPI_IFCONFIG0_READOC_READ4IO /**< Quad data line SPI. READ4IO (opcode 0xEB). */
} nrf_qspi_readoc_t;
/**
* @brief Interface configuration for a write operation.
*/
typedef enum
{
NRF_QSPI_WRITEOC_PP = QSPI_IFCONFIG0_WRITEOC_PP, /**< Single data line SPI. PP (opcode 0x02). */
NRF_QSPI_WRITEOC_PP2O = QSPI_IFCONFIG0_WRITEOC_PP2O, /**< Dual data line SPI. PP2O (opcode 0xA2). */
NRF_QSPI_WRITEOC_PP4O = QSPI_IFCONFIG0_WRITEOC_PP4O, /**< Quad data line SPI. PP4O (opcode 0x32). */
NRF_QSPI_WRITEOC_PP4IO = QSPI_IFCONFIG0_WRITEOC_PP4IO, /**< Quad data line SPI. READ4O (opcode 0x38). */
} nrf_qspi_writeoc_t;
/**
* @brief Interface configuration for addressing mode.
*/
typedef enum
{
NRF_QSPI_ADDRMODE_24BIT = QSPI_IFCONFIG0_ADDRMODE_24BIT, /**< 24-bit addressing. */
NRF_QSPI_ADDRMODE_32BIT = QSPI_IFCONFIG0_ADDRMODE_32BIT /**< 32-bit addressing. */
} nrf_qspi_addrmode_t;
/**
* @brief QSPI SPI mode. Polarization and phase configuration.
*/
typedef enum
{
NRF_QSPI_MODE_0 = QSPI_IFCONFIG1_SPIMODE_MODE0, /**< Mode 0 (CPOL=0, CPHA=0). */
NRF_QSPI_MODE_1 = QSPI_IFCONFIG1_SPIMODE_MODE3 /**< Mode 1 (CPOL=1, CPHA=1). */
} nrf_qspi_spi_mode_t;
/**
* @brief Addressing configuration mode.
*/
typedef enum
{
NRF_QSPI_ADDRCONF_MODE_NOINSTR = QSPI_ADDRCONF_MODE_NoInstr, /**< Do not send any instruction. */
NRF_QSPI_ADDRCONF_MODE_OPCODE = QSPI_ADDRCONF_MODE_Opcode, /**< Send opcode. */
NRF_QSPI_ADDRCONF_MODE_OPBYTE0 = QSPI_ADDRCONF_MODE_OpByte0, /**< Send opcode, byte0. */
NRF_QSPI_ADDRCONF_MODE_ALL = QSPI_ADDRCONF_MODE_All /**< Send opcode, byte0, byte1. */
} nrf_qspi_addrconfig_mode_t;
/**
* @brief Erasing data length.
*/
typedef enum
{
NRF_QSPI_ERASE_LEN_4KB = QSPI_ERASE_LEN_LEN_4KB, /**< Erase 4 kB block (flash command 0x20). */
NRF_QSPI_ERASE_LEN_64KB = QSPI_ERASE_LEN_LEN_64KB, /**< Erase 64 kB block (flash command 0xD8). */
NRF_QSPI_ERASE_LEN_ALL = QSPI_ERASE_LEN_LEN_All /**< Erase all (flash command 0xC7). */
} nrf_qspi_erase_len_t;
/**
* @brief Custom instruction length.
*/
typedef enum
{
NRF_QSPI_CINSTR_LEN_1B = QSPI_CINSTRCONF_LENGTH_1B, /**< Send opcode only. */
NRF_QSPI_CINSTR_LEN_2B = QSPI_CINSTRCONF_LENGTH_2B, /**< Send opcode, CINSTRDAT0.BYTE0. */
NRF_QSPI_CINSTR_LEN_3B = QSPI_CINSTRCONF_LENGTH_3B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1. */
NRF_QSPI_CINSTR_LEN_4B = QSPI_CINSTRCONF_LENGTH_4B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2. */
NRF_QSPI_CINSTR_LEN_5B = QSPI_CINSTRCONF_LENGTH_5B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3. */
NRF_QSPI_CINSTR_LEN_6B = QSPI_CINSTRCONF_LENGTH_6B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4. */
NRF_QSPI_CINSTR_LEN_7B = QSPI_CINSTRCONF_LENGTH_7B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5. */
NRF_QSPI_CINSTR_LEN_8B = QSPI_CINSTRCONF_LENGTH_8B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6. */
NRF_QSPI_CINSTR_LEN_9B = QSPI_CINSTRCONF_LENGTH_9B /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7. */
} nrf_qspi_cinstr_len_t;
/**
* @brief Pins configuration.
*/
typedef struct
{
uint8_t sck_pin; /**< SCK pin number. */
uint8_t csn_pin; /**< Chip select pin number. */
uint8_t io0_pin; /**< IO0/MOSI pin number. */
uint8_t io1_pin; /**< IO1/MISO pin number. */
uint8_t io2_pin; /**< IO2 pin number (optional).
* Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed.
*/
uint8_t io3_pin; /**< IO3 pin number (optional).
* Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed.
*/
} nrf_qspi_pins_t;
/**
* @brief Custom instruction configuration.
*/
typedef struct
{
uint8_t opcode; /**< Opcode used in custom instruction transmission. */
nrf_qspi_cinstr_len_t length; /**< Length of the custom instruction data. */
bool io2_level; /**< I/O line level during transmission. */
bool io3_level; /**< I/O line level during transmission. */
bool wipwait; /**< Wait if a Wait in Progress bit is set in the memory status byte. */
bool wren; /**< Send write enable before instruction. */
} nrf_qspi_cinstr_conf_t;
/**
* @brief Addressing mode register configuration. See @ref nrf_qspi_addrconfig_set
*/
typedef struct
{
uint8_t opcode; /**< Opcode used to enter proper addressing mode. */
uint8_t byte0; /**< Byte following the opcode. */
uint8_t byte1; /**< Byte following byte0. */
nrf_qspi_addrconfig_mode_t mode; /**< Extended addresing mode. */
bool wipwait; /**< Enable/disable waiting for complete operation execution. */
bool wren; /**< Send write enable before instruction. */
} nrf_qspi_addrconfig_conf_t;
/**
* @brief Structure with QSPI protocol interface configuration.
*/
typedef struct
{
nrf_qspi_readoc_t readoc; /**< Read operation code. */
nrf_qspi_writeoc_t writeoc; /**< Write operation code. */
nrf_qspi_addrmode_t addrmode; /**< Addresing mode (24-bit or 32-bit). */
bool dpmconfig; /**< Enable the Deep Power-down Mode (DPM) feature. */
} nrf_qspi_prot_conf_t;
/**
* @brief QSPI physical interface configuration.
*/
typedef struct
{
uint8_t sck_delay; /**< tSHSL, tWHSL, and tSHWL in number of 16 MHz periods (62.5ns). */
bool dpmen; /**< Enable the DPM feature. */
nrf_qspi_spi_mode_t spi_mode; /**< SPI phase and polarization. */
nrf_qspi_frequency_t sck_freq; /**< SCK frequency given as enum @ref nrf_qspi_frequency_t. */
} nrf_qspi_phy_conf_t;
/**
* @brief Function for activating a specific QSPI task.
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] task Task to activate.
*/
__STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task);
/**
* @brief Function for getting the address of a specific QSPI task register.
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] task Requested task.
*
* @return Address of the specified task register.
*/
__STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg,
nrf_qspi_task_t task);
/**
* @brief Function for clearing a specific QSPI event.
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] qspi_event Event to clear.
*/
__STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t qspi_event);
/**
* @brief Function for checking the state of a specific SPI event.
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] qspi_event Event to check.
*
* @retval true If the event is set.
* @retval false If the event is not set.
*/
__STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t qspi_event);
/**
* @brief Function for getting the address of a specific QSPI event register.
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] qspi_event Requested event.
*
* @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t * nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg,
nrf_qspi_event_t qspi_event);
/**
* @brief Function for enabling specified interrupts.
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] qspi_int_mask Interrupts to enable.
*/
__STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask);
/**
* @brief Function for disabling specified interrupts.
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] qspi_int_mask Interrupts to disable.
*/
__STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] qspi_int Interrupt to check.
*
* @retval true If the interrupt is enabled.
* @retval false If the interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg,
nrf_qspi_int_mask_t qspi_int);
/**
* @brief Function for enabling the QSPI peripheral.
*
* @param[in] p_reg Pointer to the peripheral register structure.
*/
__STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg);
/**
* @brief Function for disabling the QSPI peripheral.
*
* @param[in] p_reg Pointer to the peripheral register structure.
*/
__STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg);
/**
* @brief Function for configuring QSPI pins.
*
* If a given signal is not needed, pass the @ref NRF_QSPI_PIN_NOT_CONNECTED
* value instead of its pin number.
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] p_pins Pointer to the pins configuration structure. See @ref nrf_qspi_pins_t.
*/
__STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg,
const nrf_qspi_pins_t * p_pins);
/**
* @brief Function for setting the QSPI IFCONFIG0 register.
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] p_config Pointer to the QSPI protocol interface configuration structure. See @ref nrf_qspi_prot_conf_t.
*/
__STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,
const nrf_qspi_prot_conf_t * p_config);
/**
* @brief Function for setting the QSPI IFCONFIG1 register.
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] p_config Pointer to the QSPI physical interface configuration structure. See @ref nrf_qspi_phy_conf_t.
*/
__STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,
const nrf_qspi_phy_conf_t * p_config);
/**
* @brief Function for setting the QSPI ADDRCONF register.
*
* Function must be executed before sending task NRF_QSPI_TASK_ACTIVATE. Data stored in the structure
* is sent during the start of the peripheral. Remember that the reset instruction can set
* addressing mode to default in the memory device. If memory reset is necessary before configuring
* the addressing mode, use custom instruction feature instead of this function.
* Case with reset: Enable the peripheral without setting ADDRCONF register, send reset instructions
* using a custom instruction feature (reset enable and then reset), set proper addressing mode
* using the custom instruction feature.
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] p_config Pointer to the addressing mode configuration structure. See @ref nrf_qspi_addrconfig_conf_t.
*/
__STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg,
const nrf_qspi_addrconfig_conf_t * p_config);
/**
* @brief Function for setting write data into the peripheral register (without starting the process).
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] p_buffer Pointer to the writing buffer.
* @param[in] length Lenght of the writing data.
* @param[in] dest_addr Address in memory to write to.
*/
__STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,
void const * p_buffer,
uint32_t length,
uint32_t dest_addr);
/**
* @brief Function for setting read data into the peripheral register (without starting the process).
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[out] p_buffer Pointer to the reading buffer.
* @param[in] length Length of the read data.
* @param[in] src_addr Address in memory to read from.
*/
__STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,
void * p_buffer,
uint32_t length,
uint32_t src_addr);
/**
* @brief Function for setting erase data into the peripheral register (without starting the process).
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] erase_addr Start address to erase. Address must have padding set to 4 bytes.
* @param[in] len Size of erasing area.
*/
__STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg,
uint32_t erase_addr,
nrf_qspi_erase_len_t len);
/**
* @brief Function for getting the peripheral status register.
*
* @param[in] p_reg Pointer to the peripheral register structure.
*
* @return Peripheral status register.
*/
__STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg);
/**
* @brief Function for getting the device status register stored in the peripheral status register.
*
* @param[in] p_reg Pointer to the peripheral register structure.
*
* @return Device status register (lower byte).
*/
__STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg);
/**
* @brief Function for checking if the peripheral is busy or not.
*
* @param[in] p_reg Pointer to the peripheral register structure.
*
* @retval true If QSPI is busy.
* @retval false If QSPI is ready.
*/
__STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg);
/**
* @brief Function for setting registers sending with custom instruction transmission.
*
* This function can be ommited when using NRF_QSPI_CINSTR_LEN_1B as the length argument
* (sending only opcode without data).
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] length Length of the custom instruction data.
* @param[in] p_tx_data Pointer to the data to send with the custom instruction.
*/
__STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg,
nrf_qspi_cinstr_len_t length,
void const * p_tx_data);
/**
* @brief Function for getting data from register after custom instruction transmission.
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] length Length of the custom instruction data.
* @param[in] p_rx_data Pointer to the reading buffer.
*/
__STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,
nrf_qspi_cinstr_len_t length,
void * p_rx_data);
/**
* @brief Function for sending custom instruction to external memory.
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] p_config Pointer to the custom instruction configuration structure. See @ref nrf_qspi_cinstr_conf_t.
*/
__STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg,
const nrf_qspi_cinstr_conf_t * p_config);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
}
__STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg,
nrf_qspi_task_t task)
{
return ((uint32_t)p_reg + (uint32_t)task);
}
__STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t qspi_event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)qspi_event)) = 0x0UL;
}
__STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t qspi_event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)qspi_event);
}
__STATIC_INLINE uint32_t * nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg,
nrf_qspi_event_t qspi_event)
{
return (uint32_t *)((uint8_t *)p_reg + (uint32_t)qspi_event);
}
__STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask)
{
p_reg->INTENSET = qspi_int_mask;
}
__STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask)
{
p_reg->INTENCLR = qspi_int_mask;
}
__STATIC_INLINE bool nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg,
nrf_qspi_int_mask_t qspi_int)
{
return (bool)(p_reg->INTENSET & qspi_int);
}
__STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg)
{
p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Enabled << QSPI_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg)
{
p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Disabled << QSPI_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg, const nrf_qspi_pins_t * p_pins)
{
p_reg->PSEL.SCK = NRF_QSPI_PIN_VAL(p_pins->sck_pin);
p_reg->PSEL.CSN = NRF_QSPI_PIN_VAL(p_pins->csn_pin);
p_reg->PSEL.IO0 = NRF_QSPI_PIN_VAL(p_pins->io0_pin);
p_reg->PSEL.IO1 = NRF_QSPI_PIN_VAL(p_pins->io1_pin);
p_reg->PSEL.IO2 = NRF_QSPI_PIN_VAL(p_pins->io2_pin);
p_reg->PSEL.IO3 = NRF_QSPI_PIN_VAL(p_pins->io3_pin);
}
__STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,
const nrf_qspi_prot_conf_t * p_config)
{
uint32_t config = p_config->readoc;
config |= ((uint32_t)p_config->writeoc) << QSPI_IFCONFIG0_WRITEOC_Pos;
config |= ((uint32_t)p_config->addrmode) << QSPI_IFCONFIG0_ADDRMODE_Pos;
config |= (p_config->dpmconfig ? 1U : 0U ) << QSPI_IFCONFIG0_DPMENABLE_Pos;
p_reg->IFCONFIG0 = config;
}
__STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,
const nrf_qspi_phy_conf_t * p_config)
{
// IFCONFIG1 mask for reserved fields in the register.
uint32_t config = p_reg->IFCONFIG1 & 0x00FFFF00;
config |= p_config->sck_delay;
config |= (p_config->dpmen ? 1U : 0U) << QSPI_IFCONFIG1_DPMEN_Pos;
config |= ((uint32_t)(p_config->spi_mode)) << QSPI_IFCONFIG1_SPIMODE_Pos;
config |= ((uint32_t)(p_config->sck_freq)) << QSPI_IFCONFIG1_SCKFREQ_Pos;
p_reg->IFCONFIG1 = config;
}
__STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg,
const nrf_qspi_addrconfig_conf_t * p_config)
{
uint32_t config = p_config->opcode;
config |= ((uint32_t)p_config->byte0) << QSPI_ADDRCONF_BYTE0_Pos;
config |= ((uint32_t)p_config->byte1) << QSPI_ADDRCONF_BYTE1_Pos;
config |= ((uint32_t)(p_config->mode)) << QSPI_ADDRCONF_MODE_Pos;
config |= (p_config->wipwait ? 1U : 0U) << QSPI_ADDRCONF_WIPWAIT_Pos;
config |= (p_config->wren ? 1U : 0U) << QSPI_ADDRCONF_WREN_Pos;
p_reg->ADDRCONF = config;
}
__STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,
void const * p_buffer,
uint32_t length,
uint32_t dest_addr)
{
p_reg->WRITE.DST = dest_addr;
p_reg->WRITE.SRC = (uint32_t) p_buffer;
p_reg->WRITE.CNT = length;
}
__STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,
void * p_buffer,
uint32_t length,
uint32_t src_addr)
{
p_reg->READ.SRC = src_addr;
p_reg->READ.DST = (uint32_t) p_buffer;
p_reg->READ.CNT = length;
}
__STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg,
uint32_t erase_addr,
nrf_qspi_erase_len_t len)
{
p_reg->ERASE.PTR = erase_addr;
p_reg->ERASE.LEN = len;
}
__STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg)
{
return p_reg->STATUS;
}
__STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg)
{
return (uint8_t)(p_reg->STATUS & QSPI_STATUS_SREG_Msk) >> QSPI_STATUS_SREG_Pos;
}
__STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg)
{
return ((p_reg->STATUS & QSPI_STATUS_READY_Msk) >>
QSPI_STATUS_READY_Pos) == QSPI_STATUS_READY_BUSY;
}
__STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg,
nrf_qspi_cinstr_len_t length,
void const * p_tx_data)
{
uint32_t reg = 0;
uint8_t const *p_tx_data_8 = (uint8_t const *) p_tx_data;
// Load custom instruction.
switch (length)
{
case NRF_QSPI_CINSTR_LEN_9B:
reg |= ((uint32_t)p_tx_data_8[7]) << QSPI_CINSTRDAT1_BYTE7_Pos;
/* fall-through */
case NRF_QSPI_CINSTR_LEN_8B:
reg |= ((uint32_t)p_tx_data_8[6]) << QSPI_CINSTRDAT1_BYTE6_Pos;
/* fall-through */
case NRF_QSPI_CINSTR_LEN_7B:
reg |= ((uint32_t)p_tx_data_8[5]) << QSPI_CINSTRDAT1_BYTE5_Pos;
/* fall-through */
case NRF_QSPI_CINSTR_LEN_6B:
reg |= ((uint32_t)p_tx_data_8[4]);
p_reg->CINSTRDAT1 = reg;
reg = 0;
/* fall-through */
case NRF_QSPI_CINSTR_LEN_5B:
reg |= ((uint32_t)p_tx_data_8[3]) << QSPI_CINSTRDAT0_BYTE3_Pos;
/* fall-through */
case NRF_QSPI_CINSTR_LEN_4B:
reg |= ((uint32_t)p_tx_data_8[2]) << QSPI_CINSTRDAT0_BYTE2_Pos;
/* fall-through */
case NRF_QSPI_CINSTR_LEN_3B:
reg |= ((uint32_t)p_tx_data_8[1]) << QSPI_CINSTRDAT0_BYTE1_Pos;
/* fall-through */
case NRF_QSPI_CINSTR_LEN_2B:
reg |= ((uint32_t)p_tx_data_8[0]);
p_reg->CINSTRDAT0 = reg;
/* fall-through */
case NRF_QSPI_CINSTR_LEN_1B:
/* Send only opcode. Case to avoid compiler warnings. */
break;
default:
break;
}
}
__STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,
nrf_qspi_cinstr_len_t length,
void * p_rx_data)
{
uint8_t *p_rx_data_8 = (uint8_t *) p_rx_data;
uint32_t reg = p_reg->CINSTRDAT1;
switch (length)
{
case NRF_QSPI_CINSTR_LEN_9B:
p_rx_data_8[7] = (uint8_t)(reg >> QSPI_CINSTRDAT1_BYTE7_Pos);
/* fall-through */
case NRF_QSPI_CINSTR_LEN_8B:
p_rx_data_8[6] = (uint8_t)(reg >> QSPI_CINSTRDAT1_BYTE6_Pos);
/* fall-through */
case NRF_QSPI_CINSTR_LEN_7B:
p_rx_data_8[5] = (uint8_t)(reg >> QSPI_CINSTRDAT1_BYTE5_Pos);
/* fall-through */
case NRF_QSPI_CINSTR_LEN_6B:
p_rx_data_8[4] = (uint8_t)(reg);
/* fall-through */
default:
break;
}
reg = p_reg->CINSTRDAT0;
switch (length)
{
case NRF_QSPI_CINSTR_LEN_5B:
p_rx_data_8[3] = (uint8_t)(reg >> QSPI_CINSTRDAT0_BYTE3_Pos);
/* fall-through */
case NRF_QSPI_CINSTR_LEN_4B:
p_rx_data_8[2] = (uint8_t)(reg >> QSPI_CINSTRDAT0_BYTE2_Pos);
/* fall-through */
case NRF_QSPI_CINSTR_LEN_3B:
p_rx_data_8[1] = (uint8_t)(reg >> QSPI_CINSTRDAT0_BYTE1_Pos);
/* fall-through */
case NRF_QSPI_CINSTR_LEN_2B:
p_rx_data_8[0] = (uint8_t)(reg);
/* fall-through */
case NRF_QSPI_CINSTR_LEN_1B:
/* Send only opcode. Case to avoid compiler warnings. */
break;
default:
break;
}
}
__STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg,
const nrf_qspi_cinstr_conf_t * p_config)
{
p_reg->CINSTRCONF = (((uint32_t)p_config->opcode << QSPI_CINSTRCONF_OPCODE_Pos) |
((uint32_t)p_config->length << QSPI_CINSTRCONF_LENGTH_Pos) |
((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) |
((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) |
((uint32_t)p_config->wipwait << QSPI_CINSTRCONF_WIPWAIT_Pos) |
((uint32_t)p_config->wren << QSPI_CINSTRCONF_WREN_Pos));
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
#ifdef __cplusplus
}
#endif
#endif // NRF_QSPI_H__
/** @} */

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/* Copyright (c) 2016 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include "sdk_config.h"
#if QSPI_ENABLED
#include "nrf_drv_qspi.h"
#include "nrf_drv_common.h"
#include "nrf_gpio.h"
#include "nrf_assert.h"
/**
* @brief Command byte used to read status register.
*
*/
#define QSPI_STD_CMD_RDSR 0x05
/**
* @brief Byte used to mask status register and retrieve the write-in-progess bit.
*
*/
#define QSPI_MEM_STATUSREG_WIP_Pos 0x01
#define QSPI_WAIT_READY() do { \
while (!nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY)); \
} while(0)
/**
* @brief Control block - driver instance local data.
*
*/
typedef struct
{
nrf_drv_qspi_handler_t handler; /**< Handler. */
nrf_drv_state_t state; /**< Driver state. */
volatile bool interrupt_driven; /**< Information if the current operation is performed and is interrupt-driven. */
void * p_context; /**< Driver context used in interrupt. */
} qspi_control_block_t;
static qspi_control_block_t m_cb;
static ret_code_t qspi_task_perform(nrf_qspi_task_t task)
{
// Wait for peripheral
if (m_cb.interrupt_driven)
{
return NRF_ERROR_BUSY;
}
nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
if (m_cb.handler)
{
m_cb.interrupt_driven = true;
nrf_qspi_int_enable(NRF_QSPI, NRF_QSPI_INT_READY_MASK);
}
nrf_qspi_task_trigger(NRF_QSPI, task);
if (m_cb.handler == NULL)
{
QSPI_WAIT_READY();
}
return NRF_SUCCESS;
}
static bool qspi_pins_configure(nrf_qspi_pins_t const * p_config)
{
// Check if the user set meaningful values to struct fields. If not, return false.
if ((p_config->sck_pin == NRF_QSPI_PIN_NOT_CONNECTED) ||
(p_config->csn_pin == NRF_QSPI_PIN_NOT_CONNECTED) ||
(p_config->io0_pin == NRF_QSPI_PIN_NOT_CONNECTED) ||
(p_config->io1_pin == NRF_QSPI_PIN_NOT_CONNECTED))
{
return false;
}
nrf_qspi_pins_set(NRF_QSPI, p_config);
return true;
}
ret_code_t nrf_drv_qspi_init(nrf_drv_qspi_config_t const * p_config,
nrf_drv_qspi_handler_t handler,
void * p_context)
{
if (m_cb.state != NRF_DRV_STATE_UNINITIALIZED)
{
return NRF_ERROR_INVALID_STATE;
}
if (!qspi_pins_configure(&p_config->pins))
{
return NRF_ERROR_INVALID_PARAM;
}
nrf_qspi_ifconfig0_set(NRF_QSPI, &p_config->prot_if);
nrf_qspi_ifconfig1_set(NRF_QSPI, &p_config->phy_if);
m_cb.interrupt_driven = false;
m_cb.handler = handler;
m_cb.p_context = p_context;
/* QSPI interrupt is disabled because the device should be enabled in polling mode (wait for activate
task event ready)*/
nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK);
if (handler)
{
nrf_drv_common_irq_enable(QSPI_IRQn, p_config->irq_priority);
}
m_cb.state = NRF_DRV_STATE_INITIALIZED;
nrf_qspi_enable(NRF_QSPI);
nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
nrf_qspi_task_trigger(NRF_QSPI, NRF_QSPI_TASK_ACTIVATE);
// Waiting for the peripheral to activate
QSPI_WAIT_READY();
return NRF_SUCCESS;
}
ret_code_t nrf_drv_qspi_cinstr_xfer(nrf_qspi_cinstr_conf_t const * p_config,
void const * p_tx_buffer,
void * p_rx_buffer)
{
ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
if (m_cb.interrupt_driven)
{
return NRF_ERROR_BUSY;
}
nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
/* In some cases, only opcode should be sent. To prevent execution, set function code is
* surrounded by an if.
*/
if (p_tx_buffer)
{
nrf_qspi_cinstrdata_set(NRF_QSPI, p_config->length, p_tx_buffer);
}
nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK);
nrf_qspi_cinstr_transfer_start(NRF_QSPI, p_config);
QSPI_WAIT_READY();
nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
nrf_qspi_int_enable(NRF_QSPI, NRF_QSPI_INT_READY_MASK);
if (p_rx_buffer)
{
nrf_qspi_cinstrdata_get(NRF_QSPI, p_config->length, p_rx_buffer);
}
return NRF_SUCCESS;
}
ret_code_t nrf_drv_qspi_cinstr_quick_send(uint8_t opcode,
nrf_qspi_cinstr_len_t length,
void const * p_tx_buffer)
{
nrf_qspi_cinstr_conf_t config = NRF_DRV_QSPI_DEFAULT_CINSTR(opcode, length);
return nrf_drv_qspi_cinstr_xfer(&config, p_tx_buffer, NULL);
}
ret_code_t nrf_drv_qspi_mem_busy_check(void)
{
ret_code_t ret_code;
uint8_t status_value = 0;
nrf_qspi_cinstr_conf_t config = NRF_DRV_QSPI_DEFAULT_CINSTR(QSPI_STD_CMD_RDSR,
NRF_QSPI_CINSTR_LEN_2B);
ret_code = nrf_drv_qspi_cinstr_xfer(&config, &status_value, &status_value);
if (ret_code != NRF_SUCCESS)
{
return ret_code;
}
if ((status_value & QSPI_MEM_STATUSREG_WIP_Pos) != 0x00)
{
return NRF_ERROR_BUSY;
}
return NRF_SUCCESS;
}
void nrf_drv_qspi_uninit(void)
{
ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK);
nrf_qspi_disable(NRF_QSPI);
nrf_drv_common_irq_disable(QSPI_IRQn);
nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
m_cb.state = NRF_DRV_STATE_UNINITIALIZED;
}
ret_code_t nrf_drv_qspi_write(void const * p_tx_buffer,
size_t tx_buffer_length,
uint32_t dst_address)
{
ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
ASSERT(p_tx_buffer != NULL);
if (!nrf_drv_is_in_RAM(p_tx_buffer))
{
return NRF_ERROR_INVALID_ADDR;
}
nrf_qspi_write_buffer_set(NRF_QSPI, p_tx_buffer, tx_buffer_length, dst_address);
return qspi_task_perform(NRF_QSPI_TASK_WRITESTART);
}
ret_code_t nrf_drv_qspi_read(void * p_rx_buffer,
size_t rx_buffer_length,
uint32_t src_address)
{
ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
ASSERT(p_rx_buffer != NULL);
if (!nrf_drv_is_in_RAM(p_rx_buffer))
{
return NRF_ERROR_INVALID_ADDR;
}
nrf_qspi_read_buffer_set(NRF_QSPI, p_rx_buffer, rx_buffer_length, src_address);
return qspi_task_perform(NRF_QSPI_TASK_READSTART);
}
ret_code_t nrf_drv_qspi_erase(nrf_qspi_erase_len_t length,
uint32_t start_address)
{
ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
nrf_qspi_erase_ptr_set(NRF_QSPI, start_address, length);
return qspi_task_perform(NRF_QSPI_TASK_ERASESTART);
}
ret_code_t nrf_drv_qspi_chip_erase(void)
{
return nrf_drv_qspi_erase(NRF_QSPI_ERASE_LEN_ALL, 0);
}
void QSPI_IRQHandler(void)
{
// Catch Event ready interrupts
if (nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY))
{
m_cb.interrupt_driven = false;
nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
m_cb.handler(NRF_DRV_QSPI_EVENT_DONE, m_cb.p_context);
}
}
#endif // QSPI_ENABLED

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/* Copyright (c) 2016 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/**@file
* @addtogroup nrf_qspi QSPI HAL and driver
* @ingroup nrf_drivers
* @brief @tagAPI52840 Quad serial peripheral interface (QSPI) APIs.
*
* @defgroup nrf_drv_qspi QSPI driver
* @{
* @ingroup nrf_qspi
* @brief @tagAPI52840 Quad serial peripheral interface (QSPI) driver.
*/
#ifndef NRF_DRV_QSPI_H__
#define NRF_DRV_QSPI_H__
#include "nordic_common.h"
#include "sdk_config.h"
#include "nrf_qspi.h"
#include "sdk_errors.h"
#include "boards.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief QSPI driver instance configuration structure.
*/
typedef struct
{
nrf_qspi_pins_t pins; /**< Pins configuration structure. */
nrf_qspi_prot_conf_t prot_if; /**< Protocol layer interface configuration structure. */
nrf_qspi_phy_conf_t phy_if; /**< Physical layer interface configuration structure. */
uint8_t irq_priority; /**< Interrupt priority. */
} nrf_drv_qspi_config_t;
#if QSPI_PIN_SCK == NRF_QSPI_PIN_NOT_CONNECTED
#undef QSPI_PIN_SCK
#define QSPI_PIN_SCK BSP_QSPI_SCK_PIN
#endif
#if QSPI_PIN_CSN == NRF_QSPI_PIN_NOT_CONNECTED
#undef QSPI_PIN_CSN
#define QSPI_PIN_CSN BSP_QSPI_CSN_PIN
#endif
#if QSPI_PIN_IO0 == NRF_QSPI_PIN_NOT_CONNECTED
#undef QSPI_PIN_IO0
#define QSPI_PIN_IO0 BSP_QSPI_IO0_PIN
#endif
#if QSPI_PIN_IO1 == NRF_QSPI_PIN_NOT_CONNECTED
#undef QSPI_PIN_IO1
#define QSPI_PIN_IO1 BSP_QSPI_IO1_PIN
#endif
#if QSPI_PIN_IO2 == NRF_QSPI_PIN_NOT_CONNECTED
#undef QSPI_PIN_IO2
#define QSPI_PIN_IO2 BSP_QSPI_IO2_PIN
#endif
#if QSPI_PIN_IO3 == NRF_QSPI_PIN_NOT_CONNECTED
#undef QSPI_PIN_IO3
#define QSPI_PIN_IO3 BSP_QSPI_IO3_PIN
#endif
/**
* @brief QSPI instance default configuration.
*/
#define NRF_DRV_QSPI_DEFAULT_CONFIG \
{ \
.pins = { \
.sck_pin = QSPI_PIN_SCK, \
.csn_pin = QSPI_PIN_CSN, \
.io0_pin = QSPI_PIN_IO0, \
.io1_pin = QSPI_PIN_IO1, \
.io2_pin = QSPI_PIN_IO2, \
.io3_pin = QSPI_PIN_IO3, \
}, \
.irq_priority = (uint8_t)QSPI_CONFIG_IRQ_PRIORITY, \
.prot_if = { \
.readoc = (nrf_qspi_readoc_t) QSPI_CONFIG_READOC, \
.writeoc = (nrf_qspi_writeoc_t) QSPI_CONFIG_WRITEOC, \
.addrmode = (nrf_qspi_addrmode_t) QSPI_CONFIG_ADDRMODE, \
.dpmconfig = false, \
}, \
.phy_if = { \
.sck_freq = (nrf_qspi_frequency_t) QSPI_CONFIG_FREQUENCY, \
.sck_delay = (uint8_t) QSPI_CONFIG_SCK_DELAY, \
.spi_mode = (nrf_qspi_spi_mode_t) QSPI_CONFIG_MODE, \
.dpmen = false \
} \
}
/**
* @brief QSPI custom instruction helper with default configuration.
*/
#define NRF_DRV_QSPI_DEFAULT_CINSTR(opc, len) \
{ \
.opcode = (opc), \
.length = (len), \
.io2_level = false, \
.io3_level = false, \
.wipwait = false, \
.wren = false \
}
/**
* @brief QSPI master driver event types, passed to the handler routine provided
* during initialization.
*/
typedef enum
{
NRF_DRV_QSPI_EVENT_DONE, /**< Transfer done. */
} nrf_drv_qspi_evt_t;
/**
* @brief QSPI driver event handler type.
*/
typedef void (*nrf_drv_qspi_handler_t)(nrf_drv_qspi_evt_t event, void * p_context);
/**
* @brief Function for initializing the QSPI driver instance.
*
* @param[in] p_config Pointer to the structure with the initial configuration.
* @param[in] handler Event handler provided by the user. If NULL, transfers
* will be performed in blocking mode.
* @param[in] p_context Pointer to context. Use in interrupt handler.
*
*
* @retval NRF_SUCCESS If initialization was successful.
* @retval NRF_ERROR_INVALID_STATE If the driver was already initialized.
* @retval NRF_ERROR_INVALID_PARAM If the pin configuration was incorrect.
*/
ret_code_t nrf_drv_qspi_init(nrf_drv_qspi_config_t const * p_config,
nrf_drv_qspi_handler_t handler,
void * p_context);
/**
* @brief Function for uninitializing the QSPI driver instance.
*/
void nrf_drv_qspi_uninit(void);
/**
* @brief Function for reading data from QSPI memory.
*
* Write, read, and erase operations check memory device busy state before starting the operation.
* If the memory is busy, the resulting action depends on the mode in which the read operation is used:
* - blocking mode (without handler) - a delay occurs until the last operation still runs and
* until operation data is still being read.
* - interrupt mode (with handler) - event emission occurs after the last operation
* and reading of data are finished.
*
* @param[out] p_rx_buffer Pointer to the receive buffer.
* @param[in] rx_buffer_length Size of the data to read.
* @param[in] src_address Address in memory to read from.
*
* @retval NRF_SUCCESS If the operation was successful (blocking mode) or operation
* was commissioned (handler mode).
* @retval NRF_ERROR_BUSY If the driver currently handles another operation.
* @retval NRF_ERROR_INVALID_ADDR If the provided buffer is not placed in the Data RAM region.
*/
ret_code_t nrf_drv_qspi_read(void * p_rx_buffer,
size_t rx_buffer_length,
uint32_t src_address);
/**
* @brief Function for writing data to QSPI memory.
*
* Write, read, and erase operations check memory device busy state before starting the operation.
* If the memory is busy, the resulting action depends on the mode in which the write operation is used:
* - blocking mode (without handler) - a delay occurs until the last operation still runs and
* until operation data is still being sent.
* - interrupt mode (with handler) - event emission occurs after the last operation
* and sending of operation data are finished.
* To manually control operation execution in the memory device, use @ref nrf_drv_qspi_mem_busy_check
* after executing the write function.
* Remember that an incoming event signalizes only that data was sent to the memory device and the periheral
* before the write operation checked if memory was busy.
*
* @param[in] p_tx_buffer Pointer to the writing buffer.
* @param[in] tx_buffer_length Size of the data to write.
* @param[in] dst_address Address in memory to write to.
*
* @retval NRF_SUCCESS If the operation was successful (blocking mode) or operation
* was commissioned (handler mode).
* @retval NRF_ERROR_BUSY If the driver currently handles other operation.
* @retval NRF_ERROR_INVALID_ADDR If the provided buffer is not placed in the Data RAM region.
*/
ret_code_t nrf_drv_qspi_write(void const * p_tx_buffer,
size_t tx_buffer_length,
uint32_t dst_address);
/**
* @brief Function for starting erasing of one memory block - 4KB, 64KB, or the whole chip.
*
* Write, read, and erase operations check memory device busy state before starting the operation.
* If the memory is busy, the resulting action depends on the mode in which the erase operation is used:
* - blocking mode (without handler) - a delay occurs until the last operation still runs and
* until operation data is still being sent.
* - interrupt mode (with handler) - event emission occurs after the last operation
* and sending of operation data are finished.
* To manually control operation execution in the memory device, use @ref nrf_drv_qspi_mem_busy_check
* after executing the erase function.
* Remember that an incoming event signalizes only that data was sent to the memory device and the periheral
* before the erase operation checked if memory was busy.
*
* @param[in] length Size of data to erase. See @ref nrf_qspi_erase_len_t.
* @param[in] start_address Memory address to start erasing. If chip erase is performed, address
* field is ommited.
*
* @retval NRF_SUCCESS If the operation was successful (blocking mode) or operation
* was commissioned (handler mode).
* @retval NRF_ERROR_BUSY If the driver currently handles another operation.
*/
ret_code_t nrf_drv_qspi_erase(nrf_qspi_erase_len_t length,
uint32_t start_address);
/**
* @brief Function for starting an erase operation of the whole chip.
*
* @retval NRF_SUCCESS If the operation was successful (blocking mode) or operation
* was commissioned (handler mode).
* @retval NRF_ERROR_BUSY If the driver currently handles another operation.
*/
ret_code_t nrf_drv_qspi_chip_erase(void);
/**
* @brief Function for getting the current driver status and status byte of memory device with
* testing WIP (write in progress) bit.
*
* @retval NRF_SUCCESS If the driver and memory are ready to handle a new operation.
* @retval NRF_ERROR_BUSY If the driver or memory currently handle another operation.
*/
ret_code_t nrf_drv_qspi_mem_busy_check(void);
/**
* @brief Function for sending operation code, sending data, and receiving data from the memory device.
*
* Use this function to transfer configuration data to memory and to receive data from memory.
* Pointers can be addresses from flash memory.
* This function is a synchronous function and should be used only if necessary.
* See more: @ref hardware_driver_qspi.
*
* @param[in] p_config Pointer to the structure with opcode and transfer configuration.
* @param[in] p_tx_buffer Pointer to the array with data to send. Can be NULL if only opcode is transmitted.
* @param[out] p_rx_buffer Pointer to the array for data to receive. Can be NULL if there is nothing to receive.
*
* @retval NRF_SUCCESS If the operation was successful.
* @retval NRF_ERROR_BUSY If the driver currently handles other operation.
*/
ret_code_t nrf_drv_qspi_cinstr_xfer(nrf_qspi_cinstr_conf_t const * p_config,
void const * p_tx_buffer,
void * p_rx_buffer);
/**
* @brief Function for sending operation code and data to the memory device with simpler configuration.
*
* Use this function to transfer configuration data to memory and to receive data from memory.
* This function is a synchronous function and should be used only if necessary.
*
* @param[in] opcode Operation code. Sending first.
* @param[in] length Length of the data to send and opcode. See @ref nrf_qspi_cinstr_len_t.
* @param[in] p_tx_buffer Pointer to input data array.
*
* @retval NRF_SUCCESS If the operation was successful.
* @retval NRF_ERROR_BUSY If the driver currently handles another operation.
*/
ret_code_t nrf_drv_qspi_cinstr_quick_send(uint8_t opcode,
nrf_qspi_cinstr_len_t length,
void const * p_tx_buffer);
#ifdef __cplusplus
}
#endif
#endif // NRF_DRV_QSPI_H__
/** @} */

11
targets/TARGET_NORDIC/TARGET_NRF5/objects.h
View File

@ -89,6 +89,17 @@ struct trng_s {
uint32_t placeholder;
};
#if DEVICE_QSPI
// #include "nrf_drv_qspi.h"
struct qspi_s {
uint32_t placeholder;
// nrf_drv_qspi_config_t config;
};
#endif
#include "gpio_object.h"
#ifdef __cplusplus

214
targets/TARGET_NORDIC/TARGET_NRF5/qspi_api.c Normal file
View File

@ -0,0 +1,214 @@
/*
* Copyright (c) 2017 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include "qspi_api.h"
#if DEVICE_QSPI
#include "nrf_drv_common.h"
#include "nrf_drv_qspi.h"
/*
TODO
- config inside obj - nordic headers have some problems with inclusion
- free - is it really empty, nothing to do there?
- prepare command - support more protocols that nordic can do (now limited)
- nordic does not support
- alt
- dummy cycles
*/
#define MBED_HAL_QSPI_HZ_TO_CONFIG(hz) ((32000000/(hz))-1)
#define MBED_HAL_QSPI_MAX_FREQ 32000000UL
static nrf_drv_qspi_config_t config;
qspi_status_t qspi_prepare_command(qspi_t *obj, const qspi_command_t *command, bool write)
{
// we need to remap to command-address-data - x_x_x
// most commmon are 1-1-1, 1-1-4, 1-4-4
// 1-1-1
if (command->instruction.bus_width == QSPI_CFG_BUS_SINGLE &&
command->address.bus_width == QSPI_CFG_BUS_SINGLE &&
command->data.bus_width == QSPI_CFG_BUS_SINGLE) {
if (write) {
config.prot_if.writeoc = NRF_QSPI_WRITEOC_PP;
} else {
config.prot_if.readoc = NRF_QSPI_READOC_FASTREAD;
}
// 1-1-4
} else if (command->instruction.bus_width == QSPI_CFG_BUS_SINGLE &&
command->address.bus_width == QSPI_CFG_BUS_SINGLE &&
command->data.bus_width == QSPI_CFG_BUS_QUAD) {
// 1_1_4
if (write) {
config.prot_if.writeoc = QSPI_IFCONFIG0_WRITEOC_PP4O;
} else {
config.prot_if.readoc = NRF_QSPI_READOC_READ4O;
}
// 1-4-4
} else if (command->instruction.bus_width == QSPI_CFG_BUS_SINGLE &&
command->address.bus_width == QSPI_CFG_BUS_QUAD &&
command->data.bus_width == QSPI_CFG_BUS_QUAD) {
// 1_4_4
if (write) {
config.prot_if.writeoc = QSPI_IFCONFIG0_WRITEOC_PP4IO;
} else {
config.prot_if.readoc = NRF_QSPI_READOC_READ4IO;
}
}
qspi_status_t ret = QSPI_STATUS_OK;
// supporting only 24 or 32 bit address
if (command->address.size == QSPI_CFG_ADDR_SIZE_24) {
config.prot_if.addrmode = NRF_QSPI_ADDRMODE_24BIT;
} else if (command->address.size == QSPI_CFG_ADDR_SIZE_32) {
config.prot_if.addrmode = QSPI_CFG_ADDR_SIZE_32;
} else {
ret = QSPI_STATUS_INVALID_PARAMETER;
}
return ret;
}
qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, uint32_t hz, uint8_t mode)
{
(void)(obj);
if (hz > MBED_HAL_QSPI_MAX_FREQ) {
return QSPI_STATUS_INVALID_PARAMETER;
}
// memset(config, 0, sizeof(config));
config.pins.sck_pin = (uint32_t)sclk;
config.pins.csn_pin = (uint32_t)ssel;
config.pins.io0_pin = (uint32_t)io0;
config.pins.io1_pin = (uint32_t)io1;
config.pins.io2_pin = (uint32_t)io2;
config.pins.io3_pin = (uint32_t)io3;
config.irq_priority = SPI_DEFAULT_CONFIG_IRQ_PRIORITY;
config.phy_if.sck_freq = MBED_HAL_QSPI_HZ_TO_CONFIG(hz),
config.phy_if.sck_delay = 0x05,
config.phy_if.dpmen = false;
config.phy_if.spi_mode = mode == 0 ? NRF_QSPI_MODE_0 : NRF_QSPI_MODE_1;
nrf_drv_qspi_init(&config, NULL , NULL);
return 0;
}
qspi_status_t qspi_free(qspi_t *obj)
{
(void)(obj);
// possibly here uninit from SDK driver
return QSPI_STATUS_OK;
}
qspi_status_t qspi_frequency(qspi_t *obj, int hz)
{
config.phy_if.sck_freq = MBED_HAL_QSPI_HZ_TO_CONFIG(hz);
// use sync version, no handler
ret_code_t ret = nrf_drv_qspi_init(&config, NULL , NULL);
if (ret == NRF_SUCCESS ) {
return QSPI_STATUS_OK;
} else if (ret == NRF_ERROR_INVALID_PARAM) {
return QSPI_STATUS_INVALID_PARAMETER;
} else {
return QSPI_STATUS_ERROR;
}
}
qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void *data, size_t *length)
{
qspi_status_t status = qspi_prepare_command(obj, command, true);
if (status != QSPI_STATUS_OK) {
return status;
}
// write here does not return how much it transfered, we return transfered all
ret_code_t ret = nrf_drv_qspi_write(data, *length, command->address.value);
if (ret == NRF_SUCCESS ) {
return QSPI_STATUS_OK;
} else {
return QSPI_STATUS_ERROR;
}
}
qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, size_t *length)
{
qspi_status_t status = qspi_prepare_command(obj, command, false);
if (status != QSPI_STATUS_OK) {
return status;
}
ret_code_t ret = nrf_drv_qspi_read(data, *length, command->address.value);
if (ret == NRF_SUCCESS ) {
return QSPI_STATUS_OK;
} else {
return QSPI_STATUS_ERROR;
}
}
// they provide 2 functions write or nrf_drv_qspi_cinstr_xfer
// nrf_drv_qspi_cinstr_xfer seems like it accepts simplified config that is very simplified
// and might not be useful for us.
// write on other hand, needs to write some data (errors if buffer is NULL!)
qspi_status_t qspi_write_command(qspi_t *obj, const qspi_command_t *command)
{
// use simplified API, as we are sending only instruction here
nrf_qspi_cinstr_conf_t config;
config.length = NRF_QSPI_CINSTR_LEN_1B; // no data
config.opcode = command->instruction.value;
config.io2_level = false;
config.io3_level = false;
config.wipwait = false;
config.wren = false;
// no data phase, send only config
ret_code_t ret = nrf_drv_qspi_cinstr_xfer(&config, NULL, NULL);
if (ret == NRF_SUCCESS ) {
return QSPI_STATUS_OK;
} else {
return QSPI_STATUS_ERROR;
}
}
#endif
/** @}*/

2
targets/targets.json
View File

@ -3585,7 +3585,7 @@
"supported_form_factors": ["ARDUINO"],
"inherits": ["MCU_NRF52840"],
"macros_add": ["BOARD_PCA10056", "CONFIG_GPIO_AS_PINRESET", "SWI_DISABLE0", "NRF52_ERRATA_20"],
"device_has_add": ["FLASH", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "TRNG"],
"device_has_add": ["FLASH", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "TRNG", "QSPI"],
"release_versions": ["2", "5"],
"device_name": "nRF52840_xxAA",
"bootloader_supported": true