From e8614b341b947fbc80990b353b0cd397602d193e Mon Sep 17 00:00:00 2001 From: Harrison Mutai Date: Thu, 10 Dec 2020 10:11:10 +0000 Subject: [PATCH] CMake: Port Renesas targets to CMake Add targets subdirectory to high level CMake configuration file and create new configurations for MCUs and individual targets. Change the interpreter in the ARM scatter file to armclang, which is required for CMake. Remove private and public interfaces in emac target configuration. Ensure that all targets build on the arm gcc compiler and arm compiler. --- targets/CMakeLists.txt | 2 + targets/TARGET_RENESAS/CMakeLists.txt | 13 ++++++ .../TARGET_RZ_A1XX/CMakeLists.txt | 37 ++++++++++++++++ .../TARGET_GR_LYCHEE/CMakeLists.txt | 42 +++++++++++++++++++ .../device/TOOLCHAIN_ARM_STD/MBRZA1LU.sct | 2 +- .../TARGET_RZ_A1H/CMakeLists.txt | 40 ++++++++++++++++++ .../device/TOOLCHAIN_ARM_STD/MBRZA1H.sct | 2 +- .../TARGET_RZ_A2XX/CMakeLists.txt | 40 ++++++++++++++++++ .../TARGET_GR_MANGO/CMakeLists.txt | 42 +++++++++++++++++++ .../device/TOOLCHAIN_ARM_STD/MBRZA1H.sct | 2 +- 10 files changed, 219 insertions(+), 3 deletions(-) create mode 100644 targets/TARGET_RENESAS/CMakeLists.txt create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/CMakeLists.txt create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/CMakeLists.txt create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/CMakeLists.txt create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A2XX/CMakeLists.txt create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/CMakeLists.txt diff --git a/targets/CMakeLists.txt b/targets/CMakeLists.txt index 9a95cc43a3..f6442d79e7 100644 --- a/targets/CMakeLists.txt +++ b/targets/CMakeLists.txt @@ -19,6 +19,8 @@ elseif("NUVOTON" IN_LIST MBED_TARGET_LABELS) add_subdirectory(TARGET_NUVOTON) elseif("NXP" IN_LIST MBED_TARGET_LABELS) add_subdirectory(TARGET_NXP) +elseif("RENESAS" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_RENESAS) elseif("Samsung" IN_LIST MBED_TARGET_LABELS) add_subdirectory(TARGET_Samsung) elseif("Silicon_Labs" IN_LIST MBED_TARGET_LABELS) diff --git a/targets/TARGET_RENESAS/CMakeLists.txt b/targets/TARGET_RENESAS/CMakeLists.txt new file mode 100644 index 0000000000..6a1854ad4b --- /dev/null +++ b/targets/TARGET_RENESAS/CMakeLists.txt @@ -0,0 +1,13 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if ("RZ_A1XX" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_RZ_A1XX) +elseif("RZ_A2XX" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_RZ_A2XX) +endif() + +target_include_directories(mbed-core + INTERFACE + . +) diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/CMakeLists.txt b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/CMakeLists.txt new file mode 100644 index 0000000000..1e4838420d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/CMakeLists.txt @@ -0,0 +1,37 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if ("GR_LYCHEE" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_GR_LYCHEE) +elseif("RZ_A1H" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_RZ_A1H) +endif() + +target_include_directories(mbed-core + INTERFACE + . + common +) + +target_sources(mbed-core + INTERFACE + analogin_api.c + can_api.c + flash_api.c + gpio_api.c + gpio_irq_api.c + i2c_api.c + lp_ticker.c + mtu2.c + pinmap.c + port_api.c + pwmout_api.c + rtc_api.c + serial_api.c + sleep.c + spi_api.c + trng_api.c + us_ticker.c + + common/rza_io_regrw.c +) diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/CMakeLists.txt b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/CMakeLists.txt new file mode 100644 index 0000000000..76d8377e6f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/CMakeLists.txt @@ -0,0 +1,42 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(LINKER_FILE device/TOOLCHAIN_ARM_STD/MBRZA1LU.sct) + set(STARTUP_FILE device/TOOLCHAIN_ARM_STD/startup_RZ_A1LU.S) + set(WEAK_HANDLER_FILE device/TOOLCHAIN_ARM_STD/weak_handler.S) +elseif(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(LINKER_FILE device/TOOLCHAIN_GCC_ARM/RZA1LU.ld) + set(STARTUP_FILE device/TOOLCHAIN_GCC_ARM/startup_RZ1ALU.S) + set(WEAK_HANDLER_FILE device/TOOLCHAIN_GCC_ARM/weak_handler.S) +endif() + +set_property(GLOBAL PROPERTY MBED_TARGET_LINKER_FILE ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + + +target_include_directories(mbed-core + INTERFACE + . + device + device/inc + device/inc/iobitmasks + device/inc/iodefines +) + +target_sources(mbed-core + INTERFACE + trng_api_esp32.cpp + PeripheralPins.c + + device/RZ_A1_Init.c + device/cmsis_nvic.c + device/mbed_sf_boot.c + device/mmu_RZ_A1LU.c + device/nvic_wrapper.c + device/os_tick_ostm.c + device/system_RZ_A1LU.c + + ${STARTUP_FILE} + ${WEAK_HANDLER_FILE} +) + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/MBRZA1LU.sct b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/MBRZA1LU.sct index e4338b0c5f..32bf076539 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/MBRZA1LU.sct +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/MBRZA1LU.sct @@ -1,4 +1,4 @@ -#! armcc -E +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-a9 ;************************************************** ; Copyright (c) 2017 ARM Ltd. All rights reserved. ;************************************************** diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/CMakeLists.txt b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/CMakeLists.txt new file mode 100644 index 0000000000..e05e6ba7f3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/CMakeLists.txt @@ -0,0 +1,40 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(LINKER_FILE device/TOOLCHAIN_ARM_STD/MBRZA1H.sct) + set(STARTUP_FILE device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.S) + set(WEAK_HANDLER_FILE device/TOOLCHAIN_ARM_STD/weak_handler.S) +elseif(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(LINKER_FILE device/TOOLCHAIN_GCC_ARM/RZA1H.ld) + set(STARTUP_FILE device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S) + set(WEAK_HANDLER_FILE device/TOOLCHAIN_GCC_ARM/weak_handler.S) +endif() + +set_property(GLOBAL PROPERTY MBED_TARGET_LINKER_FILE ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + + +target_include_directories(mbed-core + INTERFACE + . + device + device/inc + device/inc/iobitmasks + device/inc/iodefines +) + +target_sources(mbed-core + INTERFACE + PeripheralPins.c + + device/RZ_A1_Init.c + device/cmsis_nvic.c + device/mbed_sf_boot.c + device/mmu_RZ_A1H.c + device/nvic_wrapper.c + device/os_tick_ostm.c + device/system_RZ_A1H.c + + ${STARTUP_FILE} + ${WEAK_HANDLER_FILE} +) diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct index 5cff1881d1..6b22752d77 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct @@ -1,4 +1,4 @@ -#! armcc -E +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-a9 ;************************************************** ; Copyright (c) 2017 ARM Ltd. All rights reserved. ;************************************************** diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/CMakeLists.txt b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/CMakeLists.txt new file mode 100644 index 0000000000..3793a26340 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/CMakeLists.txt @@ -0,0 +1,40 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if ("GR_MANGO" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_GR_MANGO) +endif() + +target_include_directories(mbed-core + INTERFACE + . + common + common/r_cache/inc + common/r_octabus/inc + r_can/inc +) + +target_sources(mbed-core + INTERFACE + analogin_api.c + can_api.c + flash_api.c + gpio_api.c + gpio_irq_api.c + i2c_api.c + pinmap.c + port_api.c + pwmout_api.c + rtc_api.c + serial_api.c + sleep.c + spi_api.c + us_ticker.c + + common/r_cache/src/lld/r_cache_lld_rza2m.c + common/r_octabus/src/lld/r_octabus_lld_rza2m_api.c + common/r_octabus/src/lld/r_octabus_memclk_setup.c + common/rza_io_regrw.c + + r_can/src/r_can_rz.c +) diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/CMakeLists.txt b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/CMakeLists.txt new file mode 100644 index 0000000000..8b040ad326 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/CMakeLists.txt @@ -0,0 +1,42 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(LINKER_FILE device/TOOLCHAIN_ARM_STD/MBRZA1H.sct) + set(STARTUP_FILE device/TOOLCHAIN_ARM_STD/startup_RZ_A2M.S) + set(WEAK_HANDLER_FILE device/TOOLCHAIN_ARM_STD/weak_handler.S) +elseif(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(LINKER_FILE device/TOOLCHAIN_GCC_ARM/RZA2M.ld) + set(STARTUP_FILE device/TOOLCHAIN_GCC_ARM/startup_RZA2M.S) + set(WEAK_HANDLER_FILE device/TOOLCHAIN_GCC_ARM/weak_handler.S) +endif() + +set_property(GLOBAL PROPERTY MBED_TARGET_LINKER_FILE ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + + +target_include_directories(mbed-core + INTERFACE + . + device + device/inc + device/inc/iodefine + device/inc/iodefine/iobitmasks + device/inc/iodefine/iodefines +) + +target_sources(mbed-core + INTERFACE + PeripheralPins.c + + device/RZ_A2_Init.c + device/cmsis_nvic.c + device/mbed_sf_boot.c + device/mmu_RZ_A2M.c + device/nvic_wrapper.c + device/octaram_init.c + device/os_tick_ostm.c + device/system_RZ_A2M.c + + ${STARTUP_FILE} + ${WEAK_HANDLER_FILE} +) diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct index 928bf8fa97..272acea0a8 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct @@ -1,4 +1,4 @@ -#! armcc -E +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-a9 ;************************************************** ; Copyright (c) 2017-2020 ARM Ltd. All rights reserved. ;**************************************************