targets: DISCO_H747I add support of MBED_TICKLESS

targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/h747i_sleep.c

@@ -1,23 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                        opensource.org/licenses/BSD-3-Clause
- *******************************************************************************
- */
-#if DEVICE_SLEEP
-
-/*  Deepsleep temporarily not supported on STM32H747I
- *  wrap it to sleep
- */
-void hal_deepsleep(void)
-{
-    hal_sleep();
-}
-
-#endif

targets/TARGET_STM/lp_ticker.c

@@ -67,6 +67,13 @@
 #define LPTIM_MST_IRQ             LPTIM4_IRQn
 #define LPTIM_MST_RCC             __HAL_RCC_LPTIM4_CLK_ENABLE
 
+#define LPTIM_MST_RCC_CLKAM                  __HAL_RCC_LPTIM4_CLKAM_ENABLE
+
+/* Enable LPTIM wakeup source but only for current core, and disable it for the other core */
+#define LPTIM_MST_EXTI_LPTIM_WAKEUP_CONFIG()  {\
+                                                 HAL_EXTI_D1_EventInputConfig(EXTI_LINE52, EXTI_MODE_IT, ENABLE);\
+                                                 HAL_EXTI_D2_EventInputConfig(EXTI_LINE52, EXTI_MODE_IT, DISABLE);\
+                                               }
 #define LPTIM_MST_RESET_ON        __HAL_RCC_LPTIM4_FORCE_RESET
 #define LPTIM_MST_RESET_OFF       __HAL_RCC_LPTIM4_RELEASE_RESET
 
@@ -85,6 +92,13 @@
 #define LPTIM_MST_IRQ             LPTIM5_IRQn
 #define LPTIM_MST_RCC             __HAL_RCC_LPTIM5_CLK_ENABLE
 
+#define LPTIM_MST_RCC_CLKAM       __HAL_RCC_LPTIM5_CLKAM_ENABLE
+
+/* Enable LPTIM wakeup source but only for current core, and disable it for the other core */
+#define LPTIM_MST_EXTI_LPTIM_WAKEUP_CONFIG()  {\
+                                                 HAL_EXTI_D2_EventInputConfig(EXTI_LINE53, EXTI_MODE_IT, ENABLE);\
+                                                 HAL_EXTI_D1_EventInputConfig(EXTI_LINE53, EXTI_MODE_IT, DISABLE);\
+                                               }
 #define LPTIM_MST_RESET_ON        __HAL_RCC_LPTIM5_FORCE_RESET
 #define LPTIM_MST_RESET_OFF       __HAL_RCC_LPTIM5_RELEASE_RESET
 #else
@@ -209,6 +223,10 @@ void lp_ticker_init(void)
     LPTIM_MST_RESET_ON();
     LPTIM_MST_RESET_OFF();
 #if defined(DUAL_CORE)
+    /* Configure EXTI wakeup and configure autonomous mode */
+    LPTIM_MST_RCC_CLKAM();
+    LPTIM_MST_EXTI_LPTIM_WAKEUP_CONFIG();
+
     LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
 #endif /* DUAL_CORE */
 

targets/TARGET_STM/sleep.c

@@ -204,6 +204,25 @@ __WEAK void hal_deepsleep(void)
     if (!pwrClockEnabled) {
         __HAL_RCC_PWR_CLK_DISABLE();
     }
+#elif defined(DUAL_CORE)
+    int lowPowerModeEnabled = LL_PWR_GetRegulModeDS();
+
+#if defined(CORE_CM7)
+    HAL_PWREx_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI, PWR_D3_DOMAIN);
+    HAL_PWREx_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI, PWR_D1_DOMAIN);
+
+#elif defined(CORE_CM4)
+    HAL_PWREx_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI, PWR_D3_DOMAIN);
+    HAL_PWREx_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI, PWR_D2_DOMAIN);
+
+#else
+#error "Wrong Core selection"
+#endif /* CORE_CM7 */
+
+    if (lowPowerModeEnabled) {
+        LL_PWR_SetRegulModeDS(lowPowerModeEnabled);
+    }
+
 #else /* PWR_CR1_LPMS_STOP2 */
     HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
 #endif /* PWR_CR1_LPMS_STOP2 */
@@ -220,8 +239,19 @@ __WEAK void hal_deepsleep(void)
     ForceOscOutofDeepSleep();
     ForcePeriphOutofDeepSleep();
 
-    // After wake-up from STOP reconfigure the PLL
+    /* After wake-up from STOP reconfigure the PLL */
+#if defined(DUAL_CORE)
+    while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
+    }
+
+    if ((LL_RCC_GetSysClkSource() ==  LL_RCC_SYS_CLKSOURCE_STATUS_HSI)) {
+        LL_PWR_ClearFlag_CPU();
+        SetSysClock();
+    }
+    LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
+#else
     SetSysClock();
+#endif
 
     /*  Wait for clock to be stabilized.
      *  TO DO: a better way of doing this, would be to rely on

targets/targets.json

@@ -3303,7 +3303,8 @@
         "macros_add": [
             "STM32H747xx",
             "CORE_CM7",
-            "EXTRA_IDLE_STACK_REQUIRED"
+            "EXTRA_IDLE_STACK_REQUIRED",
+            "MBED_TICKLESS"
         ],
         "overrides": { "lpticker_delay_ticks": 0 },
         "supported_form_factors": [
@@ -3338,6 +3339,11 @@
         "mbed_ram_start": "0x10000000",
         "mbed_ram_size" : "0x48000",
         "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC",
+                "macro_name": "CLOCK_SOURCE"
+            },
             "lpticker_lptim": {
                 "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
                 "value": 1
@@ -3346,7 +3352,8 @@
         "macros_add": [
             "STM32H747xx",
             "CORE_CM4",
-            "EXTRA_IDLE_STACK_REQUIRED"
+            "EXTRA_IDLE_STACK_REQUIRED",
+            "MBED_TICKLESS"
         ],
         "overrides": { "lpticker_delay_ticks": 0 },
         "supported_form_factors": [