From e82279b5d5d4958b1441284b1d925726c115ecc3 Mon Sep 17 00:00:00 2001 From: dinau Date: Sun, 16 Mar 2014 22:16:05 +0900 Subject: [PATCH] [LPC11U35][GCC_CR] Added export functionality --- .../{ => TARGET_LPC11U24}/LPC11U24.ld | 0 .../TARGET_LPC11U35_401/LPC11U35.ld | 155 ++ .../TARGET_LPC11U35_501/LPC11U35.ld | 155 ++ workspace_tools/export/codered.py | 2 +- .../export/codered_lpc11u35_401_cproject.tmpl | 1901 +++++++++++++++++ .../export/codered_lpc11u35_401_project.tmpl | 84 + .../export/codered_lpc11u35_501_cproject.tmpl | 1901 +++++++++++++++++ .../export/codered_lpc11u35_501_project.tmpl | 84 + workspace_tools/export_test.py | 3 +- workspace_tools/targets.py | 4 +- 10 files changed, 4285 insertions(+), 4 deletions(-) rename libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/{ => TARGET_LPC11U24}/LPC11U24.ld (100%) create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_401/LPC11U35.ld create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_501/LPC11U35.ld create mode 100644 workspace_tools/export/codered_lpc11u35_401_cproject.tmpl create mode 100644 workspace_tools/export/codered_lpc11u35_401_project.tmpl create mode 100644 workspace_tools/export/codered_lpc11u35_501_cproject.tmpl create mode 100644 workspace_tools/export/codered_lpc11u35_501_project.tmpl diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/LPC11U24.ld b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U24/LPC11U24.ld similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/LPC11U24.ld rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U24/LPC11U24.ld diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_401/LPC11U35.ld b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_401/LPC11U35.ld new file mode 100644 index 0000000000..0ec42868b1 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_401/LPC11U35.ld @@ -0,0 +1,155 @@ +/* mbed - LPC11U35 linker script + * Based linker script generated by Code Red Technologies Red Suite 4.1 + */ +GROUP(libgcc.a libc_s.a libstdc++_s.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o) + +MEMORY +{ + /* Define each memory region */ + MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64k */ + RamLoc8 (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 /* 8k */ + RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2k */ +} + /* Define a symbol for the top of each memory region */ + __top_MFlash32 = 0x0 + 0x10000; + __top_RamLoc8 = 0x10000000 + 0x1F40; + __top_RamUsb2 = 0x20004000 + 0x800; + +ENTRY(ResetISR) + +SECTIONS +{ + + /* MAIN TEXT SECTION */ + .text : ALIGN(4) + { + FILL(0xff) + KEEP(*(.isr_vector)) + *(.text.ResetISR) + . = 0x200; + + /* Global Section Table */ + . = ALIGN(4) ; + __section_table_start = .; + __data_section_table = .; + LONG(LOADADDR(.data)); + LONG( ADDR(.data)) ; + LONG( SIZEOF(.data)); + LONG(LOADADDR(.data_RAM2)); + LONG( ADDR(.data_RAM2)) ; + LONG( SIZEOF(.data_RAM2)); + __data_section_table_end = .; + __bss_section_table = .; + LONG( ADDR(.bss)); + LONG( SIZEOF(.bss)); + LONG( ADDR(.bss_RAM2)); + LONG( SIZEOF(.bss_RAM2)); + __bss_section_table_end = .; + __section_table_end = . ; + /* End of Global Section Table */ + + + *(.after_vectors*) + + *(.text*) + *(.rodata .rodata.*) + . = ALIGN(4); + + /* C++ constructors etc */ + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + KEEP(*(.fini)); + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + /* End C++ */ + } > MFlash32 + + /* + * for exception handling/unwind - some Newlib functions (in common + * with C++ and STDC++) use this. + */ + .ARM.extab : ALIGN(4) + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > MFlash32 + __exidx_start = .; + + .ARM.exidx : ALIGN(4) + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > MFlash32 + __exidx_end = .; + + _etext = .; + + + .data_RAM2 : ALIGN(4) + { + FILL(0xff) + *(.data.$RAM2*) + *(.data.$RamUsb2*) + . = ALIGN(4) ; + } > RamUsb2 AT>MFlash32 + + /* MAIN DATA SECTION */ + + .uninit_RESERVED : ALIGN(4) + { + KEEP(*(.bss.$RESERVED*)) + } > RamLoc8 + + .data : ALIGN(4) + { + FILL(0xff) + _data = .; + *(vtable) + *(.data*) + . = ALIGN(4) ; + _edata = .; + } > RamLoc8 AT>MFlash32 + + + .bss_RAM2 : ALIGN(4) + { + *(.bss.$RAM2*) + *(.bss.$RamUsb2*) + . = ALIGN(4) ; + } > RamUsb2 + + /* MAIN BSS SECTION */ + .bss : ALIGN(4) + { + _bss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4) ; + _ebss = .; + PROVIDE(end = .); + __end__ = .; + } > RamLoc8 + + PROVIDE(_pvHeapStart = .); + PROVIDE(_vStackTop = __top_RamLoc8 - 0); +} diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_501/LPC11U35.ld b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_501/LPC11U35.ld new file mode 100644 index 0000000000..0ec42868b1 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_501/LPC11U35.ld @@ -0,0 +1,155 @@ +/* mbed - LPC11U35 linker script + * Based linker script generated by Code Red Technologies Red Suite 4.1 + */ +GROUP(libgcc.a libc_s.a libstdc++_s.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o) + +MEMORY +{ + /* Define each memory region */ + MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64k */ + RamLoc8 (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 /* 8k */ + RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2k */ +} + /* Define a symbol for the top of each memory region */ + __top_MFlash32 = 0x0 + 0x10000; + __top_RamLoc8 = 0x10000000 + 0x1F40; + __top_RamUsb2 = 0x20004000 + 0x800; + +ENTRY(ResetISR) + +SECTIONS +{ + + /* MAIN TEXT SECTION */ + .text : ALIGN(4) + { + FILL(0xff) + KEEP(*(.isr_vector)) + *(.text.ResetISR) + . = 0x200; + + /* Global Section Table */ + . = ALIGN(4) ; + __section_table_start = .; + __data_section_table = .; + LONG(LOADADDR(.data)); + LONG( ADDR(.data)) ; + LONG( SIZEOF(.data)); + LONG(LOADADDR(.data_RAM2)); + LONG( ADDR(.data_RAM2)) ; + LONG( SIZEOF(.data_RAM2)); + __data_section_table_end = .; + __bss_section_table = .; + LONG( ADDR(.bss)); + LONG( SIZEOF(.bss)); + LONG( ADDR(.bss_RAM2)); + LONG( SIZEOF(.bss_RAM2)); + __bss_section_table_end = .; + __section_table_end = . ; + /* End of Global Section Table */ + + + *(.after_vectors*) + + *(.text*) + *(.rodata .rodata.*) + . = ALIGN(4); + + /* C++ constructors etc */ + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + KEEP(*(.fini)); + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + /* End C++ */ + } > MFlash32 + + /* + * for exception handling/unwind - some Newlib functions (in common + * with C++ and STDC++) use this. + */ + .ARM.extab : ALIGN(4) + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > MFlash32 + __exidx_start = .; + + .ARM.exidx : ALIGN(4) + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > MFlash32 + __exidx_end = .; + + _etext = .; + + + .data_RAM2 : ALIGN(4) + { + FILL(0xff) + *(.data.$RAM2*) + *(.data.$RamUsb2*) + . = ALIGN(4) ; + } > RamUsb2 AT>MFlash32 + + /* MAIN DATA SECTION */ + + .uninit_RESERVED : ALIGN(4) + { + KEEP(*(.bss.$RESERVED*)) + } > RamLoc8 + + .data : ALIGN(4) + { + FILL(0xff) + _data = .; + *(vtable) + *(.data*) + . = ALIGN(4) ; + _edata = .; + } > RamLoc8 AT>MFlash32 + + + .bss_RAM2 : ALIGN(4) + { + *(.bss.$RAM2*) + *(.bss.$RamUsb2*) + . = ALIGN(4) ; + } > RamUsb2 + + /* MAIN BSS SECTION */ + .bss : ALIGN(4) + { + _bss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4) ; + _ebss = .; + PROVIDE(end = .); + __end__ = .; + } > RamLoc8 + + PROVIDE(_pvHeapStart = .); + PROVIDE(_vStackTop = __top_RamLoc8 - 0); +} diff --git a/workspace_tools/export/codered.py b/workspace_tools/export/codered.py index 394cb9c408..70aee880b2 100644 --- a/workspace_tools/export/codered.py +++ b/workspace_tools/export/codered.py @@ -20,7 +20,7 @@ from os.path import splitext, basename class CodeRed(Exporter): NAME = 'CodeRed' - TARGETS = ['LPC1768', 'LPC4088','LPC1114'] + TARGETS = ['LPC1768', 'LPC4088','LPC1114','LPC11U35_401','LPC11U35_501'] TOOLCHAIN = 'GCC_CR' def generate(self): diff --git a/workspace_tools/export/codered_lpc11u35_401_cproject.tmpl b/workspace_tools/export/codered_lpc11u35_401_cproject.tmpl new file mode 100644 index 0000000000..4af1822d8c --- /dev/null +++ b/workspace_tools/export/codered_lpc11u35_401_cproject.tmpl @@ -0,0 +1,1901 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + <?xml version="1.0" encoding="UTF-8"?> +<TargetConfig> +<Properties property_0="" property_2="LPC11_12_13_64K_8K.cfx" property_3="NXP" property_4="LPC11U35/401" property_count="5" version="70002"/> +<infoList vendor="NXP"> +<info chip="LPC11U35/401" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x0001BC40" name="LPC11U35/401" stub="crt_emu_lpc11_13_nxp"> +<chip> +<name>LPC11U35/401</name> +<family>LPC11Uxx</family> +<vendor>NXP (formerly Philips)</vendor> +<reset board="None" core="Real" sys="Real"/> +<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> +<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> +<memory id="RAM" type="RAM"/> +<memory id="Periph" is_volatile="true" type="Peripheral"/> +<memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/> +<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/> +<memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/> +<peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/> +<peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/> +<peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/> +<peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/> +<peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/> +<peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/> +<peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/> +<peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/> +<peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/> +<peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/> +<peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/> +<peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/> +<peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/> +<peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> +<peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/> +<peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/> +<peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/> +<peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/> +<peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/> +<peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/> +<peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/> +</chip> +<processor> +<name gcc_name="cortex-m0">Cortex-M0</name> +<family>Cortex-M</family> +</processor> +<link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/> +</info> +</infoList> +</TargetConfig> + + + + + diff --git a/workspace_tools/export/codered_lpc11u35_401_project.tmpl b/workspace_tools/export/codered_lpc11u35_401_project.tmpl new file mode 100644 index 0000000000..42ef4384de --- /dev/null +++ b/workspace_tools/export/codered_lpc11u35_401_project.tmpl @@ -0,0 +1,84 @@ + + + {{name}} + This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Code-Red + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc:/{{name}}/Debug} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + diff --git a/workspace_tools/export/codered_lpc11u35_501_cproject.tmpl b/workspace_tools/export/codered_lpc11u35_501_cproject.tmpl new file mode 100644 index 0000000000..52885c75a6 --- /dev/null +++ b/workspace_tools/export/codered_lpc11u35_501_cproject.tmpl @@ -0,0 +1,1901 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + <?xml version="1.0" encoding="UTF-8"?> +<TargetConfig> +<Properties property_0="" property_2="LPC11_12_13_64K_8K.cfx" property_3="NXP" property_4="LPC11U35/501" property_count="5" version="70002"/> +<infoList vendor="NXP"> +<info chip="LPC11U35/501" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x0001BC40" name="LPC11U35/501" stub="crt_emu_lpc11_13_nxp"> +<chip> +<name>LPC11U35/501</name> +<family>LPC11Uxx</family> +<vendor>NXP (formerly Philips)</vendor> +<reset board="None" core="Real" sys="Real"/> +<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> +<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> +<memory id="RAM" type="RAM"/> +<memory id="Periph" is_volatile="true" type="Peripheral"/> +<memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/> +<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/> +<memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/> +<peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/> +<peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/> +<peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/> +<peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/> +<peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/> +<peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/> +<peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/> +<peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/> +<peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/> +<peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/> +<peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/> +<peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/> +<peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/> +<peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> +<peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/> +<peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/> +<peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/> +<peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/> +<peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/> +<peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/> +<peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/> +</chip> +<processor> +<name gcc_name="cortex-m0">Cortex-M0</name> +<family>Cortex-M</family> +</processor> +<link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/> +</info> +</infoList> +</TargetConfig> + + + + + diff --git a/workspace_tools/export/codered_lpc11u35_501_project.tmpl b/workspace_tools/export/codered_lpc11u35_501_project.tmpl new file mode 100644 index 0000000000..42ef4384de --- /dev/null +++ b/workspace_tools/export/codered_lpc11u35_501_project.tmpl @@ -0,0 +1,84 @@ + + + {{name}} + This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Code-Red + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc:/{{name}}/Debug} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + diff --git a/workspace_tools/export_test.py b/workspace_tools/export_test.py index f2bf1195c0..0b5752536e 100644 --- a/workspace_tools/export_test.py +++ b/workspace_tools/export_test.py @@ -80,7 +80,8 @@ if __name__ == '__main__': ('uvision', 'NUCLEO_F103RB'), ('uvision', 'NUCLEO_L152RE'), ('uvision', 'NUCLEO_F401RE'), ('uvision', 'NUCLEO_F030R8'), ('uvision', 'LPC11U35_501'), ('codered', 'LPC1768'), ('codered', 'LPC4088'),('codered', 'LPC1114'), - + ('codered', 'LPC11U35_401'), + ('codered', 'LPC11U35_501'), # Linux path: /home/emimon01/bin/gcc-cs/bin/ # Windows path: "C:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin/" ('codesourcery', 'LPC1768'), diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 6502985295..675a66a6e2 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -374,7 +374,7 @@ class LPC11U35_401(Target): self.extra_labels = ['NXP', 'LPC11UXX'] - self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM","GCC_CR"] class LPC11U35_501(Target): @@ -387,7 +387,7 @@ class LPC11U35_501(Target): self.extra_labels = ['NXP', 'LPC11UXX'] - self.supported_toolchains = ["ARM", "uARM"] + self.supported_toolchains = ["ARM", "uARM","GCC_CR"] class UBLOX_C027(Target):