diff --git a/targets/TARGET_STM/TARGET_STM32L5/system_clock.c b/targets/TARGET_STM/TARGET_STM32L5/system_clock.c
index 0f44cf70aa..d6b788761d 100644
--- a/targets/TARGET_STM/TARGET_STM32L5/system_clock.c
+++ b/targets/TARGET_STM/TARGET_STM32L5/system_clock.c
@@ -134,7 +134,6 @@ uint8_t SetSysClock_PLL_MSI(void)
     __HAL_RCC_RTCAPB_CLK_ENABLE();
 
 #if MBED_CONF_TARGET_LSE_AVAILABLE
-    __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
     RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE;
     RCC_OscInitStruct.LSEState       = RCC_LSE_ON;   // External 32.768 kHz clock on OSC_IN/OSC_OUT
diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TARGET_NUCLEO_WB55RG/system_clock.c b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TARGET_NUCLEO_WB55RG/system_clock.c
index 801b1400d2..f9169760b0 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TARGET_NUCLEO_WB55RG/system_clock.c
+++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TARGET_NUCLEO_WB55RG/system_clock.c
@@ -72,7 +72,6 @@ void SetSysClock(void)
 
     Config_HSE();
 
-    __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
     __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
     /* This prevents the CPU2 (M0+) to disable the HSI48 oscillator */