mirror of https://github.com/ARMmbed/mbed-os.git
Remove MTB_MTS_XDOT target
MarceloSalazar
Marcelo Salazar
parent
4b1ad8ad4c
commit
e78ba7065b
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@ -91,28 +91,6 @@
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"lora-tcxo": "NC"
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"lora-tcxo": "NC"
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},
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},
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"MTB_MTS_XDOT": {
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"lora-radio": "SX1272",
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"lora-spi-mosi": "LORA_MOSI",
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"lora-spi-miso": "LORA_MISO",
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"lora-spi-sclk": "LORA_SCK",
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"lora-cs": "LORA_NSS",
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"lora-reset": "LORA_RESET",
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"lora-dio0": "LORA_DIO0",
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"lora-dio1": "LORA_DIO1",
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"lora-dio2": "LORA_DIO2",
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"lora-dio3": "LORA_DIO3",
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"lora-dio4": "LORA_DIO4",
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"lora-dio5": "NC",
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"lora-rf-switch-ctl1": "NC",
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"lora-rf-switch-ctl2": "NC",
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"lora-txctl": "NC",
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"lora-rxctl": "NC",
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"lora-ant-switch": "NC",
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"lora-pwr-amp-ctl": "NC",
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"lora-tcxo": "NC"
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},
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"LTEK_FF1705": {
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"LTEK_FF1705": {
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"lora-radio": "SX1272",
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"lora-radio": "SX1272",
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"lora-spi-mosi": "LORA_MOSI",
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"lora-spi-mosi": "LORA_MOSI",
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@ -23,11 +23,6 @@
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using namespace utest::v1;
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using namespace utest::v1;
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// TODO HACK, replace with available ram/heap property
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#if defined(TARGET_MTB_MTS_XDOT)
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#error [NOT_SUPPORTED] Insufficient heap for heap block device tests
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#else
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#define TEST_BLOCK_SIZE 128
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#define TEST_BLOCK_SIZE 128
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#define TEST_BLOCK_DEVICE_SIZE 32*TEST_BLOCK_SIZE
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#define TEST_BLOCK_DEVICE_SIZE 32*TEST_BLOCK_SIZE
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#define TEST_BLOCK_COUNT 10
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#define TEST_BLOCK_COUNT 10
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@ -186,5 +181,3 @@ int main()
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{
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{
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return !Harness::run(specification);
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return !Harness::run(specification);
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}
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}
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#endif // defined(TARGET_MTB_MTS_XDOT)
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@ -24,11 +24,6 @@
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using namespace utest::v1;
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using namespace utest::v1;
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// TODO HACK, replace with available ram/heap property
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#if defined(TARGET_MTB_MTS_XDOT)
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#error [NOT_SUPPORTED] Insufficient heap for heap block device tests
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#else
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#define BLOCK_COUNT 16
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#define BLOCK_COUNT 16
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#define BLOCK_SIZE 512
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#define BLOCK_SIZE 512
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@ -250,5 +245,3 @@ int main()
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{
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{
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return !Harness::run(specification);
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return !Harness::run(specification);
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}
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}
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#endif // defined(TARGET_MTB_MTS_XDOT)
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@ -26,11 +26,6 @@
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using namespace utest::v1;
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using namespace utest::v1;
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// TODO HACK, replace with available ram/heap property
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#if defined(TARGET_MTB_MTS_XDOT)
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#error [NOT_SUPPORTED] Insufficient heap for heap block device tests
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#else
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#define BLOCK_COUNT 16
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#define BLOCK_COUNT 16
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#define BLOCK_SIZE 512
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#define BLOCK_SIZE 512
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@ -308,5 +303,3 @@ int main()
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{
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{
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return !Harness::run(specification);
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return !Harness::run(specification);
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}
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}
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#endif // defined(TARGET_MTB_MTS_XDOT)
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@ -1,83 +0,0 @@
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/* mbed Microcontroller Library
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*******************************************************************************
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* Copyright (c) 2015, STMicroelectronics
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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*/
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#ifndef MBED_PERIPHERALNAMES_H
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#define MBED_PERIPHERALNAMES_H
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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ADC_1 = (int)ADC1_BASE
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} ADCName;
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typedef enum {
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DAC_1 = (int)DAC_BASE
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} DACName;
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typedef enum {
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UART_1 = (int)USART1_BASE,
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UART_2 = (int)USART2_BASE,
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UART_3 = (int)USART3_BASE
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} UARTName;
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#define STDIO_UART_TX PA_2
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#define STDIO_UART_RX PA_3
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#define STDIO_UART UART_2
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#define DEVICE_SPI_COUNT 3
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typedef enum {
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SPI_1 = (int)SPI1_BASE,
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SPI_2 = (int)SPI2_BASE,
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SPI_3 = (int)SPI3_BASE
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} SPIName;
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typedef enum {
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I2C_1 = (int)I2C1_BASE,
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I2C_2 = (int)I2C2_BASE
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} I2CName;
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typedef enum {
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PWM_2 = (int)TIM2_BASE,
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PWM_3 = (int)TIM3_BASE,
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PWM_4 = (int)TIM4_BASE,
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PWM_5 = (int)TIM5_BASE,
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PWM_9 = (int)TIM9_BASE,
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PWM_10 = (int)TIM10_BASE,
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PWM_11 = (int)TIM11_BASE
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} PWMName;
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -1,136 +0,0 @@
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/* mbed Microcontroller Library
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*******************************************************************************
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* Copyright (c) 2016, STMicroelectronics
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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*/
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#include "PeripheralPins.h"
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// =====
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// Note: Commented lines are alternative possibilities which are not used per default.
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// If you change them, you will have also to modify the corresponding xxx_api.c file
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// for pwmout, analogin, analogout, ...
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// =====
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//*** ADC ***
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const PinMap PinMap_ADC[] = {
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{PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0
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{PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2
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{PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3
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{PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4
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{PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5
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{PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC_IN8
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{PB_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18
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{PB_13, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC_IN19
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{PB_14, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC_IN20
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{PB_15, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 21, 0)}, // ADC_IN21
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{NC, NC, 0}
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};
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const PinMap PinMap_ADC_Internal[] = {
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{ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
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{ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
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{NC, NC, 0}
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};
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//*** DAC ***
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const PinMap PinMap_DAC[] = {
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{PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1
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{PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 (Warning: LED1 is also on this pin)
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{NC, NC, 0}
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};
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//*** I2C ***
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const PinMap PinMap_I2C_SDA[] = {
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{PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
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{NC, NC, 0}
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};
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const PinMap PinMap_I2C_SCL[] = {
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{PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
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{NC, NC, 0}
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};
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//*** PWM ***
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// TIM2 cannot be used because it is used to clock the SE
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// TIM5 cannot be used because already used by the us_ticker.
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const PinMap PinMap_PWM[] = {
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{PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
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{PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
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{PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
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{PB_12, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
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{PB_13, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
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{PB_14, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
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{PB_15, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
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{NC, NC, 0}
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};
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//*** SERIAL ***
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const PinMap PinMap_UART_TX[] = {
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{PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
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{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
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{PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
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{NC, NC, 0}
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};
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const PinMap PinMap_UART_RX[] = {
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{PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
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{PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
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{PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
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{NC, NC, 0}
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};
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//*** SPI ***
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const PinMap PinMap_SPI_MOSI[] = {
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{PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
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{PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
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{NC, NC, 0}
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};
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const PinMap PinMap_SPI_MISO[] = {
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{PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
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{PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
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{NC, NC, 0}
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};
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const PinMap PinMap_SPI_SCLK[] = {
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{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
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{PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
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{NC, NC, 0}
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};
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const PinMap PinMap_SPI_SSEL[] = {
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{PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
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{PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
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{NC, NC, 0}
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};
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@ -1,244 +0,0 @@
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/* mbed Microcontroller Library
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*******************************************************************************
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* Copyright (c) 2016, STMicroelectronics
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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||||||
* modification, are permitted provided that the following conditions are met:
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||||||
*
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||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
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* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#ifndef MBED_PINNAMES_H
|
|
||||||
#define MBED_PINNAMES_H
|
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
#include "PinNamesTypes.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
typedef enum {
|
|
||||||
PA_0 = 0x00,
|
|
||||||
PA_1 = 0x01,
|
|
||||||
PA_2 = 0x02,
|
|
||||||
PA_3 = 0x03,
|
|
||||||
PA_4 = 0x04,
|
|
||||||
PA_5 = 0x05,
|
|
||||||
PA_6 = 0x06,
|
|
||||||
PA_7 = 0x07,
|
|
||||||
PA_8 = 0x08,
|
|
||||||
PA_9 = 0x09,
|
|
||||||
PA_10 = 0x0A,
|
|
||||||
PA_11 = 0x0B,
|
|
||||||
PA_12 = 0x0C,
|
|
||||||
PA_13 = 0x0D,
|
|
||||||
PA_14 = 0x0E,
|
|
||||||
PA_15 = 0x0F,
|
|
||||||
|
|
||||||
PB_0 = 0x10,
|
|
||||||
PB_1 = 0x11,
|
|
||||||
PB_2 = 0x12,
|
|
||||||
PB_3 = 0x13,
|
|
||||||
PB_4 = 0x14,
|
|
||||||
PB_5 = 0x15,
|
|
||||||
PB_6 = 0x16,
|
|
||||||
PB_7 = 0x17,
|
|
||||||
PB_8 = 0x18,
|
|
||||||
PB_9 = 0x19,
|
|
||||||
PB_10 = 0x1A,
|
|
||||||
PB_11 = 0x1B,
|
|
||||||
PB_12 = 0x1C,
|
|
||||||
PB_13 = 0x1D,
|
|
||||||
PB_14 = 0x1E,
|
|
||||||
PB_15 = 0x1F,
|
|
||||||
|
|
||||||
PC_0 = 0x20,
|
|
||||||
PC_1 = 0x21,
|
|
||||||
PC_2 = 0x22,
|
|
||||||
PC_3 = 0x23,
|
|
||||||
PC_4 = 0x24,
|
|
||||||
PC_5 = 0x25,
|
|
||||||
PC_6 = 0x26,
|
|
||||||
PC_7 = 0x27,
|
|
||||||
PC_8 = 0x28,
|
|
||||||
PC_9 = 0x29,
|
|
||||||
PC_10 = 0x2A,
|
|
||||||
PC_11 = 0x2B,
|
|
||||||
PC_12 = 0x2C,
|
|
||||||
PC_13 = 0x2D,
|
|
||||||
PC_14 = 0x2E,
|
|
||||||
PC_15 = 0x2F,
|
|
||||||
|
|
||||||
PD_2 = 0x32,
|
|
||||||
|
|
||||||
PH_0 = 0x70,
|
|
||||||
PH_1 = 0x71,
|
|
||||||
|
|
||||||
// Not connected
|
|
||||||
NC = (int)0xFFFFFFFF,
|
|
||||||
|
|
||||||
//Module pins. Refer device "S000645" guide, version 2.1
|
|
||||||
P_1 = NC,
|
|
||||||
P_2 = NC,
|
|
||||||
P_3 = NC,
|
|
||||||
P_4 = NC,
|
|
||||||
P_5 = NC,
|
|
||||||
P_6 = NC,
|
|
||||||
P_7 = NC,
|
|
||||||
P_8 = NC,
|
|
||||||
P_9 = PB_12,
|
|
||||||
P_10 = PB_13,
|
|
||||||
P_11 = PB_15,
|
|
||||||
P_12 = PB_14,
|
|
||||||
P_13 = PA_9, //UART_TX
|
|
||||||
P_14 = PA_10, //UART_RX
|
|
||||||
P_15 = PA_2,
|
|
||||||
P_16 = PA_3,
|
|
||||||
P_17 = NC,
|
|
||||||
P_18 = NC,
|
|
||||||
P_19 = NC,
|
|
||||||
P_20 = NC,
|
|
||||||
P_21 = NC,
|
|
||||||
P_22 = NC,
|
|
||||||
P_23 = PB_2,
|
|
||||||
P_24 = PB_0,
|
|
||||||
P_25 = PA_5,
|
|
||||||
P_26 = PA_4,
|
|
||||||
P_27 = PB_8,
|
|
||||||
P_28 = PB_9,
|
|
||||||
P_29 = PA_14,
|
|
||||||
P_30 = PA_13,
|
|
||||||
P_31 = PA_12, //UART1_RTS
|
|
||||||
P_32 = PA_11, //UART1_CTS
|
|
||||||
P_33 = NC, //NRST
|
|
||||||
P_34 = PA_0, //WAKE
|
|
||||||
P_35 = NC,
|
|
||||||
P_36 = NC,
|
|
||||||
P_37 = NC,
|
|
||||||
P_38 = NC,
|
|
||||||
P_39 = NC,
|
|
||||||
P_40 = NC,
|
|
||||||
P_41 = NC,
|
|
||||||
P_42 = NC,
|
|
||||||
P_43 = NC,
|
|
||||||
P_44 = NC,
|
|
||||||
P_45 = NC,
|
|
||||||
P_46 = NC,
|
|
||||||
P_47 = NC,
|
|
||||||
P_48 = NC,
|
|
||||||
P_49 = NC,
|
|
||||||
P_50 = NC,
|
|
||||||
P_51 = NC,
|
|
||||||
P_52 = NC,
|
|
||||||
P_53 = NC,
|
|
||||||
P_54 = NC,
|
|
||||||
P_55 = NC,
|
|
||||||
P_56 = NC,
|
|
||||||
P_57 = NC,
|
|
||||||
P_58 = NC,
|
|
||||||
|
|
||||||
// LoRa
|
|
||||||
LORA_RESET = PA_1,
|
|
||||||
LORA_MOSI = PB_5,
|
|
||||||
LORA_MISO = PB_4,
|
|
||||||
LORA_SCK = PB_3,
|
|
||||||
LORA_NSS = PA_15,
|
|
||||||
LORA_DIO0 = PA_6,
|
|
||||||
LORA_DIO1 = PA_7,
|
|
||||||
LORA_DIO2 = PA_8,
|
|
||||||
LORA_DIO3 = PB_1,
|
|
||||||
LORA_DIO4 = PC_13,
|
|
||||||
|
|
||||||
// Secure Element
|
|
||||||
SE_RESET = PB_7,
|
|
||||||
SE_CTRL = PB_6,
|
|
||||||
SE_IO = PB_10,
|
|
||||||
SE_CLK = PB_11,
|
|
||||||
|
|
||||||
// ADC internal channels
|
|
||||||
ADC_TEMP = 0xF0,
|
|
||||||
ADC_VREF = 0xF1,
|
|
||||||
|
|
||||||
// GPIOs
|
|
||||||
GPIO0 = PA_4, // analog out capable, analog in capable. Also used as A0 for LCD on MTB
|
|
||||||
GPIO1 = PA_5, // analog out capable, analog in capable. Also used as RESET for LCD on MTB
|
|
||||||
GPIO2 = PB_0, // analog in capable, pwm capable // CS for LCD on MTB
|
|
||||||
GPIO3 = PB_2,
|
|
||||||
|
|
||||||
// LED
|
|
||||||
LED1 = GPIO3,
|
|
||||||
LED2 = GPIO3,
|
|
||||||
|
|
||||||
//Standardized button name
|
|
||||||
SW1 = PA_0,
|
|
||||||
BUTTON1 = SW1,
|
|
||||||
|
|
||||||
// Wake Pin
|
|
||||||
WAKE = SW1,
|
|
||||||
|
|
||||||
// UART 1
|
|
||||||
UART1_TX = PA_9,
|
|
||||||
UART1_RX = PA_10,
|
|
||||||
UART1_CTS = PA_11,
|
|
||||||
UART1_RTS = PA_12,
|
|
||||||
|
|
||||||
UART_TX = UART1_TX,
|
|
||||||
UART_RX = UART1_RX,
|
|
||||||
UART_CTS = UART1_CTS,
|
|
||||||
UART_RTS = UART1_RTS,
|
|
||||||
|
|
||||||
//UART 2
|
|
||||||
UART2_TX = PA_2,
|
|
||||||
UART2_RX = PA_3,
|
|
||||||
|
|
||||||
// DAPLink
|
|
||||||
USBTX = MBED_CONF_TARGET_STDIO_UART_TX,
|
|
||||||
USBRX = MBED_CONF_TARGET_STDIO_UART_RX,
|
|
||||||
SWDIO = PA_13,
|
|
||||||
SWCLK = PA_14,
|
|
||||||
|
|
||||||
// SPI
|
|
||||||
SPI1_MOSI = PB_15,
|
|
||||||
SPI1_MISO = PB_14,
|
|
||||||
SPI1_SCK = PB_13,
|
|
||||||
SPI1_NSS = PB_12,
|
|
||||||
|
|
||||||
SPI_MOSI = SPI1_MOSI,
|
|
||||||
SPI_MISO = SPI1_MISO,
|
|
||||||
SPI_SCK = SPI1_SCK,
|
|
||||||
SPI_NSS = SPI1_NSS,
|
|
||||||
|
|
||||||
// I2C
|
|
||||||
I2C0_SCL = PB_8,
|
|
||||||
I2C0_SDA = PB_9,
|
|
||||||
|
|
||||||
I2C_SCL = I2C0_SCL,
|
|
||||||
I2C_SDA = I2C0_SDA,
|
|
||||||
|
|
||||||
} PinName;
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,306 +0,0 @@
|
||||||
;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
|
|
||||||
;* File Name : startup_stm32l151xc.s
|
|
||||||
;* Author : MCD Application Team
|
|
||||||
;* Version : 21-April-2017
|
|
||||||
;* Date : V2.2.1
|
|
||||||
;* Description : STM32L151XC Devices vector for MDK-ARM toolchain.
|
|
||||||
;* This module performs:
|
|
||||||
;* - Set the initial SP
|
|
||||||
;* - Set the initial PC == Reset_Handler
|
|
||||||
;* - Set the vector table entries with the exceptions ISR
|
|
||||||
;* address.
|
|
||||||
;* - Configure the system clock
|
|
||||||
;* - Branches to __main in the C library (which eventually
|
|
||||||
;* calls main()).
|
|
||||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
|
||||||
;********************************************************************************
|
|
||||||
;*
|
|
||||||
;* COPYRIGHT(c) 2017 STMicroelectronics
|
|
||||||
;*
|
|
||||||
;* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
;* are permitted provided that the following conditions are met:
|
|
||||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
;* this list of conditions and the following disclaimer.
|
|
||||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
;* this list of conditions and the following disclaimer in the documentation
|
|
||||||
;* and/or other materials provided with the distribution.
|
|
||||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
;* may be used to endorse or promote products derived from this software
|
|
||||||
;* without specific prior written permission.
|
|
||||||
;*
|
|
||||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
;
|
|
||||||
;*******************************************************************************
|
|
||||||
|
|
||||||
PRESERVE8
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
|
|
||||||
; Vector Table Mapped to Address 0 at Reset
|
|
||||||
AREA RESET, DATA, READONLY
|
|
||||||
EXPORT __Vectors
|
|
||||||
EXPORT __Vectors_End
|
|
||||||
EXPORT __Vectors_Size
|
|
||||||
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
|
|
||||||
|
|
||||||
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
|
|
||||||
DCD Reset_Handler ; Reset Handler
|
|
||||||
DCD NMI_Handler ; NMI Handler
|
|
||||||
DCD HardFault_Handler ; Hard Fault Handler
|
|
||||||
DCD MemManage_Handler ; MPU Fault Handler
|
|
||||||
DCD BusFault_Handler ; Bus Fault Handler
|
|
||||||
DCD UsageFault_Handler ; Usage Fault Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD SVC_Handler ; SVCall Handler
|
|
||||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD PendSV_Handler ; PendSV Handler
|
|
||||||
DCD SysTick_Handler ; SysTick Handler
|
|
||||||
|
|
||||||
; External Interrupts
|
|
||||||
DCD WWDG_IRQHandler ; Window Watchdog
|
|
||||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
|
||||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
|
||||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
|
||||||
DCD FLASH_IRQHandler ; FLASH
|
|
||||||
DCD RCC_IRQHandler ; RCC
|
|
||||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
|
||||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
|
||||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
|
||||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
|
||||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
|
||||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
|
||||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
|
||||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
|
||||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
|
||||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
|
||||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
|
||||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
|
||||||
DCD ADC1_IRQHandler ; ADC1
|
|
||||||
DCD USB_HP_IRQHandler ; USB High Priority
|
|
||||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
|
||||||
DCD DAC_IRQHandler ; DAC
|
|
||||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
|
||||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD TIM9_IRQHandler ; TIM9
|
|
||||||
DCD TIM10_IRQHandler ; TIM10
|
|
||||||
DCD TIM11_IRQHandler ; TIM11
|
|
||||||
DCD TIM2_IRQHandler ; TIM2
|
|
||||||
DCD TIM3_IRQHandler ; TIM3
|
|
||||||
DCD TIM4_IRQHandler ; TIM4
|
|
||||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
|
||||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
|
||||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
|
||||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
|
||||||
DCD SPI1_IRQHandler ; SPI1
|
|
||||||
DCD SPI2_IRQHandler ; SPI2
|
|
||||||
DCD USART1_IRQHandler ; USART1
|
|
||||||
DCD USART2_IRQHandler ; USART2
|
|
||||||
DCD USART3_IRQHandler ; USART3
|
|
||||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
|
||||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
|
||||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
|
||||||
DCD TIM6_IRQHandler ; TIM6
|
|
||||||
DCD TIM7_IRQHandler ; TIM7
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD TIM5_IRQHandler ; TIM5
|
|
||||||
DCD SPI3_IRQHandler ; SPI3
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
|
||||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
|
||||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
|
||||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
|
||||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
|
||||||
|
|
||||||
__Vectors_End
|
|
||||||
|
|
||||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
|
||||||
|
|
||||||
AREA |.text|, CODE, READONLY
|
|
||||||
|
|
||||||
; Reset handler routine
|
|
||||||
Reset_Handler PROC
|
|
||||||
EXPORT Reset_Handler [WEAK]
|
|
||||||
IMPORT __main
|
|
||||||
IMPORT SystemInit
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
LDR R0, =__main
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
|
||||||
|
|
||||||
NMI_Handler PROC
|
|
||||||
EXPORT NMI_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
HardFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT HardFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
MemManage_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT MemManage_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
BusFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT BusFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
UsageFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT UsageFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
SVC_Handler PROC
|
|
||||||
EXPORT SVC_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
DebugMon_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT DebugMon_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
PendSV_Handler PROC
|
|
||||||
EXPORT PendSV_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
SysTick_Handler PROC
|
|
||||||
EXPORT SysTick_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Default_Handler PROC
|
|
||||||
|
|
||||||
EXPORT WWDG_IRQHandler [WEAK]
|
|
||||||
EXPORT PVD_IRQHandler [WEAK]
|
|
||||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
|
|
||||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
|
||||||
EXPORT FLASH_IRQHandler [WEAK]
|
|
||||||
EXPORT RCC_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI0_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI1_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI2_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI3_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI4_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
|
||||||
EXPORT ADC1_IRQHandler [WEAK]
|
|
||||||
EXPORT USB_HP_IRQHandler [WEAK]
|
|
||||||
EXPORT USB_LP_IRQHandler [WEAK]
|
|
||||||
EXPORT DAC_IRQHandler [WEAK]
|
|
||||||
EXPORT COMP_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM9_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM10_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM11_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM2_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM3_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM4_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI1_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI2_IRQHandler [WEAK]
|
|
||||||
EXPORT USART1_IRQHandler [WEAK]
|
|
||||||
EXPORT USART2_IRQHandler [WEAK]
|
|
||||||
EXPORT USART3_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
|
||||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
|
||||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM6_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM7_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM5_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI3_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
|
||||||
EXPORT COMP_ACQ_IRQHandler [WEAK]
|
|
||||||
|
|
||||||
WWDG_IRQHandler
|
|
||||||
PVD_IRQHandler
|
|
||||||
TAMPER_STAMP_IRQHandler
|
|
||||||
RTC_WKUP_IRQHandler
|
|
||||||
FLASH_IRQHandler
|
|
||||||
RCC_IRQHandler
|
|
||||||
EXTI0_IRQHandler
|
|
||||||
EXTI1_IRQHandler
|
|
||||||
EXTI2_IRQHandler
|
|
||||||
EXTI3_IRQHandler
|
|
||||||
EXTI4_IRQHandler
|
|
||||||
DMA1_Channel1_IRQHandler
|
|
||||||
DMA1_Channel2_IRQHandler
|
|
||||||
DMA1_Channel3_IRQHandler
|
|
||||||
DMA1_Channel4_IRQHandler
|
|
||||||
DMA1_Channel5_IRQHandler
|
|
||||||
DMA1_Channel6_IRQHandler
|
|
||||||
DMA1_Channel7_IRQHandler
|
|
||||||
ADC1_IRQHandler
|
|
||||||
USB_HP_IRQHandler
|
|
||||||
USB_LP_IRQHandler
|
|
||||||
DAC_IRQHandler
|
|
||||||
COMP_IRQHandler
|
|
||||||
EXTI9_5_IRQHandler
|
|
||||||
TIM9_IRQHandler
|
|
||||||
TIM10_IRQHandler
|
|
||||||
TIM11_IRQHandler
|
|
||||||
TIM2_IRQHandler
|
|
||||||
TIM3_IRQHandler
|
|
||||||
TIM4_IRQHandler
|
|
||||||
I2C1_EV_IRQHandler
|
|
||||||
I2C1_ER_IRQHandler
|
|
||||||
I2C2_EV_IRQHandler
|
|
||||||
I2C2_ER_IRQHandler
|
|
||||||
SPI1_IRQHandler
|
|
||||||
SPI2_IRQHandler
|
|
||||||
USART1_IRQHandler
|
|
||||||
USART2_IRQHandler
|
|
||||||
USART3_IRQHandler
|
|
||||||
EXTI15_10_IRQHandler
|
|
||||||
RTC_Alarm_IRQHandler
|
|
||||||
USB_FS_WKUP_IRQHandler
|
|
||||||
TIM6_IRQHandler
|
|
||||||
TIM7_IRQHandler
|
|
||||||
TIM5_IRQHandler
|
|
||||||
SPI3_IRQHandler
|
|
||||||
DMA2_Channel1_IRQHandler
|
|
||||||
DMA2_Channel2_IRQHandler
|
|
||||||
DMA2_Channel3_IRQHandler
|
|
||||||
DMA2_Channel4_IRQHandler
|
|
||||||
DMA2_Channel5_IRQHandler
|
|
||||||
COMP_ACQ_IRQHandler
|
|
||||||
|
|
||||||
B .
|
|
||||||
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
ALIGN
|
|
||||||
END
|
|
||||||
|
|
@ -1,76 +0,0 @@
|
||||||
#! armcc -E
|
|
||||||
; Scatter-Loading Description File
|
|
||||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
||||||
; Copyright (c) 2015, STMicroelectronics
|
|
||||||
; All rights reserved.
|
|
||||||
;
|
|
||||||
; Redistribution and use in source and binary forms, with or without
|
|
||||||
; modification, are permitted provided that the following conditions are met:
|
|
||||||
;
|
|
||||||
; 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
; this list of conditions and the following disclaimer.
|
|
||||||
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
; this list of conditions and the following disclaimer in the documentation
|
|
||||||
; and/or other materials provided with the distribution.
|
|
||||||
; 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
; may be used to endorse or promote products derived from this software
|
|
||||||
; without specific prior written permission.
|
|
||||||
;
|
|
||||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
||||||
|
|
||||||
#if !defined(MBED_APP_START)
|
|
||||||
#define MBED_APP_START 0x08000000
|
|
||||||
#endif
|
|
||||||
|
|
||||||
; STM32L151RC: 256KB FLASH
|
|
||||||
#if !defined(MBED_APP_SIZE)
|
|
||||||
#define MBED_APP_SIZE 0x40000
|
|
||||||
#endif
|
|
||||||
|
|
||||||
; 32KB SRAM
|
|
||||||
#if !defined(MBED_RAM_START)
|
|
||||||
#define MBED_RAM_START 0x20000000
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_RAM_SIZE)
|
|
||||||
#define MBED_RAM_SIZE 0x8000
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
#if !defined(MBED_BOOT_STACK_SIZE)
|
|
||||||
#define MBED_BOOT_STACK_SIZE 0x400
|
|
||||||
#endif
|
|
||||||
|
|
||||||
; 73 vectors = 292 bytes (0x124) 8-byte aligned = 0x128 (0x124 + 0x4) to be reserved in RAM
|
|
||||||
#define VECTOR_SIZE 0x128
|
|
||||||
|
|
||||||
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
|
|
||||||
|
|
||||||
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
|
|
||||||
|
|
||||||
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
|
|
||||||
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
|
|
||||||
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
|
|
||||||
}
|
|
||||||
|
|
||||||
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -1,306 +0,0 @@
|
||||||
;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
|
|
||||||
;* File Name : startup_stm32l151xc.s
|
|
||||||
;* Author : MCD Application Team
|
|
||||||
;* Version : 21-April-2017
|
|
||||||
;* Date : V2.2.1
|
|
||||||
;* Description : STM32L151XC Devices vector for MDK-ARM toolchain.
|
|
||||||
;* This module performs:
|
|
||||||
;* - Set the initial SP
|
|
||||||
;* - Set the initial PC == Reset_Handler
|
|
||||||
;* - Set the vector table entries with the exceptions ISR
|
|
||||||
;* address.
|
|
||||||
;* - Configure the system clock
|
|
||||||
;* - Branches to __main in the C library (which eventually
|
|
||||||
;* calls main()).
|
|
||||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
|
||||||
;********************************************************************************
|
|
||||||
;*
|
|
||||||
;* COPYRIGHT(c) 2017 STMicroelectronics
|
|
||||||
;*
|
|
||||||
;* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
;* are permitted provided that the following conditions are met:
|
|
||||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
;* this list of conditions and the following disclaimer.
|
|
||||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
;* this list of conditions and the following disclaimer in the documentation
|
|
||||||
;* and/or other materials provided with the distribution.
|
|
||||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
;* may be used to endorse or promote products derived from this software
|
|
||||||
;* without specific prior written permission.
|
|
||||||
;*
|
|
||||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
;
|
|
||||||
;*******************************************************************************
|
|
||||||
|
|
||||||
PRESERVE8
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
|
|
||||||
; Vector Table Mapped to Address 0 at Reset
|
|
||||||
AREA RESET, DATA, READONLY
|
|
||||||
EXPORT __Vectors
|
|
||||||
EXPORT __Vectors_End
|
|
||||||
EXPORT __Vectors_Size
|
|
||||||
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
|
|
||||||
|
|
||||||
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
|
|
||||||
DCD Reset_Handler ; Reset Handler
|
|
||||||
DCD NMI_Handler ; NMI Handler
|
|
||||||
DCD HardFault_Handler ; Hard Fault Handler
|
|
||||||
DCD MemManage_Handler ; MPU Fault Handler
|
|
||||||
DCD BusFault_Handler ; Bus Fault Handler
|
|
||||||
DCD UsageFault_Handler ; Usage Fault Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD SVC_Handler ; SVCall Handler
|
|
||||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD PendSV_Handler ; PendSV Handler
|
|
||||||
DCD SysTick_Handler ; SysTick Handler
|
|
||||||
|
|
||||||
; External Interrupts
|
|
||||||
DCD WWDG_IRQHandler ; Window Watchdog
|
|
||||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
|
||||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
|
||||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
|
||||||
DCD FLASH_IRQHandler ; FLASH
|
|
||||||
DCD RCC_IRQHandler ; RCC
|
|
||||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
|
||||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
|
||||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
|
||||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
|
||||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
|
||||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
|
||||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
|
||||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
|
||||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
|
||||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
|
||||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
|
||||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
|
||||||
DCD ADC1_IRQHandler ; ADC1
|
|
||||||
DCD USB_HP_IRQHandler ; USB High Priority
|
|
||||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
|
||||||
DCD DAC_IRQHandler ; DAC
|
|
||||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
|
||||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD TIM9_IRQHandler ; TIM9
|
|
||||||
DCD TIM10_IRQHandler ; TIM10
|
|
||||||
DCD TIM11_IRQHandler ; TIM11
|
|
||||||
DCD TIM2_IRQHandler ; TIM2
|
|
||||||
DCD TIM3_IRQHandler ; TIM3
|
|
||||||
DCD TIM4_IRQHandler ; TIM4
|
|
||||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
|
||||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
|
||||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
|
||||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
|
||||||
DCD SPI1_IRQHandler ; SPI1
|
|
||||||
DCD SPI2_IRQHandler ; SPI2
|
|
||||||
DCD USART1_IRQHandler ; USART1
|
|
||||||
DCD USART2_IRQHandler ; USART2
|
|
||||||
DCD USART3_IRQHandler ; USART3
|
|
||||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
|
||||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
|
||||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
|
||||||
DCD TIM6_IRQHandler ; TIM6
|
|
||||||
DCD TIM7_IRQHandler ; TIM7
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD TIM5_IRQHandler ; TIM5
|
|
||||||
DCD SPI3_IRQHandler ; SPI3
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
|
||||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
|
||||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
|
||||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
|
||||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
|
||||||
|
|
||||||
__Vectors_End
|
|
||||||
|
|
||||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
|
||||||
|
|
||||||
AREA |.text|, CODE, READONLY
|
|
||||||
|
|
||||||
; Reset handler routine
|
|
||||||
Reset_Handler PROC
|
|
||||||
EXPORT Reset_Handler [WEAK]
|
|
||||||
IMPORT __main
|
|
||||||
IMPORT SystemInit
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
LDR R0, =__main
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
|
||||||
|
|
||||||
NMI_Handler PROC
|
|
||||||
EXPORT NMI_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
HardFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT HardFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
MemManage_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT MemManage_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
BusFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT BusFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
UsageFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT UsageFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
SVC_Handler PROC
|
|
||||||
EXPORT SVC_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
DebugMon_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT DebugMon_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
PendSV_Handler PROC
|
|
||||||
EXPORT PendSV_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
SysTick_Handler PROC
|
|
||||||
EXPORT SysTick_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Default_Handler PROC
|
|
||||||
|
|
||||||
EXPORT WWDG_IRQHandler [WEAK]
|
|
||||||
EXPORT PVD_IRQHandler [WEAK]
|
|
||||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
|
|
||||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
|
||||||
EXPORT FLASH_IRQHandler [WEAK]
|
|
||||||
EXPORT RCC_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI0_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI1_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI2_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI3_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI4_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
|
||||||
EXPORT ADC1_IRQHandler [WEAK]
|
|
||||||
EXPORT USB_HP_IRQHandler [WEAK]
|
|
||||||
EXPORT USB_LP_IRQHandler [WEAK]
|
|
||||||
EXPORT DAC_IRQHandler [WEAK]
|
|
||||||
EXPORT COMP_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM9_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM10_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM11_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM2_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM3_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM4_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI1_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI2_IRQHandler [WEAK]
|
|
||||||
EXPORT USART1_IRQHandler [WEAK]
|
|
||||||
EXPORT USART2_IRQHandler [WEAK]
|
|
||||||
EXPORT USART3_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
|
||||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
|
||||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM6_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM7_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM5_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI3_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
|
||||||
EXPORT COMP_ACQ_IRQHandler [WEAK]
|
|
||||||
|
|
||||||
WWDG_IRQHandler
|
|
||||||
PVD_IRQHandler
|
|
||||||
TAMPER_STAMP_IRQHandler
|
|
||||||
RTC_WKUP_IRQHandler
|
|
||||||
FLASH_IRQHandler
|
|
||||||
RCC_IRQHandler
|
|
||||||
EXTI0_IRQHandler
|
|
||||||
EXTI1_IRQHandler
|
|
||||||
EXTI2_IRQHandler
|
|
||||||
EXTI3_IRQHandler
|
|
||||||
EXTI4_IRQHandler
|
|
||||||
DMA1_Channel1_IRQHandler
|
|
||||||
DMA1_Channel2_IRQHandler
|
|
||||||
DMA1_Channel3_IRQHandler
|
|
||||||
DMA1_Channel4_IRQHandler
|
|
||||||
DMA1_Channel5_IRQHandler
|
|
||||||
DMA1_Channel6_IRQHandler
|
|
||||||
DMA1_Channel7_IRQHandler
|
|
||||||
ADC1_IRQHandler
|
|
||||||
USB_HP_IRQHandler
|
|
||||||
USB_LP_IRQHandler
|
|
||||||
DAC_IRQHandler
|
|
||||||
COMP_IRQHandler
|
|
||||||
EXTI9_5_IRQHandler
|
|
||||||
TIM9_IRQHandler
|
|
||||||
TIM10_IRQHandler
|
|
||||||
TIM11_IRQHandler
|
|
||||||
TIM2_IRQHandler
|
|
||||||
TIM3_IRQHandler
|
|
||||||
TIM4_IRQHandler
|
|
||||||
I2C1_EV_IRQHandler
|
|
||||||
I2C1_ER_IRQHandler
|
|
||||||
I2C2_EV_IRQHandler
|
|
||||||
I2C2_ER_IRQHandler
|
|
||||||
SPI1_IRQHandler
|
|
||||||
SPI2_IRQHandler
|
|
||||||
USART1_IRQHandler
|
|
||||||
USART2_IRQHandler
|
|
||||||
USART3_IRQHandler
|
|
||||||
EXTI15_10_IRQHandler
|
|
||||||
RTC_Alarm_IRQHandler
|
|
||||||
USB_FS_WKUP_IRQHandler
|
|
||||||
TIM6_IRQHandler
|
|
||||||
TIM7_IRQHandler
|
|
||||||
TIM5_IRQHandler
|
|
||||||
SPI3_IRQHandler
|
|
||||||
DMA2_Channel1_IRQHandler
|
|
||||||
DMA2_Channel2_IRQHandler
|
|
||||||
DMA2_Channel3_IRQHandler
|
|
||||||
DMA2_Channel4_IRQHandler
|
|
||||||
DMA2_Channel5_IRQHandler
|
|
||||||
COMP_ACQ_IRQHandler
|
|
||||||
|
|
||||||
B .
|
|
||||||
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
ALIGN
|
|
||||||
END
|
|
||||||
|
|
@ -1,62 +0,0 @@
|
||||||
#! armcc -E
|
|
||||||
; Scatter-Loading Description File
|
|
||||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
||||||
; Copyright (c) 2015, STMicroelectronics
|
|
||||||
; All rights reserved.
|
|
||||||
;
|
|
||||||
; Redistribution and use in source and binary forms, with or without
|
|
||||||
; modification, are permitted provided that the following conditions are met:
|
|
||||||
;
|
|
||||||
; 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
; this list of conditions and the following disclaimer.
|
|
||||||
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
; this list of conditions and the following disclaimer in the documentation
|
|
||||||
; and/or other materials provided with the distribution.
|
|
||||||
; 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
; may be used to endorse or promote products derived from this software
|
|
||||||
; without specific prior written permission.
|
|
||||||
;
|
|
||||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
||||||
|
|
||||||
#if !defined(MBED_APP_START)
|
|
||||||
#define MBED_APP_START 0x08000000
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_APP_SIZE)
|
|
||||||
#define MBED_APP_SIZE 0x40000
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_BOOT_STACK_SIZE)
|
|
||||||
#define MBED_BOOT_STACK_SIZE 0x400
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define Stack_Size MBED_BOOT_STACK_SIZE
|
|
||||||
|
|
||||||
; STM32L151RC: 256KB FLASH + 32KB SRAM
|
|
||||||
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
|
|
||||||
|
|
||||||
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
|
|
||||||
; 73 vectors = 292 bytes (0x124) + 0x4(8-byte aligned) to be reserved in RAM
|
|
||||||
RW_IRAM1 (0x20000000+0x128) (0x8000-0x128-Stack_Size) { ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
|
|
||||||
ARM_LIB_STACK (0x20000000+0x8000) EMPTY -Stack_Size { ; stack
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -1,172 +0,0 @@
|
||||||
/* Linker script to configure memory regions. */
|
|
||||||
#if !defined(MBED_APP_START)
|
|
||||||
#define MBED_APP_START 0x08000000
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_APP_SIZE)
|
|
||||||
#define MBED_APP_SIZE 256k
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_BOOT_STACK_SIZE)
|
|
||||||
#define MBED_BOOT_STACK_SIZE 0x400
|
|
||||||
#endif
|
|
||||||
|
|
||||||
STACK_SIZE = MBED_BOOT_STACK_SIZE;
|
|
||||||
|
|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
/* 256KB FLASH, 32KB RAM, Reserve up till 0x13C. There are 0x73 vectors = 292
|
|
||||||
* bytes (0x124) in RAM. But all GCC scripts seem to require BootRAM @0x138
|
|
||||||
* 8-byte aligned(0x13C) = 0x140
|
|
||||||
*/
|
|
||||||
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
|
|
||||||
RAM (rwx) : ORIGIN = 0x20000140, LENGTH = 0x8000-0x140
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Linker script to place sections and symbol values. Should be used together
|
|
||||||
* with other linker script that defines memory regions FLASH and RAM.
|
|
||||||
* It references following symbols, which must be defined in code:
|
|
||||||
* Reset_Handler : Entry of reset handler
|
|
||||||
*
|
|
||||||
* It defines following symbols, which code can use without definition:
|
|
||||||
* __exidx_start
|
|
||||||
* __exidx_end
|
|
||||||
* __etext
|
|
||||||
* __data_start__
|
|
||||||
* __preinit_array_start
|
|
||||||
* __preinit_array_end
|
|
||||||
* __init_array_start
|
|
||||||
* __init_array_end
|
|
||||||
* __fini_array_start
|
|
||||||
* __fini_array_end
|
|
||||||
* __data_end__
|
|
||||||
* __bss_start__
|
|
||||||
* __bss_end__
|
|
||||||
* __end__
|
|
||||||
* end
|
|
||||||
* __HeapLimit
|
|
||||||
* __StackLimit
|
|
||||||
* __StackTop
|
|
||||||
* __stack
|
|
||||||
* _estack
|
|
||||||
*/
|
|
||||||
ENTRY(Reset_Handler)
|
|
||||||
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
KEEP(*(.isr_vector))
|
|
||||||
*(.text*)
|
|
||||||
KEEP(*(.init))
|
|
||||||
KEEP(*(.fini))
|
|
||||||
|
|
||||||
/* .ctors */
|
|
||||||
*crtbegin.o(.ctors)
|
|
||||||
*crtbegin?.o(.ctors)
|
|
||||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
|
||||||
*(SORT(.ctors.*))
|
|
||||||
*(.ctors)
|
|
||||||
|
|
||||||
/* .dtors */
|
|
||||||
*crtbegin.o(.dtors)
|
|
||||||
*crtbegin?.o(.dtors)
|
|
||||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
|
||||||
*(SORT(.dtors.*))
|
|
||||||
*(.dtors)
|
|
||||||
|
|
||||||
*(.rodata*)
|
|
||||||
|
|
||||||
KEEP(*(.eh_frame*))
|
|
||||||
} > FLASH
|
|
||||||
|
|
||||||
.ARM.extab :
|
|
||||||
{
|
|
||||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
|
||||||
} > FLASH
|
|
||||||
|
|
||||||
__exidx_start = .;
|
|
||||||
.ARM.exidx :
|
|
||||||
{
|
|
||||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
|
||||||
} > FLASH
|
|
||||||
__exidx_end = .;
|
|
||||||
|
|
||||||
__etext = .;
|
|
||||||
_sidata = .;
|
|
||||||
|
|
||||||
.data : AT (__etext)
|
|
||||||
{
|
|
||||||
__data_start__ = .;
|
|
||||||
_sdata = .;
|
|
||||||
*(vtable)
|
|
||||||
*(.data*)
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
/* preinit data */
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
|
||||||
KEEP(*(.preinit_array))
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
/* init data */
|
|
||||||
PROVIDE_HIDDEN (__init_array_start = .);
|
|
||||||
KEEP(*(SORT(.init_array.*)))
|
|
||||||
KEEP(*(.init_array))
|
|
||||||
PROVIDE_HIDDEN (__init_array_end = .);
|
|
||||||
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
/* finit data */
|
|
||||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
|
||||||
KEEP(*(SORT(.fini_array.*)))
|
|
||||||
KEEP(*(.fini_array))
|
|
||||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
|
||||||
|
|
||||||
KEEP(*(.jcr*))
|
|
||||||
. = ALIGN(8);
|
|
||||||
/* All data end */
|
|
||||||
__data_end__ = .;
|
|
||||||
_edata = .;
|
|
||||||
|
|
||||||
} > RAM
|
|
||||||
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
__bss_start__ = .;
|
|
||||||
_sbss = .;
|
|
||||||
*(.bss*)
|
|
||||||
*(COMMON)
|
|
||||||
. = ALIGN(8);
|
|
||||||
__bss_end__ = .;
|
|
||||||
_ebss = .;
|
|
||||||
} > RAM
|
|
||||||
|
|
||||||
.heap (COPY):
|
|
||||||
{
|
|
||||||
__end__ = .;
|
|
||||||
end = __end__;
|
|
||||||
*(.heap*)
|
|
||||||
. = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;
|
|
||||||
__HeapLimit = .;
|
|
||||||
} > RAM
|
|
||||||
|
|
||||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
|
||||||
* used for linker to calculate size of stack sections, and assign
|
|
||||||
* values to stack symbols later */
|
|
||||||
.stack_dummy (COPY):
|
|
||||||
{
|
|
||||||
*(.stack*)
|
|
||||||
} > RAM
|
|
||||||
|
|
||||||
/* Set stack top to end of RAM, and stack limit move down by
|
|
||||||
* size of stack_dummy section */
|
|
||||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
|
||||||
_estack = __StackTop;
|
|
||||||
__StackLimit = __StackTop - STACK_SIZE;
|
|
||||||
PROVIDE(__stack = __StackTop);
|
|
||||||
|
|
||||||
/* Check if data + heap + stack exceeds RAM limit */
|
|
||||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
|
||||||
}
|
|
||||||
|
|
@ -1,401 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file startup_stm32l151xc.s
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief STM32L151XC Devices vector table for
|
|
||||||
* Atollic toolchain.
|
|
||||||
* This module performs:
|
|
||||||
* - Set the initial SP
|
|
||||||
* - Set the initial PC == Reset_Handler,
|
|
||||||
* - Set the vector table entries with the exceptions ISR address
|
|
||||||
* - Configure the clock system
|
|
||||||
* - Branches to main in the C library (which eventually
|
|
||||||
* calls main()).
|
|
||||||
* After Reset the Cortex-M3 processor is in Thread mode,
|
|
||||||
* priority is Privileged, and the Stack is set to Main.
|
|
||||||
******************************************************************************
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
.syntax unified
|
|
||||||
.cpu cortex-m3
|
|
||||||
.fpu softvfp
|
|
||||||
.thumb
|
|
||||||
|
|
||||||
.global g_pfnVectors
|
|
||||||
.global Default_Handler
|
|
||||||
|
|
||||||
/* start address for the initialization values of the .data section.
|
|
||||||
defined in linker script */
|
|
||||||
.word _sidata
|
|
||||||
/* start address for the .data section. defined in linker script */
|
|
||||||
.word _sdata
|
|
||||||
/* end address for the .data section. defined in linker script */
|
|
||||||
.word _edata
|
|
||||||
|
|
||||||
.equ BootRAM, 0xF108F85F
|
|
||||||
/**
|
|
||||||
* @brief This is the code that gets called when the processor first
|
|
||||||
* starts execution following a reset event. Only the absolutely
|
|
||||||
* necessary set is performed, after which the application
|
|
||||||
* supplied main() routine is called.
|
|
||||||
* @param None
|
|
||||||
* @retval : None
|
|
||||||
*/
|
|
||||||
|
|
||||||
.section .text.Reset_Handler
|
|
||||||
.weak Reset_Handler
|
|
||||||
.type Reset_Handler, %function
|
|
||||||
Reset_Handler:
|
|
||||||
|
|
||||||
/* Copy the data segment initializers from flash to SRAM */
|
|
||||||
movs r1, #0
|
|
||||||
b LoopCopyDataInit
|
|
||||||
|
|
||||||
CopyDataInit:
|
|
||||||
ldr r3, =_sidata
|
|
||||||
ldr r3, [r3, r1]
|
|
||||||
str r3, [r0, r1]
|
|
||||||
adds r1, r1, #4
|
|
||||||
|
|
||||||
LoopCopyDataInit:
|
|
||||||
ldr r0, =_sdata
|
|
||||||
ldr r3, =_edata
|
|
||||||
adds r2, r0, r1
|
|
||||||
cmp r2, r3
|
|
||||||
bcc CopyDataInit
|
|
||||||
|
|
||||||
/* Call the clock system intitialization function.*/
|
|
||||||
bl SystemInit
|
|
||||||
/* Call static constructors */
|
|
||||||
//bl __libc_init_array
|
|
||||||
/* Call the application's entry point.*/
|
|
||||||
//bl main
|
|
||||||
bl _start
|
|
||||||
.size Reset_Handler, .-Reset_Handler
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This is the code that gets called when the processor receives an
|
|
||||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
|
||||||
* the system state for examination by a debugger.
|
|
||||||
*
|
|
||||||
* @param None
|
|
||||||
* @retval : None
|
|
||||||
*/
|
|
||||||
.section .text.Default_Handler,"ax",%progbits
|
|
||||||
Default_Handler:
|
|
||||||
Infinite_Loop:
|
|
||||||
b Infinite_Loop
|
|
||||||
.size Default_Handler, .-Default_Handler
|
|
||||||
/******************************************************************************
|
|
||||||
*
|
|
||||||
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
|
||||||
* must be placed on this to ensure that it ends up at physical address
|
|
||||||
* 0x0000.0000.
|
|
||||||
*
|
|
||||||
******************************************************************************/
|
|
||||||
.section .isr_vector,"a",%progbits
|
|
||||||
.type g_pfnVectors, %object
|
|
||||||
.size g_pfnVectors, .-g_pfnVectors
|
|
||||||
|
|
||||||
|
|
||||||
g_pfnVectors:
|
|
||||||
.word _estack
|
|
||||||
.word Reset_Handler
|
|
||||||
.word NMI_Handler
|
|
||||||
.word HardFault_Handler
|
|
||||||
.word MemManage_Handler
|
|
||||||
.word BusFault_Handler
|
|
||||||
.word UsageFault_Handler
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word SVC_Handler
|
|
||||||
.word DebugMon_Handler
|
|
||||||
.word 0
|
|
||||||
.word PendSV_Handler
|
|
||||||
.word SysTick_Handler
|
|
||||||
.word WWDG_IRQHandler
|
|
||||||
.word PVD_IRQHandler
|
|
||||||
.word TAMPER_STAMP_IRQHandler
|
|
||||||
.word RTC_WKUP_IRQHandler
|
|
||||||
.word FLASH_IRQHandler
|
|
||||||
.word RCC_IRQHandler
|
|
||||||
.word EXTI0_IRQHandler
|
|
||||||
.word EXTI1_IRQHandler
|
|
||||||
.word EXTI2_IRQHandler
|
|
||||||
.word EXTI3_IRQHandler
|
|
||||||
.word EXTI4_IRQHandler
|
|
||||||
.word DMA1_Channel1_IRQHandler
|
|
||||||
.word DMA1_Channel2_IRQHandler
|
|
||||||
.word DMA1_Channel3_IRQHandler
|
|
||||||
.word DMA1_Channel4_IRQHandler
|
|
||||||
.word DMA1_Channel5_IRQHandler
|
|
||||||
.word DMA1_Channel6_IRQHandler
|
|
||||||
.word DMA1_Channel7_IRQHandler
|
|
||||||
.word ADC1_IRQHandler
|
|
||||||
.word USB_HP_IRQHandler
|
|
||||||
.word USB_LP_IRQHandler
|
|
||||||
.word DAC_IRQHandler
|
|
||||||
.word COMP_IRQHandler
|
|
||||||
.word EXTI9_5_IRQHandler
|
|
||||||
.word 0
|
|
||||||
.word TIM9_IRQHandler
|
|
||||||
.word TIM10_IRQHandler
|
|
||||||
.word TIM11_IRQHandler
|
|
||||||
.word TIM2_IRQHandler
|
|
||||||
.word TIM3_IRQHandler
|
|
||||||
.word TIM4_IRQHandler
|
|
||||||
.word I2C1_EV_IRQHandler
|
|
||||||
.word I2C1_ER_IRQHandler
|
|
||||||
.word I2C2_EV_IRQHandler
|
|
||||||
.word I2C2_ER_IRQHandler
|
|
||||||
.word SPI1_IRQHandler
|
|
||||||
.word SPI2_IRQHandler
|
|
||||||
.word USART1_IRQHandler
|
|
||||||
.word USART2_IRQHandler
|
|
||||||
.word USART3_IRQHandler
|
|
||||||
.word EXTI15_10_IRQHandler
|
|
||||||
.word RTC_Alarm_IRQHandler
|
|
||||||
.word USB_FS_WKUP_IRQHandler
|
|
||||||
.word TIM6_IRQHandler
|
|
||||||
.word TIM7_IRQHandler
|
|
||||||
.word 0
|
|
||||||
.word TIM5_IRQHandler
|
|
||||||
.word SPI3_IRQHandler
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word DMA2_Channel1_IRQHandler
|
|
||||||
.word DMA2_Channel2_IRQHandler
|
|
||||||
.word DMA2_Channel3_IRQHandler
|
|
||||||
.word DMA2_Channel4_IRQHandler
|
|
||||||
.word DMA2_Channel5_IRQHandler
|
|
||||||
.word 0
|
|
||||||
.word COMP_ACQ_IRQHandler
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word BootRAM /* @0x108. This is for boot in RAM mode for
|
|
||||||
STM32L151XC devices. */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
*
|
|
||||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
|
||||||
* As they are weak aliases, any function with the same name will override
|
|
||||||
* this definition.
|
|
||||||
*
|
|
||||||
*******************************************************************************/
|
|
||||||
|
|
||||||
.weak NMI_Handler
|
|
||||||
.thumb_set NMI_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak HardFault_Handler
|
|
||||||
.thumb_set HardFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak MemManage_Handler
|
|
||||||
.thumb_set MemManage_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak BusFault_Handler
|
|
||||||
.thumb_set BusFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak UsageFault_Handler
|
|
||||||
.thumb_set UsageFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak SVC_Handler
|
|
||||||
.thumb_set SVC_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak DebugMon_Handler
|
|
||||||
.thumb_set DebugMon_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak PendSV_Handler
|
|
||||||
.thumb_set PendSV_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak SysTick_Handler
|
|
||||||
.thumb_set SysTick_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak WWDG_IRQHandler
|
|
||||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak PVD_IRQHandler
|
|
||||||
.thumb_set PVD_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TAMPER_STAMP_IRQHandler
|
|
||||||
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RTC_WKUP_IRQHandler
|
|
||||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak FLASH_IRQHandler
|
|
||||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RCC_IRQHandler
|
|
||||||
.thumb_set RCC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI0_IRQHandler
|
|
||||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI1_IRQHandler
|
|
||||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI2_IRQHandler
|
|
||||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI3_IRQHandler
|
|
||||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI4_IRQHandler
|
|
||||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel1_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel2_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel3_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel4_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel5_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel6_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel7_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak ADC1_IRQHandler
|
|
||||||
.thumb_set ADC1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USB_HP_IRQHandler
|
|
||||||
.thumb_set USB_HP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USB_LP_IRQHandler
|
|
||||||
.thumb_set USB_LP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DAC_IRQHandler
|
|
||||||
.thumb_set DAC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak COMP_IRQHandler
|
|
||||||
.thumb_set COMP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI9_5_IRQHandler
|
|
||||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM9_IRQHandler
|
|
||||||
.thumb_set TIM9_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM10_IRQHandler
|
|
||||||
.thumb_set TIM10_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM11_IRQHandler
|
|
||||||
.thumb_set TIM11_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM2_IRQHandler
|
|
||||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM3_IRQHandler
|
|
||||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM4_IRQHandler
|
|
||||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C1_EV_IRQHandler
|
|
||||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C1_ER_IRQHandler
|
|
||||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C2_EV_IRQHandler
|
|
||||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C2_ER_IRQHandler
|
|
||||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI1_IRQHandler
|
|
||||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI2_IRQHandler
|
|
||||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USART1_IRQHandler
|
|
||||||
.thumb_set USART1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USART2_IRQHandler
|
|
||||||
.thumb_set USART2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USART3_IRQHandler
|
|
||||||
.thumb_set USART3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI15_10_IRQHandler
|
|
||||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RTC_Alarm_IRQHandler
|
|
||||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USB_FS_WKUP_IRQHandler
|
|
||||||
.thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM6_IRQHandler
|
|
||||||
.thumb_set TIM6_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM7_IRQHandler
|
|
||||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM5_IRQHandler
|
|
||||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI3_IRQHandler
|
|
||||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel1_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel2_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel3_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel4_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel5_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak COMP_ACQ_IRQHandler
|
|
||||||
.thumb_set COMP_ACQ_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
||||||
|
|
@ -1,536 +0,0 @@
|
||||||
;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
|
|
||||||
;* File Name : startup_stm32l152xc.s
|
|
||||||
;* Author : MCD Application Team
|
|
||||||
;* Version : 21-April-2017
|
|
||||||
;* Date : V2.2.1
|
|
||||||
;* Description : STM32L152XC Devices vector for EWARM toolchain.
|
|
||||||
;* This module performs:
|
|
||||||
;* - Set the initial SP
|
|
||||||
;* - Set the initial PC == __iar_program_start,
|
|
||||||
;* - Set the vector table entries with the exceptions ISR
|
|
||||||
;* address.
|
|
||||||
;* - Configure the system clock
|
|
||||||
;* - Branches to main in the C library (which eventually
|
|
||||||
;* calls main()).
|
|
||||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
|
||||||
;********************************************************************************
|
|
||||||
;*
|
|
||||||
;* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
|
||||||
;*
|
|
||||||
;* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
;* are permitted provided that the following conditions are met:
|
|
||||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
;* this list of conditions and the following disclaimer.
|
|
||||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
;* this list of conditions and the following disclaimer in the documentation
|
|
||||||
;* and/or other materials provided with the distribution.
|
|
||||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
;* may be used to endorse or promote products derived from this software
|
|
||||||
;* without specific prior written permission.
|
|
||||||
;*
|
|
||||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
;*
|
|
||||||
;*******************************************************************************
|
|
||||||
;
|
|
||||||
;
|
|
||||||
; The modules in this file are included in the libraries, and may be replaced
|
|
||||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
|
||||||
; a user defined start symbol.
|
|
||||||
; To override the cstartup defined in the library, simply add your modified
|
|
||||||
; version to the workbench project.
|
|
||||||
;
|
|
||||||
; The vector table is normally located at address 0.
|
|
||||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
|
||||||
; The name "__vector_table" has special meaning for C-SPY:
|
|
||||||
; it is where the SP start value is found, and the NVIC vector
|
|
||||||
; table register (VTOR) is initialized to this address if != 0.
|
|
||||||
;
|
|
||||||
; Cortex-M version
|
|
||||||
;
|
|
||||||
|
|
||||||
MODULE ?cstartup
|
|
||||||
|
|
||||||
;; Forward declaration of sections.
|
|
||||||
SECTION CSTACK:DATA:NOROOT(3)
|
|
||||||
|
|
||||||
SECTION .intvec:CODE:NOROOT(2)
|
|
||||||
|
|
||||||
EXTERN __iar_program_start
|
|
||||||
EXTERN SystemInit
|
|
||||||
PUBLIC __vector_table
|
|
||||||
|
|
||||||
DATA
|
|
||||||
__vector_table
|
|
||||||
DCD sfe(CSTACK)
|
|
||||||
DCD Reset_Handler ; Reset Handler
|
|
||||||
|
|
||||||
DCD NMI_Handler ; NMI Handler
|
|
||||||
DCD HardFault_Handler ; Hard Fault Handler
|
|
||||||
DCD MemManage_Handler ; MPU Fault Handler
|
|
||||||
DCD BusFault_Handler ; Bus Fault Handler
|
|
||||||
DCD UsageFault_Handler ; Usage Fault Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD SVC_Handler ; SVCall Handler
|
|
||||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD PendSV_Handler ; PendSV Handler
|
|
||||||
DCD SysTick_Handler ; SysTick Handler
|
|
||||||
|
|
||||||
; External Interrupts
|
|
||||||
DCD WWDG_IRQHandler ; Window Watchdog
|
|
||||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
|
||||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
|
||||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
|
||||||
DCD FLASH_IRQHandler ; FLASH
|
|
||||||
DCD RCC_IRQHandler ; RCC
|
|
||||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
|
||||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
|
||||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
|
||||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
|
||||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
|
||||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
|
||||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
|
||||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
|
||||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
|
||||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
|
||||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
|
||||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
|
||||||
DCD ADC1_IRQHandler ; ADC1
|
|
||||||
DCD USB_HP_IRQHandler ; USB High Priority
|
|
||||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
|
||||||
DCD DAC_IRQHandler ; DAC
|
|
||||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
|
||||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
|
||||||
DCD LCD_IRQHandler ; LCD
|
|
||||||
DCD TIM9_IRQHandler ; TIM9
|
|
||||||
DCD TIM10_IRQHandler ; TIM10
|
|
||||||
DCD TIM11_IRQHandler ; TIM11
|
|
||||||
DCD TIM2_IRQHandler ; TIM2
|
|
||||||
DCD TIM3_IRQHandler ; TIM3
|
|
||||||
DCD TIM4_IRQHandler ; TIM4
|
|
||||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
|
||||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
|
||||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
|
||||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
|
||||||
DCD SPI1_IRQHandler ; SPI1
|
|
||||||
DCD SPI2_IRQHandler ; SPI2
|
|
||||||
DCD USART1_IRQHandler ; USART1
|
|
||||||
DCD USART2_IRQHandler ; USART2
|
|
||||||
DCD USART3_IRQHandler ; USART3
|
|
||||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
|
||||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
|
||||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
|
||||||
DCD TIM6_IRQHandler ; TIM6
|
|
||||||
DCD TIM7_IRQHandler ; TIM7
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD TIM5_IRQHandler ; TIM5
|
|
||||||
DCD SPI3_IRQHandler ; SPI3
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
|
||||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
|
||||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
|
||||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
|
||||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
|
||||||
|
|
||||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
||||||
;;
|
|
||||||
;; Default interrupt handlers.
|
|
||||||
;;
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
PUBWEAK Reset_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
Reset_Handler
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
LDR R0, =__iar_program_start
|
|
||||||
BX R0
|
|
||||||
|
|
||||||
PUBWEAK NMI_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
NMI_Handler
|
|
||||||
B NMI_Handler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK HardFault_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
HardFault_Handler
|
|
||||||
B HardFault_Handler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK MemManage_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
MemManage_Handler
|
|
||||||
B MemManage_Handler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK BusFault_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
BusFault_Handler
|
|
||||||
B BusFault_Handler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK UsageFault_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
UsageFault_Handler
|
|
||||||
B UsageFault_Handler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK SVC_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
SVC_Handler
|
|
||||||
B SVC_Handler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK DebugMon_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
DebugMon_Handler
|
|
||||||
B DebugMon_Handler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK PendSV_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
PendSV_Handler
|
|
||||||
B PendSV_Handler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK SysTick_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
SysTick_Handler
|
|
||||||
B SysTick_Handler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK WWDG_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
WWDG_IRQHandler
|
|
||||||
B WWDG_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK PVD_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
PVD_IRQHandler
|
|
||||||
B PVD_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK TAMPER_STAMP_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
TAMPER_STAMP_IRQHandler
|
|
||||||
B TAMPER_STAMP_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK RTC_WKUP_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
RTC_WKUP_IRQHandler
|
|
||||||
B RTC_WKUP_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK FLASH_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
FLASH_IRQHandler
|
|
||||||
B FLASH_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK RCC_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
RCC_IRQHandler
|
|
||||||
B RCC_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK EXTI0_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
EXTI0_IRQHandler
|
|
||||||
B EXTI0_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK EXTI1_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
EXTI1_IRQHandler
|
|
||||||
B EXTI1_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK EXTI2_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
EXTI2_IRQHandler
|
|
||||||
B EXTI2_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK EXTI3_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
EXTI3_IRQHandler
|
|
||||||
B EXTI3_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK EXTI4_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
EXTI4_IRQHandler
|
|
||||||
B EXTI4_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel1_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
DMA1_Channel1_IRQHandler
|
|
||||||
B DMA1_Channel1_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel2_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
DMA1_Channel2_IRQHandler
|
|
||||||
B DMA1_Channel2_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel3_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
DMA1_Channel3_IRQHandler
|
|
||||||
B DMA1_Channel3_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel4_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
DMA1_Channel4_IRQHandler
|
|
||||||
B DMA1_Channel4_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel5_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
DMA1_Channel5_IRQHandler
|
|
||||||
B DMA1_Channel5_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel6_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
DMA1_Channel6_IRQHandler
|
|
||||||
B DMA1_Channel6_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel7_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
DMA1_Channel7_IRQHandler
|
|
||||||
B DMA1_Channel7_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK ADC1_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
ADC1_IRQHandler
|
|
||||||
B ADC1_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK USB_HP_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
USB_HP_IRQHandler
|
|
||||||
B USB_HP_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK USB_LP_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
USB_LP_IRQHandler
|
|
||||||
B USB_LP_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK DAC_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
DAC_IRQHandler
|
|
||||||
B DAC_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK COMP_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
COMP_IRQHandler
|
|
||||||
B COMP_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK EXTI9_5_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
EXTI9_5_IRQHandler
|
|
||||||
B EXTI9_5_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK LCD_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
LCD_IRQHandler
|
|
||||||
B LCD_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK TIM9_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
TIM9_IRQHandler
|
|
||||||
B TIM9_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK TIM10_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
TIM10_IRQHandler
|
|
||||||
B TIM10_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK TIM11_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
TIM11_IRQHandler
|
|
||||||
B TIM11_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK TIM2_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
TIM2_IRQHandler
|
|
||||||
B TIM2_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK TIM3_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
TIM3_IRQHandler
|
|
||||||
B TIM3_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK TIM4_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
TIM4_IRQHandler
|
|
||||||
B TIM4_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK I2C1_EV_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
I2C1_EV_IRQHandler
|
|
||||||
B I2C1_EV_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK I2C1_ER_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
I2C1_ER_IRQHandler
|
|
||||||
B I2C1_ER_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK I2C2_EV_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
I2C2_EV_IRQHandler
|
|
||||||
B I2C2_EV_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK I2C2_ER_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
I2C2_ER_IRQHandler
|
|
||||||
B I2C2_ER_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK SPI1_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
SPI1_IRQHandler
|
|
||||||
B SPI1_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK SPI2_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
SPI2_IRQHandler
|
|
||||||
B SPI2_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK USART1_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
USART1_IRQHandler
|
|
||||||
B USART1_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK USART2_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
USART2_IRQHandler
|
|
||||||
B USART2_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK USART3_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
USART3_IRQHandler
|
|
||||||
B USART3_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK EXTI15_10_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
EXTI15_10_IRQHandler
|
|
||||||
B EXTI15_10_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK RTC_Alarm_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
RTC_Alarm_IRQHandler
|
|
||||||
B RTC_Alarm_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK USB_FS_WKUP_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
USB_FS_WKUP_IRQHandler
|
|
||||||
B USB_FS_WKUP_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK TIM6_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
TIM6_IRQHandler
|
|
||||||
B TIM6_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK TIM7_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
TIM7_IRQHandler
|
|
||||||
B TIM7_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK TIM5_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
TIM5_IRQHandler
|
|
||||||
B TIM5_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SPI3_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
SPI3_IRQHandler
|
|
||||||
B SPI3_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel1_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
DMA2_Channel1_IRQHandler
|
|
||||||
B DMA2_Channel1_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel2_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
DMA2_Channel2_IRQHandler
|
|
||||||
B DMA2_Channel2_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel3_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
DMA2_Channel3_IRQHandler
|
|
||||||
B DMA2_Channel3_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel4_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
DMA2_Channel4_IRQHandler
|
|
||||||
B DMA2_Channel4_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel5_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
DMA2_Channel5_IRQHandler
|
|
||||||
B DMA2_Channel5_IRQHandler
|
|
||||||
|
|
||||||
|
|
||||||
PUBWEAK COMP_ACQ_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
COMP_ACQ_IRQHandler
|
|
||||||
B COMP_ACQ_IRQHandler
|
|
||||||
|
|
||||||
END
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,35 +0,0 @@
|
||||||
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
|
|
||||||
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x40000; }
|
|
||||||
/* [ROM = 256kb = 0x40000] */
|
|
||||||
define symbol __intvec_start__ = MBED_APP_START;
|
|
||||||
define symbol __region_ROM_start__ = MBED_APP_START;
|
|
||||||
define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
|
|
||||||
|
|
||||||
/* [RAM = 32kb = 0x8000] Vector table dynamic copy: 73 vectors = 292 bytes (0x124) to be reserved in RAM */
|
|
||||||
define symbol __NVIC_start__ = 0x20000000;
|
|
||||||
define symbol __NVIC_end__ = 0x20000127; /* Add 4 more bytes to be aligned on 8 bytes */
|
|
||||||
define symbol __region_RAM_start__ = 0x20000128;
|
|
||||||
define symbol __region_RAM_end__ = 0x20007FFF;
|
|
||||||
|
|
||||||
/* Memory regions */
|
|
||||||
define memory mem with size = 4G;
|
|
||||||
define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
|
|
||||||
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
|
|
||||||
|
|
||||||
/* Stack and Heap */
|
|
||||||
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
|
|
||||||
define symbol MBED_BOOT_STACK_SIZE = 0x400;
|
|
||||||
}
|
|
||||||
define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE;
|
|
||||||
define symbol __size_heap__ = 0x800;
|
|
||||||
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
|
||||||
define block HEAP with alignment = 8, size = __size_heap__ { };
|
|
||||||
define block STACKHEAP with fixed order { block HEAP, block CSTACK };
|
|
||||||
|
|
||||||
initialize by copy with packing = zeros { readwrite };
|
|
||||||
do not initialize { section .noinit };
|
|
||||||
|
|
||||||
place at address mem:__intvec_start__ { readonly section .intvec };
|
|
||||||
|
|
||||||
place in ROM_region { readonly };
|
|
||||||
place in RAM_region { readwrite, block STACKHEAP };
|
|
||||||
|
|
@ -1,41 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2015, STMicroelectronics
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
|
||||||
#define MBED_CMSIS_NVIC_H
|
|
||||||
|
|
||||||
// STM32L151CC
|
|
||||||
// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
|
|
||||||
// MCU Peripherals: 57 vectors = 228 bytes from 0x40 to 0x123
|
|
||||||
// Total: 73 vectors = 292 bytes (0x124) to be reserved in RAM
|
|
||||||
#define NVIC_NUM_VECTORS 73
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM
|
|
||||||
|
|
||||||
#endif
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,261 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32l1xx.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief CMSIS STM32L1xx Device Peripheral Access Layer Header File.
|
|
||||||
*
|
|
||||||
* The file is the unique include file that the application programmer
|
|
||||||
* is using in the C source code, usually in main.c. This file contains:
|
|
||||||
* - Configuration section that allows to select:
|
|
||||||
* - The STM32L1xx device used in the target application
|
|
||||||
* - To use or not the peripheral’s drivers in application code(i.e.
|
|
||||||
* code will be based on direct access to peripheral’s registers
|
|
||||||
* rather than drivers API), this option is controlled by
|
|
||||||
* "#define USE_HAL_DRIVER"
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup CMSIS
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup stm32l1xx
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __STM32L1XX_H
|
|
||||||
#define __STM32L1XX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
|
|
||||||
/** @addtogroup Library_configuration_section
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief STM32 Family
|
|
||||||
*/
|
|
||||||
#if !defined (STM32L1)
|
|
||||||
#define STM32L1
|
|
||||||
#endif /* STM32L1 */
|
|
||||||
|
|
||||||
/* Uncomment the line below according to the target STM32L device used in your
|
|
||||||
application
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \
|
|
||||||
!defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xDX) && !defined (STM32L151xE) && \
|
|
||||||
!defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xDX) && !defined (STM32L152xE) && \
|
|
||||||
!defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xDX) && !defined (STM32L162xE)
|
|
||||||
/* #define STM32L100xB */ /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */
|
|
||||||
/* #define STM32L100xBA */ /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */
|
|
||||||
/* #define STM32L100xC */ /*!< STM32L100RC Devices */
|
|
||||||
/* #define STM32L151xB */ /*!< STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB and STM32L151VB */
|
|
||||||
/* #define STM32L151xBA */ /*!< STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A and STM32L151VB-A */
|
|
||||||
#define STM32L151xC /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */
|
|
||||||
/* #define STM32L151xCA */ /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */
|
|
||||||
/* #define STM32L151xD */ /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */
|
|
||||||
/* #define STM32L151xDX */ /*!< STM32L151VD-X Devices */
|
|
||||||
/* #define STM32L151xE */ /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */
|
|
||||||
/* #define STM32L152xB */ /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */
|
|
||||||
/* #define STM32L152xBA */ /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */
|
|
||||||
/* #define STM32L152xC */ /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */
|
|
||||||
/* #define STM32L152xCA */ /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */
|
|
||||||
/* #define STM32L152xD */ /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */
|
|
||||||
/* #define STM32L152xDX */ /*!< STM32L152VD-X Devices */
|
|
||||||
/* #define STM32L152xE */ /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */
|
|
||||||
/* #define STM32L162xC */ /*!< STM32L162RC and STM32L162VC */
|
|
||||||
/* #define STM32L162xCA */ /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */
|
|
||||||
/* #define STM32L162xD */ /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */
|
|
||||||
/* #define STM32L162xDX */ /*!< STM32L162VD-X Devices */
|
|
||||||
/* #define STM32L162xE */ /*!< STM32L162RE, STM32L162VE and STM32L162ZE */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
|
||||||
devices, you can define the device in your toolchain compiler preprocessor.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if !defined (USE_HAL_DRIVER)
|
|
||||||
/**
|
|
||||||
* @brief Comment the line below if you will not use the peripherals drivers.
|
|
||||||
In this case, these drivers will not be included and the application code will
|
|
||||||
be based on direct access to peripherals registers
|
|
||||||
*/
|
|
||||||
#define USE_HAL_DRIVER
|
|
||||||
#endif /* USE_HAL_DRIVER */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief CMSIS Device version number
|
|
||||||
*/
|
|
||||||
#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
|
||||||
#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
|
||||||
#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
|
|
||||||
#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
|
||||||
#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
|
|
||||||
|(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\
|
|
||||||
|(__STM32L1xx_CMSIS_VERSION_SUB2 << 8 )\
|
|
||||||
|(__STM32L1xx_CMSIS_VERSION_RC))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup Device_Included
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined(STM32L100xB)
|
|
||||||
#include "stm32l100xb.h"
|
|
||||||
#elif defined(STM32L100xBA)
|
|
||||||
#include "stm32l100xba.h"
|
|
||||||
#elif defined(STM32L100xC)
|
|
||||||
#include "stm32l100xc.h"
|
|
||||||
#elif defined(STM32L151xB)
|
|
||||||
#include "stm32l151xb.h"
|
|
||||||
#elif defined(STM32L151xBA)
|
|
||||||
#include "stm32l151xba.h"
|
|
||||||
#elif defined(STM32L151xC)
|
|
||||||
#include "stm32l151xc.h"
|
|
||||||
#elif defined(STM32L151xCA)
|
|
||||||
#include "stm32l151xca.h"
|
|
||||||
#elif defined(STM32L151xD)
|
|
||||||
#include "stm32l151xd.h"
|
|
||||||
#elif defined(STM32L151xDX)
|
|
||||||
#include "stm32l151xdx.h"
|
|
||||||
#elif defined(STM32L151xE)
|
|
||||||
#include "stm32l151xe.h"
|
|
||||||
#elif defined(STM32L152xB)
|
|
||||||
#include "stm32l152xb.h"
|
|
||||||
#elif defined(STM32L152xBA)
|
|
||||||
#include "stm32l152xba.h"
|
|
||||||
#elif defined(STM32L152xC)
|
|
||||||
#include "stm32l152xc.h"
|
|
||||||
#elif defined(STM32L152xCA)
|
|
||||||
#include "stm32l152xca.h"
|
|
||||||
#elif defined(STM32L152xD)
|
|
||||||
#include "stm32l152xd.h"
|
|
||||||
#elif defined(STM32L152xDX)
|
|
||||||
#include "stm32l152xdx.h"
|
|
||||||
#elif defined(STM32L152xE)
|
|
||||||
#include "stm32l152xe.h"
|
|
||||||
#elif defined(STM32L162xC)
|
|
||||||
#include "stm32l162xc.h"
|
|
||||||
#elif defined(STM32L162xCA)
|
|
||||||
#include "stm32l162xca.h"
|
|
||||||
#elif defined(STM32L162xD)
|
|
||||||
#include "stm32l162xd.h"
|
|
||||||
#elif defined(STM32L162xDX)
|
|
||||||
#include "stm32l162xdx.h"
|
|
||||||
#elif defined(STM32L162xE)
|
|
||||||
#include "stm32l162xe.h"
|
|
||||||
#else
|
|
||||||
#error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup Exported_types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
RESET = 0,
|
|
||||||
SET = !RESET
|
|
||||||
} FlagStatus, ITStatus;
|
|
||||||
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
DISABLE = 0,
|
|
||||||
ENABLE = !DISABLE
|
|
||||||
} FunctionalState;
|
|
||||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
|
||||||
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
ERROR = 0,
|
|
||||||
SUCCESS = !ERROR
|
|
||||||
} ErrorStatus;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @addtogroup Exported_macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
|
||||||
|
|
||||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
|
||||||
|
|
||||||
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
|
||||||
|
|
||||||
#define CLEAR_REG(REG) ((REG) = (0x0))
|
|
||||||
|
|
||||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
|
||||||
|
|
||||||
#define READ_REG(REG) ((REG))
|
|
||||||
|
|
||||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
|
||||||
|
|
||||||
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined (USE_HAL_DRIVER)
|
|
||||||
#include "stm32l1xx_hal.h"
|
|
||||||
#endif /* USE_HAL_DRIVER */
|
|
||||||
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
|
|
||||||
#endif /* __STM32L1xx_H */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,252 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* Copyright (c) 2006-2017 ARM Limited
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* This file configures the system clock as follows:
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
|
|
||||||
* | (external 24 MHz clock) | (internal 16 MHz)
|
|
||||||
* | 2- PLL_HSE_XTAL |
|
|
||||||
* | (external 24 MHz xtal) |
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* SYSCLK(MHz) | 32 | 32
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* AHBCLK (MHz) | 32 | 32
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* APB1CLK (MHz) | 32 | 32
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* APB2CLK (MHz) | 32 | 32
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* USB capable (48 MHz precise clock) | YES | NO
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "stm32l1xx.h"
|
|
||||||
#include "stdio.h"
|
|
||||||
#include "mbed_debug.h"
|
|
||||||
|
|
||||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
|
||||||
Internal SRAM. */
|
|
||||||
/* #define VECT_TAB_SRAM */
|
|
||||||
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
|
|
||||||
This value must be a multiple of 0x200. */
|
|
||||||
|
|
||||||
/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
|
|
||||||
#define USE_PLL_HSE_EXTC (0) /* Use external clock */
|
|
||||||
#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
|
|
||||||
|
|
||||||
|
|
||||||
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
|
||||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
uint8_t SetSysClock_PLL_HSI(void);
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Setup the microcontroller system.
|
|
||||||
* Initialize the Embedded Flash Interface, the PLL and update the
|
|
||||||
* SystemCoreClock variable.
|
|
||||||
* @param None
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void SystemInit (void)
|
|
||||||
{
|
|
||||||
/*!< Set MSION bit */
|
|
||||||
RCC->CR |= (uint32_t)0x00000100;
|
|
||||||
|
|
||||||
/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
|
|
||||||
RCC->CFGR &= (uint32_t)0x88FFC00C;
|
|
||||||
|
|
||||||
/*!< Reset HSION, HSEON, CSSON and PLLON bits */
|
|
||||||
RCC->CR &= (uint32_t)0xEEFEFFFE;
|
|
||||||
|
|
||||||
/*!< Reset HSEBYP bit */
|
|
||||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
|
||||||
|
|
||||||
/*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
|
|
||||||
RCC->CFGR &= (uint32_t)0xFF02FFFF;
|
|
||||||
|
|
||||||
/*!< Disable all interrupts */
|
|
||||||
RCC->CIR = 0x00000000;
|
|
||||||
|
|
||||||
#ifdef DATA_IN_ExtSRAM
|
|
||||||
SystemInit_ExtMemCtl();
|
|
||||||
#endif /* DATA_IN_ExtSRAM */
|
|
||||||
|
|
||||||
|
|
||||||
#if defined(__ICCARM__)
|
|
||||||
#pragma section=".intvec"
|
|
||||||
#define FLASH_VTOR_BASE ((uint32_t)__section_begin(".intvec"))
|
|
||||||
#elif defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
|
||||||
extern uint32_t Load$$LR$$LR_IROM1$$Base[];
|
|
||||||
#define FLASH_VTOR_BASE ((uint32_t)Load$$LR$$LR_IROM1$$Base)
|
|
||||||
#elif defined(__GNUC__)
|
|
||||||
extern uint32_t g_pfnVectors[];
|
|
||||||
#define FLASH_VTOR_BASE ((uint32_t)g_pfnVectors)
|
|
||||||
#else
|
|
||||||
#error "Flash vector address not set for this toolchain"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef VECT_TAB_SRAM
|
|
||||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
|
|
||||||
#else
|
|
||||||
SCB->VTOR = FLASH_VTOR_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
|
||||||
* AHB/APBx prescalers and Flash settings
|
|
||||||
* @note This function should be called only once the RCC clock configuration
|
|
||||||
* is reset to the default reset state (done in SystemInit() function).
|
|
||||||
* @param None
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void SetSysClock(void)
|
|
||||||
{
|
|
||||||
/* 1- Try to start with HSE and external clock */
|
|
||||||
#if USE_PLL_HSE_EXTC != 0
|
|
||||||
if (SetSysClock_PLL_HSE(1) == 0)
|
|
||||||
#endif
|
|
||||||
{
|
|
||||||
/* 2- If fail try to start with HSE and external xtal */
|
|
||||||
#if USE_PLL_HSE_XTAL != 0
|
|
||||||
if (SetSysClock_PLL_HSE(0) == 0)
|
|
||||||
#endif
|
|
||||||
{
|
|
||||||
/* 3- If fail start with HSI clock */
|
|
||||||
if (SetSysClock_PLL_HSI() == 0) {
|
|
||||||
while(1) {
|
|
||||||
// [TODO] Put something here to tell the user that a problem occured...
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Output clock on MCO1 pin(PA8) for debugging purpose */
|
|
||||||
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
|
|
||||||
}
|
|
||||||
|
|
||||||
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
|
||||||
/******************************************************************************/
|
|
||||||
/* PLL (clocked by HSE) used as System clock source */
|
|
||||||
/******************************************************************************/
|
|
||||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
|
||||||
{
|
|
||||||
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
|
||||||
RCC_OscInitTypeDef RCC_OscInitStruct;
|
|
||||||
|
|
||||||
/* Used to gain time after DeepSleep in case HSI is used */
|
|
||||||
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* The voltage scaling allows optimizing the power consumption when the device is
|
|
||||||
clocked below the maximum system frequency, to update the voltage scaling value
|
|
||||||
regarding system frequency refer to product datasheet. */
|
|
||||||
__PWR_CLK_ENABLE();
|
|
||||||
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
||||||
|
|
||||||
/* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
|
|
||||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
|
||||||
if (bypass == 0) {
|
|
||||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 24 MHz xtal on OSC_IN/OSC_OUT */
|
|
||||||
} else {
|
|
||||||
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 24 MHz clock on OSC_IN */
|
|
||||||
}
|
|
||||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
|
||||||
// SYSCLK = 32 MHz ((24 MHz * 4) / 3)
|
|
||||||
// USBCLK = 48 MHz ((24 MHz * 4) / 2) --> USB OK
|
|
||||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
||||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
|
||||||
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
|
|
||||||
RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3;
|
|
||||||
|
|
||||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
|
||||||
return 0; // FAIL
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
|
|
||||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
|
||||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
|
|
||||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
|
|
||||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
|
|
||||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
|
|
||||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
|
|
||||||
return 0; // FAIL
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Output clock on MCO1 pin(PA8) for debugging purpose */
|
|
||||||
//if (bypass == 0)
|
|
||||||
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
|
|
||||||
//else
|
|
||||||
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
|
|
||||||
|
|
||||||
return 1; // OK
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/******************************************************************************/
|
|
||||||
/* PLL (clocked by HSI) used as System clock source */
|
|
||||||
/******************************************************************************/
|
|
||||||
uint8_t SetSysClock_PLL_HSI(void)
|
|
||||||
{
|
|
||||||
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
|
||||||
RCC_OscInitTypeDef RCC_OscInitStruct;
|
|
||||||
|
|
||||||
/* The voltage scaling allows optimizing the power consumption when the device is
|
|
||||||
clocked below the maximum system frequency, to update the voltage scaling value
|
|
||||||
regarding system frequency refer to product datasheet. */
|
|
||||||
__PWR_CLK_ENABLE();
|
|
||||||
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
||||||
|
|
||||||
/* Enable HSI oscillator and activate PLL with HSI as source */
|
|
||||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
|
|
||||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
|
||||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
|
||||||
// SYSCLK = 32 MHz ((16 MHz * 4) / 2)
|
|
||||||
// USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
|
|
||||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
||||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
|
|
||||||
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
|
|
||||||
RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2;
|
|
||||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
|
||||||
return 0; // FAIL
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
|
|
||||||
while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
|
|
||||||
|
|
||||||
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
|
|
||||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
|
||||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
|
|
||||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
|
|
||||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
|
|
||||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
|
|
||||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
|
|
||||||
return 0; // FAIL
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Output clock on MCO1 pin(PA8) for debugging purpose */
|
|
||||||
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
|
|
||||||
|
|
||||||
return 1; // OK
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -1,126 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file system_stm32l1xx.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup CMSIS
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup stm32l1xx_system
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Define to prevent recursive inclusion
|
|
||||||
*/
|
|
||||||
#ifndef __SYSTEM_STM32L1XX_H
|
|
||||||
#define __SYSTEM_STM32L1XX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_System_Includes
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_System_Exported_types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* This variable is updated in three ways:
|
|
||||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
|
||||||
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
|
|
||||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
|
||||||
Note: If you use this function to configure the system clock; then there
|
|
||||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
|
||||||
variable is updated automatically.
|
|
||||||
*/
|
|
||||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
|
||||||
/*
|
|
||||||
*/
|
|
||||||
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
|
|
||||||
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
|
|
||||||
extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_System_Exported_Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_System_Exported_Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup STM32L1xx_System_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
extern void SystemInit(void);
|
|
||||||
extern void SystemCoreClockUpdate(void);
|
|
||||||
extern void SetSysClock(void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /*__SYSTEM_STM32L1XX_H */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,45 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* Copyright (c) 2006-2018 ARM Limited
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
#ifndef __US_TICKER_DATA_H
|
|
||||||
#define __US_TICKER_DATA_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#include "stm32l1xx.h"
|
|
||||||
#include "stm32l1xx_ll_tim.h"
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define TIM_MST TIM5
|
|
||||||
#define TIM_MST_IRQ TIM5_IRQn
|
|
||||||
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
|
|
||||||
#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5()
|
|
||||||
|
|
||||||
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
|
|
||||||
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
|
|
||||||
|
|
||||||
#define TIM_MST_BIT_WIDTH 32 // 16 or 32
|
|
||||||
|
|
||||||
#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
|
|
||||||
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif // __US_TICKER_DATA_H
|
|
||||||
|
|
||||||
|
|
@ -1,64 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2016, STMicroelectronics
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#ifndef MBED_OBJECTS_H
|
|
||||||
#define MBED_OBJECTS_H
|
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
#include "PortNames.h"
|
|
||||||
#include "PeripheralNames.h"
|
|
||||||
#include "PinNames.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
struct gpio_irq_s {
|
|
||||||
IRQn_Type irq_n;
|
|
||||||
uint32_t irq_index;
|
|
||||||
uint32_t event;
|
|
||||||
PinName pin;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct port_s {
|
|
||||||
PortName port;
|
|
||||||
uint32_t mask;
|
|
||||||
PinDirection direction;
|
|
||||||
__IO uint32_t *reg_in;
|
|
||||||
__IO uint32_t *reg_out;
|
|
||||||
};
|
|
||||||
|
|
||||||
#define GPIO_IP_WITHOUT_BRR
|
|
||||||
#include "common_objects.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,287 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2016, MultiTech Systems
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of MultiTech nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "xdot_eeprom.h"
|
|
||||||
|
|
||||||
#define XDOT_EEPROM_START 0x08080000
|
|
||||||
#define XDOT_EEPROM_SIZE 0x00002000
|
|
||||||
|
|
||||||
typedef union {
|
|
||||||
uint32_t *w;
|
|
||||||
uint8_t *b;
|
|
||||||
} b2w;
|
|
||||||
|
|
||||||
typedef union {
|
|
||||||
uint16_t *hw;
|
|
||||||
uint8_t *b;
|
|
||||||
} b2hw;
|
|
||||||
|
|
||||||
enum {
|
|
||||||
byte_write = 0,
|
|
||||||
hword_write,
|
|
||||||
word_write
|
|
||||||
};
|
|
||||||
|
|
||||||
static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data)
|
|
||||||
{
|
|
||||||
if (addr > XDOT_EEPROM_SIZE - 1) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_BYTE, XDOT_EEPROM_START + addr, (uint32_t)data) != HAL_OK) {
|
|
||||||
return -1;
|
|
||||||
} else {
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data)
|
|
||||||
{
|
|
||||||
if (addr > XDOT_EEPROM_SIZE - 2) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_HALFWORD, XDOT_EEPROM_START + addr, (uint32_t)data) != HAL_OK) {
|
|
||||||
return -1;
|
|
||||||
} else {
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static int xdot_eeprom_write_word(uint32_t addr, uint32_t data)
|
|
||||||
{
|
|
||||||
if (addr > XDOT_EEPROM_SIZE - 4) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_WORD, XDOT_EEPROM_START + addr, (uint32_t)data) != HAL_OK) {
|
|
||||||
return -1;
|
|
||||||
} else {
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static int xdot_eeprom_read_byte(uint32_t addr, uint8_t *data)
|
|
||||||
{
|
|
||||||
if (addr > XDOT_EEPROM_SIZE - 1) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
*data = (*((uint8_t *)(XDOT_EEPROM_START + addr)));
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
int xdot_eeprom_write_buf(uint32_t addr, uint8_t *buf, uint32_t size)
|
|
||||||
{
|
|
||||||
uint32_t bytes_written = 0;
|
|
||||||
|
|
||||||
if (addr + size > XDOT_EEPROM_SIZE) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
HAL_FLASHEx_DATAEEPROM_Unlock();
|
|
||||||
|
|
||||||
while (bytes_written < size) {
|
|
||||||
uint32_t bytes_remaining = size - bytes_written;
|
|
||||||
uint32_t current_addr = addr + bytes_written;
|
|
||||||
uint8_t write_type = 0xFF;
|
|
||||||
uint8_t mismatch[4];
|
|
||||||
uint8_t match_byte = 0xFF;
|
|
||||||
b2w byte2word;
|
|
||||||
b2hw byte2hword;
|
|
||||||
//printf("0x%04X (%lu) bytes remaining\r\n", bytes_remaining, bytes_remaining);
|
|
||||||
//printf("addr 0x%04X\t%d\r\n", current_addr, current_addr % 4);
|
|
||||||
|
|
||||||
mismatch[0] = mismatch[1] = mismatch[2] = mismatch[3] = 0;
|
|
||||||
|
|
||||||
if ((current_addr % 4 == 0) && bytes_remaining >= 4) {
|
|
||||||
// aligned for word write
|
|
||||||
//printf("aligned for word write\r\n");
|
|
||||||
//printf("addr\tcurrent\t\tnew\r\n");
|
|
||||||
for (int i = 0; i < 4; i++) {
|
|
||||||
if (xdot_eeprom_read_byte(current_addr + i, &match_byte)) {
|
|
||||||
HAL_FLASHEx_DATAEEPROM_Lock();
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
//printf("0x%04X\t0x%08X\t0x%08X\t", current_addr + i, match_byte, buf[bytes_written + i]);
|
|
||||||
if (match_byte != buf[bytes_written + i]) {
|
|
||||||
mismatch[i] = 1;
|
|
||||||
}
|
|
||||||
//printf("%smatch\r\n", mismatch[i] ? "mis" : "");
|
|
||||||
}
|
|
||||||
if (!(mismatch[0] || mismatch[1] || mismatch[2] || mismatch[3])) {
|
|
||||||
//printf("all match - no write necessary\r\n");
|
|
||||||
bytes_written += 4;
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if ((mismatch[0] || mismatch[1]) && (mismatch[2] || mismatch[3])) {
|
|
||||||
// if at least one of byte 1 or byte 2 and one of byte 3 or byte 4 needs to be written, write a word
|
|
||||||
// this should also account for all 3 or 4 byte combinations as well
|
|
||||||
write_type = word_write;
|
|
||||||
} else if ((mismatch[0] && mismatch[1]) || (mismatch[2] && mismatch[3])) {
|
|
||||||
// if only bytes 1 and 2 or only bytes 3 and 4 need to be written, write a half-word
|
|
||||||
write_type = hword_write;
|
|
||||||
// increment bytes_written if we're skipping bytes that match
|
|
||||||
if (mismatch[2] && mismatch[3]) {
|
|
||||||
bytes_written += 2;
|
|
||||||
current_addr += 2;
|
|
||||||
}
|
|
||||||
} else if (mismatch[0] || mismatch[1] || mismatch[2] || mismatch[3]) {
|
|
||||||
// anything else is just a byte write
|
|
||||||
write_type = byte_write;
|
|
||||||
// increment bytes_written if we're skipping bytes that match
|
|
||||||
if (mismatch[1]) {
|
|
||||||
bytes_written += 1;
|
|
||||||
current_addr += 1;
|
|
||||||
} else if (mismatch[2]) {
|
|
||||||
bytes_written += 2;
|
|
||||||
current_addr += 2;
|
|
||||||
} else if (mismatch[3]) {
|
|
||||||
bytes_written += 3;
|
|
||||||
current_addr += 3;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
} else if ((current_addr % 2 == 0) && bytes_remaining >= 2) {
|
|
||||||
// aligned for half word write
|
|
||||||
//printf("aligned for half word write\r\n");
|
|
||||||
//printf("addr\tcurrent\t\tnew\r\n");
|
|
||||||
for (int i = 0; i < 2; i++) {
|
|
||||||
if (xdot_eeprom_read_byte(current_addr + i, &match_byte)) {
|
|
||||||
HAL_FLASHEx_DATAEEPROM_Lock();
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
//printf("0x%04X\t0x%08X\t0x%08X\t", current_addr + i, match_byte, buf[bytes_written + i]);
|
|
||||||
if (match_byte != buf[bytes_written + i]) {
|
|
||||||
mismatch[i] = 1;
|
|
||||||
}
|
|
||||||
//printf("%smatch\r\n", mismatch[i] ? "mis" : "");
|
|
||||||
}
|
|
||||||
if (!(mismatch[0] || mismatch[1])) {
|
|
||||||
//printf("all match - no write necessary\r\n");
|
|
||||||
bytes_written += 2;
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (mismatch[0] && mismatch[1]) {
|
|
||||||
// if bytes 1 and 2 need to be written, we truly want to write a half word
|
|
||||||
write_type = hword_write;
|
|
||||||
} else {
|
|
||||||
// anything else is just a byte write
|
|
||||||
write_type = byte_write;
|
|
||||||
// increment bytes_written if we're skipping bytes that match
|
|
||||||
if (mismatch[1]) {
|
|
||||||
bytes_written += 1;
|
|
||||||
current_addr += 1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
// aligned for byte write
|
|
||||||
//printf("aligned for byte write\r\n");
|
|
||||||
//printf("addr\tcurrent\t\tnew\r\n");
|
|
||||||
for (int i = 0; i < 1; i++) {
|
|
||||||
if (xdot_eeprom_read_byte(current_addr + i, &match_byte)) {
|
|
||||||
HAL_FLASHEx_DATAEEPROM_Lock();
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
//printf("0x%04X\t0x%08X\t0x%08X\t", current_addr + i, match_byte, buf[bytes_written + i]);
|
|
||||||
if (match_byte != buf[bytes_written + i]) {
|
|
||||||
mismatch[i] = 1;
|
|
||||||
}
|
|
||||||
//printf("%smatch\r\n", mismatch[i] ? "mis" : "");
|
|
||||||
}
|
|
||||||
if (! mismatch[0]) {
|
|
||||||
//printf("all match - no write necessary\r\n");
|
|
||||||
bytes_written += 1;
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
write_type = byte_write;
|
|
||||||
}
|
|
||||||
|
|
||||||
switch (write_type) {
|
|
||||||
case word_write:
|
|
||||||
// we can write a word (32 bits)
|
|
||||||
//printf("word write\r\n");
|
|
||||||
byte2word.b = buf + bytes_written;
|
|
||||||
if (xdot_eeprom_write_word(current_addr, *byte2word.w)) {
|
|
||||||
HAL_FLASHEx_DATAEEPROM_Lock();
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
bytes_written += 4;
|
|
||||||
break;
|
|
||||||
case hword_write:
|
|
||||||
// we can write a half-word (16 bits)
|
|
||||||
//printf("half-word write\r\n");
|
|
||||||
byte2hword.b = buf + bytes_written;
|
|
||||||
if (xdot_eeprom_write_hword(current_addr, *byte2hword.hw)) {
|
|
||||||
HAL_FLASHEx_DATAEEPROM_Lock();
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
bytes_written += 2;
|
|
||||||
break;
|
|
||||||
case byte_write:
|
|
||||||
// we can write a byte (8 bits)
|
|
||||||
//printf("byte write\r\n");
|
|
||||||
if (xdot_eeprom_write_byte(current_addr, buf[bytes_written])) {
|
|
||||||
HAL_FLASHEx_DATAEEPROM_Lock();
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
bytes_written += 1;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
//printf("no write needed\r\n");
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
HAL_FLASHEx_DATAEEPROM_Lock();
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int xdot_eeprom_read_buf(uint32_t addr, uint8_t *buf, uint32_t size)
|
|
||||||
{
|
|
||||||
if (addr + size > XDOT_EEPROM_SIZE) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
HAL_FLASHEx_DATAEEPROM_Unlock();
|
|
||||||
|
|
||||||
for (uint32_t i = 0; i < size; i++) {
|
|
||||||
if (xdot_eeprom_read_byte(addr + i, buf + i)) {
|
|
||||||
HAL_FLASHEx_DATAEEPROM_Lock();
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
HAL_FLASHEx_DATAEEPROM_Lock();
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
@ -1,63 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2016, MultiTech Systems
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of MultiTech nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __XDOT_EEPROM_H__
|
|
||||||
#define __XDOT_EEPROM_H__
|
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* xdot_eeprom_write_buf
|
|
||||||
* attempts to write size bytes from buf to addr
|
|
||||||
* implements read-before-write because writes are expensive
|
|
||||||
* uses most efficient write possible (byte, half-word, or word write) based on alignment
|
|
||||||
* and number of bytes that need to be written
|
|
||||||
* buf must be non-null and size bytes or larger
|
|
||||||
* valid addresses are 0x0000 - 0x1FFF
|
|
||||||
* returns 0 if all data was successfully written otherwise -1
|
|
||||||
*/
|
|
||||||
int xdot_eeprom_write_buf(uint32_t addr, uint8_t *buf, uint32_t size);
|
|
||||||
|
|
||||||
/* xdot_eeprom_read_buf
|
|
||||||
* attempts to read size bytes into buf starting at addr
|
|
||||||
* buf must be non-null and size bytes or larger
|
|
||||||
* valid addresses are 0x0000 - 0x1FFF
|
|
||||||
* returns 0 if all data was successfully read otherwise -1
|
|
||||||
*/
|
|
||||||
int xdot_eeprom_read_buf(uint32_t addr, uint8_t *buf, uint32_t size);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __XDOT_EEPROM_H__ */
|
|
||||||
|
|
@ -1,313 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2016, MultiTech Systems
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of MultiTech nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "xdot_low_power.h"
|
|
||||||
#include "stdio.h"
|
|
||||||
#include "mbed_debug.h"
|
|
||||||
|
|
||||||
static uint32_t portA[6];
|
|
||||||
static uint32_t portB[6];
|
|
||||||
static uint32_t portC[6];
|
|
||||||
static uint32_t portH[6];
|
|
||||||
|
|
||||||
void xdot_disable_systick_int()
|
|
||||||
{
|
|
||||||
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
|
|
||||||
}
|
|
||||||
|
|
||||||
void xdot_enable_systick_int()
|
|
||||||
{
|
|
||||||
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
|
|
||||||
}
|
|
||||||
|
|
||||||
void xdot_save_gpio_state()
|
|
||||||
{
|
|
||||||
portA[0] = GPIOA->MODER;
|
|
||||||
portA[1] = GPIOA->OTYPER;
|
|
||||||
portA[2] = GPIOA->OSPEEDR;
|
|
||||||
portA[3] = GPIOA->PUPDR;
|
|
||||||
portA[4] = GPIOA->AFR[0];
|
|
||||||
portA[5] = GPIOA->AFR[1];
|
|
||||||
|
|
||||||
portB[0] = GPIOB->MODER;
|
|
||||||
portB[1] = GPIOB->OTYPER;
|
|
||||||
portB[2] = GPIOB->OSPEEDR;
|
|
||||||
portB[3] = GPIOB->PUPDR;
|
|
||||||
portB[4] = GPIOB->AFR[0];
|
|
||||||
portB[5] = GPIOB->AFR[1];
|
|
||||||
|
|
||||||
portC[0] = GPIOC->MODER;
|
|
||||||
portC[1] = GPIOC->OTYPER;
|
|
||||||
portC[2] = GPIOC->OSPEEDR;
|
|
||||||
portC[3] = GPIOC->PUPDR;
|
|
||||||
portC[4] = GPIOC->AFR[0];
|
|
||||||
portC[5] = GPIOC->AFR[1];
|
|
||||||
|
|
||||||
portH[0] = GPIOH->MODER;
|
|
||||||
portH[1] = GPIOH->OTYPER;
|
|
||||||
portH[2] = GPIOH->OSPEEDR;
|
|
||||||
portH[3] = GPIOH->PUPDR;
|
|
||||||
portH[4] = GPIOH->AFR[0];
|
|
||||||
portH[5] = GPIOH->AFR[1];
|
|
||||||
}
|
|
||||||
|
|
||||||
void xdot_restore_gpio_state()
|
|
||||||
{
|
|
||||||
GPIOA->MODER = portA[0];
|
|
||||||
GPIOA->OTYPER = portA[1];
|
|
||||||
GPIOA->OSPEEDR = portA[2];
|
|
||||||
GPIOA->PUPDR = portA[3];
|
|
||||||
GPIOA->AFR[0] = portA[4];
|
|
||||||
GPIOA->AFR[1] = portA[5];
|
|
||||||
|
|
||||||
GPIOB->MODER = portB[0];
|
|
||||||
GPIOB->OTYPER = portB[1];
|
|
||||||
GPIOB->OSPEEDR = portB[2];
|
|
||||||
GPIOB->PUPDR = portB[3];
|
|
||||||
GPIOB->AFR[0] = portB[4];
|
|
||||||
GPIOB->AFR[1] = portB[5];
|
|
||||||
|
|
||||||
GPIOC->MODER = portC[0];
|
|
||||||
GPIOC->OTYPER = portC[1];
|
|
||||||
GPIOC->OSPEEDR = portC[2];
|
|
||||||
GPIOC->PUPDR = portC[3];
|
|
||||||
GPIOC->AFR[0] = portC[4];
|
|
||||||
GPIOC->AFR[1] = portC[5];
|
|
||||||
|
|
||||||
GPIOH->MODER = portH[0];
|
|
||||||
GPIOH->OTYPER = portH[1];
|
|
||||||
GPIOH->OSPEEDR = portH[2];
|
|
||||||
GPIOH->PUPDR = portH[3];
|
|
||||||
GPIOH->AFR[0] = portH[4];
|
|
||||||
GPIOH->AFR[1] = portH[5];
|
|
||||||
}
|
|
||||||
|
|
||||||
void xdot_enter_stop_mode()
|
|
||||||
{
|
|
||||||
GPIO_InitTypeDef GPIO_InitStruct;
|
|
||||||
|
|
||||||
// disable ADC and DAC - they can consume power in stop mode
|
|
||||||
ADC1->CR2 &= ~ADC_CR2_ADON;
|
|
||||||
ADC->CCR &= ~ADC_CCR_TSVREFE;
|
|
||||||
DAC->CR &= ~DAC_CR_EN1;
|
|
||||||
DAC->CR &= ~DAC_CR_EN2;
|
|
||||||
|
|
||||||
// enable ULP and enable fast wakeup
|
|
||||||
HAL_PWREx_EnableUltraLowPower();
|
|
||||||
HAL_PWREx_EnableFastWakeUp();
|
|
||||||
|
|
||||||
// disable HSI, MSI, and LSI if they are running
|
|
||||||
if (RCC->CR & RCC_CR_HSION) {
|
|
||||||
RCC->CR &= ~RCC_CR_HSION;
|
|
||||||
}
|
|
||||||
if (RCC->CR & RCC_CR_MSION) {
|
|
||||||
RCC->CR &= ~RCC_CR_MSION;
|
|
||||||
}
|
|
||||||
if (RCC->CSR & RCC_CSR_LSION) {
|
|
||||||
RCC->CSR &= ~RCC_CSR_LSION;
|
|
||||||
}
|
|
||||||
|
|
||||||
// configure USBTX & USBRX, LORA SPI, LORA_DIO, LORA_RESET, Secure Element, crystal pins, and SWD pins to analog nopull
|
|
||||||
// the application must do the same with WAKE, GPIO*, UART1_*, I2C_*, and SPI_*
|
|
||||||
|
|
||||||
// GPIO Ports Clock Enable
|
|
||||||
__GPIOA_CLK_ENABLE();
|
|
||||||
__GPIOB_CLK_ENABLE();
|
|
||||||
__GPIOC_CLK_ENABLE();
|
|
||||||
__GPIOH_CLK_ENABLE();
|
|
||||||
|
|
||||||
// USBTX & USBRX to analog nopull
|
|
||||||
GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_3;
|
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
||||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
||||||
|
|
||||||
// LORA_RESET to analog nopull
|
|
||||||
GPIO_InitStruct.Pin = GPIO_PIN_1;
|
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
||||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
||||||
|
|
||||||
// LORA_MISO to analog nopull
|
|
||||||
GPIO_InitStruct.Pin = GPIO_PIN_4;
|
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
||||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
||||||
|
|
||||||
// LORA_SCK & LORA_MOSI to input pulldown - additional current draw if left floating
|
|
||||||
GPIO_InitStruct.Pin = GPIO_PIN_3 | GPIO_PIN_5;
|
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
||||||
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
|
||||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
||||||
|
|
||||||
// LORA_NSS to analog nopull
|
|
||||||
GPIO_InitStruct.Pin = GPIO_PIN_15;
|
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
||||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
||||||
|
|
||||||
// LORA_DIO0 - LORA_DIO2 to analog nopull
|
|
||||||
GPIO_InitStruct.Pin = GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8;
|
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
||||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
||||||
|
|
||||||
// LORA_DIO3 - LORA_DIO4 to analog nopull
|
|
||||||
GPIO_InitStruct.Pin = GPIO_PIN_6 | GPIO_PIN_7;
|
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
||||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
||||||
|
|
||||||
// SE_CTRL, SE_IO, & SE_CLK to analog nopull
|
|
||||||
GPIO_InitStruct.Pin = GPIO_PIN_1 | GPIO_PIN_10 | GPIO_PIN_11;
|
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
||||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
||||||
|
|
||||||
// SE_RESET to analog nopull
|
|
||||||
GPIO_InitStruct.Pin = GPIO_PIN_13;
|
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
||||||
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
||||||
|
|
||||||
// SWDIO & SWCLK to analog nopull
|
|
||||||
GPIO_InitStruct.Pin = GPIO_PIN_13 | GPIO_PIN_14;
|
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
||||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
||||||
|
|
||||||
// OSC32_IN & OSC32_OUT to analog nopull
|
|
||||||
GPIO_InitStruct.Pin = GPIO_PIN_14 | GPIO_PIN_15;
|
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
||||||
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
||||||
|
|
||||||
// OSC_IN & OSC_OUT to analog nopull
|
|
||||||
GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1;
|
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
||||||
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
|
|
||||||
|
|
||||||
// done configuring pins to analog nopull
|
|
||||||
|
|
||||||
// make sure wakeup flag is cleared
|
|
||||||
PWR->CR |= PWR_CR_CWUF;
|
|
||||||
|
|
||||||
// enter stop mode - don't execute past here until woken up
|
|
||||||
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
|
|
||||||
|
|
||||||
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
|
||||||
RCC_OscInitTypeDef HSERCC_OscInitStruct;
|
|
||||||
/* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
|
|
||||||
HSERCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
|
|
||||||
HSERCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 24 MHz xtal on OSC_IN/OSC_OUT */
|
|
||||||
HSERCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
|
||||||
// SYSCLK = 32 MHz ((24 MHz * 4) / 3)
|
|
||||||
// USBCLK = 48 MHz ((24 MHz * 4) / 2) --> USB OK
|
|
||||||
HSERCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
||||||
HSERCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
|
||||||
HSERCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
|
|
||||||
HSERCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3;
|
|
||||||
if (HAL_RCC_OscConfig(&HSERCC_OscInitStruct) != HAL_OK) {
|
|
||||||
debug("OSC initialization failed - initiating soft reset\r\n");
|
|
||||||
NVIC_SystemReset();
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
|
|
||||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
|
||||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
|
|
||||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
|
|
||||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
|
|
||||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
|
|
||||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
|
|
||||||
debug("PLL initialization failed - initiating soft reset\r\n");
|
|
||||||
NVIC_SystemReset();
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Enable the HSI for ADC peripherals */
|
|
||||||
RCC_OscInitTypeDef HSIRCC_OscInitStruct;
|
|
||||||
HAL_RCC_GetOscConfig(&HSIRCC_OscInitStruct);
|
|
||||||
if (HSIRCC_OscInitStruct.HSIState != RCC_HSI_ON) {
|
|
||||||
HSIRCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
|
||||||
HSIRCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
|
|
||||||
HSIRCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
|
||||||
HAL_StatusTypeDef ret = HAL_RCC_OscConfig(&HSIRCC_OscInitStruct);
|
|
||||||
if (ret != HAL_OK) {
|
|
||||||
debug("HSI initialization failed - ADC will not function properly\r\n");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
SystemCoreClockUpdate();
|
|
||||||
|
|
||||||
// clear wakeup flag in power control register
|
|
||||||
PWR->CR |= PWR_CR_CWUF;
|
|
||||||
|
|
||||||
// enable the ADC and DAC
|
|
||||||
ADC->CCR |= ADC_CCR_TSVREFE;
|
|
||||||
ADC1->CR2 |= ADC_CR2_ADON;
|
|
||||||
DAC->CR |= DAC_CR_EN1;
|
|
||||||
DAC->CR |= DAC_CR_EN2;
|
|
||||||
}
|
|
||||||
|
|
||||||
void xdot_enter_standby_mode()
|
|
||||||
{
|
|
||||||
// enable ULP and enable fast wakeup
|
|
||||||
HAL_PWREx_EnableUltraLowPower();
|
|
||||||
HAL_PWREx_EnableFastWakeUp();
|
|
||||||
|
|
||||||
// disable HSI, MSI, and LSI if they are running
|
|
||||||
if (RCC->CR & RCC_CR_HSION) {
|
|
||||||
RCC->CR &= ~RCC_CR_HSION;
|
|
||||||
}
|
|
||||||
if (RCC->CR & RCC_CR_MSION) {
|
|
||||||
RCC->CR &= ~RCC_CR_MSION;
|
|
||||||
}
|
|
||||||
if (RCC->CSR & RCC_CSR_LSION) {
|
|
||||||
RCC->CSR &= ~RCC_CSR_LSION;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
// make sure wakeup and standby flags are cleared
|
|
||||||
PWR->CR |= PWR_CR_CWUF;
|
|
||||||
PWR->CR |= PWR_CR_CSBF;
|
|
||||||
|
|
||||||
// enter standby mode
|
|
||||||
HAL_PWR_EnterSTANDBYMode();
|
|
||||||
}
|
|
||||||
|
|
||||||
void xdot_enable_standby_wake_pin()
|
|
||||||
{
|
|
||||||
HAL_PWR_EnableWakeUpPin(PWR_WAKEUP_PIN1);
|
|
||||||
}
|
|
||||||
|
|
||||||
void xdot_disable_standby_wake_pin()
|
|
||||||
{
|
|
||||||
HAL_PWR_DisableWakeUpPin(PWR_WAKEUP_PIN1);
|
|
||||||
}
|
|
||||||
|
|
@ -1,105 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2016, MultiTech Systems
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of MultiTech nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __XDOT_LOW_POWER_H__
|
|
||||||
#define __XDOT_LOW_POWER_H__
|
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* xdot_disable_systick_int
|
|
||||||
* disable the systick interrupt
|
|
||||||
* call this before xdot_enter_stop_mode so systick interrupt doesn't wake up the processor
|
|
||||||
* only necessary if RTOS is used
|
|
||||||
*/
|
|
||||||
void xdot_disable_systick_int();
|
|
||||||
|
|
||||||
/* xdot_enable_systick_int
|
|
||||||
* enable the systick interrupt
|
|
||||||
* call this after xdot_enter_stop_mode so RTOS can function again
|
|
||||||
* only necessary if RTOS is used
|
|
||||||
*/
|
|
||||||
void xdot_enable_systick_int();
|
|
||||||
|
|
||||||
/* xdot_save_gpio_state
|
|
||||||
* save current state of all GPIOs
|
|
||||||
* call this before xdot_enter_stop_mode
|
|
||||||
* to achieve the lowest possible power consumption possible all GPIO pins must be configured for
|
|
||||||
* analog mode with no pull resistors enabled before entering STOP mode
|
|
||||||
* the xdot_enter_stop_mode function does this for USBTX/RX and all internal pins
|
|
||||||
* after calling xdot_save_gpio_state, the user application must do the same for WAKE, GPIO*,
|
|
||||||
* UART1_*, I2C_*, and SPI_* pins
|
|
||||||
* the user application should make a call to xdot_restore_gpio_state after waking from STOP mode
|
|
||||||
* in order to restore GPIO functionality
|
|
||||||
*/
|
|
||||||
void xdot_save_gpio_state();
|
|
||||||
|
|
||||||
/* xdot_restore_gpio_state
|
|
||||||
* restore all GPIOs to the state they were in when xdot_save_gpio_state was called
|
|
||||||
* call this after exiting from STOP mode
|
|
||||||
*/
|
|
||||||
void xdot_restore_gpio_state();
|
|
||||||
|
|
||||||
/* xdot_enter_stop_mode
|
|
||||||
* put the processor into STOP mode
|
|
||||||
* RAM and peripheral state is retained
|
|
||||||
* can be woken up by a number of interrupt sources including GPIOs and internal interrupts
|
|
||||||
* program execution resumes after this function when the device wakes up
|
|
||||||
*/
|
|
||||||
void xdot_enter_stop_mode();
|
|
||||||
|
|
||||||
/* xdot_enter_standby_mode
|
|
||||||
* put the processor into STANDBY mode
|
|
||||||
* RAM and peripheral state is lost
|
|
||||||
* can be woken up by the RTC alarm and rising edge on WAKE pin (WAKE pin must be configured first)
|
|
||||||
* program execution starts from the beginning of the application when the device wakes up
|
|
||||||
*/
|
|
||||||
void xdot_enter_standby_mode();
|
|
||||||
|
|
||||||
/* xdot_enable_standby_wake_pin
|
|
||||||
* configure the WAKE pin as a wakeup source from standby mode
|
|
||||||
* after this call, a rising edge on the WAKE pin will wake the processor up from standby mode
|
|
||||||
* this function should be called immediately before xdot_enter_standby_mode
|
|
||||||
*/
|
|
||||||
void xdot_enable_standby_wake_pin();
|
|
||||||
|
|
||||||
/* xdot_disnable_standby_wake_pin
|
|
||||||
* should be called after waking up from standby mode
|
|
||||||
*/
|
|
||||||
void xdot_disable_standby_wake_pin();
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __XDOT_LOW_POWER_H__ */
|
|
||||||
|
|
@ -6700,48 +6700,6 @@
|
||||||
"8080"
|
"8080"
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
"MTB_MTS_XDOT": {
|
|
||||||
"inherits": [
|
|
||||||
"FAMILY_STM32"
|
|
||||||
],
|
|
||||||
"core": "Cortex-M3",
|
|
||||||
"default_toolchain": "ARM",
|
|
||||||
"extra_labels_add": [
|
|
||||||
"STM32L1",
|
|
||||||
"STM32L151CC"
|
|
||||||
],
|
|
||||||
"config": {
|
|
||||||
"hse_value": {
|
|
||||||
"value": "24000000",
|
|
||||||
"macro_name": "HSE_VALUE"
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"overrides": {
|
|
||||||
"stdio_uart_tx": "PA_2",
|
|
||||||
"stdio_uart_rx": "PA_3"
|
|
||||||
},
|
|
||||||
"supported_toolchains": [
|
|
||||||
"ARM",
|
|
||||||
"GCC_ARM",
|
|
||||||
"IAR"
|
|
||||||
],
|
|
||||||
"device_has_add": [
|
|
||||||
"ANALOGOUT",
|
|
||||||
"FLASH",
|
|
||||||
"MPU"
|
|
||||||
],
|
|
||||||
"device_has_remove": [
|
|
||||||
"SERIAL_FC"
|
|
||||||
],
|
|
||||||
"release_versions": [
|
|
||||||
"5"
|
|
||||||
],
|
|
||||||
"device_name": "STM32L151CC",
|
|
||||||
"bootloader_supported": true,
|
|
||||||
"detect_code": [
|
|
||||||
"0453"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
"MTB_RAK811": {
|
"MTB_RAK811": {
|
||||||
"inherits": [
|
"inherits": [
|
||||||
"FAMILY_STM32"
|
"FAMILY_STM32"
|
||||||
|
|
|
||||||
|
|
@ -164,7 +164,7 @@
|
||||||
"sub-repo-example": false,
|
"sub-repo-example": false,
|
||||||
"subs": [],
|
"subs": [],
|
||||||
"features" : [],
|
"features" : [],
|
||||||
"targets" : ["DISCO_L072CZ_LRWAN1", "MTB_MTS_XDOT", "MTS_MDOT_F411RE"],
|
"targets" : ["DISCO_L072CZ_LRWAN1", "MTS_MDOT_F411RE"],
|
||||||
"toolchains" : [],
|
"toolchains" : [],
|
||||||
"exporters": [],
|
"exporters": [],
|
||||||
"compile" : true,
|
"compile" : true,
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue