mirror of https://github.com/ARMmbed/mbed-os.git
[LPC11U68] Fixed PLL lock issue etc
Fixed PLL lock issue Corrected system clock related codepull/301/head
parent
94f9d1fcc1
commit
e756237ebf
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@ -91,7 +91,7 @@
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// <2=> P = 4
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// <3=> P = 8
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// </h>
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#define SYSPLLCTRL_Val 0x00000003 // Reset value: 0x000
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#define SYSPLLCTRL_Val 0x00000023 // Reset value: 0x000
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//
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// <o.0..1> Main Clock Source Select (MAINCLKSEL)
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// <0=> IRC Oscillator
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@ -445,6 +445,25 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
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}
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#define PDRUN_VALID_BITS 0x000025FFL
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#define PDRUN_RESERVED_ONE 0x0000C800L
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static void power_down_config(uint32_t val)
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{
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volatile uint32_t tmp;
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tmp = (LPC_SYSCON->PDRUNCFG & PDRUN_VALID_BITS);
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tmp |= (val & PDRUN_VALID_BITS);
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LPC_SYSCON->PDRUNCFG = (tmp | PDRUN_RESERVED_ONE);
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}
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static void power_up_config(uint32_t val)
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{
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volatile uint32_t tmp;
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tmp = (LPC_SYSCON->PDRUNCFG & PDRUN_VALID_BITS);
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tmp &= ~(val & PDRUN_VALID_BITS);
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LPC_SYSCON->PDRUNCFG = (tmp | PDRUN_RESERVED_ONE);
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}
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/**
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* Initialize the system
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*
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@ -455,27 +474,30 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
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*/
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void SystemInit (void) {
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#if (CLOCK_SETUP)
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volatile uint32_t i;
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volatile uint32_t i, tmp;
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#endif
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LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
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LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
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#warning "should not return here, need to fix an issue with PLL lock"
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return;
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#if (CLOCK_SETUP) /* Clock Setup */
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#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
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// Initialize XTALIN/XTALOUT pins
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LPC_IOCON->PIO2_0 = 0x01;
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LPC_IOCON->PIO2_1 = 0x01;
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LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
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LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up sysosc */
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for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
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power_up_config(1<<5); /* Power-up sysosc */
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for (i = 0; i < 2500; i++) __NOP(); /* Wait for osc to stabilize */
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#endif
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#if ((SYSPLLCLKSEL_Val & 0x03) == 3)
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LPC_SYSCON->RTCOSCCTRL = (1 << 0); /* Enable 32 kHz output */
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for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
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#endif
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LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
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//LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
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LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
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LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
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LPC_SYSCON->SYSPLLCLKUEN = 0x01;
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while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
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@ -485,13 +507,13 @@ void SystemInit (void) {
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#if (((MAINCLKSEL_Val & 0x03) == 2) )
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LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
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LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
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for (i = 0; i < 2000; i++) __NOP(); /* Wait for osc to stabilize */
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for (i = 0; i < 2000; i++) __NOP(); /* Wait for osc to stabilize */
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#endif
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#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
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LPC_SYSCON->PDRUNCFG |= (1 << 7); /* Power-down SYSPLL */
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power_down_config(1<<7); /* Power-down SYSPLL */
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LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
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LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
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power_up_config(1<<7); /* Power-up SYSPLL */
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while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
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#endif
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@ -549,7 +571,4 @@ void SystemInit (void) {
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#endif /* Clock Setup */
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/* System clock to the IOCON needs to be enabled or
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most of the I/O related peripherals won't work. */
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LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
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}
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@ -31,30 +31,18 @@ typedef enum {
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} UARTName;
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typedef enum {
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ADC0_0 = 0,
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ADC0_1,
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ADC0_2,
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ADC0_3,
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ADC0_4,
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ADC0_5,
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ADC0_6,
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ADC0_7,
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ADC0_8,
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ADC0_9,
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ADC0_10,
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ADC0_11,
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ADC1_0,
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ADC1_1,
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ADC1_2,
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ADC1_3,
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ADC1_4,
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ADC1_5,
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ADC1_6,
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ADC1_7,
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ADC1_8,
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ADC1_9,
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ADC1_10,
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ADC1_11,
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ADC_0 = 0,
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ADC_1,
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ADC_2,
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ADC_3,
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ADC_4,
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ADC_5,
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ADC_6,
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ADC_7,
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ADC_8,
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ADC_9,
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ADC_10,
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ADC_11,
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} ADCName;
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typedef enum {
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@ -0,0 +1,131 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "analogin_api.h"
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#include "cmsis.h"
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#include "pinmap.h"
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#include "error.h"
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#ifdef DEVICE_ANALOGIN
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#define ANALOGIN_MEDIAN_FILTER 1
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#define ADC_10BIT_RANGE 0x3FF
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#define ADC_12BIT_RANGE 0xFFF
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#define PDRUN_VALID_BITS 0x000025FFL
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#define PDRUN_RESERVED_ONE 0x0000C800L
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#define ADC_RANGE ADC_12BIT_RANGE
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static const PinMap PinMap_ADC[] = {
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{P1_9 , ADC_0, 3},
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{P0_23, ADC_1, 1},
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{P0_16, ADC_2, 1},
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{P0_15, ADC_3, 3},
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{P1_22, ADC_4, 3},
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{P1_3 , ADC_5, 4},
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{P0_14, ADC_6, 2},
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{P0_13, ADC_7, 2},
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{P0_12, ADC_8, 2},
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{P0_11, ADC_9, 2},
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{P1_29, ADC_10,4},
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{P0_22, ADC_11,1},
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{NC , NC ,0}
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};
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void analogin_init(analogin_t *obj, PinName pin) {
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volatile uint32_t tmp;
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obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
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if (obj->adc == (uint32_t)NC) {
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error("ADC pin mapping failed");
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}
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pinmap_pinout(pin, PinMap_ADC);
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// ADC Powered
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tmp = (LPC_SYSCON->PDRUNCFG & PDRUN_VALID_BITS);
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tmp &= ~((1 << 4) & PDRUN_VALID_BITS);
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LPC_SYSCON->PDRUNCFG = (tmp | PDRUN_RESERVED_ONE);
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// Enable clock for ADC
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LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 13);
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// Start ADC self-calibration
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LPC_ADC->CTRL = (1UL << 30) || (100);
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do {
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tmp = LPC_ADC->CTRL;
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} while ((tmp & (1UL << 30)) != 0);
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LPC_ADC->CTRL = 100;
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}
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static inline uint32_t adc_read(analogin_t *obj) {
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// select channel
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LPC_ADC->SEQA_CTRL &= ~(0xFFF);
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LPC_ADC->SEQA_CTRL |= (1UL << obj->adc);
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// start conversion, sequence enable with async mode
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LPC_ADC->SEQA_CTRL |= ((1UL << 26) | (1UL << 31) | (1UL << 29) /*| (1UL << 19)*/);
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// Repeatedly get the sample data until DONE bit
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volatile uint32_t data;
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do {
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data = LPC_ADC->SEQA_GDAT;
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} while ((data & (1UL << 31)) == 0);
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data = LPC_ADC->DAT[obj->adc];
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// Stop conversion
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LPC_ADC->SEQA_CTRL &= ~(1UL << 31);
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return ((data >> 4) & ADC_RANGE);
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}
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static inline void order(uint32_t *a, uint32_t *b) {
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if (*a > *b) {
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uint32_t t = *a;
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*a = *b;
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*b = t;
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}
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}
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static inline uint32_t adc_read_u32(analogin_t *obj) {
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uint32_t value;
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#if ANALOGIN_MEDIAN_FILTER
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uint32_t v1 = adc_read(obj);
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uint32_t v2 = adc_read(obj);
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uint32_t v3 = adc_read(obj);
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order(&v1, &v2);
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order(&v2, &v3);
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order(&v1, &v2);
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value = v2;
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#else
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value = adc_read(obj);
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#endif
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return value;
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}
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uint16_t analogin_read_u16(analogin_t *obj) {
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uint32_t value = adc_read_u32(obj);
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return (value << 4) | ((value >> 8) & 0x000F); // 12 bit
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}
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float analogin_read(analogin_t *obj) {
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uint32_t value = adc_read_u32(obj);
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return (float)value * (1.0f / (float)ADC_RANGE);
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}
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#endif
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@ -22,14 +22,14 @@
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#define DEVICE_INTERRUPTIN 1
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#define DEVICE_ANALOGIN 0
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#define DEVICE_ANALOGIN 1
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#define DEVICE_ANALOGOUT 0
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#define DEVICE_SERIAL 1
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#define DEVICE_SERIAL_FC 1
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#define DEVICE_I2C 1
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#define DEVICE_I2CSLAVE 0
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#define DEVICE_I2CSLAVE 1
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#define DEVICE_SPI 1
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#define DEVICE_SPISLAVE 0
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@ -44,10 +44,9 @@ static const PinMap PinMap_I2C_SCL[] = {
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#define I2C_SCLL(x, val) (x->i2c->SCLL = val)
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#define I2C_SCLH(x, val) (x->i2c->SCLH = val)
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#warning [TODO] just copied from LPC11UXX code, need to check
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static const uint32_t I2C_addr_offset[2][4] = {
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{0x0C, 0x20, 0x24, 0x28},
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{0x30, 0x34, 0x38, 0x3C}
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{0x0C, 0x20, 0x24, 0x28}, // slave address offset
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{0x30, 0x34, 0x38, 0x3C} // slave address mask offset
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};
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static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
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void i2c_frequency(i2c_t *obj, int hz) {
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// No peripheral clock divider on the M0
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#warning "[TODO] This should be fixed to handle system core clock correctly."
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uint32_t PCLK = 12000000; //SystemCoreClock;
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uint32_t PCLK = SystemCoreClock;
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uint32_t pulse = PCLK / (hz * 2);
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@ -29,17 +29,17 @@
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* INITIALIZATION
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******************************************************************************/
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#define UART_NUM 5
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#define UART_NUM 1
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static const PinMap PinMap_UART_TX[] = {
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{P0_19, UART_0, 1},
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{P1_18, UART_0, 2},
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{P1_27, UART_0, 2},
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{P1_18, UART_1, 2},
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{P1_0 , UART_2, 3},
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{P1_23, UART_2, 3},
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{P2_4 , UART_3, 1},
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{P2_12, UART_4, 1},
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// {P1_18, UART_1, 2},
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// {P1_0 , UART_2, 3},
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// {P1_23, UART_2, 3},
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// {P2_4 , UART_3, 1},
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// {P2_12, UART_4, 1},
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{ NC , NC , 0}
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};
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{P0_18, UART_0, 1},
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{P1_17, UART_0, 2},
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{P1_26, UART_0, 2},
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{P1_2 , UART_1, 3},
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{P0_20, UART_2, 2},
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{P1_6 , UART_2, 2},
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{P2_3 , UART_3, 1},
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{P2_11, UART_4, 1},
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// {P1_2 , UART_1, 3},
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// {P0_20, UART_2, 2},
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// {P1_6 , UART_2, 2},
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// {P2_3 , UART_3, 1},
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// {P2_11, UART_4, 1},
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{NC , NC , 0}
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};
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// set the baud rate, taking in to account the current SystemFrequency
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void serial_baud(serial_t *obj, int baudrate) {
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LPC_SYSCON->USART0CLKDIV = 0x1;
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#warning "[TODO] This should be fixed to handle system core clock correctly."
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uint32_t PCLK = 12000000; //SystemCoreClock;
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uint32_t PCLK = SystemCoreClock;
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// First we check to see if the basic divide with no DivAddVal/MulVal
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// ratio gives us an integer result. If it does, we set DivAddVal = 0,
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// MulVal = 1. Otherwise, we search the valid ratio value range to find
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@ -27,8 +27,7 @@ void us_ticker_init(void) {
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us_ticker_inited = 1;
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LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10); // Clock CT32B1
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#warning "[TODO] this should read from SystemCoreClock grobal variable."
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uint32_t PCLK = 12000000;//SystemCoreClock;
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uint32_t PCLK = SystemCoreClock;
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US_TICKER_TIMER->TCR = 0x2; // reset
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